TWI782470B - Fingerprint identification module, chip and electronic device - Google Patents

Abstract

The present application provides a fingerprint identification module, a fingerprint identification chip and an electronic device. The fingerprint identification module includes an encapsulation layer and a die. The die includes a pixel array sensing circuit, which includes a number of pixel circuits with matrix distribution. Each pixel circuit includes a first metal layer that detects fingerprint of the finger. A distance between a curved outer surface of the encapsulation layer and the first metal layer of the pixel circuit on each column of the encapsulation layer changes linearly proportionally to an arc of the curved outer surface of the encapsulation layer, and the surface area of the first metal layer of the pixel circuit on each column of the pixel array sensing circuit changes linearly proportionally to the arc of the curved outer surface of the package layer. The present application can solve a problem of poor fingerprint signal quality collected by the pixel array sensing circuit with the curved package layer, and a problem of an uneven noise volume.

Description

Fingerprint identification module, chip and electronic equipment

The present application relates to the technical field of wireless communication, in particular to a fingerprint identification module, a chip and an electronic device with a fingerprint collection chip.

With the popularization of full-screen smartphones, fingerprint collection and recognition solutions tend to be optical under-screen fingerprint recognition and capacitive side fingerprint recognition. Among them, the capacitive side fingerprint recognition solution is not affected by the light source, and the active unlocking experience is especially good. However, in consideration of the uniformity of the signal quantity, almost all existing fingerprint collection and identification schemes adopt a planar molding structure. However, the side fingerprint recognition module in the capacitive side fingerprint recognition solution is located on the side of the mobile phone (such as the left or right side, generally designed on the right side). At present, more than 95% of the mobile phone sides are arc-shaped. Due to the structural design, the fingerprint identification module with a flat molding structure does not fit well with the mobile phone. The side of the mobile phone is uneven in appearance, and the unlocking experience by fingerprint is not ideal.

In addition, the unit area size of each pixel (Pixel) in the sensor array (Sensor Array) of the existing fingerprint identification scheme is consistent, corresponding to the planar molding, the deviation of the signal amount and noise amount collected by the Sensor Array is not large, and the acquisition The signal-to-noise ratio (Signal Noise Ratio, SNR) uniformity of the signal is very good, and the obtained image is clear and high in contrast. However, for curved surface molding, since the thickness of curved surface molding differs on each column of Pixels, there are obvious gradient differences in the signal and noise quantities on each column of pixels, and the SNR also shows an obvious gradient trend. However, there is a fixed gradient deviation in each column of data (such as thickness) in curved surface molding, which further reduces the SNR, and leads to a decrease in the quality of the collected fingerprint image and poor fingerprint recognition effect.

In view of this, a fingerprint identification module, a chip and an electronic device with a fingerprint collection chip are provided to solve the problems of poor quality of fingerprint signal and uneven noise amount collected by a picture element array sensing circuit with a curved packaging layer.

In one embodiment of the present application, a fingerprint recognition module is provided, including an encapsulation layer and a die, the encapsulation layer covers the die, the die contains a picture element array sensing circuit, and the picture element array sensing circuit includes A plurality of graphic element circuits distributed in a matrix, the graphic element circuits include a first metal layer for detecting fingerprints, and the first metal layer is arranged on the side of the crystal grain facing the packaging layer, The encapsulation layer has an arc-shaped outer surface, and the distance from the arc-shaped outer surface of the encapsulation layer to the first metal layer of the element circuit on each column of the element array sensing circuit is equal to the arc shape of the encapsulation layer The curvature of the outer surface varies linearly, and the first gold element circuit on each column of the element array induction circuit The surface area of the metal layer varies linearly with the curvature of the curved outer surface of the encapsulation layer.

，其中，d1、d2...dn分別為所述封裝層的弧形外表面到所述圖元陣列感應電路的第1、2...n列上的圖元電路的第一金屬層的距離；S1、S2...Sn分別為所述圖元陣列感應電路上n列的第一金屬層的表面面積，n為正整數。 In some embodiments of the present application, the distance d from the arc-shaped outer surface of the encapsulation layer to the first metal layer of the graphic element circuit on the n columns of the graphic element array sensing circuit is the same as that of the graphic element array sensing circuit The surface area s of the first metal layer of the primitive circuit on the n columns satisfies

, wherein, d1, d2...dn are the distances from the arc-shaped outer surface of the packaging layer to the first metal layer of the picture element circuit on the 1st, 2...n columns of the picture element array sensing circuit The distances; S1, S2...Sn are respectively the surface areas of the first metal layers in n columns on the sensing circuit of the graphic element array, and n is a positive integer.

In some embodiments of the present application, the graphic element circuit further includes a second metal layer, a third metal layer, and a substrate layer, and the second metal layer and the third metal layer are disposed on the first metal layer and the substrate layer, the projection of the second metal layer and the third metal layer on the substrate layer covers the projection of the first metal layer on the substrate layer, so that the first metal layer The layer is isolated from the substrate layer, the first metal layer generates a fingerprint signal when a finger approaches, and the second metal layer and the third metal layer are overlapped or staggered.

In some embodiments of the present application, the fingerprint identification module further includes an integrating circuit, and the integrating circuit is connected to the sensing circuit of the array of graphic elements, and is used to amplify the fingerprint signal generated by the sensing circuit of the array of graphic elements ; The picture element array sensing circuit includes a first switch group and a second switch group, the first switch group includes a first sub-switch, a second sub-switch, and a third sub-switch, and the second switch group includes a first A sub-switch, a second sub-switch, and a third sub-switch; the second metal layer is connected to the power supply voltage through the first sub-switch of the first switch group and connected to the power supply through the first sub-switch of the second switch group connected to the floating ground; the third metal layer is connected to the power supply voltage through the second sub-switch of the first switch group and connected to the first reference voltage through the second sub-switch of the second switch group connected; the first metal layer is connected to the first reference voltage through the third sub-switch of the first switch group and connected to the integration circuit through the third sub-switch of the second switch group.

In some embodiments of the present application, when the peripheral state control signal Tx=0, the voltage of the floating ground terminal VNVSS=0, and when the peripheral state control signal Tx=1, the floating ground terminal is connected to a preset negative voltage, The voltage of the floating ground terminal VNVSS=-VTX, wherein -VTX is the preset negative voltage.

In some embodiments of the present application, a negative voltage output circuit is included for providing -VTX to the floating ground terminal.

In some embodiments of the present application, the integration circuit includes an operational amplifier and a feedback loop, the operational amplifier includes a non-inverting input terminal, an inverting input terminal and an output terminal, and the non-inverting input terminal and the first reference voltage The output voltage of the output terminal is adjusted by adjusting the first reference voltage, and the first metal layer is connected to the inverting input terminal through the third sub-switch of the second switch group, so The output end is connected to the reverse input end through the feedback loop; the feedback loop includes a feedback capacitor, a third switch group and a fourth switch group, and the upper plate of the feedback capacitor is connected by the The first sub-switch of the third switch group is connected to the second reference voltage, the lower plate of the feedback capacitor is connected to the power supply voltage through the second sub-switch of the third switch group, and the upper plate of the feedback capacitor The pole plate is connected to the reverse input terminal through the first sub-switch of the fourth switch group, and the lower plate of the feedback capacitor is connected to the output terminal through the second sub-switch of the fourth switch group. connected, the inverting input terminal is connected to the output terminal through the third sub-switch of the third switch group.

In some embodiments of the present application, the graphic element array sensing circuit provides a first timing control signal, a second timing control signal, a third timing control signal and a fourth timing control signal, and the first timing control signal The second timing control signal is a clock signal with a phase difference of 180°, the third timing control signal φ1 and the fourth timing control signal φ2 are non-overlapping clock signals with a phase difference of 180°, and the first The timing control signal is used to control the opening and closing of the first sub-switch, the second sub-switch, and the third sub-switch of the third switch group, and the second timing control signal is used to control the fourth switch group The opening and closing of the first sub-switch and the second sub-switch of the first switch group, the third timing control signal is used to control the opening and closing of the first sub-switch, the second sub-switch, and the third sub-switch of the first switch group and closing, the fourth timing control signal is used to control the opening and closing of the first sub-switch, the second sub-switch and the third sub-switch of the second switch group.

(a) Initial stage; the first timing control signal is high level, the second timing control signal is low level, and the first sub-switch, the second sub-switch, and the third sub-switch of the third switch group are simultaneously turn on, the first sub-switch and the second sub-switch of the fourth switch group are turned off at the same time; (b) scanning phase: the first timing control signal is low, and the second timing control signal is high Level, the first sub-switch, the second sub-switch, and the third sub-switch of the third switch group are turned off at the same time, and the first sub-switch and the second sub-switch of the fourth switch group are turned on at the same time; (c) Pre-charging stage: the peripheral state control signal TX=0, the floating ground terminal is connected to the ground terminal, the voltage V _NVSS of the floating ground terminal =0, the first sub-switch of the first switch group, the second sub-switch of the first switch group The switch is turned off, the third sub-switch of the first switch group is turned on, the first sub-switch of the second switch group and the second sub-switch of the second switch group are turned on at the same time, the third sub-switch of the second switch group The sub-switch is turned off, the second metal layer is connected to the ground terminal, the first metal layer and the third metal layer are connected to the first reference voltage at the same time, and the first metal layer is disconnected from the amplifier; (d ) In the charge transfer stage, the peripheral state control signal Tx=1, the floating ground terminal is connected to a preset negative voltage, the third sub-switch of the first switch group changes from on to off, and the third sub-switch of the second switch group From off to on, the first sub-switch of the first switch group, the second sub-switch of the first switch group, the first sub-switch of the second switch group, and the second sub-switch of the second switch group maintain the state unchanged, the preset negative voltage -VTX=(-1)*VDD, wherein VDD is the power supply voltage, the second sub-switch of the second switch group is turned on, and the inverting input terminal of the amplifier is connected by the second The third sub-switch of the switch group is connected to the first metal layer, and the output terminal of the amplifier is connected to the inverting input terminal through the feedback capacitor.

In some embodiments of the present application, the fingerprint recognition module further includes a PCB board and a flexible circuit board, the PCB board is arranged on the flexible circuit board, the crystal grain is arranged on the PCB board, and the The encapsulation layer covers the die and the PCB board.

An embodiment of the present application also provides a fingerprint identification chip including the above-mentioned die, the die includes a picture element array sensing circuit, and the picture element array sensing circuit includes a plurality of picture element circuits distributed in a matrix. The element circuit includes a first metal layer for detecting fingerprints, and the first metal layer is arranged on the die and faces the encapsulation layer covering the die, and the surface area of the first metal layer is the same as The thickness of the overlying encapsulation layer scales linearly.

The embodiment of the present application also provides an electronic device, which adopts the fingerprint chip provided above.

According to the distance from the arc-shaped outer surface of the packaging layer to the first metal layer, the application differentiates the surface area of the first metal layer to ensure that the unit capacitance value collected by the sensor array sensor circuit of the graphics element is consistent, and solves the problem of having a curved surface. The quality of the fingerprint signal collected by the graphic element array sensing circuit on the packaging layer is poor and the amount of noise is uneven.

10:Fingerprint identification system

12: Graphic element array sensing circuit

13: Integrator circuit

14: Analog-to-digital conversion circuit

15: Digital signal processor

16: Host

121:Picture circuit

131: Integrator

1211: the first metal layer

1212: second metal layer

1213: the third metal layer

1214: substrate layer

GND: ground terminal

C _finger : the first parasitic capacitance

2: Fingerprint identification module

3: Electronic equipment

21: Encapsulation layer

22: grain

23: PCB board

24:Flexible circuit board

212: Curved outer surface

211: outer plane

25: Connector

16: Host

φ11: The first sub-switch

φ12: Second sub-switch

φ13: The third sub-switch

φ21: The first sub-switch

φ22: Second sub-switch

φ23: The third sub-switch

V _DD : power supply voltage

NVSS: floating ground

222: second capacitor

V _REF : first reference voltage

1218: resistance

131: Operational amplifier

132: Feedback loop

1311: Non-inverting input terminal

1312: reverse input terminal

1313: output terminal

C _FB : Feedback capacitance

rst_a1: the first sub-switch

rst_a2: the second sub-switch

rst_a3: the third sub-switch

rst_b1: the first sub-switch

rst_b2: the second sub-switch

reset_a: the first timing control signal

reset_b: the second timing control signal

φ1: The third timing control signal

φ2: The fourth timing control signal

14: Analog-to-digital conversion circuit

FIG. 1 is a system frame of a fingerprint recognition system in an embodiment of the present application.

FIG. 2 is a schematic diagram of a connection between a picture element array sensing circuit and an integrating circuit in an embodiment of the present application.

FIG. 3 is a circuit structure diagram of a graphic element circuit in an embodiment of the present application.

FIG. 4 is a schematic diagram of a fingerprint identification module installed on an electronic device in an embodiment of the present application.

FIG. 5 is a cross-sectional view of the fingerprint recognition module of FIG. 4 along the V-V plane.

FIG. 6 is a cross-sectional view of an existing fingerprint identification module.

Fig. 7a is a schematic diagram of the encapsulation layer of the existing fingerprint identification module.

Fig. 7b is a schematic diagram of the encapsulation layer of the fingerprint identification module in an embodiment of the present application.

Fig. 8a is a schematic diagram of a fingerprint signal collected by a picture element array sensing circuit of an existing encapsulation layer.

Fig. 8b is a schematic diagram of fingerprint signals collected by the pixel array sensing circuit in an embodiment of the present application.

9 is a schematic diagram of the relationship between the curvature of the curved surface packaging layer and the area of the first metal layer of the graphic element circuit in an embodiment of the present application.

FIG. 10 is a schematic diagram of a specific connection between a picture element array sensing circuit and an integrating circuit in an embodiment of the present application.

FIG. 11 is a timing diagram of fingerprint collection performed by the pixel array sensing circuit in an embodiment of the present application.

In order to better understand the above purpose, features and advantages of the embodiments of the present application, the present application will be described in detail below in conjunction with the accompanying drawings and specific implementation methods. It should be noted that, in the case of no conflict, the features in the embodiments of the present application may be combined with each other.

A lot of specific details are set forth in the following description so as to fully understand the embodiments of the present application, and the described implementation manners are part of the implementation manners of the present application, but not all of the implementation manners.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field of the embodiments of this application. The terminology used in the description of the present application is only for the purpose of describing specific implementation manners, and is not intended to limit the embodiments of the present application.

Please refer to FIG. 1 , which shows a system frame of a fingerprint identification system 10 in an embodiment of the present application. In this embodiment, the fingerprint identification system 10 includes a pixel array sensing circuit 12 , an integrating circuit 13 , an analog-to-digital conversion circuit 14 , a digital signal processor 15 and a host 16 . In this embodiment, the graphic element array The induction circuit 12, the integration circuit 13, the analog-to-digital conversion circuit 14, the digital signal processor 15 and the host computer 16 are connected in this way, that is, the picture element array induction circuit 12 is connected with the integration circuit 13, and the integration circuit 13 is connected with the integration circuit 13. The analog-to-digital conversion circuit 14 is connected, the analog-to-digital conversion circuit 14 is connected to the digital signal processor 15 , and the digital signal processor 15 is connected to the host computer 16 .

In this embodiment, the graphic element array sensing circuit 12 scans according to a certain timing control to detect the user's fingerprint signal. The integration circuit 13 integrates the charge variation of the collected fingerprint signal multiple times at the same time, and amplifies the fingerprint signal. The analog-to-digital conversion circuit 14 converts the amplified fingerprint signal into a digital signal with fingerprint information. The digital signal processor 15 performs digital file processing on the digital signal with fingerprint information to obtain a digital file processing result. The host 16 identifies the fingerprint information according to the digital document processing result.

In this embodiment, since the analog-to-digital conversion circuit 14, the digital signal processor 15, and the host computer 16 are existing circuit structures in the art, and this application does not discuss the circuits of the analog-to-digital conversion circuit 14, the digital signal processor 15, and the host computer 16. The structure is improved. This application does not introduce the analog-to-digital conversion circuit 14, the digital signal processor 15, and the host computer 16 in detail. The following only specifically describes the improvement schemes of the pixel array sensing circuit 12 and the integration circuit 13 of the present application.

In this embodiment, the pixel array sensing circuit 12 includes a sensor matrix array (Sensor Array) composed of pixel circuits 121 (Pixels) in m rows and n columns, where m and n are positive integers. Please refer to FIG. 2 , which is a schematic diagram of the connection between the pixel array sensing circuit 12 and the integrating circuit 13 in an embodiment of the present application. In this embodiment, the integration circuit 13 includes a plurality of integrators 131 . In this embodiment, the number of integrators 131 shown is the same as the number of columns of the sensor array. For example, if the sensor array includes n columns of primitive circuits 121 , then the number of integrators 131 of the integrating circuit 13 is n. In this embodiment, the primitive circuits 121 of each column in the sensor array are connected to the integrator 131 of the same integrating circuit 13 , and the primitive circuits 121 of different columns are connected to different integrators 131 .

In this embodiment, since the structure and working principle of each picture element circuit 121 in the picture element array sensing circuit 12 are the same, this application only introduces the circuit structure of a single picture element circuit 121 . Please refer to FIG. 3 , which shows a circuit structure diagram of the graphic element circuit 121 in an embodiment of the present application. The graphic element circuit 121 includes a first metal layer 1211 , a second metal layer 1212 , a third metal layer 1213 , and a substrate layer 1214 . In this embodiment, the first metal layer 1211 is used to detect the user's fingerprint. When the user's finger touches the first metal layer 1211, since the human body itself is a good conductor, it can be regarded as the ground terminal GND, and the user's finger and the first metal layer 1211 of the fingerprint recognition module form a first parasitic capacitance C _finger . In this embodiment, the distance between the valleys and ridges of the fingerprint and the first metal layer 1211 is different, and the size of the first parasitic capacitance _Cfinger is different _accordingly . fingerprint signal. In this embodiment, the fingerprint signal is the charge amount of the first parasitic capacitor C _finger .

After the finger touches the first metal layer 1211, C _finger is formed between the first metal layer 1211 and the human body, and a second parasitic capacitance C _pex is also formed between the first metal layer 1211 and the substrate layer 1214, so that the first metal layer 1211 and the substrate layer The total parasitic capacitance C _top of the bottom layer (GND) =C ₁ +C ₂ , expressed as where C ₁ is the first parasitic capacitance C _finger , and C ₂ is the second parasitic capacitance C _pex . In this way, the capacitance detected from the first metal layer 1211l includes not only the first parasitic capacitance C _finger , but also the second parasitic capacitance C _pex . To improve the fingerprint detection accuracy, it is hoped that the first parasitic capacitance C _finger is infinitely close to the total parasitic capacitance C _top , and the closer the second parasitic capacitance C _{pex is} to zero, the better. In order to reduce the impact of the second parasitic capacitance _Cpex on the detection accuracy of fingerprints, the present application sets the second metal layer 1212 and the third metal layer 1213 between the first metal layer 1211 and the substrate layer 1214 to combine the first metal layer 1211 with the substrate layer 1214. The substrate layer 1214 is isolated, and the projection of the second metal layer 1212 and the third metal layer 1213 on the substrate layer 1214 covers the projection of the first metal layer 1211 on the substrate layer 1214, so as to eliminate the formation between the first metal layer 1211 and the substrate layer 1214. The second parasitic capacitance C _pex improves the detection accuracy of the fingerprint signal. Specifically, the first metal layer 1211 and the second metal layer 1212 are spaced apart, and the first capacitor 21 is formed between the first metal layer 1211 and the second metal layer 1212 . The first metal layer 1211 and the third metal layer 1213 are spaced apart, and a second capacitor 222 is formed between the first metal layer 1211 and the third metal layer 1213 . The second metal layer 1212 and the third metal layer 1213 can overlap or be staggered, and the total coverage of the second metal layer 1212 and the third metal layer 1213 should be greater than or equal to the range of the first metal layer.

Referring to FIG. 2 , in this embodiment, when the graphic element array sensing circuit 12 performs fingerprint scanning work, the graphic element circuit 121 collects and converts the first parasitic capacitance C _finger signal variation between the finger and the first metal layer 1211 into The amount of charge change, the integrator 131 connected to the graphic element circuit 121 integrates the charge change amount of the collected fingerprint signal multiple times at the same time, amplifies the fingerprint signal, and transmits the processed fingerprint signal to the subsequent stage The analog-to-digital conversion circuit 14. In this embodiment, when the picture element array sensing circuit 12 scans, the n picture element circuits 121 and n integrators 131 of the sensor array operate simultaneously, and the n fingerprint signals collected by the n picture element circuits 121 change each time. After being integrated and amplified by n integrators 131, the quantity is output to the analog-to-digital conversion circuit 14 of the subsequent stage at the same time. After the scanning of a row of graphic element circuits 121 is completed, the scanning of the next row of graphic element circuits 121 is performed until the mth row is scanned. The recognition system 10 completes the entire frame scan.

Please refer to FIG. 4 , which is a schematic diagram showing the fingerprint identification module 2 installed on the electronic device 3 in an embodiment of the present application. In this embodiment, the electronic device 3 may be, but not limited to, a smart phone, a tablet computer, a notebook computer or a game device. The fingerprint identification module 2 is installed on the side of the electronic device 3 . In this embodiment, the area where the fingerprint identification module 2 is installed on the electronic device 3 can form a fingerprint identification area alone or be integrated with the power key area of the electronic device 3 .

Please refer to FIG. 5 , which is a cross-sectional view of the fingerprint recognition module 2 taken along the V-V plane in an embodiment of the present application. In this embodiment, the fingerprint recognition module 2 includes a packaging layer 21 , a die 22 , a PCB (Printed Circuit Board) board 23 , and a flexible circuit board 24 . In this embodiment, the encapsulation layer 21 is realized in a curved shape. The curved encapsulation layer 21 has a curved outer surface 212 . In this embodiment, the PCB board 23 is arranged on the flexible circuit board 24 . The die 22 is disposed on the PCB board 23 . The encapsulation layer 21 at least covers the die 22 and the PCB board 23 . In this embodiment, the graphic element array sensing circuit 121 is implanted on the die 22 . In this embodiment, the fingerprint recognition module 2 has a long strip structure. In other implementations, the fingerprint recognition module 2 can also be in a square, circular or irregular shape.

In this embodiment, the graphic element array sensing circuit 12 is disposed on the surface of the die 22 and the surface of the die 22 is packaged to form the encapsulation layer 21 . Specifically, the graphic element array sensing circuit 12 is disposed on a side of the die facing 22 facing the encapsulation layer 21 . When the user's finger touches the arc-shaped outer surface 212 of the encapsulation layer 21, the picture element array sensing circuit 12 can collect the fingerprint of the finger, so as to avoid scratches on the surface of the picture element array sensing circuit 12 when the finger is in direct contact with the die 22. Flower, damage problem. In this embodiment, the encapsulation layer refers to the injection molding layer obtained after injection molding encapsulation and coating treatment. In this embodiment, the function of the encapsulation layer 21 is to protect the picture element array sensing circuit 12, and to protect the chip 22, the PCB board 23, The flexible circuit board 24 is integrated to realize modularization. In this embodiment, the signal that the graphic element array sensing circuit 12 needs to collect is the first parasitic capacitance Cfinger between the finger surface touching the arc-shaped outer surface 212 of the packaging layer 21 and the first metal layer 1211 of the graphic element array sensing circuit 12. signal, and the encapsulation layer 21 is located between the surface of the finger and the first metal layer 1211 , the thickness of the encapsulation layer 21 is the distance between the arc-shaped outer surface 212 of the encapsulation layer 21 and the first metal layer 1211 .

Referring to FIG. 6 , it is a cross-sectional view of a conventional fingerprint recognition module 2 . The packaging layer 21 of the fingerprint identification module 2 is planar. The planar encapsulation layer 21 has an outer plane 211 . In a specific implementation manner, the thickness of the encapsulation layer 21 with the outer plane 211 should be as small as possible, and the flatness should be as good as possible, so as to ensure the uniformity of the collected signals.

Referring to FIG. 4 , in this embodiment, the fingerprint identification module 2 is installed in the electronic device 3 through a connector 25 . Specifically, the die 22 of the fingerprint recognition module 2 is connected to the PCB 23 by bonding. The PCB board 23 is welded together with the flexible circuit board 24 through a pad (PAD), and the flexible circuit board 24 is connected to the electronic device 3 through a connector 25 (such as a cable), such as connecting the The host 16 of the electronic device 3 .

In this embodiment, in the scheme of setting the fingerprint recognition module 2 on the side of the electronic device 3, since the side surface of the electronic device 3 is arc-shaped, the fingerprint recognition module 2 has an arc shape. The encapsulation layer 21 of the outer surface 212 can eliminate the uneven feeling of the side of the electronic device 3 , so that the appearance of the electronic device 3 installed with the fingerprint identification module 2 is curved and integrated.

In one embodiment, referring to FIG. 6 , in the scheme of setting the fingerprint recognition module 2 on the front glass cover of the electronic device 3 or on the rear coating cover of the electronic device 3 , since The surface of the electronic device 3 is plane, and in consideration of the thickness and flatness of the packaging layer 21 , the packaging layer 21 of the fingerprint recognition module 2 is realized in a planar shape. That is, the encapsulation layer 21 of the fingerprint identification module 2 has an outer plane 211 .

Referring to FIG. 7 a , it is a schematic diagram of a conventional planar encapsulation layer 21 . Referring to FIG. 7 b , it shows a curved encapsulation layer 21 in an embodiment of the present application. The distance from the outer plane 211 of the encapsulation layer 21 to the first metal layer 1211 (that is, the surface of the die 22 ) of the picture element circuit 121 on each column of the picture element array sensing circuit 12 (that is, the distance of the encapsulation layer 21 thickness) are equal. For example, the distances d1, d2, d3 from any three points on the outer plane 211 of the planar encapsulation layer 21 of the fingerprint recognition module 2 to the first metal layer 1212 (that is, the surface of the crystal grain 22) of the graphic element array sensing circuit 12 Both are equal. In this embodiment, the surface area of the first metal layer 1211 of the picture element circuit 121 on each column of the picture element array sensing circuit 12 is equal. Referring to FIG. 8 a , it is a schematic diagram of fingerprint signals collected by the picture element array sensing circuit 12 of the conventional planar encapsulation layer 21 . The amount of fingerprint signals (first parasitic capacitance Cfinger) collected by the picture element circuits 121 on each column of the picture element array sensing circuit 12 is uniform.

Referring to FIG. 7 b , the distance d1 between any three points on the curved outer surface 212 of the curved encapsulation layer 21 of the fingerprint recognition module 2 and the first metal layer 1212 (that is, the surface of the die 22 ) of the array sensing circuit 12 , d2, and d3 are not equal, and the thickness of the encapsulation layer 21 varies linearly with the curvature of the outer surface 212 of the encapsulation layer 21 . Referring to FIG. 8 b , it is a schematic diagram of fingerprint signals collected by the pixel array sensing circuit 12 of the curved encapsulation layer 21 in an embodiment of the present application. The fingerprint signal amount (the first parasitic capacitance Cfinger signal) collected by the picture element circuit 121 on each column of the picture element array sensing circuit 12 is distributed in a gradient manner. Curved The inhomogeneous characteristics of the fingerprint signal collected by the fingerprint recognition module 2 of the encapsulation layer 21 will cause troubles for the subsequent fingerprint recognition algorithm to distinguish between fingerprint ridges and valleys, and increase the misjudgment rate.

，ε表示介質介電常數，S表示兩極板間正對面積，即正對手指的第一金屬層1212的面積，d表示手指到第一金屬層1212的距離。本實施方式中，假設封裝層21在圖元陣列感應電路12的n列上的厚度分別為d1、d2...dn，且d1=x2*d2=...xn*dn，x2、x3...xn分別為封裝層21在圖元陣列感應電路12的第2、3......n列上的厚度相比於封裝層21在圖元陣列感應電路12的第1列的厚度係數。圖元陣列感應電路12上n列的第一金屬層1212的表面面積為S1、 S2...Sn，根據

，則S1=x2*S2=...=xn*Sn。因而，封裝層21在圖元陣列感應電路12的n列上的厚度與圖元陣列感應電路12的n列上的圖元電路的第一 金屬層的表面面積滿足

。本實施方式中，根據曲面型的封裝層21的弧形外表面212的弧度特性，得出封裝層21在圖元陣列感應電路12不同列上的厚度係數，進而推算出圖元陣列感應電路12在不同列上的圖元電路121的第一金屬層1212的表面面積。 In this embodiment, the capacitance between the finger and the first metal layer 1212 of the array sensing circuit 12 is expressed as

, ε represents the dielectric constant of the medium, S represents the facing area between the two plates, that is, the area of the first metal layer 1212 facing the finger, and d represents the distance from the finger to the first metal layer 1212. In this embodiment, it is assumed that the thicknesses of the encapsulation layer 21 on the n columns of the picture element array sensing circuit 12 are d1, d2...dn, and d1=x2*d2=...xn*dn, x2, x3. ..xn are the thicknesses of the encapsulation layer 21 on the second, third...n columns of the picture element array sensing circuit 12 compared to the thickness of the encapsulation layer 21 on the first column of the picture element array sensing circuit 12 coefficient. The surface area of the first metal layer 1212 in n columns on the picture element array sensing circuit 12 is S1, S2...Sn, according to

, then S1=x2*S2=...=xn*Sn. Therefore, the thickness of the encapsulation layer 21 on the n columns of the picture element array sensing circuit 12 and the surface area of the first metal layer of the picture element circuit on the n columns of the picture element array sensing circuit 12 satisfy

. In this embodiment, according to the radian characteristics of the curved outer surface 212 of the curved packaging layer 21, the thickness coefficients of the packaging layer 21 on different columns of the graphic element array sensing circuit 12 are obtained, and then the graphic element array sensing circuit 12 is calculated. The surface area of the first metal layer 1212 of the primitive circuit 121 on different columns.

Referring to FIG. 9 , it is a schematic diagram showing the relationship between the curvature of the curved encapsulation layer 21 and the area of the first metal layer 1212 of the graphic element circuit 121 in an embodiment of the present application.

In this embodiment, the distances from the curved outer surface 212 of the curved encapsulation layer 21 to the first metal layer 1212 of the picture element array sensing circuit 12 in different columns are different, and the first metal layer 1212 of the corresponding column on the picture element array sensing circuit 12 The surface area of the layer 1212 is also different. The distance from the arc-shaped outer surface 212 of the packaging layer 21 to the first metal layer 1212 of the array sensing circuit 12 is linearly proportional to the surface area of the first metal layer 1212 .

This application calculates the distance from the arc-shaped outer surface 212 of the encapsulation layer 21 to the first metal layer 1212 according to the curvature of the arc-shaped outer surface 212 of the encapsulation layer 21, and calculates a single graphic element circuit under the corresponding arc according to the distance The surface area of the first metal layer 1212 of 121, by differentially designing the surface area of the first metal layer 1212, ensures that the unit capacitance value collected by the pixel array sensing circuit 12 is consistent, and solves the problem of having a curved packaging layer 21 The signal quality of the picture element array sensing circuit 12 is poor and the SNR is not uniform.

In one embodiment, the fingerprint recognition module 2 further includes an integrating circuit 13 . The graphic element array sensing circuit 12 is connected with an integrating circuit 13 . Please refer to FIG. 10 , which is a schematic diagram of specific connections between the pixel array sensing circuit 12 and the integrating circuit 13 in an embodiment of the present application. In this embodiment, the first metal layer 1211 forms a first parasitic capacitance C _finger with the human body regarded as GND. The first capacitor 21 is a parasitic capacitor formed between the first metal layer 1211 and the second metal layer 1212 . The picture element array sensing circuit 12 includes a first switch group and a second switch group. The first switch group includes a first sub-switch φ11, a second sub-switch φ12, and a third sub-switch φ13. The second switch group includes a first sub-switch φ21, a second sub-switch φ22, and a third sub-switch φ23.

The first metal layer 1211 and the second metal layer 1212 form the first capacitor 21 . The second metal layer 1212 is connected to the power supply voltage V _DD through the first sub-switch φ11 of the first switch group, and the second metal layer 1212 is connected to the floating ground terminal NVSS through the first sub-switch φ21 of the second switch group. The third sub-switch φ23

The first metal layer and the third metal layer 1213 form a second capacitor 222 . The third metal layer 1213 is connected to the power supply voltage V _DD through the second sub-switch φ12 of the first switch group, and connected to the first reference voltage V _REF through the second sub-switch φ22 of the second switch group.

The first metal layer 1211 is connected to the first reference voltage V _REF through the third sub-switch φ13 of the first switch group and connected to the integrating circuit connection 13 through the third sub-switch φ23 of the second switch group. Specifically, the graphic element array sensing circuit 12 is further provided with a resistor 1218 , and the first metal layer 1211 is connected to one end of the resistor 1218 . The other end of the resistor 1218 is connected to the power supply voltage VDD through the third sub-switch φ13 of the first switch group, and connected to the integration circuit 13 through the second sub-switch φ23 of the second switch group.

In this embodiment, the integration circuit 13 is used to amplify the fingerprint signal detected by the pixel array sensing circuit 12 . In this embodiment, the integration circuit 13 includes an operational amplifier 131 and a feedback loop 132 . The operational amplifier 131 includes a non-inverting input terminal 1311 , an inverting input terminal 1312 and an output terminal 1313 . The non-inverting input terminal 1311 is connected to the first reference voltage V _REF . The resistor 1218 is connected to the inverting input terminal 1312 through the second sub-switch φ23 of the second switch group. The output terminal 1313 is connected to the inverting input terminal 1312 through the feedback loop 132 .

In this embodiment, the feedback loop 132 includes a feedback capacitor C _FB , a third switch group and a fourth switch group. The third switch group includes a first sub-switch rst_a1, a second sub-switch rst_a2, and a third sub-switch rst_a3. The fourth switch group includes a first sub-switch rst_b1 and a second sub-switch rst_b2. The upper plate of the feedback capacitor C _FB is connected to the second reference voltage V _{DC_OS} through the first sub-switch rst_a1 of the third switch group. The lower plate of the feedback capacitor C _FB is connected to the power supply voltage VDD through the second sub-switch rst_a2 of the third switch group. The upper plate of the feedback capacitor C _FB is connected to the inverting input terminal 1312 through the first sub-switch rst_b1 of the fourth switch group. The lower plate of the feedback capacitor C _FB is connected to the output terminal 1313 through the second sub-switch rst_b2 of the fourth switch group. The inverting input terminal 1312 is also connected to the output terminal 1313 through the third sub-switch rst_a3 of the third switch group.

Please refer to FIG. 11 , which is a timing diagram of fingerprint collection performed by the pixel array sensing circuit 12 in an embodiment of the present application. The pixel array sensing circuit 12 provides a first timing control signal reset_a, a second timing control signal reset_b, a third timing control signal φ1 and a fourth timing control signal φ2. The first timing control signal reset_a and the second timing control signal reset_b are clock signals with a phase difference of 180°. The third timing control signal φ1 and the fourth timing control signal φ2 are non-overlapping clock signals with a phase difference of 180°.

The first timing control signal reset_a is used to control the opening and closing of the first sub-switch rst_a1 , the second sub-switch rst_a2 and the third sub-switch rst_a3 of the third switch group. The timings of switching on and off of the first sub-switch rst_a1 , the second sub-switch rst_a2 and the third sub-switch rst_a3 of the third switch group are exactly the same. The second timing control signal reset_b is used to control the opening and closing of the first sub-switch rst_b1 and the second sub-switch rst_b2 of the fourth switch group. The opening and closing timings of the first sub-switch rst_b1 and the second sub-switch rst_b2 of the fourth switch group are exactly the same. The third timing control signal φ1 is used to control the opening and closing of the first sub-switch φ11 , the second sub-switch φ12 and the third sub-switch φ13 of the first switch group. The opening and closing timings of the first sub-switch φ11 , the second sub-switch φ12 and the third sub-switch φ13 of the first switch group are the same. The fourth timing control signal φ2 is used to control the opening and closing of the first sub-switch φ21 , the second sub-switch φ22 and the third sub-switch φ23 of the second switch group. The timing of switching on and off of the first sub-switch φ21 , the second sub-switch φ22 and the third sub-switch φ23 of the second switch group is the same.

Below in conjunction with Fig. 10 and Fig. 11 specifically describe the working process of the fingerprint recognition system 10 of the present application Procedure. The working process includes the following stages.

(a) In the initial stage, the first timing control signal reset_a is at a high level, and the second timing control signal reset_b is at a low level. At this time, the first sub-switch rst_a1, the second sub-switch rst_a2, and the The three sub-switches rst_a3 are turned on at the same time, and the first sub-switch rst_b1 and the second sub-switch rst_b2 of the fourth switch group are turned off at the same time. The output terminal 1313 of the operational amplifier is connected to the inverting input terminal 1312 , and the operational amplifier 131 has a buffer structure, Vn=VREF. The upper plate of the feedback capacitor C _FB is connected to the second reference voltage V _{DC_OS} , the lower plate is connected to the power supply voltage VDD, and the voltage of the feedback capacitor C _FB is calculated according to the formula V _{CFB 1} = V _DD - V _{DC _ OS} , where V _CFB1 represents The voltage across the feedback capacitor C _FB . The charge of the feedback capacitor C _FB is calculated according to the formula Q _{CFB 1} = C _FB *( V _DD - V _{DC _ OS} ), where, C _FB is the capacitance of the feedback capacitor C _FB , and Q _CFB1 is the charge of the feedback capacitor C _FB , V _{DC_OS} is the second reference voltage.

(b) In the scanning phase, the first timing control signal reset_a is at low level, and the second timing control signal reset_b is at high level. At this time, the first sub-switch rst_a1, the second sub-switch rst_a2, and the third The sub-switch rst_a3 is turned off at the same time, and the first sub-switch rst_b1 and the second sub-switch rst_b2 of the fourth switch group are turned on at the same time. The upper plate of the feedback capacitor C _FB is connected to the inverting input terminal 1312 of the operational amplifier 131 , and the lower plate is connected to the output terminal 1313 of the operational amplifier 131 . The voltage of the feedback capacitor C _FB is calculated according to the formula V _{CFB 2} = V _OUT − V _REF , wherein V _OUT represents the output voltage of the output terminal 1313 of the operational amplifier 131 , and V _REF represents the first reference voltage. The charge of the feedback capacitor C _FB is calculated according to the formula Q _{CFB 2} = C _FB *( V _OUT - V _REF ).

Since the charge of the feedback capacitor C _FB does not change during the initial stage and the scanning stage, Q _{CFB 1} = Q _{CFB 2} , so the output voltage V OUT of the output terminal 1313 of the operational amplifier 131 is deduced V _OUT = V _REF + V _DD - V _{DC _ OS} . According to the charge conservation law, the charge of the feedback capacitor C _FB is calculated according to the formula Q _CFB = Q _{CFB 1} + Q _{CFB 2} = C _FB *( V _DD - V _{DC _ OS} )+ C _FB *( V _OUT - V _REF ).

(c) In the pre-charging stage, the ground terminal GND in the picture element array sensing circuit 12 is divided into a floating ground terminal NVSS and a ground terminal GND. Wherein, the voltage of the floating ground terminal NVSS is a preset negative voltage -VTX or zero, and the voltage of the ground terminal GND is zero. In this embodiment, the voltage of the floating ground terminal NVSS is controlled by the peripheral state control signal Tx. When the peripheral state control signal Tx=0, the floating ground terminal NVSS is connected to the ground terminal GND, and the voltage V of the floating ground terminal NVSS _NVSS =0; when the peripheral state control signal Tx=1, the floating ground terminal NVSS is connected to the preset negative voltage -VTX, and the voltage V _{NVSS of the floating ground terminal NVSS} =-VTX. When the graphic element array sensing circuit 12 collects fingerprint information, the peripheral state control signal TX=0, the floating ground terminal NVSS is connected to the ground terminal GND, the voltage V _{NVSS of the floating ground terminal NVSS} =0, the first switch group of the first switch group The sub-switch φ11 and the second sub-switch φ12 of the first switch group are turned off, φ13 of the first switch group is turned on, the first sub-switch φ21 of the second switch group and the second sub-switch φ22 of the second switch group are turned on at the same time, the second The third sub-switch φ23 of the two switch groups is turned off, the second metal layer 1212 is connected to the ground terminal GND, the first metal layer 1211 and the third metal layer 1213 are connected to the first reference voltage VREF at the same time, and the first metal layer 1211 is disconnected from the amplifier 131. On, the charge on the first metal layer 1211 is expressed as Q ₁ =( C _finger + C ₂ )× V _REF , where Q1 includes the first parasitic capacitance C _finger of the fingerprint signal.

=V _REF * C ₂。手指到第一金屬層1211的第一寄生電容C _finger 的兩端電壓(即第一參考電壓V_REF到接地端GND的壓降)表示為V _REF -V _TX ，故第一寄生電容C _finger 為

=(V _REF -V _TX )* C _finger 。第一金屬層1211到接地端GND的總寄生電容為C ₂+C _finger ，總寄生電容為C ₂+C _finger 的電荷量可表示為(V _REF -V _TX )* C _finger +V _REF * C ₂。第二開關組的第三子開關φ23導通之前，放大器131的反向輸入端1312的電荷量Q _CFB =C _FB *(V _DD -V _{DC_OS} )+C _FB *(V _OUT -V _REF )。第二開關組的第三子開關φ23導通後，總電荷量Q ₂=(V _REF -V _TX )* C _finger +V _REF * C ₂+(V _DD -V _{DC_OS} )* C _FB +(V _REF -V _OUT )* C _FB (d) In the charge transfer stage, when the peripheral state control signal Tx=1, the floating ground terminal NVSS is connected to the preset negative voltage -VTX, the voltage V _{NVSS of the floating ground terminal NVSS} = -VTX, the third sub-switch of the first switch group φ13 changes from on to off, the third sub-switch φ23 of the second switch group changes from off to on, the first sub-switch φ11 of the first switch group, the second sub-switch φ12 of the first switch group, the second switch Both the first sub-switch φ21 of the group and the second sub-switch φ22 of the second switch group remain unchanged. In addition, when the connection relationship between the floating ground terminal NVSS and the ground terminal GND is converted to the connection relationship between the floating ground terminal NVSS and the preset negative voltage -VTX, since the preset negative voltage -VTX is a negative voltage (generated by the external negative voltage generating circuit Generate), set -VTX=(-1)*VDD, the second sub-switch φ23 of the second switch group is turned on, and the inverting input terminal 1312 of the amplifier 131 is connected to the first sub-switch φ23 of the second switch group. The metal layer 1211, the output terminal 1313 of the amplifier 131 and the inverting input terminal 1312 are connected through the feedback capacitor C _FB to form a feedback structure. The voltage of the output terminal 1313 of the amplifier 131 is equal to the voltage of the non-inverting input terminal 1311 (ie, the first reference voltage V _REF ). The second sub-switch φ22 of the second switch group is turned on, and the third metal layer 1213 is connected to the first reference voltage V _REF . The voltage between the first metal layer 1211 and the second metal layer, that is, the voltage across the second capacitor 222 is the first reference voltage V _REF , and the second capacitor 222 has no charge transfer. The first sub-switch φ21 of the second switch group is in the conduction state, the second metal layer 1212 is connected to the preset negative voltage -VTX, the capacitance between the first metal layer 1211 and the floating ground terminal NVSS is the first capacitance 21, and the first reference voltage V _REF and the floating ground terminal NVSS are in the same voltage domain, so the voltage drop from the first reference voltage V _REF on the first capacitor 21 to the floating ground terminal NVSS is equal to V _REF , that is, the charge amount of the first capacitor 21

= V _REF * C ₂ . The voltage across the first parasitic capacitance C _finger from the finger to the first metal layer 1211 (that is, the voltage drop from the first reference voltage V _REF to the ground terminal GND) is expressed as V _REF - V _TX , so the first parasitic capacitance C _finger is

=( V _REF - V _TX )* C _finger . The total parasitic capacitance from the first metal layer 1211 to the ground terminal GND is C ₂ + C _finger , and the total parasitic capacitance is C ₂ + C _finger , and the charge amount of the finger can be expressed as ( V _REF - V _TX )* C _finger + V _REF * C ₂ . Before the third sub-switch φ23 of the second switch group is turned on, the charge amount Q _CFB of the inverting input terminal 1312 of the amplifier 131 = C _FB *( V _DD - V _{DC _ OS} ) + C _FB *( V _OUT - V _REF ) . After the third sub-switch φ23 of the second switch group is turned on, the total charge Q ₂ =( V _REF - V _TX )* C _finger + V _REF * C ₂ +( V _DD - V _{DC _ OS} )* C _FB +( V _REF - V _OUT )* C _FB

According to the principle of conservation of charge, Q ₁ = Q ₂

Then the output voltage of the output terminal 1313

由上式可以看到，輸出端1313的輸出電壓Vout僅與第一寄生電容C_finger、回饋電容C_FB、預設負電壓-Vtx有關，與圖元電路121的第一電容21、第二電容23均無關係。進行空掃時，第一寄生電容C _finger =0，因此V _{OUT_VIR} =V _DD -V _{DC_OS} +V _REF ，無論圖元電路121的表面面積大小如何，空掃的輸出Vout_vir均可以保持恒定，如此解決了指紋識別模組2的封裝層21為曲面或異形封裝的情況下，每一列的圖元電路121的第一金屬層1211的表面面積大小會隨封裝層 21的表面的弧度變化而變化而導致每列的圖元電路121的第一電容22的電容值是不相等，進而造成經過積分過後的信號量必然會過大或過小，超過模數轉換電路14的輸入動態範圍，導致指紋識別系統10無法正常工作的問題。 After N times of integration, the output voltage of the output terminal 1313 is

It can be seen from the above formula that the output voltage Vout of the output terminal 1313 is only related to the first parasitic capacitor C _finger , the feedback capacitor C _FB , and the preset negative voltage -Vtx, and is related to the first capacitor 21 and the second capacitor of the primitive circuit 121 23 are not related. During empty scanning, the first parasitic capacitance C _finger =0, so V _{OUT _ VIR} = V _DD - V _{DC _ OS} + V _REF , no matter how large the surface area of the primitive circuit 121 is, the empty scanning output Vout_vir can be maintained constant, thus solving the problem that the encapsulation layer 21 of the fingerprint identification module 2 is a curved surface or a special-shaped encapsulation, the surface area of the first metal layer 1211 of the graphic element circuit 121 of each column will change with the curvature of the surface of the encapsulation layer 21 The change causes the capacitance values of the first capacitors 22 of the graphic element circuits 121 in each column to be unequal, and the signal amount after integration will inevitably be too large or too small, exceeding the input dynamic range of the analog-to-digital conversion circuit 14, resulting in fingerprints. Identify problems with system 10 not functioning properly.

In this embodiment, the packaging layer 21 of the fingerprint recognition module 2 is a 2.5D curved surface or a 3D curved surface. The shape of the curved surface of the encapsulation layer 21 of the fingerprint recognition module 2 can be concave or sawtooth. In this embodiment, the shape of the fingerprint identification module 2 is strip, square, circle and other irregular shapes.

The entire graphic element array sensing circuit 12 and integrating circuit 13 in this embodiment are simple in structure, and the required power supply voltage V _DD and ground GND do not need special treatment, and the V _DD and GND of other modules of the compatible chip do not need ng Using a special process, it can be realized by a common CMOS process.

The sensitivity of the fingerprint signal sensed in this embodiment is high, and there is no need to increase the sensitivity by increasing the area of the sensing circuit of the picture element array. Compared with the general acquisition circuit, the area of the sensing circuit of the picture element array in this embodiment can be reduced. Save wafer cost.

In other implementation manners, the feedback capacitor C _FB of the amplifier 131 in the present application can be set in a variety of ways to suit the application of different external conditions.

In other embodiments, after the graphic element array sensing circuit 12 of the fingerprint identification system 10 performs one fingerprint sampling, the analog-to-digital conversion circuit 14 performs multiple analog-to-digital conversions; or after the graphic element array sensing circuit 12 performs multiple fingerprint sampling, The analog-to-digital conversion circuit 14 performs an analog-to-digital conversion; or after the graphic element array sensing circuit 12 performs multiple fingerprint samplings, the analog-to-digital conversion circuit 14 performs multiple analog-to-digital conversions and other different working modes to effectively increase the signal amount of the fingerprint .

The embodiment of the present application also provides a fingerprint chip, and the fingerprint chip includes crystal grains. The grains are provided as in the above embodiments. I won't repeat them here.

The embodiment of the present application also provides an electronic device, which includes the fingerprint chip provided in the above embodiment.

In summary, the present invention meets the requirements of an invention patent, and a patent application is filed according to law. However, the above description is only a preferred implementation mode of the present invention. For those who are familiar with the technology of this case, the equivalent modifications or changes made in accordance with the creative spirit of this case should be included in the scope of the following patent application.

21: Encapsulation layer

22: grain

23: PCB board

24:Flexible circuit board

212: Curved outer surface

Claims (12)

A fingerprint identification module, comprising a packaging layer and a die, the packaging layer covers the die, wherein the die contains a picture element array sensing circuit, and the picture element array sensing circuit includes a plurality of arrays distributed in a matrix A graphic element circuit, the graphic element circuit includes a first metal layer for detecting fingerprints, and the first metal layer is arranged on the side of the crystal grain facing the encapsulation layer, and the encapsulation layer has The arc-shaped outer surface, the distance from the arc-shaped outer surface of the packaging layer to the first metal layer of the graphic element circuit on each column of the graphic element array induction circuit is proportional to the arc of the arc-shaped outer surface of the packaging layer The linear ratio changes, and the surface area of the first metal layer of the graphic element circuit on each column of the graphic element array sensing circuit changes in linear proportion to the curvature of the arc-shaped outer surface of the packaging layer. The fingerprint identification module according to claim 1, wherein the distance d from the arc-shaped outer surface of the packaging layer to the first metal layer of the graphic element circuit on the n column of the graphic element array sensing circuit is equal to the The surface area s of the first metal layer of the picture element circuit on the n columns of the picture element array sensing circuit satisfies

, wherein, d1, d2...dn are the distances from the arc-shaped outer surface of the packaging layer to the first metal layer of the picture element circuit on the 1st, 2...n columns of the picture element array sensing circuit The distances; S1, S2...Sn are respectively the surface areas of the first metal layers in n columns on the sensing circuit of the graphic element array, and n is a positive integer. The fingerprint identification module as claimed in item 2, wherein the graphic element circuit further includes a second metal layer, a third metal layer, and a substrate layer, and the second metal layer and the third metal layer are arranged on the Between the first metal layer and the substrate layer, the projections of the second metal layer and the third metal layer on the substrate layer cover the projection of the first metal layer on the substrate layer, so that The first metal layer is isolated from the substrate layer, the first metal layer generates a fingerprint signal when a finger approaches, and the second metal layer and the third metal layer are overlapped or staggered. The fingerprint identification module as claimed in claim 3, wherein the fingerprint identification module further includes an integration circuit, the integration circuit is connected to the sensing circuit of the graphic element array, and is used to generate The fingerprint signal is amplified; the picture element array sensing circuit includes a first switch group and a second switch group, and the first switch group includes a first sub-switch, a second sub-switch, and a third sub-switch, and the second The switch group includes a first sub-switch, a second sub-switch, and a third sub-switch; the second metal layer is connected to the power supply voltage through the first sub-switch of the first switch group and connected to the power supply voltage through the second switch group The first sub-switch of the first switch group is connected to the floating ground terminal; the third metal layer is connected to the power supply voltage through the second sub-switch of the first switch group and through the second sub-switch of the second switch group connected to the first reference voltage; the first metal layer is connected to the first reference voltage through the third sub-switch of the first switch group and connected to the integration circuit through the third sub-switch of the second switch group . The fingerprint identification module as described in claim 4, wherein, when the peripheral state control signal Tx=0, the voltage VNVSS of the floating ground terminal=0, and when the peripheral state control signal Tx=1, the floating ground terminal is connected to A preset negative voltage, the voltage of the floating ground terminal VNVSS=-VTX, wherein -VTX is the preset negative voltage. The fingerprint identification module as claimed in item 5, wherein it includes a negative voltage output circuit for providing -VTX to the floating ground terminal. The fingerprint identification module as claimed in claim 4, wherein the integration circuit includes An operational amplifier and a feedback loop, the operational amplifier includes a non-inverting input terminal, an inverting input terminal and an output terminal, the non-inverting input terminal is connected to the first reference voltage, and adjusted by adjusting the first reference voltage The output voltage of the output terminal, the first metal layer is connected to the inverting input terminal through the third sub-switch of the second switch group, and the output terminal is connected to the inverting input terminal through the feedback loop. Connected to the input terminal; the feedback loop includes a feedback capacitor, a third switch group and a fourth switch group, the upper plate of the feedback capacitor is connected to the second reference voltage by the first sub-switch of the third switch group The lower plate of the feedback capacitor is connected to the power supply voltage through the second sub-switch of the third switch group, and the upper plate of the feedback capacitor is connected to the power supply voltage through the first sub-switch of the fourth switch group. The switch is connected to the reverse input terminal, the lower plate of the feedback capacitor is connected to the output terminal through the second sub-switch of the fourth switch group, and the reverse input terminal is connected to the output terminal through the third sub-switch. The third sub-switch of the switch group is connected to the output terminal. The fingerprint recognition module as claimed in item 7, wherein the graphic element array sensing circuit provides a first timing control signal, a second timing control signal, a third timing control signal and a fourth timing control signal, and the first A timing control signal and the second timing control signal are clock signals with a phase difference of 180°, and the third timing control signal φ1 and the fourth timing control signal φ2 are non-overlapping clock signals with a phase difference of 180° , the first timing control signal is used to control the opening and closing of the first sub-switch, the second sub-switch, and the third sub-switch of the third switch group, and the second timing control signal is used to control the The opening and closing of the first sub-switch and the second sub-switch of the fourth switch group, the third timing control signal is used to control the first sub-switch, the second sub-switch, the third sub-switch of the first switch group The opening and closing of the sub-switches, the fourth timing control signal is used to control the opening and closing of the first sub-switch, the second sub-switch and the third sub-switch of the second switch group. The fingerprint identification module as described in claim 8, wherein the working steps of the graphic element array sensing circuit are: (a) initial stage; the first timing control signal is at high level, and the second timing control signal is at low level Level, the first sub-switch, the second sub-switch, and the third sub-switch of the third switch group are turned on at the same time, and the first sub-switch and the second sub-switch of the fourth switch group are turned off at the same time; (b) Scanning phase: the first timing control signal is at low level, the second timing control signal is at high level, and the first sub-switch, the second sub-switch, and the third sub-switch of the third switch group simultaneously disconnected, the first sub-switch and the second sub-switch of the fourth switch group are turned on at the same time; (c) pre-charging stage: the peripheral state control signal TX=0, the floating ground terminal is connected to the ground terminal, and the voltage of the floating ground terminal V _NVSS =0, the first sub-switch of the first switch group and the second sub-switch of the first switch group are turned off, the third sub-switch of the first switch group is turned on, and the second sub-switch of the second switch group A sub-switch and the second sub-switch of the second switch group are turned on at the same time, the third sub-switch of the second switch group is turned off, the second metal layer is connected to the ground terminal, the first metal layer and the second The three metal layers are connected to the first reference voltage at the same time, and the first metal layer is disconnected from the amplifier; (d) in the charge transfer stage, the peripheral state control signal Tx=1, the floating ground terminal is connected to a preset negative voltage, and the The third sub-switch of the first switch group changes from on to off, the third sub-switch of the second switch group changes from off to on, the first sub-switch of the first switch group, the first sub-switch of the first switch group The state of the second sub-switch, the first sub-switch of the second switch group, and the second sub-switch of the second switch group remain unchanged, and the preset negative voltage -VTX=(-1)*VDD, wherein VDD is the power supply voltage, the The second sub-switch of the second switch group is turned on, the inverting input terminal of the amplifier is connected to the first metal layer through the third sub-switch of the second switch group, the output terminal of the amplifier and the The inverting input terminal is connected through the feedback capacitor. The fingerprint recognition module according to claim 1, wherein the fingerprint recognition module further includes a PCB board and a flexible circuit board, the PCB board is arranged on the flexible circuit board, and the crystal grain is arranged on the On the PCB, the encapsulation layer covers the die and the PCB. A fingerprint identification chip, comprising the fingerprint identification module provided in claim 1, wherein the surface area of the first metal layer varies linearly with the thickness of the encapsulation layer covering it. An electronic device, wherein the electronic device adopts the fingerprint recognition chip provided by claim 11.

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