TW202147651A - Resistive random acessory memory and method of manufacturing the same - Google Patents

Abstract

A resistive random accessory memory is provided. The resistive random accessory memory includes a substrate, a first dielectric layer, a bottom electrode, a resistance switching layer, an oxygen exchange layer, a barrier and a top electrode. The first dielectric is disposed on the substrate. The bottom electrode is disposed on the first dielectric layer. The resistance switching layer is disposed on the bottom electrode. The oxygen exchange layer is disposed on the resistance switching layer, wherein a contact area between the oxygen atom exchange layer and the resistance switching layer is smaller than a top surface area of the resistance switching layer. The barrier layer is disposed on the oxygen exchange layer. The top electrode is disposed on the barrier layer.

Description

Resistive random access memory and method of making the same

Embodiments of the present invention relate to a memory, and more particularly, to a resistive random access memory and a manufacturing method thereof.

Resistive random access memory (RRAM) has low power consumption, low operating voltage, short write and erase time, long durability, long data retention time, non-destructive read operation, multiple states (multi-state), the advantages of simple manufacturing and scalable nature, and thus become the emerging mainstream of non-volatile memory. The basic structure of a resistive random access memory includes a metal-insulator-metal (MIM) structure formed by stacking a bottom electrode, a resistance switching layer and a top electrode.

The state transition mechanism of the resistive random access memory is to utilize oxygen vacancies or the movement of oxygen atoms in the resistance switching layer or the oxygen atom exchange layer to form conductive filaments.

When a positive setting voltage is applied to the resistive random access memory, the oxygen atoms in the resistance switching layer move to the oxygen atom exchange layer, forming a conductive path and changing from a high resistance state to a low resistance state, this process is called setting (SET) operation. When a reverse reset voltage is applied to the resistive random access memory, the oxygen atoms in the oxygen atom exchange layer move to the resistance switching layer, so that the conductive path in the resistance switching layer is disconnected to change from a low resistance state to a high resistance state resistance state, this process is called reset (RESET) operation. The level of the resistance is controlled by the polarity of the applied voltage, so as to achieve the purpose of storing data.

Although existing resistive random access memories can roughly meet their original intended use, they have not yet fully met the requirements in every respect. For example, each time the memory is switched to a high resistance state, the oxygen atoms in the oxygen atom exchange layer do not necessarily fill the oxygen vacancies in the resistance transition layer, resulting in a large variability in the operating voltage of the memory, and the device Poor stability. Therefore, there is still a need for a novel resistive random access memory to improve the above problems.

The present invention provides a resistive random access memory and a manufacturing method thereof, which can effectively increase the exchange efficiency of oxygen atoms and increase the stability of the device.

According to some embodiments of the present invention, a resistive random access memory is provided. The resistive random access memory includes a substrate, a dielectric layer, a bottom electrode, a resistance switching layer, an oxygen atom exchange layer, a barrier layer and a top electrode. The aforementioned dielectric layer is disposed on the substrate. The aforementioned bottom electrode is disposed on the dielectric layer. The aforementioned resistance conversion layer is disposed on the bottom electrode. The aforementioned oxygen atom exchange layer is disposed on the resistance conversion layer, wherein the contact area between the oxygen atom exchange layer and the resistance conversion layer is smaller than the top surface area of the resistance conversion layer. The aforementioned barrier layer is disposed on the oxygen atom exchange layer. The aforementioned top electrode is disposed on the barrier layer.

According to some embodiments of the present invention, a method for manufacturing a resistive random access memory is provided. The method comprises: providing a substrate; forming a dielectric layer on the substrate; forming a bottom electrode on the dielectric layer; forming a resistance conversion layer on the bottom electrode; forming an oxygen atom exchange layer on the resistance conversion layer, wherein the oxygen atom exchange layer and the The contact area of the resistance switching layer is smaller than the top surface area of the resistance switching layer; a barrier layer is formed on the oxygen atom exchange layer; and a top electrode is formed on the barrier layer.

The present invention is more fully described with reference to the drawings of this embodiment. However, the present invention may be embodied in various forms and should not be limited to the embodiments described herein. The thicknesses of layers and regions in the drawings are exaggerated for clarity. The same or similar reference numerals denote the same or similar elements, and will not be repeated in the following paragraphs.

FIGS. 1-6 are cross-sectional views illustrating different manufacturing stages of the resistive random access memory 100 according to some embodiments of the present invention. Referring to FIG. 1, a substrate 102 is provided first. The substrate 102 may be a semiconductor substrate. The aforementioned semiconductor substrate can be elemental semiconductor, including silicon or germanium; compound semiconductor, including gallium nitride, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and/or indium antimonide; alloy semiconductor, including Silicon-germanium alloy, phosphorus-arsenide-gallium alloy, arsenic-aluminum-indium alloy, arsenic-aluminum-gallium alloy, arsenic-indium-gallium alloy, phosphorus-indium-gallium alloy and/or phosphorus-indium-arsenide-gallium alloy, or a combination of the above materials. In one embodiment, the substrate 102 may be a single crystal substrate, a multi-layer substrate, a gradient substrate, other suitable substrates, or a combination thereof. In addition, the substrate 102 can also be a silicon-on-insulator substrate, and the second semiconductor-on-dielectric layer can include a substrate, a buried oxide layer disposed on the substrate, or a semiconductor layer disposed on the buried oxide layer. Additionally, the substrate 102 may be formed to have active and/or passive elements and interconnect structures (eg, conductive layers, contacts, etc.) therein. Active elements may include transistors, diodes, etc., while passive elements may include resistors, capacitors, inductors, and the like.

Next, as shown in FIG. 1, by chemical vapor deposition (CVD) process, atomic layer deposition (ALD) process, physical vapor deposition (PVD) process, molecular The dielectric layer 104 is formed on the substrate 102 by a molecular beam deposition (MBD) process, plasma enhanced chemical vapor deposition (PECVD), or other suitable deposition process, or a combination thereof. In one embodiment, the dielectric layer 104 may be an oxide (eg, silicon oxide, silicon dioxide), a nitride, a low-k dielectric material (eg, a material with a lower dielectric constant than silicon dioxide), nitrogen Silicon oxide, phosphosilicate glass, borosilicate glass, borophosphosilicate glass, undoped silicate glass, fluorine doped silicate glass, organosilicate glass, SiO _x C _y , carbon silicon material or a combination of the above. In one embodiment, the thickness of the dielectric layer 104 is between 300 nm and 400 nm. In addition, conductive structures 105 are formed on the dielectric layer 104 for connecting the resistive random access memory to active devices and/or interconnect structures in the substrate 102 .

In one embodiment, the conductive structure 105 includes a liner 106 and a conductive material 108 . The material of the liner 106 may include conductive materials such as tungsten nitride, titanium nitride, tantalum nitride, or a combination thereof. The material of the conductive material 108 may include amorphous silicon, polysilicon, metal, metal nitride, conductive metal oxide, or a combination thereof. For example, the material of the conductive material 108 may include tungsten, copper, ochre nitride, ruthenium, silver, gold, rhodium, molybdenum, nickel, cobalt, cadmium, zinc, alloys or combinations thereof.

Next, a bottom electrode 110 is formed on the dielectric layer 104 . Methods of forming the bottom electrode 110 may include CVD, ALD, PVD, MBD, PECVD, other suitable deposition processes, or a combination of the foregoing. In one embodiment, the material of the bottom electrode 110 includes a conductive material, such as amorphous silicon, polysilicon, metal, metal nitride, conductive metal oxide, or a combination thereof. For example, the material of the bottom electrode 110 may include tungsten, copper, ochre nitride, ruthenium, silver, gold, rhodium, molybdenum, nickel, cobalt, cadmium, zinc, alloys or combinations thereof. In one embodiment, the thickness of the bottom electrode 110 is between 25 nm and 35 nm.

Next, the resistance switching layer 112 is formed on the bottom electrode 110 . Methods of forming the resistance switching layer 112 may include CVD, ALD, PVD, MBD, PECVD, other suitable deposition processes, or a combination of the foregoing. In one embodiment, the material of the resistance conversion layer 112 includes transition metal oxides, such as hafnium oxide, titanium oxide, tungsten oxide, tantalum oxide, zirconium oxide, or a combination thereof. In one embodiment, the thickness of the resistance conversion layer 112 is between 3 nm and 10 nm.

Next, an oxygen atom exchange layer 114 is formed on the resistance conversion layer 112 . Methods of forming the oxygen atom exchange layer 114 may include CVD, ALD, PVD, MBD, PECVD, other suitable deposition processes, or a combination of the foregoing. In one embodiment, the material of the oxygen atom exchange layer 114 includes aluminum, titanium, hafnium, tantalum, iridium, or a combination thereof.

Then, a hard mask 116 is formed on the oxygen atom exchange layer 114 . Methods of forming hard mask 116 may include CVD, ALD, PVD, MBD, PECVD, other suitable deposition processes, or a combination of the foregoing. In one embodiment, the material of the hard mask layer 116 may be nitride or tetraethoxysilane (TEOS).

Next, a photoresist material is formed on the top surface of the hard mask 116 by a suitable process such as spin coating, CVD, ALD, PVD, MBD, PECVD, other suitable deposition processes, or a combination of the foregoing, and then optical Exposure, post-exposure bake and development to remove part of the photoresist material and form a patterned photoresist layer that will serve as an etch mask for etching. Double or triple photoresist can be performed. The oxygen atom exchange layer 114 and hard mask 116 are then etched using any acceptable etching process, such as reactive ion etching, neutral beam etching, or a combination of the foregoing, to form patterned oxygen atoms corresponding to the conductive structures 105 Exchange layer 114 and hard mask 116 . Next, the patterned photoresist layer can be removed by etching or other suitable methods.

The patterned oxygen atom exchange layer 114 does not completely cover the resistance switching layer 112 . In other words, the contact area between the patterned oxygen atom exchange layer 114 and the resistance switching layer 112 is smaller than the top surface area of the resistance switching layer 112 . Since the oxygen atom exchange layer does not completely cover the top surface of the resistance conversion layer, when the memory switches from a high resistance state to a low resistance state, only the oxygen atoms in a certain area of the resistance conversion layer will move to the oxygen atom exchange layer, And the conductive path is only formed in a specific area. Therefore, when the memory is switched from a low-resistance state to a high-resistance state, oxygen atoms are more likely to backfill into the oxygen vacancies generated when the resistance switching layer is in the low-resistance state, thereby increasing the stability of the device.

The resistance conversion layer 112 has a left side wall and a right side wall opposite to the left side wall. In one embodiment, the oxygen atom exchange layer 114 is interposed between the left side wall and the right side wall. Specifically, the oxygen atom exchange layer 114 is not flush with the left and right side walls of the resistance conversion layer 112 . Since the oxygen atom exchange layer of the existing resistive random access memory is not between the sidewalls of the resistance switching layer, and the sidewalls of the resistance switching layer are easily affected by subsequent processes, during the transition from the low-resistance state to the high-resistance state , a part of the oxygen atoms will move from the oxygen atom exchange layer to the sidewall of the resistance conversion layer to generate dangling bonds, reducing the efficiency of the oxygen atom exchange. Therefore, when the oxygen atom exchange layer is between the left side wall and the right side wall, the oxygen atoms in the oxygen atom exchange layer will not move to the side wall of the resistance conversion layer, and no dangling bonds will be generated, thereby increasing the number of oxygen atoms exchange efficiency.

Please continue to refer to FIG. 1 , a dielectric layer 118 is formed on the resistance conversion layer 112 . Methods of forming the dielectric layer 118 may include CVD, ALD, PVD, MBD, PECVD, other suitable deposition processes, or a combination of the foregoing. In one embodiment, the material of the dielectric layer 118 is similar to the material of the dielectric layer 104 .

Next, referring to FIG. 2 , a planarization process such as chemical mechanical polishing is performed to remove part of the dielectric layer 118 and the hard mask 116 . Then, a nitride layer 120 is formed over the dielectric layer 118 and the hard mask 116 . Methods of forming the nitride layer 120 may include CVD, ALD, PVD, MBD, PECVD, other suitable deposition processes, or a combination of the foregoing. In one embodiment, the material of the nitride layer 120 includes silicon nitride, silicon carbon nitride, silicon carbide, or a combination thereof.

Next, referring to FIG. 3, a photoresist material is formed on top of the nitride layer 120 by a suitable process such as spin coating, CVD, ALD, PVD, MBD, PECVD, other suitable deposition processes, or a combination of the foregoing. Then, optical exposure, post-exposure bake and development are performed to remove part of the photoresist material and form a patterned photoresist layer, which will serve as an etch mask for etching. Double or triple photoresist can be performed. Then, the nitride layer 120, the dielectric layer 118, the resistance switching layer 112, and the bottom electrode 110 are etched to form the trenches 121 using any acceptable etching process, such as reactive ion etching, neutral beam etching, or a combination of the foregoing, to define individual memory cells 10 . Next, the patterned photoresist layer can be removed by etching or other suitable methods.

Since the resistance conversion layer and the oxygen atom exchange layer are etched in different processes, the sidewalls of the oxygen atom exchange layer can be prevented from being damaged.

Next, referring to FIG. 4 , a dielectric layer 122 is formed in the trench 121 and on the nitride layer 120 by CVD, ALD, PVD, MBD, PECVD, other suitable deposition processes, or a combination thereof. In one embodiment, the material of the dielectric layer 122 is similar to the material of the dielectric layer 104 .

Next, referring to FIG. 5 , the dielectric layer 122 , the nitride layer 120 and the dielectric layer 118 are etched by a similar process described above to form the opening O exposing the oxygen atom exchange layer 114 . In one embodiment, the dielectric layer 122, the nitride layer 120, and the dielectric layer 118 may be etched in the same process. In another embodiment, the dielectric layer 122, the nitride layer 120, and the dielectric layer 118 may be etched in different processes.

Next, referring to FIG. 6 , the barrier layer 124 is conformally formed in the opening O. Methods of forming barrier layer 124 may include CVD, ALD, PVD, MBD, PECVD, other suitable deposition processes, or a combination of the foregoing. The barrier layer 124 prevents oxygen atoms from diffusing to other unnecessary layers. In one embodiment, the material of the barrier layer 124 includes aluminum oxide, hafnium oxide, zirconium oxide, or a combination thereof.

Then, a top electrode 126 is formed on the barrier layer 124 . Methods of forming the top electrode 126 may include CVD, ALD, PVD, MBD, PECVD, other suitable deposition processes, or a combination of the foregoing. In one embodiment, the material of the top electrode 126 is similar to the material of the bottom electrode 110 . Specifically, the top electrode 126 covers the top surface and sidewalls of the oxygen atom exchange layer 114 . Since the top electrode covers both the top surface and the sidewall of the oxygen atom exchange layer, when a reverse reset voltage is applied to the resistive random access memory, the oxygen atoms in the oxygen atom exchange layer will move in a specific direction, thereby Increase the efficiency of oxygen atom exchange. Through the formation of the opening O, the top electrode 126 has the function of self-alignment.

A portion of the top electrode 126 extends onto the nitride layer 120 . Since the nitride layer 120 is between the dielectric layer 118 and a portion of the top electrode 126, it is better to control the shape of the opening O, thereby increasing the process margin.

The top electrode 126 has an upper portion and a lower portion, wherein the upper portion of the top electrode 126 is on the nitride layer 120 ; and the lower portion of the top electrode 126 is under the nitride layer 120 . The upper portion of the top electrode 126 serves as a wire for electrical connection with other components. Next, a planarization process is performed to make the top surfaces of the dielectric layer 122 , the barrier layer 124 and the top electrode 126 coplanar.

The resistive random access memory and its manufacturing method provided by the present invention have the following advantages: (1) Since the top electrode covers the top and sidewalls of the oxygen atom exchange layer at the same time, when the resistive random access memory is subjected to reverse The reset voltage of , will promote the oxygen atoms in the oxygen atom exchange layer to move in a specific direction, thereby increasing the efficiency of oxygen atom exchange. (2) By making the oxygen atom exchange layer incompletely covering the top surface of the resistance switching layer, when the memory switches from a high resistance state to a low resistance state, only a certain area of oxygen atoms in the resistance switching layer will move to oxygen atoms Atomic exchange layer, and the conductive path will only be formed in a specific area. Therefore, when the memory is switched from a low-resistance state to a high-resistance state, oxygen atoms are more likely to backfill into the oxygen vacancies generated when the resistance switching layer is in the low-resistance state, thereby increasing the stability of the device. (3) Since the oxygen atom exchange layer is between the left side wall and the right side wall, the oxygen atoms in the oxygen atom exchange layer will not move to the side wall of the resistance conversion layer, and no dangling bonds will be generated, thereby increasing the oxygen Efficiency of atomic swaps. (4) Since the resistance conversion layer and the oxygen atom exchange layer are etched in different processes, the sidewalls of the oxygen atom exchange layer can be prevented from being damaged. (5) Since the nitride layer is between the second dielectric layer and part of the top electrode, it is better to control the shape of the opening, thereby increasing the process margin.

Although the embodiments of the present invention and their advantages have been disclosed above, it should be understood that those skilled in the art can make changes, substitutions and modifications without departing from the spirit and scope of the present disclosure. Therefore, the protection scope of the present invention should be determined by the scope of the appended patent application.

10: Memory unit 100: Resistive random access memory 102: Substrate 104, 118, 122: Dielectric layer 105: Conductive Structure 106: Liner 108: Conductive Materials 110: Bottom electrode 112: Resistance conversion layer 114: Oxygen atom exchange layer 116:Hard Mask 120: Nitride layer 121: Groove 124: Barrier Layer 126: Top electrode O: open

In order to make the features and advantages of the embodiments of the present invention more obvious and easy to understand, some embodiments are listed below and described in detail with the accompanying drawings as follows: FIGS. 1-6 are cross-sectional views illustrating different manufacturing stages of a resistive random access memory according to some embodiments of the present invention.

10: Memory unit

100: Resistive random access memory

102: Substrate

104, 118, 122: Dielectric Layers

105: Conductive Structure

106: Liner

108: Conductive Materials

110: Bottom electrode

112: Resistance conversion layer

114: Oxygen atom exchange layer

120: Nitride layer

124: Barrier Layer

126: Top electrode

Claims (16)

A resistive random access memory, comprising: a base; a first dielectric layer disposed on the substrate; a bottom electrode disposed on the first dielectric layer; a resistance conversion layer disposed on the bottom electrode; an oxygen atom exchange layer, disposed on the resistance conversion layer, wherein a contact area between the oxygen atom exchange layer and the resistance conversion layer is smaller than a top surface area of the resistance conversion layer; a barrier layer disposed on the oxygen atom exchange layer; and A top electrode is disposed on the barrier layer. The resistive random access memory of claim 1, wherein the resistance conversion layer has a left sidewall and a right sidewall opposite to the left sidewall, and the oxygen atom exchange layer is interposed between the left sidewall and the right sidewall . The resistive random access memory of claim 2, wherein the oxygen atom exchange layer is not flush with the left side wall and the right side wall. The resistive random access memory of claim 1, wherein the barrier layer further covers a sidewall of the oxygen atom exchange layer. The resistive random access memory of claim 1, wherein the top electrode further covers a sidewall of the oxygen atom exchange layer. Such as the resistive random access memory of claim 1, further including: a second dielectric layer disposed on the resistance conversion layer; and A nitride layer is disposed on the second dielectric layer. The resistive random access memory of claim 6, wherein the second dielectric layer and the nitride layer have an opening exposing the oxygen atom exchange layer. The resistive random access memory of claim 6, wherein the top electrode extends over the nitride layer. A manufacturing method of a resistive random access memory, comprising: provide a base; forming a first dielectric layer on the substrate; forming a bottom electrode on the first dielectric layer; forming a resistance switching layer on the bottom electrode; forming an oxygen atom exchange layer on the resistance conversion layer, wherein a contact area between the oxygen atom exchange layer and the resistance conversion layer is smaller than a top surface area of the resistance conversion layer; forming a barrier layer on the oxygen atom exchange layer; and A top electrode is formed on the barrier layer. The method for manufacturing a resistive random access memory as claimed in claim 9, wherein the resistance conversion layer has a left side wall and a right side wall opposite to the left side wall, and the oxygen atom exchange layer is located between the left side wall and the right side between the walls. The manufacturing method of a resistive random access memory as claimed in claim 10, wherein the oxygen atom exchange layer is not flush with the left side wall and the right side wall. The manufacturing method of a resistive random access memory as claimed in claim 9, wherein the barrier layer further covers a sidewall of the oxygen atom exchange layer. The method for manufacturing a resistive random access memory as claimed in claim 9, wherein the top electrode further covers a sidewall of the oxygen atom exchange layer. The manufacturing method of the resistive random access memory as claimed in claim 9, further comprising: forming a second dielectric layer on the resistance switching layer; and A nitride layer is formed on the second dielectric layer. The manufacturing method of a resistive random access memory as claimed in claim 14, wherein the second dielectric layer and the nitride layer have an opening exposing the oxygen atom exchange layer. The method for manufacturing a resistive random access memory as claimed in claim 14, wherein the top electrode extends on the nitride layer.

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