TW202147568A - Three-dimensional memory arrays, and methods of forming the same - Google Patents

Abstract

An example apparatus includes a three-dimensional (3D) memory array including a sense line and a plurality of vertical stacks. Each respective on of the vertical stacks includes a different respective portion of the sense line, a first memory cell coupled to that portion of the sense line, a second memory cell coupled to that portion of the sense line, a first access line coupled to the first memory cell and a second access line coupled to the second memory cell. The first and second access lines are perpendicular to the sense line.

Description

Three-dimensional memory array and method of forming the same

The present invention relates generally to semiconductor devices and methods, and more particularly, to three-dimensional memory arrays and methods of forming the same.

Memory devices are typically provided as internal, semiconductor, integrated circuit and/or external removable devices in a computer or other electronic device. There are many different types of memory, including volatile and non-volatile memory. Volatile memory may require power to maintain its data, and may include random access memory (RAM), dynamic random access memory (DRAM), and synchronous dynamic random access memory (SDRAM), among others. Non-volatile memory provides persistent data by retaining stored data when no power is supplied, and can include NAND flash memory, NOR flash memory, read only memory (ROM), and resistive variable memory , such as phase change random access memory (PCRAM), resistive random access memory (RRAM), magnetic random access memory (MRAM) and programmable conductive memory.

Memory devices can be used as volatile and non-volatile memory for a wide range of electronic applications requiring high memory density, high reliability, and low power consumption. Non-volatile memory can be used in, for example, personal computers, portable memory sticks, solid-state drives (SSDs), digital cameras, cellular phones, portable music players (such as MP3 players), and movie players and other electronic devices.

Resistive variable memory devices can include resistive variable memory cells that can store data based on the resistance state of a storage element (eg, a memory element having a variable resistance). Thus, resistance variable memory cells can be programmed to store data corresponding to target data states by varying the resistance levels of the memory elements. can be achieved by applying an electric field source or energy source, such as a positive or negative electrical pulse (eg, a positive voltage pulse or a negative voltage pulse or a positive current pulse or a negative current pulse) to the cell (eg, to The resistance variable memory cell is programmed to a target data state (eg, corresponding to a particular resistance state) by using the memory element of the cell. The state of a resistance variable memory cell can be determined by sensing the current through the cell in response to an applied interrogation voltage. The sensed current, which varies based on the resistance level of the cell, can indicate the state of the cell.

Various memory arrays can be organized in a cross-point architecture, where memory cells (eg, variable resistance cells) are located at the intersections of first and second signal lines used to access the cells (eg, access lines and at the intersection of the sensing lines). Some resistance variable memory cells may include a selection element (eg, a diode) in series with a storage element (eg, a phase change material programmable to different resistance levels, a metal oxide material, and/or some other material) , transistors or other switching devices). Some resistive variable memory cells, which may be referred to as optional memory cells, may contain a single material that can serve as both the select element and the storage element of the memory cell.

The present invention includes apparatus for three-dimensional memory arrays and methods of forming the same. Embodiments include a sense line and a plurality of vertical stacks, wherein each respective one of the vertical stacks includes a different respective portion of the sense line; a first memory cell coupled to the other portion of the sense line; coupled to a second memory cell on the other part of the sense line; a first access line coupled to the first memory cell, wherein the first access line is orthogonal to the sense line; and a first access line coupled to the second memory cell Two access lines, wherein the second access line is orthogonal to the other part of the sensing lines.

Various types of memory devices are disclosed, including volatile and/or non-volatile memory cell arrays (eg, memory arrays), in which sense lines are formed to reduce cross tile differences and improve the Current delivery. As used herein, the term "cross block difference" may refer to voltage spikes in a memory cell caused by supplying an increased amount of current to different memory cells on the same sense line that are farther from a voltage source. In one example, current flowing from a voltage source to a particular memory cell may flow through other memory cells and other electrical components connected to the sense lines. Due to the resistance of these other cells and components along the sense lines and the connectors used to connect them to the sense lines, the magnitude of the current to the memory cells can be reduced. When a memory cell receives a reduced current, this reduction in current may make the magnitude of the current too small for the memory cell to perform its intended function (eg, program or sense as intended), which may Reduce the performance of the memory array.

Thus, a sense line that will allow current to flow to its intended memory cell while reducing the amount of current lost in transmission due to resistance of other memory cells and components along the sense line is beneficial. For example, reducing current consumption when flowing through the sense lines can ensure that the amount of current reaching a memory cell is sufficient for the cell to perform its intended function, and thus can increase the performance of the memory array. Example embodiments herein disclose a process for forming sense lines that will reduce the amount of current lost when flowing to a memory cell.

Forming sense lines as described herein can enable increased memory density in 3D memory arrays. As used herein, the term "memory density" can refer to the amount of information that can be stored in a given portion of a memory array. The more information that can be stored in a given portion of the memory array, the higher the density of the memory array. The ability to store more information in a given portion of a memory array may allow the memory array to store more data in less space. This may allow more memory to be stored in the memory device in which the memory array is formed. This may allow for the use of more space to incorporate and/or improve other aspects of memory devices.

The vertical portions of the sensing lines may be formed in a plurality of openings in the storage element material layer and the dielectric material layer. In some embodiments, the vertical sense line material may be formed in the plurality of openings using atomic layer deposition (ALD). In some embodiments, the sense line material may be an ALD compatible material, such as, but not limited to, titanium nitride (TiN) material.

Forming sense lines that will reduce the amount of loss and increase the density of the memory array when current flows through the sense lines may involve depositing sense line material in openings formed in the layers of dielectric material and storage element material. In some embodiments, the horizontal portions of the sense lines may connect the vertical portions of the sense lines at the top and/or bottom of the vertical stack.

In the following detailed description of the invention, reference is made to the accompanying drawings, which form a part hereof, and which show, by way of illustration, how one or more embodiments of the invention may be practiced. These embodiments are described in sufficient detail to allow those of ordinary skill in the art to practice the embodiments of the invention, and it is to be understood that other embodiments may be utilized and process, electrical and/or structural changes may be made without departing from the invention category. As used herein, "several" of something can refer to one or more of such things. For example, the vertical portions of the sensing line may refer to at least one vertical portion of the sensing line.

Figures herein follow a numbering convention in which the first digit corresponds to the figure number and the remaining digits identify the element or component in the figure. Similar elements or components between different figures can be identified by the use of similar digits. For example, reference numeral 102 may refer to element "02" in FIG. 1 and similar elements may be referred to as 202 in FIG. 2 . Similar elements within a figure may be referred to by a reference numeral followed by a hyphen followed by another number or letter. For example, 104-1 may refer to element 04-1 in FIG. 1, and 104-2 may refer to element 04-2, which may be similar to element 104-1. Such similar elements may be referred to generally without hyphens and additional numbers or letters. For example, elements 104 - 1 and 104 - 2 or other similar elements may be generally referred to as 104 .

1 illustrates a 3D view of an example 3D memory array 100 with sense lines formed in accordance with several embodiments of the present disclosure. For example, as shown in FIG. 1, array 100 includes: sense lines 101-1 and 101-2 (individually or collectively referred to as sense lines 101), vertical portions 102-1, 102-2, 102- of sense line 101 3, 102-4, 102-5, 102-6, 102-7 and 102-8 (individually or collectively referred to as vertical portion 102), horizontal portion 104-1, 104-2, 104-3 of sensing line 101 and 104-4 (individually or collectively the horizontal portion 104), access lines 106-1, 106-2, 106-3, 106-4, 106-5, 106-6, 106-7, 106-8, 106-9, 106-10, 106-11, and 106-12 (individually or collectively, access line 106), and memory cell 108-1 coupled to the vertical portion of sense line 101 and access line 106 and 108-2 (individually or collectively referred to as memory cells 108). However, embodiments of the present invention are not limited to a specific number of sense lines, access lines, or memory cells.

The memory array 100 may include sense lines 101 . The sense lines 101 may also be referred to as conductive lines, data lines, or bit lines. Current applied to device 100 can flow through sense line 101 and access line 106 to select memory cell 108 . Access lines 106 may also be referred to as conductive lines or word lines. As will be described further herein (eg, in conjunction with FIG. 4 ), each of the plurality of vertical portions 102 of the sense line 101 may be included in each of the plurality of vertical stacks. In some embodiments, the vertical portions 102 of the sense lines 101 may be connected by the horizontal portions 104 of the sense lines 101 at the top and bottom portions of the vertical stack.

In some embodiments, the horizontal portions 104-2 and 104-4 of the sense lines 101 at the bottom portion of the vertical stack may be formed in the substrate material of the 3D memory array. For example, the horizontal portions 104-2 and 104-4 of the sense line 101 may be formed before other semiconductor materials, such as dielectric materials and storage element materials, are formed on the substrate material. The vertical portion 102 of the sense line 101 can then be formed over the horizontal portions 104-2 and 104-4 of the sense line 101. The vertical portion 102 can be formed such that a vertical stack including the vertical portion 102 therein can be connected to the horizontal portions 104-2 and 104-4. In some embodiments, horizontal portions 104-1 and 104-3 may then be formed over vertical portion 102 and connected to the top portion of the vertical stack that includes vertical portion 102 therein. In some embodiments, the horizontal portions 104-1 and 104-3 of the sense line 101-1 at the top portion of the vertical stack may be the same as the horizontal portion 104 of the sense line 101-1 at the bottom portion of the vertical stack -2 and 104-4 alignment.

In some embodiments, activating (eg, applying current to) the horizontal portions 104 of the sense lines 101 at the bottom or top portion of the vertical stack can activate different respective portions of the sense lines 101 of each vertical stack . For example, activating the horizontal portion 104-1 of the sensing line 101 at the top portion of the vertical stack can activate the vertical portion 102 of the sensing line 101 in the vertical stack, and the sensing line 101 at the bottom portion of the vertical stack. Horizontal section 104-2. The vertical portion 102 of the sensing line 101 and the horizontal portion 104 of the sensing line 101 may be formed as a single sensing line. Current applied to any vertical portion 102 or horizontal portion 104 of the sense line 101 may be able to flow to other vertical portions 102 and horizontal portions 104 of the sense line 101 . Therefore, the current applied to any part of the sense line 101 to activate that part of the sense line 101 can also flow to other parts of the sense line 101 and also activate those parts.

Applying current to sense line 101 and access line 106 selects memory cells 108 coupled to sense line 101 and access line 106 that receive the current. Any memory cell 108 coupled to any portion of the sense line 101 will receive current applied to any portion of the sense line 101 . In order to select a memory cell, both the sense line 101 and the access line 106 to which the memory cell 108 is coupled must be enabled. Thus, the memory cells 108 coupled to the sense lines 101 can be selected by applying current to any portion of the sense lines 101 and applying current to the word lines 106 coupled to the memory cells 108 .

The sense lines 101 can provide benefits to the memory array, such as reducing cross-block differences and improving current delivery within the memory array. As stated above, cross block difference is a voltage spike in a memory cell caused by applying an increased amount of current to the memory cell on the same sense line that is farther from the voltage source. The amount of current is increased to overcome the parasitic resistance of memory cells further away from the voltage source. As used herein, the term "parasitic resistance" may refer to resistance in an electrical component that was not included in the original design and that is not desirable for the electrical component's intended purpose. Parasitic resistance is an inherent and unintended resistance of an electrical component due to the materials comprising the electrical component and the fabrication of the electrical component. The current applied to the sense line 101 or the access line 106 may decrease as it flows through the sense line 101 or the access line 106 . An increased amount of current can be applied to sense line 101 to compensate for the decrease in current flow to the intended memory cell so that the current is still sufficient to power the memory cell after the decrease. However, this can cause too much current to be applied to memory cells 108 that are closer than expected, and cause the closer memory cells 108 to experience voltage spikes. If the closer memory cell 108 is a phase change memory cell, this voltage spike would inadvertently cause the phase change memory cell to change state.

As used herein, the term "phase change memory" may refer to a type of RAM that stores data by changing the state of the material of the storage elements from which the memory device is made. In some embodiments, the storage element material may be a chalcogenide material. Examples of chalcogenide materials that can serve as storage element materials can include indium (In)-antimony (Sb)-tellurium (Te) (IST) materials such as In ₂ Sb ₂ Te ₅ , In ₁ Sb ₂ Te ₄ , In ₁ Sb ₄ Te ₇ etc., and germanium (Ge)-antimony (Sb)-tellurium (Te) (GST) materials such as Ge ₈ Sb ₅ Te ₈ , Ge ₂ Sb ₂ Te ₅ , Ge ₁ Sb ₂ Te ₄ , Ge _{1 Sb 4 Te 7, Ge 4 Sb} 4 Te 7 , etc., or other chalcogenide materials, including for example, the alloy phase does not change during operation (e.g., sulfur, selenium based chalcogenide alloy of). In addition, the chalcogenide material may include very small concentrations of other dopant materials. As used herein, a hyphenated chemical composition designation indicates an element included in a particular mixture or compound and is intended to represent all stoichiometry relative to the indicated element.

As used herein, the term "change state" refers to a storage element material changing its state from an amorphous state to a polycrystalline state, or from a polycrystalline state to an amorphous state. The storage element material can change its state in response to heat generated by an electrical current applied to the storage element material. Inadvertently changing the state of the storage element material can be detrimental to the memory array in which the storage element material is formed. For example, inadvertently changing the state of the storage element material can cause inaccurate readings. The two states of the storage element material can have different resistances. Circuits can be formed around the storage element material to read the resistance of the storage element material. Reading the resistance of the storage element material allows the circuit to detect whether a "1" or a "0" is stored on a memory cell formed from the storage element material. Inadvertently changing the state of a memory cell can cause the memory cell to erroneously store a "1" or a "0" when it was expected to store the opposite value. This can reduce the performance of the memory array because the memory array will store the opposite value to what is intended for the memory array to perform its intended function.

The vertical portion 102 and horizontal portion 104 of the sense line 101 can improve the flow of current through the memory array and reduce the voltage spikes described above. In some embodiments, the current applied to the sense line 101 may flow through the horizontal portion 104 of the sense line 101 connected at the bottom portion of the vertical stack. For example, if the vertical portion 102-1 of the sense line 101-1 is closer to the power source than the vertical portion 102-4 of the sense line 101-1, then current can flow to the sense line by flowing through the horizontal portion 104-2 Vertical portion 102-4 of 101-1. This can prevent current from flowing through various other regions of the memory array, and thus, reduces the amount of current that is lost when flowing to the vertical portion 102-4 of the sense line 101-1. The amount of current lost when flowing to the vertical portion 102-4 of the sense line 101-1 can be reduced because by flowing through the horizontal portion 104-2 of the sense line 101-1 rather than through the memory array Alternatively, current may not flow through various electrical components and lose current due to the parasitic resistance of those electrical components. The horizontal portion 104-2 of the sense line 101-1 may have parasitic resistance, but that parasitic resistance may be lower than the parasitic resistance of the electrical components on the alternate route through the memory cell. Therefore, flowing current through the horizontal portion 104-2 of the sense line 101-1 can reduce the amount of current lost as it flows through the memory array. This can improve the flow of current and avoid the voltage spikes discussed above. In some embodiments, current can flow through horizontal portion 104-1 of sense line 101-1 and experience improved current flow similar to that experienced by flowing through horizontal portion 104-2 of sense line 101-1 .

2 illustrates a 3D view of an example 3D memory array 210 with sense lines formed in accordance with several embodiments of the present disclosure. For example, as shown in FIG. 2, array 210 includes: sense lines 201-1 and 201-2 (individually or collectively referred to as sense lines 201), vertical portions 202-1, 202-2, 202- of sense lines 201 3, 202-4, 202-5, 202-6, 202-7 and 202-8 (individually or collectively referred to as the vertical portion 202), the horizontal portions 204-1 and 204-3 of the sensing line 201 (individually or collectively referred to as horizontal portion 204), access lines 206-1, 206-2, 206-3, 206-4, 206-5, 206-6, 206-7, 206-8, 206-9, 206-10, 206-11 and 206-12 (individually or collectively, access line 206), and memory cells 208-1 and 208-2 (individually or collectively) coupled to the vertical portion of sense line 201 and access line 206 Collectively referred to as memory unit 208). However, embodiments of the present invention are not limited to a specific number of sense lines, access lines, or memory cells.

The sensing line 201 may include a vertical portion 202 and a horizontal portion 204 . Each of the vertical portions 202 of the sense lines 201 may be located in different vertical stacks, as will be described further herein (eg, in conjunction with FIG. 4 ). The horizontal portion 204 of the sense line 201 may connect the vertical portion 202 of the sense line 201 at the top portion of the vertical stack. In some embodiments, the vertical portions 202 of the sense lines 201 connected to the horizontal portions 204 of the sense lines 201 at the top portion of the vertical stack may not be connected to the horizontal portions of the sense lines 201 at the bottom portion of the vertical stack (eg, horizontal portion 104-2 of sense line 102 of FIG. 1).

The horizontal portion 204 connecting the vertical portion 202 of the sense line 201 can benefit the memory array by reducing the cross-block difference and improving current flow in the memory array. In some embodiments, these benefits can be achieved because current can flow through the horizontal portion 204 of the sense line 201 . For example, if the power source is closer to the vertical portion 202-1 of the sense line 201-1 than the vertical portion 202-4 of the sense line 202-1, the power source may generate a current to be applied to the sense line 201-1. In some embodiments, current may flow from the bottom portion of the vertical portion 202-1 of the sense line 201-1 to the top portion of the vertical portion 202-1 of the sense line 201-1. Current can flow from the top portion of the vertical portion 202-1 of the sense line 201-1 to the top of the vertical portion 202-4 of the sense line 201-1 by flowing across the horizontal portion 204-1 of the sense line 201-1 part. That current can then flow to memory cell 208 coupled to vertical portion 202-4 of sense line 201-1.

The horizontal portion 204 of the sense line 201 can be beneficial to the memory device in which the current is applied. For example, allowing current to flow through the horizontal portion 204 of the sense line 201 may reduce (eg, prevent) cross-block differentials and improve current flow, in a manner similar to that previously described in connection with FIG. 1 for the sense line 101 .

3 illustrates a 3D view of an example 3D memory array 312 with sense lines formed in accordance with several embodiments of the present disclosure. For example, as shown in FIG. 3, array 312 includes: sense lines 301-1 and 301-2 (individually or collectively referred to as sense lines 301), vertical portions 302-1, 302-2, 302- of sense lines 301 3, 302-4, 302-5, 302-6 and 302-8 (individually or collectively referred to as vertical portion 302), horizontal portion 304-1, 304-2, 304-3 and 304-4 of sense line 301 (individually or collectively as horizontal portion 304), access lines 306-1, 306-2, 306-3, 306-4, 306-5, 306-6, 306-7, 306-8, 306-9, 306-10, 306-11, and 306-12 (individually or collectively, access line 306), and memory cells 308-1 and 308-2 coupled to the vertical portion of sense line 301 and access line 306 (individually or collectively referred to as memory cells 308). However, embodiments of the present invention are not limited to a specific number of sense lines, access lines, or memory cells.

The sensing line 301 may include a vertical portion 302 and a horizontal portion 304 . Each of the vertical portions 302 of the sense lines 301 may be included in a vertical stack. The horizontal portion 304 of the sense line 301 can be connected to the vertical portion 302 at the top portion of the vertical stack and at the bottom portion of the vertical stack. In some embodiments, the vertical portions 302 of the sense lines 301 connected to the horizontal portions 304 of the sense lines 301 at the bottom portion of the vertical stack may not be connected to the horizontal portions of the sense lines 301 at the top portion of the vertical stack 304. For example, as shown in FIG. 3, if the vertical portions 302-2 and 302-3 of the sensing line 301-1 can be connected at the bottom portion of the vertical stack, the vertical portions 302-2 and 302-3 cannot be Attached at the top portion of the vertical stack. In some embodiments, the vertical portions 302 of the sense lines 301 connected to the horizontal portions 304 of the sense lines 301 at the top portion of the vertical stack may not be connected to the horizontal portions of the sense lines 301 at the bottom portion of the vertical stack 304. For example, as shown in FIG. 3, if the vertical portions 302-1 and 302-2 of the sensing line 301-1 are connected to the horizontal portion 304-1 of the sensing line 301-1 at the top portion of the vertical stack, the sensing The vertical portions 302-1 and 302-2 of the sensing line 301-1 may not be connected to the horizontal portion 304-2 of the sensing line 301-1 nor at the bottom portion of the vertical stack. In some embodiments, the vertical portions 302 of the sense lines 301 may be connected to the horizontal portions 304 of the sense lines 301 at the top and bottom portions of some vertical stacks. For example, as shown in FIG. 3, the vertical portion 302-2 of the sense line 301-1 may be connected to the vertical portion 302-1 at the top portion of the vertical stack, and the vertical portion 302 of the sense line 301-1 -2 may be connected to vertical portion 302-3 at the bottom portion of the vertical stack.

The horizontal portion 304 connecting the vertical portion 302 of the sense line 301 can benefit the memory array by reducing cross block differences and improving current flow in the memory array. In some embodiments, these benefits can be achieved because current can flow through the horizontal portion 304 of the sense line 301 . For example, if the power source is closer to the vertical portion 302-1 of the sense line 301-1 than the vertical portion 302-4 of the sense line 301-1, the power source can generate a current applied to the sense line 301-1. In some embodiments, current may flow from the bottom of the vertical portion 302-1 of the sense line 301-1 to the top of the vertical portion 302-1 of the sense line 301-1. Current can flow from the top of the vertical portion 302-1 of the sense line 301-1 to the top of the vertical portion 302-2 of the sense line 301-1 by flowing across the horizontal portion 304-1 of the sense line 301-1. That current can flow from the top of the vertical portion 302-2 of the sense line 301-1 to the bottom of the vertical portion 302-2 of the sense line 301-1. Current can then flow from the bottom of the vertical portion 302-2 of the sense line 301-1 to the bottom of the vertical portion 302-3 of the sense line 301-1 through the horizontal portion 304-2 of the sense line 301-1. Current can continue to flow in this pattern until it reaches its intended memory cell. By flowing through the memory array as described above, the amount of current lost when flowing through the memory cells may be reduced compared to if the current does not flow through the memory array, as described above.

4 illustrates a cross-sectional side view of an example vertical stack 414 of 3D memory arrays in accordance with several embodiments of the present invention. As shown in FIG. 4, vertical stack 414 may include: vertical portion 402 of a sense line (eg, sense line 101 of FIG. 1); memory cells 408-1, 408-3, 408-4, 408-5 , 408-6 and 408-7 (individually or collectively referred to as memory cells 408) having electrodes 416-1, 416-2, 416-3, 416-4, 416-5, 416-6, 416-7 , 416-8, 416-9, 418-10, 416-11 and 416-12 (individually or collectively electrodes 416) and storage element materials 418-1, 418-2, 418-3, 418-4, 418 -5 and 418-6 (individually or collectively, storage element material 418); and access lines 406-1, 406-2, 406-7, 406-8, 406-13, and 406-14 (individually or collectively) for access line 406).

As shown in FIG. 4 , a plurality of memory cells 408 may be coupled to the vertical portion of the sense line 402 . Each memory cell 408 may include a storage element material 418 and two electrodes 416 on opposite sides of the storage element material. In some embodiments, the memory cells 408 may be coupled to opposite sides of the sense lines 402 . For example, memory cells 408-1 and 408-5 may be coupled to opposite sides of sense line 402, memory cells 408-3 and 408-6 may be coupled to opposite sides of sense line 402, and memory cells 408-4 and 408-7 may be coupled to opposite sides of the sense line 402. In some embodiments, each electrode 416 may have a width of ten nanometers (nm), and each storage element material 418 may have a width of 25 nm or 26 nm.

As shown in FIG. 4 , each of the memory cells 408 may be coupled to a different respective access line 406 . For example, memory cell 408-1 may be coupled to access line 406-1, memory cell 408-5 may be coupled to access line 406-2, and so on. Each access line 406 coupled to the memory cell 408 may be orthogonal to the sense line 402 . In some embodiments, each access line 406 may have a height of 50 nm and a width of 20 nm.

As stated above, a horizontal portion (eg, horizontal portion 104 of FIG. 1 ) of a sense line (eg, sense line 101 of FIG. 1 ) may be on top of vertical portion 402 of vertical stack 414 that includes the sense line and/or The vertical portion 402 of the sense line is connected at the bottom portion. For example, in some embodiments, the horizontal portion of the sense line may connect the vertical portion 402 of the sense line at the top of the vertical stack 414 rather than at the bottom. In some embodiments, the horizontal sense lines may connect the vertical portions 402 of the sense lines at the bottom of the vertical stack 414 rather than at the top. In some embodiments, horizontal sense lines may connect the vertical portions 402 of sense lines at both the top and bottom portions of the vertical stack 414 . In some embodiments, the horizontal portion of the sense line may connect the vertical portion 402 of the sense line to another vertical portion of the sense line at the top of the vertical stack 414, and the horizontal portion may connect the vertical portion of the sense line 402 is connected to yet another vertical portion of the sense lines at the bottom portion of the vertical stack. That is, the horizontal portion of the sense line can couple the single vertical portion 402 of the sense line to two separate vertical portions of the sense line, where the vertical portion 402 of the sense line can be connected to the vertical portion 402 at the top of the vertical stack 414 One of the other vertical portions of the sense lines, and connected to the other vertical portion of the sense lines at the bottom of the vertical stack 414 .

5 illustrates a top-down view of an example vertical stack 514 of a 3D memory array in accordance with several embodiments of the present invention. As shown in FIG. 5, vertical stacks 514-1, 514-2, and 514-3 (individually or collectively vertical stack 514) may include: vertical portions 502-1, 502-2, and 502 of sense lines -3 (individually or collectively vertical section 502); memory cells 508-1, 508-2, 508-5, 508-8, 508-10, and 508-11 (individually or collectively memory cells 508 ) with electrodes 516-1, 516-2, 516-7, 516-8, 516-13, 516-14, 516-15, 516-16, 516-17, 518-18, 516-19 and 516 -20 (individually or collectively, electrodes 516) and storage element materials 518-1, 518-4, 518-7, 518-8, 518-9, and 518-10 (individually or collectively, storage element materials 518); and access lines 506-1 and 506-2 (individually or collectively, access lines 506).

As shown in FIG. 5, each of the plurality of vertical stacks 514 may include a vertical portion 502 of the sense line, a plurality of memory cells 508 coupled to the vertical portion 502 of the sense line, and coupled to A plurality of access lines 506 of the memory cell 508 . In some embodiments, the vertical portion 502 of the sense line may have a width of 50 nm. Each memory cell 508 may include storage element material 518 coupled to a plurality of electrodes 516 . As shown in FIG. 5, each of the plurality of vertical stacks 514 may be formed adjacent to each other.

FIG. 5 shows a particular portion of a plurality of vertical stacks 514 . As previously shown in FIG. 4, each of the plurality of vertical stacks 514 may be coupled to memory cells 508 and access lines 506 at different portions of the vertical portion 502 of the sense line. As shown in FIG. 5 , memory cells 508 coupled to the same portion of each of the plurality of vertical portions 502 of the sense line may be coupled to the same access line 506 .

6A-6J illustrate cross-sectional views of processing steps associated with forming a 3D memory array in accordance with several embodiments of the present invention. The processes illustrated in Figures 6A-6J are shown at specific points in time corresponding to the processing activities of the 3D memory array formation process. For ease of illustration, other processing activities included in a particular 3D memory array formation sequence may be omitted.

FIG. 6A illustrates the formation (eg, deposition) of dielectric material 622 and storage element material 624 at time point 620 . In some embodiments, the storage element material 624 may be a chalcogenide material, and the dielectric material may be an oxide material, such as, but not limited to, aluminum oxide (AlOx). Dielectric material 622 and storage element material 624 may be formed over semiconductor material formed over substrate material, or may be formed over sense line material (not shown in Figure 6A). As illustrated in Figure 6A, dielectric material 622 and storage element material 624 may be alternately formed. In some embodiments, the dielectric material 622 and the storage element material 624 may be alternately formed repeatedly to form a stack of up to 64 layers of the dielectric material 622 and the storage element material 624 . In some embodiments, the horizontal portion of the sense line can be formed in the substrate material, and the dielectric material 622 and the storage element material 624 can be formed over the horizontal portion of the sense line material.

6B-6E illustrate the formation of the vertical portion of the sense line at time point 621 . In FIG. 6B , openings 625 may be formed in dielectric material 622 and storage element material 624 . In some embodiments, the openings may be formed using non-selective etching. In some embodiments, a plurality of openings similar to opening 625 may be formed.

In FIG. 6C, the storage element material 624 adjacent to the opening 625 may be removed using selective etching.

In FIG. 6D, electrode materials 626-1, 626-2, 626-3, and 626-4 (individually or collectively referred to as electrode material 626) may be formed on the portion from which storage element material 624 adjacent opening 625 is removed region, and then a portion of electrode material 626 may be removed.

In FIG. 6E , sense line material 628 may be formed in opening 625 . For example, sense line material 628 may be formed adjacent to electrode material 626 in opening 625 . In some embodiments, the sense line material 628 may be formed using atomic layer deposition (ALD). In some embodiments, access line material (eg, access line material 630 of FIG. 6H ) rather than sense line material 628 may be deposited in openings 625 .

6F-6I illustrate the formation of an access line at time point 630. FIG. In FIG. 6F , openings 627 may be formed in dielectric material 622 and storage element material 624 . In some embodiments, openings 627 may be formed using non-selective etching. Opening 627 may be formed adjacent to opening 625 . In some embodiments, a plurality of openings similar to opening 627 may be formed. In addition, as shown in FIG. 6F, selective etching may be used to further remove portions of storage element material 624 adjacent openings 627. In some embodiments, more storage element material 624 is removed adjacent opening 627 than adjacent opening 625 .

In FIG. 6G, electrode materials 626-5, 626-6, 626-7, and 626-8 (individually or collectively, electrode material 626) may be formed in regions from which portions of storage element material 624 are removed. A portion of electrode material 626 may be removed from the area adjacent to opening 627, as shown in Figure 6G.

In FIG. 6H , access line material 630 may be formed (eg, deposited) in openings 627 adjacent to electrode material 626 . For example, access line material 630 may fill the space from which electrode material 626 was removed, as shown in Figure 6H.

In Figure 6I, access line material 630 can be removed from opening 627 and remain in the space from which electrode material 626 was removed. After the access line material 630 is removed from the openings 627, a dielectric material 632 may be formed in the openings 627, as shown in FIG. 6I. In some embodiments, the dielectric material 622 and the dielectric material 632 may be different materials. In some embodiments, dielectric material 622 and dielectric material 632 may be the same material.

FIG. 6J illustrates the formation of the horizontal portion 629 of the sense line at time point 634 . In FIG. 6J , the horizontal portion 629 of the sense line may be formed over the vertical portion 628 of the sense line and the dielectric material 632 . In some embodiments, the vertical portion 628 of the sensing line and the horizontal portion 629 of the sensing line may be the same material. In some embodiments, the vertical portion 628 and the horizontal portion 629 of the sensing line may be of different materials. The horizontal portion 629 of the sense line may connect the vertical portion 628 of the sense line at the top of a vertical stack (eg, the vertical stack 414 of FIG. 4). In some embodiments, the access line material and the sense line material may be the same material. In some embodiments, the horizontal portion of the access line may connect the vertical portion of the access line formed in the opening at the top of the vertical stack instead of the sense line material.

7 is a functional block diagram of a computing system 756 including at least one memory array 770 formed in accordance with several embodiments of the present invention. The numbering convention used in connection with FIG. 7 does not follow the numbering convention and sequence applicable to the earlier presentations of FIGS. 1-6.

In the embodiment illustrated in FIG. 7, memory system 762 includes memory interface 764, a number of memory devices 768-1 . . . 768-N, and optionally coupled to memory interface 764 and memory devices Controller 766 of 768-1...768-N. Memory interface 764 may be used to communicate information between memory system 762 and another device, such as host 758 . Host 758 may include a processor (not shown). As used herein, a "processor" may be a number of processors, such as a parallel processing system, a number of co-processors, and the like. Example hosts may include or be implemented in laptops, personal computers, digital cameras, digital recording and playback devices, mobile phones, PDAs, memory card readers, interface hubs, and the like. This host 758 may be associated with manufacturing operations performed on semiconductor devices and/or SSDs.

In several embodiments, host 758 may be associated with (eg, include or be coupled to) host interface 760 . Host interface 760 may enable input of scaled preferences (eg, in numerically and/or structurally defined gradients) to define, eg, a memory device to be implemented by a processing device (not shown) (eg, as shown at 768 ) ) and/or the critical dimension (CD) of the final or intermediate structure of the memory cell array formed thereon (eg, as shown at 770). The array includes access devices having semiconductor structures, access lines, and dielectric materials formed in accordance with embodiments described herein. The scaled preferences may be provided to the host interface by entering several preferences stored by the host 758, entering preferences from another storage system (not shown), and/or entering preferences made by a user (eg, an operator) 760.

The memory interface 764 may be in the form of a standardized physical interface. For example, when memory system 762 is used for information (eg, data) storage in computing system 756, memory interface 764 may be a Serial Advanced Attachment Technology (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface or Universal Serial Bus (USB) interface, and other physical connectors and/or interfaces. In general, however, memory interface 764 may be provided for transferring control, addresses, information, scaled preferences, and/or between controller 766 of memory system 762 and host 758 (eg, via host interface 760 ) interface to other signals.

Controller 766 may include, for example, firmware and/or control circuitry (eg, hardware). Controller 766 is operably coupled to and/or included on the same physical device (eg, die) as one or more of memory devices 768-1 . . . 768-N. For example, controller 766 may be or may include an ASIC that is hardware operably coupled to circuitry (eg, a printed circuit board) including memory interface 764 and memory devices 768-1 . . . 768-N. Alternatively, controller 766 may be included on a separate physical device communicatively coupled to a physical device (eg, a die) including one or more of memory devices 768-1 . . . 768-N.

Controller 766 may communicate with memory devices 768-1 . . . 768-N to instruct operations to sense (eg, read), program (eg, write) and/or erase information, and for Manage other functions and/or operations of memory cells. Controller 766 may have circuits that may include several integrated circuits and/or discrete components. In several embodiments, circuitry in controller 766 may include control circuitry for controlling access across memory devices 768-1 . . . 768-N, and/or for providing host 758 and memory system 762 circuit between the translation layer.

The memory devices 768-1 . . . 768-N may include, for example, a number of memory arrays 770 (eg, arrays of volatile and/or non-volatile memory cells). For example, memory devices 768-1 . . . 768-N may include arrays of memory cells formed in accordance with embodiments disclosed herein. As will be appreciated, the memory cells in memory array 770 of memory devices 768-1 . . . 768-N may be in a RAM architecture (eg, DRAM, SRAM, SDRAM, FeRAM, MRAM, ReRAM, etc.), a flash architecture ( For example, NAND, NOR, etc.), three-dimensional (3D) RAM and/or flash memory cell architecture, or some other memory array architecture that includes pillars and adjacent trenches.

Memory device 768 may be formed on the same die. A memory device (eg, memory device 768-1) may include one or more arrays of memory cells 770 formed on a die. The memory device may include sensing circuits 772 and control circuits 774 associated with one or more arrays 770 or portions thereof formed on the die. Sensing circuit 772 may be used to determine (sensing) a particular data value (eg, 0 or 1) stored at a particular memory cell in a row of array 770 . In addition to instructing data values such as saving, erasing, etc., in response to commands from the host 758 and/or the host interface 760, the control circuit 774 can also be used to instruct the sensing circuit 772 to sense specific data values. Commands may be sent directly to control circuit 774 via memory interface 764 or to control circuit 774 via controller 766 .

The embodiment illustrated in FIG. 7 may include additional circuitry not illustrated so as not to obscure embodiments of the invention. For example, memory device 768 may include address circuitry to latch address signals provided over I/O connectors through the I/O circuitry. Address signals may be received and decoded by column and row decoders to access memory array 770 . It should be appreciated that the number of address input connectors may depend on the density and/or architecture of memory device 768 and/or memory array 770 .

In the foregoing detailed description of the present invention, reference is made to the accompanying drawings, which form a part hereof, and which show, by way of illustration, how one or more embodiments of the present invention may be practiced. These embodiments are described in sufficient detail to allow those of ordinary skill in the art to practice the embodiments of the invention, and it is to be understood that other embodiments may be utilized and process, electrical and/or structural changes may be made without departing from the invention category.

It is to be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, unless the context clearly dictates otherwise, the singular forms "a", "an" and "the" include both singular and plural referents, "a plurality", "at least one" and The same is true for "one or more" (eg, a number of memory arrays may refer to one or more memory arrays), although "plurality" is intended to refer to more than one of such things. Furthermore, the word "can/may" is used throughout this application in a permissive sense (ie, may, can) rather than a mandatory sense (ie, must). The term "including" and its derivatives means "including (but not limited to)". The term "coupled/coupling" means physically connected, directly or indirectly, and unless otherwise stated, may include, as appropriate to the context, the use of access instructions (eg, control signals, address signals, etc.) and data and/or a wireless connection for moving (transmitting) commands and data.

Although illustrated and described herein include semiconductor materials, underlying materials, structural materials, dielectric materials, capacitor materials, substrate materials, silicate materials, oxide materials, nitride materials, buffer materials, etch chemistries, etch processes, Example embodiments of various combinations and configurations of solvents, memory devices, memory cells, openings, and other materials and/or components related to semiconductor structure formation, although embodiments of the invention are not limited to those expressly recited herein combination. Semiconductor Materials, Substrate Materials, Structural Materials, Dielectric Materials, Capacitor Materials, Substrate Materials, Silicate Materials, Oxide Materials, Nitride Materials, Buffer Materials, Etching Chemicals, Etching Processes, Solvents, Memory Devices, Memory Other combinations and configurations of sidewalls of cells, openings and/or trenches associated with semiconductor structure formation than those disclosed herein are expressly included within the scope of the present invention.

Although specific embodiments have been illustrated and described herein, those of ordinary skill in the art will appreciate that configurations calculated to achieve the same results may be substituted for the specific embodiments shown. The present invention is intended to cover adaptations or variations of one or more embodiments of the present invention. It is to be understood that the foregoing description has been made in an illustrative fashion, and not a restrictive one. Combinations of the above embodiments and other embodiments not specifically described herein will be apparent to those skilled in the art upon reviewing the above description. The scope of one or more embodiments of the present invention includes other applications using the above structures and processes. Therefore, the scope of one or more embodiments of the invention should be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.

In the foregoing embodiments, for the purpose of streamlining the disclosure, some features were grouped together in a single embodiment. This method of the invention should not be interpreted as reflecting an intention that the disclosed embodiments of the invention must employ more features than are expressly recited in each claim. Rather, as reflected in the following claims, inventive subject matter resides in less than all features of a single disclosed embodiment. Thus, the following claims are hereby incorporated into the Embodiments, with each claim standing on its own as a separate example.

100: Three-dimensional (3D) memory arrays, devices 101-1: Sensing line 101-2: Sensing line 102-1: Vertical Section 102-2: Vertical Section 102-3: Vertical Section 102-4: Vertical Section 102-5: Vertical Section 102-6: Vertical Section 102-7: Vertical Section 102-8: Vertical Section 104-1: Horizontal Section 104-2: Horizontal Section 104-3: Horizontal Section 104-4: Horizontal Section 106-1: Access Line 106-2: Access Line 106-3: Access Line 106-4: Access Line 106-5: Access Line 106-6: Access Line 106-7: Access Line 106-8: Access Line 106-9: Access Line 106-10: Access Line 106-11: Access Line 106-12: Access Line 108-1: Memory Cell 108-2: Memory Cell 201-1: Sensing line 201-2: Sensing line 202-1: Vertical Section 202-2: Vertical Section 202-3: Vertical Section 202-4: Vertical Section 202-5: Vertical Section 202-6: Vertical Section 202-7: Vertical Section 202-8: Vertical Section 204-1: Horizontal Section 204-3: Horizontal Section 206-1: Access Line 206-2: Access Line 206-3: Access Line 206-4: Access Line 206-5: Access Line 206-6: Access Line 206-7: Access Line 206-8: Access Line 206-9: Access Line 206-10: Access Line 206-11: Access Line 206-12: Access Line 208-1: Memory Cell 208-2: Memory Cell 210: 3D Memory Array 301-1: Sensing line 301-2: Sensing line 302-1: Vertical Section 302-2: Vertical Section 302-3: Vertical Section 302-4: Vertical Section 302-5: Vertical Section 302-6: Vertical Section 302-8: Vertical Section 304-1: Horizontal Section 304-2: Horizontal Section 304-3: Horizontal Section 304-4: Horizontal Section 306-1: Access Line 306-2: Access Line 306-3: Access Line 306-4: Access Line 306-5: Access Line 306-6: Access Line 306-7: Access Line 306-8: Access Line 306-9: Access Line 306-10: Access Line 306-11: Access Line 306-12: Access Line 308-1: Memory Cell 308-2: Memory Cell 312: 3D Memory Array 402: Vertical Section, Sensing Line 406-1: Access Line 406-2: Access Line 406-7: Access Line 406-8: Access Line 406-13: Access Line 406-14: Access Line 408-1: Memory Cell 408-3: Memory Cell 408-4: Memory Cell 408-5: Memory Cell 408-6: Memory Cell 408-7: Memory Cell 414: vertical stack 416-1: Electrodes 416-2: Electrodes 416-3: Electrodes 416-4: Electrodes 416-5: Electrodes 416-6: Electrodes 416-7: Electrodes 416-8: Electrodes 416-9: Electrodes 418-10: Electrodes 416-11: Electrodes 416-12: Electrodes 418-1: Storage Element Materials 418-2: Storage Element Materials 418-3: Storage Element Materials 418-4: Storage Element Materials 418-5: Storage Element Materials 418-6: Storage Element Materials 502-1: Vertical Section 502-2: Vertical Section 502-3: Vertical Section 506-1: Access Line 506-2: Access Line 508-1: Memory Cell 508-2: Memory Cell 508-5: Memory Cell 508-8: Memory Cell 508-10: Memory Cell 508-11: Memory Cell 514: vertical stack 514-1: Vertical stacking 514-2: Vertical Stack 514-3: Vertical stacking 516-1: Electrodes 516-2: Electrodes 516-7: Electrodes 516-8: Electrodes 516-13: Electrodes 516-14: Electrodes 516-15: Electrodes 516-16: Electrodes 516-17: Electrodes 518-18: Electrodes 516-19: Electrodes 516-20: Electrodes 518-1: Storage Element Materials 518-4: Storage Element Materials 518-7: Storage Element Materials 518-8: Storage Element Materials 518-9: Storage Element Materials 518-10: Storage Element Materials 620: time point 621: time point 622: Dielectric Materials 624: Storage element material 625: Opening 626-1: Electrode Materials 626-2: Electrode Materials 626-3: Electrode Materials 626-4: Electrode Materials 626-5: Electrode Materials 626-6: Electrode Materials 626-7: Electrode Materials 626-8: Electrode Materials 627: Opening 628: Sensing wire material 629: Horizontal Section 630: Access Line Materials, Time Points 632: Dielectric Materials 634: time point 756: Computing Systems 758: Host 760:Host Interface 762: Memory System 764: Memory interface 766: Controller 768-1-768-N: Memory Devices 770: Memory Array 772: Sensing circuit 774: Control circuit

1 illustrates a 3D view of an example three-dimensional (3D) memory array with sense lines formed in accordance with several embodiments of the present disclosure.

2 illustrates a 3D view of another example three-dimensional (3D) memory array with sense lines formed in accordance with several embodiments of the present disclosure.

3 illustrates a 3D view of another example three-dimensional (3D) memory array with sense lines formed in accordance with several embodiments of the present disclosure.

4 illustrates a cross-sectional side view of an example vertical stack of 3D memory arrays in accordance with several embodiments of the present disclosure.

5 illustrates a top-down view of an example vertical stacking of a 3D memory array in accordance with several embodiments of the present disclosure.

6A-6J illustrate cross-sectional views of processing steps associated with forming a 3D memory array in accordance with several embodiments of the present invention.

7 is a functional block diagram of a computing system including at least one memory array formed in accordance with several embodiments of the present invention.

100: Three-dimensional (3D) memory arrays, devices

101-1: Sensing line

101-2: Sensing line

102-1: Vertical Section

102-2: Vertical Section

102-3: Vertical Section

102-4: Vertical Section

102-5: Vertical Section

102-6: Vertical Section

102-7: Vertical Section

102-8: Vertical Section

104-1: Horizontal Section

104-2: Horizontal Section

104-3: Horizontal Section

104-4: Horizontal Section

106-1: Access Line

106-2: Access Line

106-3: Access Line

106-4: Access Line

106-5: Access Line

106-6: Access Line

106-7: Access Line

106-8: Access Line

106-9: Access Line

106-10: Access Line

106-11: Access Line

106-12: Access Line

108-1: Memory Cell

108-2: Memory Cell

Claims (20)

A device comprising: A three-dimensional (3D) memory array comprising: a sensing line; and a plurality of vertical stacks, wherein each respective one of the vertical stacks includes: a different portion of the sense line; a first memory unit coupled to the other part of the sensing line; a second memory unit coupled to the other part of the sensing line; a first access line coupled to the first memory cell, wherein the first access line is orthogonal to the sense line; and A second access line coupled to the second memory cell, wherein the second access line is orthogonal to that portion of the sensing line. The equipment of claim 1, wherein: The first memory cell and the second memory cell each include a storage element material and a plurality of electrodes; and The storage element material is a chalcogenide material. The apparatus of any one of claims 1 to 2, wherein each of the vertical stacks comprises: a third memory unit coupled to the other part of the sensing line; a fourth memory unit coupled to the other part of the sensing line; a third access line coupled to the third memory cell, wherein the third access line is orthogonal to that portion of the sensing line; and A fourth access line is coupled to the fourth memory cell, wherein the fourth access line is orthogonal to that portion of the sensing line. The apparatus of any one of claims 1 to 2, wherein the different respective portions of the sensing line are connected by a horizontal portion of the sensing line at a top portion of the vertical stacks. The apparatus of any one of claims 1 to 2, wherein the different respective portions of the sensing line are connected by a horizontal portion of the sensing line at a bottom portion of the vertical stacks. A device comprising: A three-dimensional (3D) memory array comprising: a sensing line; and a plurality of vertical stacks, wherein each respective one of the vertical stacks includes: A different respective portion of the sensing line, wherein the different respective portions of the sensing line are at a top portion of the vertical stacks and a bottom portion of the vertical stacks by a horizontal portion of the sensing line connect; a first memory cell and a second memory cell coupled to opposite sides of the respective portion of the sense line; and A first access line and a second access line are coupled to the first memory cell and the second memory cell, respectively, wherein the first access line and the second access line are orthogonal to the The other part of the sensing line. 6. The apparatus of claim 6, wherein the horizontal portion of the sense lines at the bottom portion of the vertical stacks is formed in a substrate material of the 3D memory array. The apparatus of any one of claims 6 to 7, wherein the horizontal portion of the sensing line at the top portion of the vertical stacks and the sensing line at the bottom portion of the vertical stacks The horizontal portion is aligned. The apparatus of any one of claims 6 to 7, wherein activating the horizontal portion of the sensing line at the bottom portion or the top portion of the vertical stacks activates the sensing line of each vertical stack and so on for different parts. A device comprising: A three-dimensional (3D) crosspoint memory array comprising: a sensing line; and a plurality of vertical stacks, wherein each respective one of the vertical stacks includes: A different respective portion of the sense line, wherein the different respective portions of the sense line of some vertical stacks are connected to a horizontal portion of the sense line at a top portion of the vertical stack, and other vertical stacks are connected to a horizontal portion of the sense line the different respective portions of the sense lines of the vertical stack are connected to a horizontal portion of the sense lines at a bottom portion of the vertical stacks; a first memory cell and a second memory cell coupled to opposite sides of their respective portions of the bit line; and A first access line and a second access line are coupled to the first memory cell and the second memory cell, respectively, wherein the first access line and the second access line are orthogonal to the The other part of the sensing line. The apparatus of claim 10, wherein: The portions of the sense line connected to the horizontal portion of the sense line at the top portion of the vertical stacks are not connected to the horizontal portion of the sense line at the bottom portion of the vertical stacks part; and The portions of the sense line connected to the horizontal portion of the sense line at the bottom portion of the vertical stacks are not connected to the horizontal portion of the sense line at the top portion of the vertical stacks part. The apparatus of claim 10, wherein the different respective portions of the sense lines of some vertical stacks are connected to the horizontal portion of the sense lines at the top portion and the bottom portion of their vertical stacks. A method that includes: forming a first dielectric material and a storage element material over a semiconductor material; forming a first plurality of openings in the first dielectric material and the storage element material; removing portions of the storage element material adjacent the first plurality of openings; forming a first electrode material in an area from which the portions of the storage element material are removed; forming a sensing line material in the first plurality of openings adjacent to the first electrode material; forming a second plurality of openings in the first dielectric material and the storage element material; removing portions of the storage element material adjacent the second plurality of openings; forming a second electrode material in an area from which the portions of the storage element material adjacent the second plurality of openings are removed; forming an access line material in the second plurality of openings adjacent to the second electrode material; removing a portion of the access line material from the second plurality of openings; forming a second dielectric material in an area from which the portion of the access line material was removed; and A horizontal sensing line material is formed over the sensing line material to connect the sensing line material formed in the first plurality of openings. The method of claim 13, further comprising alternately forming the first dielectric material and the storage element material. The method of any of claims 13-14, further comprising removing more storage element material adjacent the second plurality of openings than storage element material adjacent the first plurality of openings. The method of claim 15, further comprising removing a portion of the first electrode material and the second electrode material. The method of any one of claims 13-14, further comprising forming the second plurality of openings adjacent to the first plurality of openings. A method that includes: forming a first horizontal sensing line material in a substrate material; forming a first dielectric material and a storage element material over the horizontal sensing line material; forming a first plurality of openings in the first dielectric material and the storage element material; removing portions of the storage element material adjacent the first plurality of openings; forming a first electrode material in an area from which the storage element material was removed; forming a sensing line material in the first plurality of openings; forming a second plurality of openings in the first dielectric material and the storage element material; removing portions of the storage element material adjacent the second plurality of openings; forming a second electrode material in an area from which the portions of the storage element material adjacent the second plurality of openings are removed; forming an access line material in the second plurality of openings adjacent to the second electrode material; removing a portion of the access line material from the second plurality of openings; forming a second dielectric material in an area from which the access line material was removed; and A second horizontal sensing line material is formed over the sensing line material to connect the sensing line material formed in the first plurality of openings. The method of claim 18, further comprising forming the second dielectric material in the second plurality of openings. The method of claim 18, further comprising: forming the access line material in the first plurality of openings and forming the sense line material in the second plurality of openings; and A horizontal access line material is formed over the access line material to connect the access line material formed in the first plurality of openings.

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