TW202145697A - Resonant switching power converter - Google Patents

Abstract

The present invention provides a resonant switching power converter including: a plurality of capacitors; a plurality of switches; at least one charging inductor; at least one discharging inductor; a controller configured to operably generate a charging operation signal and at least one discharging operation signal; and at least one zero current detection circuit configured to operably detect a charging resonant current flowing through the charging inductor during a charging process and/or detect a discharging resonant current flowing through the discharging inductor during a discharging process, the zero current detection circuit correspondingly generates at least one zero current detection signal to the controller when detecting that the charging resonant current and/or the discharging resonant current is zero respectively; wherein the controller determines start time points and end time points of the charging process and the at least one discharging process according to the at least one zero current detecting signal correspondingly.

Description

Resonant Switching Power Converters

The present invention relates to a resonant switching power converter, in particular, to a resonant switching power converter that uses detecting zero current to determine the switching time point.

FIG. 1 shows a conventional power converter. During the charging operation, the switches Q1, Q3, Q5, Q8, and Q9 are turned on, and the switches Q2, Q4, Q6, Q7, and Q10 are turned off, so that the capacitor C1 is connected in series with the inductor L1 between the input voltage VIN and the output voltage VOUT, and The capacitor C2 is connected in series with the capacitor C3 and the inductor L2 between the ground potential and the output voltage VOUT. During the discharge operation, the switches Q2, Q4, Q6, Q7, and Q10 are turned on, and the switches Q1, Q3, Q5, Q8, and Q9 are turned off, so that the inductor L1 is connected in series with the capacitor C1 and the capacitor C2 between the ground potential and the output voltage VOUT. , and the inductor L2 is connected in series with the capacitor C3 between the ground potential and the output voltage VOUT. The capacitor of the conventional power converter needs to withstand higher rated voltage, for example, the DC bias voltage of capacitor C1 is 3 times the output voltage Vc1=3VOUT, the DC bias voltage of capacitor C2 is 2 times the output voltage Vc2=2VOUT, The DC bias voltage of the capacitor C3 is equivalent to the output voltage Vc3=VOUT. Because the DC bias voltage of the capacitor is relatively high, the conventional power converter needs to use a capacitor with a larger volume. In addition, the capacitance value of the capacitor usually decreases as the DC bias voltage increases. When the input voltage range is between 36V and 76V, the DC bias voltage range of capacitor C1 will be between 27V and 57V. The variation range of the bias voltage is wide, so the capacitance value of the conventional power converter varies considerably, and the resonant frequency also varies with the variation of the capacitance. This causes large switching power losses and requires complex control to change the power conversion efficiency. Furthermore, the voltage conversion ratio of the input voltage VIN to the output voltage VOUT of the conventional power converter can only be 4:1 or 2:1, and the voltage conversion ratio of 3:1 cannot be achieved. FIG. 2 shows an example of the capacitance value of the capacitor changing with the DC bias. The capacitance value decreases by 70% when the DC bias is increased to 50V.

In view of this, the present invention proposes an innovative power converter aiming at the above-mentioned deficiencies of the prior art.

In one aspect, the present invention provides a resonant switching power converter for converting an input voltage into an output voltage, the resonant switching power converter comprising: a complex capacitor; a complex switch, which is correspondingly coupled to the complex capacitor ; at least one charging inductance, correspondingly connected in series with at least one of the complex capacitors; at least one discharging inductance, correspondingly connected in series with at least one of the complex capacitors; a controller for generating a charging operation signal with at least one of the complex capacitors a discharge operation signal corresponding to a charging process and at least one discharging process respectively, and operating the corresponding switches to switch the electrical connection relationship of the corresponding capacitor; and at least one zero current detection circuit for the Detecting a charging resonant current flowing through the at least one charging inductor during the charging process and/or detecting at least one discharging resonant current flowing through the at least one discharging inductor during the at least one discharging process, when the at least one zero current is detected When the detection circuit detects that the charging resonant current and/or the at least one discharging resonant current is zero, at least one zero current detection signal is correspondingly generated to the controller; wherein the charging operation signal and the at least one discharging operation signal are respectively Each is switched to a conduction level for a conduction period, and the plurality of conduction periods do not overlap each other, so that the charging process and the at least one discharging process do not overlap each other; wherein, in the charging process, the controller uses the The charging operation signal controls the switching of the plurality of switches, so that the plurality of capacitors and the at least one charging inductor are connected in series between the input voltage and the output voltage to form a charging path; wherein, in the at least one discharging process, the The controller controls the switching of the plurality of switches through the at least one discharge operation signal, so that each of the capacitors and the corresponding discharge inductance are connected in series between the output voltage and a ground potential to form a plurality of discharge paths simultaneously or alternately; wherein , the controller determines the respective start time and end time of the charging process and the at least one discharging process according to the at least one zero-current detection signal; wherein, the charging process and the at least one discharging process are repeatedly and staggered in sequence, to convert the input voltage to the output voltage.

In one embodiment, the controller further determines the respective start time and end time of the charging process and the at least one discharging process according to the charging operation signal and/or the at least one discharging operation signal.

In one embodiment, the at least one zero current detection circuit includes a current sensing circuit for sensing the charging resonant current during the charging process or sensing the at least one discharging resonant current during the at least one discharging process to generate a current sensing signal; and a comparator for comparing the current sensing signal with a reference signal to generate the at least one zero current sensing signal.

In one embodiment, the resonant switching power converter further includes a plurality of switch drivers, which are respectively coupled between the controller and the corresponding switch, and are used for the corresponding charging operation signal or the corresponding discharging operation signal. , and control the complex switches respectively.

In one embodiment, the controller includes: a logic circuit, coupled to the at least one zero current detection circuit, for the at least one zero current detection signal and the charging operation signal and/or the at least one discharging an operation signal for generating a charging judging signal and a discharging judging signal; and a decision circuit coupled to the logic circuit for generating the charging operating signal and the at least one discharging operation according to the charging judging signal and the discharging judging signal The signal is used to determine the respective start time point and end time point of the charging process and the at least one discharging process.

In one embodiment, the controller further includes a delay circuit, coupled between the logic circuit and the decision circuit, for delaying the charging process and/or the starting point of the at least one discharging process by a delay time.

In one embodiment, the charging determination signal is used to determine a start time point of the charging process and an end time point of the at least one discharge process.

In one embodiment, the logic circuit performs and logic operation on the at least one zero-current detection signal and an inversion signal of the charging operation signal to generate the charging determination signal.

In one embodiment, the determination circuit includes a first latch circuit for setting the charging operation signal according to the charging determination signal, switching the level of the charging operation signal according to the discharging determination signal, and generating the charging operation signal. The inversion signal of the charging operation signal is input to the logic circuit.

In one embodiment, the discharge determination signal is used to determine a start time point of the at least one discharge process and an end time point of the charging process.

In one embodiment, the logic circuit performs and logical operation on the at least one zero-current detection signal and the inverted signal of the at least one discharge operation signal to generate the discharge determination signal.

In one embodiment, the determination circuit includes a second latch circuit for setting the at least one discharge operation signal according to the discharge judgment signal, and switching the level of the at least one discharge operation signal according to the charge judgment signal , and the inversion signal of the at least one discharge operation signal is generated to be input to the logic circuit.

In one embodiment, the at least one charging inductor is a single charging inductor, and the at least one discharging inductor is a single discharging inductor.

In one embodiment, the inductance value of the single charging inductor is equal to the inductance value of the single discharging inductor.

In one embodiment, the at least one charging inductor and the at least one discharging inductor are a single same inductor.

In one embodiment, the single identical inductor is a variable inductor.

In one embodiment, the charging process has a charging resonant frequency, and the at least one discharging process has a discharging resonant frequency, and the charging resonant frequency is the same as the discharging resonant frequency.

In one embodiment, the charging process has a charging resonant frequency, and the at least one discharging process has a discharging resonant frequency, and the charging resonant frequency is different from the discharging resonant frequency.

In one embodiment, the level of the reference signal is adjusted to adjust the duration of the charging process to achieve zero-voltage switching of soft switching.

In one embodiment, the level of the reference signal is adjusted to adjust the duration of the at least one discharge procedure to achieve zero-voltage switching of soft switching.

In one embodiment, the resonant switching power converter is a bidirectional resonant switching power converter.

In one embodiment, the voltage conversion ratio of the input voltage to the output voltage of the resonant switching power converter is 4:1, 3:1 or 2:1.

In one embodiment, when the at least one zero-current detection circuit detects the time point when the charging resonant current is zero and generates the at least one zero-current detection signal, a delay time is delayed, and after the delay time At the end time point, the discharge operation signal is switched to perform the at least one discharge procedure.

In one embodiment, when the at least one zero-current detection circuit detects the time point when the discharge resonant current is zero and generates the at least one zero-current detection signal, a delay time is delayed, and after the delay time At the end point, the charging operation signal is switched to perform the charging procedure.

One advantage of the present invention is that the present invention can reduce the number of inductances, compensate for component variations due to DC bias or operating temperature, and reduce switching frequency to improve efficiency at low loads.

Another advantage of the present invention is that the present invention can support the output voltage regulation function, can reduce the voltage stress, and can make all the resonant capacitors have the same rated current and rated voltage, and can use smaller volume capacitors.

Another advantage of the present invention is that the present invention can be dynamically controlled to achieve flexible switching with zero current switching (ZCS) or zero voltage switching (ZVS), better dynamic load transient response, and better current-voltage balance.

Another advantage of the present invention is that the present invention can have a stable resonant frequency, can modulate the voltage conversion ratio more flexibly, and can operate bidirectionally.

The following describes in detail with specific embodiments, when it is easier to understand the purpose, technical content, characteristics and effects of the present invention.

The drawings in the present invention are schematic, mainly intended to represent the coupling relationship between the circuits and the relationship between the signal waveforms, and the circuits, signal waveforms and frequencies are not drawn to scale.

FIG. 3A is a schematic circuit diagram showing a resonant switching power converter 30 according to an embodiment of the present invention. In this embodiment, a plurality of capacitors share a charging inductor or a discharging inductor, so that no matter how many capacitors there are, only one charging inductor and one discharging inductor are needed, which can further reduce the number of inductors. As shown in FIG. 3A, the resonant switching power converter 30 of the present invention includes capacitors C1, C2, C3, switches Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, a charging inductor L1, a discharge Inductor L2 , controller 301 , at least one zero current detection circuit 302 and switch driver 303 . The switches Q1-Q3 are respectively connected in series with the corresponding capacitors C1-C3, and the switch Q4 is connected in series with the charging inductor L1. It should be noted that the number of capacitors in the resonant switching power converter 30 of the present invention is not limited to three in this embodiment, but can also be two or more than four. The number of components shown in this embodiment is only for the purpose of The description of the present invention is not intended to limit the present invention.

As shown in FIG. 3A, one end of the switch Q5 is coupled to the node between the switch Q1 and the capacitor C1, one end of the switch Q6 is coupled to the node between the switch Q2 and the capacitor C2, and one end of the switch Q7 is coupled to the switch Q3 and capacitor C3. One end of the switch Q8 is coupled to the node between the capacitor C1 and the switch Q2, one end of the switch Q9 is coupled to the node between the capacitor C2 and the switch Q3, and one end of the switch Q10 is coupled to the node between the capacitor C3 and the switch Q4. node. As shown in FIG. 3A , after the other ends of the switches Q5-Q7 are electrically connected to a node in common, they are connected in series to the discharge inductor L2. The other ends of the switches Q8-Q10 are commonly coupled to the ground potential. The other ends of the charging inductor L1 and the discharging inductor L2 are commonly coupled to the output voltage Vout, and the other end of the switch Q1 is coupled to the input voltage Vin. The controller 301 is used for generating a charging operation signal GA and a discharging operation signal GB to correspond to a charging procedure and a discharging procedure respectively, and operate the corresponding switches Q1-Q10 to switch the electrical connections of the corresponding capacitors C1-C3 relation. The zero current detection circuit 302 is coupled between the controller 301 and the output voltage Vout to detect a charging resonant current IL1 on the node between the charging inductor L1 and the output voltage Vout during the charging process or during the discharging process When detecting a discharge resonant current IL2 at the node between the discharge inductor L2 and the output voltage Vout. When the zero current detection circuit 302 detects that the charging resonant current IL1 or the discharging resonant current I12 is zero, it generates a zero current detection signal ZCD to the controller 301 for the controller 301 to generate the charging operation signal GA and the discharging operation signal GB.

In one embodiment, the controller 301 can determine the respective start time and end time of the charging process and the discharging process according to the zero current detection signal ZCD, the charging operation signal GA and/or the discharging operation signal GB. The zero current detection circuit 302 may include a current sensing circuit 3021 for sensing the charging resonant current IL1 during the charging process or sensing the discharging resonant current IL2 during the discharging process. The zero current detection circuit 302 may further include a comparator 3022 for comparing the sensed charging resonant current IL1 or discharging resonant current IL2 with a reference signal Vref1 to generate the zero current detection signal ZCD. The switch driver 303 is coupled between the controller 301 and the plurality of switches Q1-Q10 for controlling the plurality of switches Q1-Q10 according to the charging operation signal GA or the discharging operation signal GB. In this embodiment and other embodiments, when the zero current detection circuit 302 detects the time point when the charging resonant current IL1 is zero and generates the zero current detection signal ZCD, a delay time is delayed, and after the delay time At the end point, the discharge operation signal GB is switched to a high level signal to perform the discharge procedure. In this embodiment and other embodiments, when the zero current detection circuit 302 detects the time point when the discharge resonant current IL2 is zero and generates the zero current detection signal ZCD, a delay time is delayed, and after the delay time At the end point, the charging operation signal GA is switched to a high level signal to perform the charging procedure.

The switches Q1-Q10 can be controlled by the switch driver 303 according to the charging operation signal GA and the discharging operation signal GB generated by the controller 301 to switch the electrical connection relationship between the corresponding capacitors C1-C3 and the charging inductance L1 and the discharging inductance L2. In one embodiment, the charging operation signal GA and the discharging operation signal GB are respectively switched to a conduction level for a period of conduction, and the plurality of conduction periods do not overlap with each other.

In a charging process, according to the charging operation signal GA, the switches Q1-Q4 are turned on, and the switches Q5-Q10 are turned off, so that the capacitors C1-C3 are connected in series with each other and the charging inductor L1 is connected in series with the input voltage Vin and the output voltage Vout. between to form a charging path. In a discharge process, according to the discharge operation signal GB, the switches Q5-Q10 are turned on, and the switches Q1-Q4 are turned off, so that the capacitor C1, the capacitor C2 and the capacitor C3 are connected in parallel with each other and then the discharge inductor L2 is connected in series to form a complex discharge path.

It should be noted that, the above-mentioned charging process and the above-mentioned discharging process are repeatedly performed in different time periods, but are not performed simultaneously. Wherein, the charging procedure and the discharging procedure are repeatedly and alternately sequenced, so as to convert the input voltage Vin into the output voltage Vout. In this embodiment, the DC bias voltage of each of the first capacitors C1, C2, and C3 is Vo, so the first capacitors C1, C2, and C3 in this embodiment have the same input voltage and output as the prior art. In voltage applications, only lower rated voltages are required, so smaller capacitors can be used.

In one embodiment, the charging resonant frequency of the above-mentioned charging procedure is the same as the discharging resonant frequency of the above-mentioned discharging procedure. In one embodiment, the charging resonant frequency of the above-mentioned charging procedure is different from the discharging resonant frequency of the above-mentioned discharging procedure. In one embodiment, the resonant switching power converter 30 can be a bidirectional resonant switching power converter. The so-called bidirectional resonant switching power converter means that the roles of the input terminal (providing the input voltage Vin) and the output terminal (providing the output voltage Vout) are reversed, which means that in the embodiment shown in FIG. 3A , the resonant switching power conversion The converter 30 may convert the output voltage Vout to the input voltage Vin. In one embodiment, the voltage conversion ratio of the input voltage Vin to the output voltage Vout of the resonant switching power converter 30 may be 4:1, 3:1 or 2:1.

In one embodiment, the duration of the charging process (Ton1) is related to the charging resonant frequency (fr1) of the charging process. In a preferred embodiment, the duration of the charging process (Ton1) is related to the positive half-wave of the charging resonant current during the charging process. For example, the on-time and off-time of the switches Q1-Q4 are substantially synchronized with the charging process. The start time and end time of the positive half-wave of a charging resonant current. In one embodiment, the duration of the discharge process (Ton2) is related to the discharge resonance frequency (fr2) of the discharge process. In a preferred embodiment, the duration of the discharge process (Ton2) is related to the positive half-wave of the discharge resonant current during the discharge process. For example, the on-time and off-time of the switches Q5-Q10 are substantially synchronized with the discharge process. The start time and end time of the positive half-wave of a discharge resonant current.

In the embodiment in which the charging resonant frequency (fr1) of the above-mentioned charging procedure is equal to the discharging resonant frequency (fr2) of the above-mentioned discharging procedure, when the duration (Ton1) of the above-mentioned charging procedure is equal to the duration (Ton2) of the above-mentioned discharging procedure, for example, When the duty cycle is approximately equal to 50%, the current flowing through the switch can be switched at a relatively low level of its positive half-wave, so as to achieve flexible switching. In a preferred embodiment, zero current switch (ZCS) can be achieved.

In addition, it should be noted that due to the parasitic effect of the circuit components or the mutual matching between components is not necessarily ideal, therefore, although the duration of the charging process is intended to be equal to the duration of the discharging process (that is, in this embodiment The duration of the charging procedure is fifty percent of the duty cycle) to achieve zero-current switching for soft switching. However, the actual duty cycle may not be exactly 50%, but only close to 50% duty cycle. That is, according to the present invention, it is acceptable to make the charging procedure unsatisfactory due to circuit imperfections. There is a certain degree of error between the duration and the 50% duty cycle, which means that the aforementioned discharge to "substantially" means the 50% duty cycle. The same is true everywhere.

In one embodiment, the duration of the charging process is less than a certain percentage of the duty cycle for a predetermined period, for example, less than 50% of the duty cycle for a predetermined period; thereby the switches Q1-Q4 are not turned on in advance and still remain There is a small current flowing through the charging inductor L1, so the accumulated charge of the parasitic capacitance stored in the switch Q10 can be taken away through the parasitic diode of the switch Q4, and the cross-voltage of the switch Q10 can be reduced to achieve Flexible switching. In a preferred embodiment, the level of the reference signal is adjusted to adjust the preset period to achieve zero voltage switch (ZVS). In one embodiment, relatively, the duration of the above-mentioned discharge process is longer than a certain proportion of the duty cycle for a predetermined period, for example, a predetermined period greater than 50% of the duty cycle; thereby, the switch Q5 is not turned on after a delay. - The negative current of the discharge inductor L2 after the Q10 will charge the parasitic capacitance of the switch Q1 through the parasitic diode of the switch Q5, thereby reducing the cross-voltage of the switch Q1, so as to achieve flexible switching. In a preferred embodiment, the level of the reference signal is adjusted to adjust the preset period to achieve zero-voltage switching.

3B is a schematic circuit diagram showing a resonant switching power converter according to an embodiment of the present invention. The difference between this embodiment and the embodiment of FIG. 3A is that the discharge procedures of this embodiment are plural. The controller 301 is used for generating a charging operation signal GA and a plurality of discharging operation signals GB1, GB2 and GB3, respectively corresponding to one charging procedure and three discharging procedures, and operates the corresponding plurality of switches Q1-Q10 to switch the corresponding capacitor C1 -The electrical connection relationship of C3. The zero current detection circuit 302 is coupled between the controller 301 and the output voltage Vout for detecting a charging resonant current IL1 at the node between the charging inductor L1 and the output voltage Vout during the charging process; During a discharge procedure, a discharge resonant current IL2 at the node between the discharge inductor L2 and the output voltage Vout is detected. When the zero current detection circuit 302 detects that the charging resonant current IL1 or the discharging resonant current I12 is zero, it generates a zero current detection signal ZCD to the controller 301 for the controller 301 to generate the charging operation signal GA and the discharging operation signal GB1, GB2 and GB3.

In one embodiment, the controller 301 can determine the respective start time and end time of the charging process and the discharging process according to the zero current detection signal ZCD, the charging operation signal GA and/or the discharging operation signals GB1 , GB2 and GB3 . The zero current detection circuit 302 may include a current sensing circuit 3021 for sensing the charging resonant current IL1 during the charging process or sensing the discharging resonant current IL2 during the discharging process. The zero current detection circuit 302 may further include a comparator 3022 for comparing the sensed charging resonant current IL1 or discharging resonant current IL2 with a reference signal Vref1 to generate the zero current detection signal ZCD. The switch driver 303 is coupled between the controller 301 and the plurality of switches Q1-Q10 for controlling the plurality of switches Q1-Q10 according to the charging operation signal GA or the discharging operation signal GB.

The switches Q1-Q10 can be controlled by the switch driver 303 according to the charging operation signal GA, the discharging operation signals GB1, GB2 and GB3 generated by the controller 301 to switch the power of the corresponding capacitors C1-C3 and the charging inductor L1 and the discharging inductor L2. connection relationship. In one embodiment, the charging operation signal GA and the discharging operation signals GB1 , GB2 and GB3 are respectively switched to a conduction level for one conduction period, and the plurality of conduction periods do not overlap with each other.

For example, in a charging process, according to the charging operation signal GA, the switches Q1-Q4 are turned on, and the switches Q5-Q10 are turned off, so that the capacitors C1-C3 are connected in series with each other and the charging inductor L1 is connected in series with the input voltage Vin and the output voltage Vout to form a charging path. In the first discharge procedure, according to the discharge operation signal GB1, the switches Q5 and Q8 are turned on, and the switches Q1-Q4, Q6, Q7, Q9 and Q10 are turned off, so that the capacitor C1 is connected in series with the discharge inductance L2 to form a first discharge path . In the second discharge procedure, according to the discharge operation signal GB2, the switches Q6 and Q9 are turned on, and the switches Q1-Q4, Q5, Q7, Q8 and Q10 are turned off, so that the capacitor C2 is connected in series with the discharge inductance L2 to form a second discharge path . In the third discharge procedure, according to the discharge operation signal GB3, the switches Q7 and Q10 are turned on, and the switches Q1-Q4, Q5, Q6, Q8 and Q9 are turned off, so that the capacitor C3 discharges the inductor L2 in series to form a third discharge path .

It should be noted that, the above-mentioned charging procedure, the above-mentioned first discharging procedure, the second discharging procedure and the third discharging procedure are repeatedly performed in different time periods, but are not performed simultaneously. Wherein, the charging procedure and the above-mentioned three discharging procedures are repeatedly and interleaved with each other to convert the input voltage Vin into the output voltage Vout, that is, after one charging procedure is completed, the first discharging procedure, the second discharging procedure and the third discharging procedure are followed The procedures are executed in turn, followed by the charging procedure, and so on.

Please refer to FIG. 4 , which is a schematic circuit diagram of a resonant switching power converter 40 according to another embodiment of the present invention. The configurations of capacitors C1-C3, charging inductor L1, discharging inductor L2, switches Q1-Q10, zero current detection circuit 402, current sensing circuit 4021, comparator 4022, and switch driver 403 in FIG. 4 are similar to those shown in FIG. 3A, so I won't go into details. The difference between this embodiment and the embodiment of FIG. 3A is that the controller 401 of this embodiment may include a logic circuit 4011, a decision circuit 4012 and a delay circuit 4013, and the decision circuit 4012 may include a first latch circuit 4012a and a second latch circuit 4012b.

In one embodiment, the delay circuit 4013 is optional. The logic circuit 4011 can be coupled to the zero current detection circuit 402 for generating a charging determination signal and a discharging determination signal according to the zero current detection signal and the charging operation signal GA and/or the discharging operation signal GB. In one embodiment, the charging determination signal can be used to determine the starting time point of the charging process and the ending time point of the discharging process. The logic circuit 4011, for example, but not limited to, performs and logical operations on the inversion signal of the zero current detection signal and the charging operation signal GA to generate the charging judgment signal. In one embodiment, the discharge determination signal can be used to determine the start time point of the discharge process and the end time point of the charging process. For example, but not limited to, the logic circuit 4011 performs and logical operations on the inversion signal of the zero current detection signal and the discharge operation signal GB to generate the discharge judgment signal. The determination circuit 4012 can be coupled with the logic circuit 4011 to generate the charge operation signal GA and the discharge operation signal GB according to the charge determination signal and the discharge determination signal, so as to determine the respective start time and end time of the charging process and the discharging process. The delay circuit 4013 is coupled between the logic circuit 4011 and the decision circuit 4012 for delaying the start point of the charging process and/or the discharging process by a delay time, thereby reducing the switching frequency and adjusting the input voltage Vin and the output voltage Vout proportion.

For example, in the charging process, the charging operation signal GA is at a high level, and when the logic circuit 4011 switches the zero current detection signal ZCD of the zero current detection circuit 402 to a high level, the logic circuit 4011 charges according to the high level at this time. The operation signal GA and the high-level zero-current detection signal ZCD generate a high-level discharge judgment signal to output to the decision circuit 4012, and the decision circuit 4012 then generates a high-level discharge operation signal GB to output to the switch driver 403, The switches Q5-Q10 are turned on. On the other hand, the logic circuit 4011 generates a low-level charging determination signal according to the low-level inversion signal of the charging operation signal GA in the charging process. The decision circuit 4012 switches the charging operation signal GA to a low level according to the high-level discharge determination signal and the low-level charging determination signal, so that the switches Q1-Q4 are turned off, and the charging process is ended.

On the other hand, in the discharge process, the discharge operation signal GB is at a high level, and the logic circuit 4011 receives the zero current detection signal ZCD from the zero current detection circuit 402 and switches to a high level, the logic circuit 4011 discharges according to the high level at this time. The operation signal GB and the high-level zero-current detection signal ZCD generate a high-level charging judgment signal to output to the decision circuit 4012, and the decision circuit 4012 then generates a high-level charging operation signal GA to output to the switch driver 403, The switches Q1-Q4 are turned on. On the other hand, the logic circuit 4011 generates a low-level discharge determination signal according to the low-level inversion signal of the discharge operation signal GB in the discharge process. The decision circuit 4012 switches the discharge operation signal GB to a low level according to the high-level charging determination signal and the low-level discharging determination signal, so that the switches Q5-Q10 are turned off, and the discharging process is ended.

The first latch circuit 4012a can be used to set the charge operation signal GA according to the charge judgment signal, switch the level of the charge operation signal GA according to the discharge judgment signal, and generate an inversion signal of the charge operation signal GA to be input to the logic circuit 4011, For example, when the first latch circuit 4012a receives a high-level charging determination signal, the first latch circuit 4012a sets the charging operation signal GA to a high level, and generates an inversion signal of the low-level charging operation signal GA to input Logic circuit 4011. On the other hand, when the first latch circuit 4012a receives a high-level discharge determination signal, the first latch circuit 4012a switches the level of the charging operation signal GA to a low level, and generates a high-level charging operation signal. The inverted signal is input to the logic circuit 4011 .

The second latch circuit 4012b can be used to set the discharge operation signal GB according to the discharge judgment signal, switch the level of the discharge operation signal GB according to the charge judgment signal, and generate an inversion signal of the discharge operation signal GB to be input to the logic circuit 4011, For example, when the second latch circuit 4012b receives a high-level discharge determination signal, the second latch circuit 4012b sets the discharge operation signal GB to a high level, and generates an inversion signal of the low-level discharge operation signal GB to input Logic circuit 4011. On the other hand, when the second latch circuit 4012b receives the high-level charge determination signal, the second latch circuit 4012b switches the level of the discharge operation signal GB to a low level, and generates a high-level discharge operation signal. The inverted signal is input to the logic circuit 4011 .

Please refer to FIG. 5 , which shows a more specific circuit schematic diagram of a resonant switching power converter 50 according to yet another embodiment of the present invention. The configurations of capacitors C1-C3, charging inductor L1, discharging inductor L2, switches Q1-Q10, zero current detection circuit 502, current sensing circuit 5021, comparator 5022, and switch driver 503 in FIG. 5 are similar to those in FIG. 3A, so I won't go into details. The difference between this embodiment and the embodiment of FIG. 3A is that the controller 501 of this embodiment may include a logic circuit 5011 , a decision circuit 5012 and a delay circuit 5013 . The decision circuit 5012 may include a first latch circuit 5012a and a second latch circuit 5012b. The delay circuit 5013 may include a delay unit 5013a and a delay unit 5013b.

In one embodiment, the delay circuit 5013 is optional. In this embodiment, the logic circuit 5011 may include a first gate 5011a, a second gate 5011b, and an anti-gate 5011c. The first and gate 5011a is coupled between the comparator 5022 and the first latch circuit 5012a; the second and gate 5011b is coupled between the comparator 5022 and the second latch circuit 5012b; and the reverse gate 5011c It is coupled between the first latch circuit 5012a and the second gate 5011b. In the decision circuit 5012, the first latch circuit 5012a is coupled between the first and gate 5011a and the corresponding switch driver 503, and the second latch circuit 5012b is coupled between the second and gate 5011b and the corresponding switch between drives 503 .

The embodiment shown in FIG. 5 is used to illustrate an operation mode according to the present invention. At the beginning of the charging process, the reset terminal R of the second latch circuit 5012b receives a high-level charging judgment signal, and resets the output terminal Q of the second latch circuit 5012b, so that the output terminal of the second latch circuit 5012b is reset. Q, outputs a low-level discharge operation signal GB, so as not to turn on the switches Q5-Q10. During the charging process, the output terminal Q of the first latch circuit 5012a outputs a high-level charging operation signal GA to turn on the switches Q1-Q4. At this time, the inverting gate 5011c performs an inverse logic operation on the inverting output terminal of the first latch circuit 5012a, the inverting signal (low level) of the charging operation signal GA output, to generate a high-level operation result, which is then input to the second and gate 5011b. The second gate 5011b keeps the low-level discharge determination signal until the zero-current detection signal ZCD of the zero-current detection circuit 502 detects that the charging resonant current IL1 decreases to zero current, and switches to a high-level (indicating the end of the charging process) , the second gate 5011b performs a logic operation on the high-level operation result output by the reverse gate 5011c, and the high-level zero-current detection signal ZCD to generate a high-level discharge judgment signal to output to the decision circuit 5012, The second latch circuit 5012b then generates a high-level discharge operation signal GB at its output terminal Q to output to the switch driver 503, so that the switches Q5-Q10 are turned on, and the discharge process starts. In addition, the reset terminal R of the first latch circuit 5012a receives the high-level discharge determination signal, and resets the output terminal Q of the first latch circuit 5012a, so that the output terminal Q of the first latch circuit 5012a generates the low-level charging operation signal GA, so as to The output is output to the switch driver 503, so that the switches Q1-Q4 are turned off, and the charging process is ended.

On the other hand, when the discharge process starts, the reset terminal R of the first latch circuit 5012a receives a high-level discharge judgment signal, and resets the output terminal Q of the first latch circuit 5012a, so that the first latch circuit The output terminal Q of the 5012a outputs a low-level charging operation signal GA to turn off the switches Q1-Q4. And during the discharge process, the output terminal Q of the second latch circuit 5012b outputs a high-level discharge operation signal GB to turn on the switches Q5-Q10. At this time, the inverting signal (high level) of the charging operation signal GA output from the inverting output terminal of the first latch circuit 5012a is input to the first gate 5011a. The first and gate 5011a keep the low-level charging judgment signal until the zero-current detection signal ZCD of the zero-current detection circuit 502 detects that the discharge resonant current IL2 decreases to zero current, and switches to a high-level (indicating the end of the discharge process) , the first and gate 5011a performs logical operations on the inversion signal of the high-level inverting output terminal, the charging operation signal GA, and the high-level zero-current detection signal ZCD to generate a high-level charging judgment The signal is output to the decision circuit 5012, so that the first latch circuit 5012a generates a high-level charging operation signal GA at its output Q to output to the switch driver 503, so that the switches Q1-Q4 are turned on, and the charging process starts. In addition, the reset terminal R of the second latch circuit 5012b receives the high-level charging judgment signal, and resets the output terminal Q of the second latch circuit 5012b, so that the output terminal Q of the second latch circuit 5012b generates the low-level discharge operation signal GB, so as to The output is output to the switch driver 503, so that the switches Q5-Q10 are turned off, and the discharge procedure is ended.

The delay unit 5013a is coupled between the first and gate 5011a and the setting end S of the first latch circuit 5012a, and is used to delay the turn-on timing of the complex switches Q1-Q4 by a delay time. During the delay time, all corresponding The switches Q1-Q4 are all non-conductive to delay the start point of the charging process for a delay time. The delay unit 5013b is coupled between the second and gate 5011b and the setting end S of the second latch circuit 5012b, and is used for delaying the turn-on timing of the plurality of switches Q5-Q10 by a delay time. During the delay time, all the corresponding switches Q5-Q10 are all non-conductive to delay the start point of the discharge process for a delay time.

In one embodiment, the inductance value of L1 may be equal to the inductance value of L2. In one embodiment, it is worth noting that a special case where the inductance value of L1 is equal to the inductance value of L2 is that the charging inductor L1 and the discharging inductor L2 can share the same inductor and function as the charging inductor and the discharging inductor at different times.

Therefore, please refer to FIG. 6 , which is a schematic circuit diagram showing a resonant switching power converter 60 according to yet another embodiment of the present invention. The configurations of the controller 601 , the zero current detection circuit 602 , the current sensing circuit 6021 , the comparator 6022 , and the switch driver 603 in FIG. 6 are similar to those shown in FIG. 3A , so they are not repeated here. The difference between this embodiment and FIG. 3A is that the charging inductance and the discharging inductance of this embodiment can be the same inductance L3 , which can further reduce the number of inductances. As shown in FIG. 6 , the resonant switching power converter 60 of the present invention includes capacitors C1 , C2 , C3 , switches Q1 , Q2 , Q3 , Q4 , Q5 , Q6 , Q7 , Q8 , Q9 , Q10 , and an inductor L3 . The switches Q1-Q3 are respectively connected in series with the corresponding capacitors C1-C3, and the switch Q4 is connected in series with the inductor L3. It should be noted that the number of capacitors in the resonant switching power converter of the present invention is not limited to three in this embodiment, but can also be two or more than four. The number of components shown in this embodiment is only for illustration. The present invention is not intended to limit the present invention.

It should be noted that, in this embodiment, the charging inductance and the discharging inductance are a single identical inductance L3. During the discharging process, through the switching of the switches Q1-Q10, the capacitors C1-C3 are connected in parallel with each other and then connected in series with a single identical inductance L3. Inductor L3. The so-called charging inductance and discharging inductance are a single same inductance L3, which means that in the charging process and the discharging process, the charging resonant current and the discharging resonant current respectively only flow through a single inductance L3, and do not flow through other inductive elements.

As shown in FIG. 6 , one end of the switch Q5 is coupled to the node between the switch Q1 and the capacitor C1, one end of the switch Q6 is coupled to the node between the switch Q2 and the capacitor C2, and one end of the switch Q7 is coupled to the switch Q3 and capacitor C3. One end of the switch Q8 is coupled to the node between the capacitor C1 and the switch Q2, one end of the switch Q9 is coupled to the node between the capacitor C2 and the switch Q3, and one end of the switch Q10 is coupled to the node between the capacitor C3 and the switch Q4. node. As shown in FIG. 6 , after the other ends of the switches Q5-Q7 are electrically connected to a node in common, they are coupled to the node between the switch Q4 and the inductor L3, and the other ends of the switches Q8-Q10 are commonly coupled to the ground potential. The other end of the inductor L3 is coupled to the output voltage Vout, and the other end of the switch Q1 is coupled to the input voltage Vin.

The switches Q1-Q10 can be controlled by the switch driver 603 according to the charging operation signal GA and the discharging operation signal GB generated by the controller 601 to switch the electrical connection relationship between the corresponding capacitors C1-C3 and the inductor L3. In a charging process, according to the charging operation signal GA, the switches Q1-Q4 are turned on, and the switches Q5-Q10 are turned off, so that the capacitors C1-C3 are connected in series with each other and the inductor L3 is connected in series between the input voltage Vin and the output voltage Vout. to form a charging path. In a discharge process, according to the discharge operation signal GB, the switches Q5-Q10 are turned on, and the switches Q1-Q4 are turned off, so that the capacitor C1, the capacitor C2 and the capacitor C3 are connected in parallel with each other and the inductor L3 is connected in series to form a complex discharge path. It should be noted that, the above-mentioned charging process and the above-mentioned discharging process are repeatedly performed in different time periods, but are not performed simultaneously. Wherein, the charging procedure and the discharging procedure are repeatedly and alternately sequenced, so as to convert the input voltage Vin into the output voltage Vout. In this embodiment, the DC bias voltage of each of the first capacitors C1, C2, and C3 is Vo, so the first capacitors C1, C2, and C3 in this embodiment need to withstand a lower rated voltage, so a relatively low voltage can be used. Small size capacitors.

In the present embodiment where the charging inductance and the discharging inductance are set as a single same inductance L1, the ratio of the duration of the charging procedure (Ton1) and the duration of the discharging procedure (Ton2) can be appropriately configured to achieve zero flexible switching current switching. Specifically, in one embodiment, the duration of the above-mentioned charging process is approximately equal to, for example, 25% of the duty cycle; thereby, the switch can make the current flowing through the switch at a relatively low level of its positive half-wave. Switch at the right time to achieve flexible switching. In a preferred embodiment, zero current switch (ZCS) can be achieved. In one embodiment, the duration of the charging process is shorter than a certain percentage of the duty cycle for a predetermined period, for example, less than 25% of the duty cycle for a predetermined period; thus, the switches Q1-Q4 are not turned on in advance. A small current is maintained and flows through the charging inductor L1, so the accumulated charge of the parasitic capacitance stored in the switch Q10 can be taken away through the parasitic diode of the switch Q4, and the cross-voltage of the switch Q10 can be reduced to reduce the cross-voltage of the switch Q10. achieve flexible switching.

In a preferred embodiment, the level of the reference signal is adjusted to adjust the preset period to achieve zero voltage switch (ZVS). In one embodiment, relatively, the duration of the above-mentioned discharge procedure is longer than a certain proportion of the duty cycle for a predetermined period, for example, greater than 75% of the duty cycle for a predetermined period; thereby, the switch is not turned on after a delay The negative current of the post-discharge inductor L2 of Q5-Q10 will charge the parasitic capacitance of the switch Q1 through the parasitic diode of the switch Q5, thereby reducing the cross-voltage of the switch Q1, so as to achieve flexible switching. In a preferred embodiment, the level of the reference signal is adjusted to adjust the preset period to achieve zero voltage switch (ZVS).

In one embodiment, the resonant switching power converter 60 can be a bidirectional resonant switching power converter. In one embodiment, the voltage conversion ratio of the input voltage Vin to the output voltage Vout of the resonant switching power converter 60 may be 4:1, 3:1 or 2:1. In one embodiment, the voltage conversion ratio of the resonant switching power converter 60 can be flexibly adjusted, for example, by selectively keeping switch Q7 on and switches Q10 and Q4 off during charging and discharging procedures. When turned on, the voltage conversion ratio of the resonant switching power converter 60 can be adjusted to 3:1. Similarly, for example, the switch Q6 can be selected to be turned on, and the switches Q9, Q3, Q7, Q10, and Q4 can be selected to be non-conductive, so that the voltage conversion ratio of the resonant switching power converter 60 can be adjusted to 2:1.

Please refer to FIG. 7 , which is a schematic diagram showing a circuit 70 of a resonant switching power converter according to yet another embodiment of the present invention. The controller 701, the logic circuit 7011, the decision circuit 7012, the first latch circuit 7012a, the second latch circuit 7012b, the delay circuit 7013, the zero current detection circuit 702, the current sensing circuit 7021, the comparator 7022 in FIG. 7 7. The switch driver 703 is similar to FIG. 4, and the capacitors C1-C3, switches Q1-10, and inductor L3 in FIG. 7 are similar to those shown in FIG. This embodiment mainly applies the controller architecture in FIG. 4 to a resonant switching power converter with a single inductor.

Please refer to FIG. 8A , which is a schematic diagram showing a circuit 80 of a resonant switching power converter according to yet another embodiment of the present invention. The capacitors C1-C3, the switches Q1-10, and the inductor L3 in FIG. 8A are similar to those shown in FIG. 6, so they will not be described in detail. This embodiment applies the controller architecture of FIG. 5 to a single inductor resonant switching power converter. In addition, the controller 801 of this embodiment may include a logic circuit 8011 , a decision circuit 8012 and a delay circuit 8013 . The decision circuit 8012 may include a first latch circuit 8012a and a second latch circuit 8012b. The delay circuit 8013 may include a delay unit 8013a and a delay unit 8013b.

In one embodiment, the delay circuit 8013 is optional. In this embodiment, the logic circuit 8011 may include a first and gate 8011a, a second and gate 8011b, and an anti-gate 8011c. The first and gate 8011a is coupled between the comparator 8022 and the first latch circuit 8012a; the second and gate 8011b is coupled between the comparator 8022 and the second latch circuit 8012b; and the reverse gate 8011c It is coupled between the second latch circuit 8012b and the first gate 8011a. In the decision circuit 8012, the first latch circuit 8012a is coupled between the first and gate 8011a and the corresponding switch driver 803, and the second latch circuit 8012b is coupled between the second and gate 8011b and the corresponding switch between drives 803.

The embodiment shown in FIG. 8A is used to illustrate an operation mode according to the present invention. At the beginning of the charging process, the reset terminal R of the second latch circuit 8012b receives a high-level charging judgment signal, and resets the output terminal Q of the second latch circuit 8012b, so that the output terminal of the second latch circuit 8012b is reset. Q, outputs a low-level discharge operation signal GB, so as not to turn on the switches Q5-Q10. During the charging process, the output terminal Q of the first latch circuit 8012a outputs a high-level charging operation signal GA to turn on the switches Q1-Q4. At this time, the inversion signal (high level) of the discharge operation signal GB output from the inversion output terminal of the second latch circuit 8012b is input to the second gate 8011b. The second gate 8011b maintains the low-level discharge determination signal until the zero-current detection signal ZCD of the zero-current detection circuit 802 detects that the charging resonant current IL1 decreases to zero current, and switches to a high-level (signifying the end of the charging process) , the second sum gate 8011b performs logic operation on the high-level inverting output terminal of the discharge operation signal GB, and the high-level zero-current detection signal ZCD to generate a high-level discharge judgment. The signal is output to the decision circuit 8012, so that the second latch circuit 8012b generates a high-level discharge operation signal GB at its output terminal Q to output to the switch driver 803, so that the switches Q5-Q10 are turned on, and the discharge process starts. In addition, the reset terminal R of the first latch circuit 8012a receives the high-level discharge judgment signal, and resets the output terminal Q of the first latch circuit 8012a, so that the output terminal Q of the first latch circuit 8012a generates the low-level charging operation signal GA, so as to The output is output to the switch driver 803, so that the switches Q1-Q4 are turned off, and the charging process is ended.

On the other hand, when the discharge process starts, the reset terminal R of the first latch circuit 8012a receives a high-level discharge judgment signal, and resets the output terminal Q of the first latch circuit 8012a, so that the first latch circuit The output terminal Q of the 8012a outputs a low-level charging operation signal GA to turn off the switches Q1-Q4. And during the discharge process, the output terminal Q of the second latch circuit 8012b outputs a high-level discharge operation signal GB to turn on the switches Q5-Q10. At this time, the reverse gate 8011c performs an inverse logic operation on the inverting output terminal of the second latch circuit 8012b, the inverting signal (low level) of the discharge operation signal GB outputted, to generate a high level operation result for inputting the first and gate 8011a. The first and gate 8011a keep the low-level charging determination signal until the zero-current detection signal ZCD of the zero-current detection circuit 802 detects that the discharge resonant current IL2 decreases to zero current, and switches to a high-level (indicating the end of the discharge process) , the first and gate 8011a outputs the high-level operation result to the reverse gate 8011c, and the high-level zero-current detection signal ZCD performs logical operation to generate a high-level charging judgment signal, which is output to the decision circuit 8012, The first latch circuit 8012a then generates a high-level charging operation signal GA at its output terminal Q to output to the switch driver 803, so that the switches Q1-Q4 are turned on, and the charging process starts. In addition, the reset terminal R of the second latch circuit 8012b receives the high-level charging determination signal, and resets the output terminal Q of the second latch circuit 8012b, so that the output terminal Q of the second latch circuit 8012b generates the low-level discharge operation signal GB, so as to The output is output to the switch driver 803, so that the switches Q5-Q10 are turned off, and the discharge procedure is ended.

The delay unit 8013a is coupled between the first and gate 8011a and the setting end S of the first latch circuit 8012a, so as to delay the turn-on timing of the plurality of switches Q1-Q4 by a delay time. During the delay time, all corresponding The switches Q1-Q4 are all non-conductive to delay the start point of the charging process for a delay time. The delay unit 8013b is coupled between the second and gate 8011b and the setting end S of the second latch circuit 8012b, and is used to delay the turn-on time point of the plurality of switches Q5-Q10 by a delay time. During the delay time, all the corresponding switches Q5-Q10 are all non-conductive to delay the start point of the discharge process for a delay time.

FIG. 8B shows a schematic diagram of signal waveforms of related signals when the resonant switching power converter shown in FIG. 8A does not include the delay circuit 8013 . The charging resonance current/discharging resonance current (also called inductor current) IL3, the input current Iin, the zero current detection signal ZCD, the charging operation signal GA and the discharging operation signal GB are shown in FIG. 8B . In this embodiment, the duration of the charging procedure is approximately 25% of the duty cycle, and the duration of the discharge procedure is approximately 75% of the duty cycle. It should be noted that the inductor current IL3 sensed during the charging process is the charging resonant current, and the inductor current IL3 sensed during the discharging process is the discharging resonant current. As shown in FIG. 8B , for example, every time the zero current detection signal ZCD generates a pulse signal, the charging operation signal GA and the discharging operation signal GB are triggered to switch levels to determine the starting time of the charging process and the discharging process. with the end point.

Please refer to FIG. 9 , which is a schematic circuit diagram showing a resonant switching power converter 90 according to yet another embodiment of the present invention. The configuration and diagram of the controller 901, the zero current detection circuit 902, the current sensing circuit 9021, the comparator 9022, the switch driver 903, the capacitors C1-C3, the switches Q1-Q10, the charging inductor L1 and the discharging inductor L2 in FIG. 9 3A is similar, so it is not repeated here. In this embodiment, the discharge procedure is mainly divided into a plurality of discharge procedures to be performed in turn at different time periods. Therefore, the discharge operation signal G2 is used to turn on the switches Q5 and Q8, and make the switches Q1-Q4, Q6, Q7, Q9, and Q10 not turn on. It is turned on to discharge the capacitor C1 in the first period, and the discharge operation signal G3 is used to turn on the switches Q6 and Q9, and make the switches Q1-Q5, Q7, Q8, and Q10 non-conductive, so as to discharge the capacitor C2 in the second period. To discharge, the discharge operation signal G4 is used to turn on the switches Q7, Q10, and make the switches Q1-Q6, Q8-Q9 non-conductive, so as to discharge the capacitor C3 in the third period, and the charge operation signal G1 is used to make Switches Q1-Q4 are turned on and switches Q5-Q10 are turned off to charge capacitors C1-C3. It should be appreciated that, in one embodiment, the controller 901 of this embodiment can also be implemented by replacing the controller structure of FIG. 4 or FIG. 5 .

Please refer to FIG. 10 again, which is a schematic circuit diagram of a resonant switching power converter 100 according to yet another embodiment of the present invention. The controller 1001 , the zero current detection circuit 1002 , the current sensing circuit 10021 , the comparator 10022 , and the switch driver 1003 in FIG. 10 are similar to those shown in FIG. 3A , so they are not described in detail. As shown in FIG. 10, the resonant switching power converter 100 of the present invention includes capacitors C1, C2, C3, switches Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, inductors L1, L2, L3. The switches Q1-Q3 are respectively connected in series with the corresponding capacitors C1-C3, and the capacitors C1-C3 are respectively connected in series with the corresponding inductors L1-L3. It should be noted that the number of capacitors in the resonant switching power converter of the present invention is not limited to three in this embodiment, but may also be two or more, and the number of inductors is not limited to three in this embodiment. , or more than two or four, the number of elements shown in this embodiment is only used to illustrate the present invention and not to limit the present invention. It should be appreciated that, in one embodiment, the controller 1001 of this embodiment can also be implemented in an alternative manner with the controller architecture of FIG. 4 or FIG. 5 .

As shown in FIG. 10 , one end of switch Q5 is coupled to the node between switch Q1 and capacitor C1, one end of switch Q6 is coupled to the node between switch Q2 and capacitor C2, and one end of switch Q7 is coupled to switch Q3 and capacitor C3. One end of the switch Q8 is coupled to the node between the inductor L1 and the switch Q2, one end of the switch Q9 is coupled to the node between the inductor L2 and the switch Q3, and one end of the switch Q10 is coupled to the node between the inductor L3 and the switch Q4. node. As shown in FIG. 10 , the other ends of the switches Q5-Q7 are commonly coupled to the output voltage Vout. The other ends of the switches Q8-Q10 are commonly coupled to the ground potential. The switch Q4 is coupled between the inductor L3 and the output voltage Vout, and one end of the switch Q1 is coupled to the input voltage Vin.

The switches Q1-Q10 can be controlled by the switch driver 1003 according to the charging operation signal GA and the discharging operation signal GB generated by the controller 1001 to switch the electrical connection relationship between the corresponding capacitors C1-C3 and the inductors L1-L3. In a charging process, the switches Q1-Q4 are turned on, and the switches Q5-Q10 are turned off, so that the capacitors C1-C3 and the inductors L1-L3 are connected in series between the input voltage Vin and the output voltage Vout to form a charging process. path. In a discharge process, the switches Q5-Q10 are turned on, and the switches Q1-Q4 are not turned on, so that the capacitor C1 and the corresponding inductor L1 are connected in series between the output voltage Vout and the ground potential, and the capacitor C2 and the corresponding inductor L2 are connected in series with the output voltage. Between Vout and the ground potential, the capacitor C3 and the corresponding inductor L3 are connected in series between the output voltage Vout and the ground potential to form a complex discharge path. It should be noted that the above-mentioned charging procedure and the above-mentioned discharging procedure are performed alternately in different time periods, rather than being performed simultaneously. Wherein, the charging procedure and the discharging procedure are repeatedly and alternately sequenced, so as to convert the input voltage Vin into the output voltage Vout. In this embodiment, the DC bias voltage of each capacitor C1, C2, and C3 is Vo, so the capacitors C1, C2, and C3 in this embodiment need to withstand a lower rated voltage, so capacitors with smaller volume can be used. .

In one embodiment, the duration of the above-mentioned charging process is approximately a certain proportion of the duty cycle, such as, but not limited to, approximately 50% duty cycle; The current is switched at a relatively low level of its positive half-wave to achieve flexible switching. In a preferred embodiment, zero current switch (ZCS) can be achieved.

In one embodiment, the above-mentioned specific ratio is related to the resonance frequency. In one embodiment, the charging process has a charging resonant frequency, and the discharging process has a discharging resonant frequency. In a preferred embodiment, the charging resonant frequency is the same as the discharging resonant frequency.

FIG. 11A is a schematic diagram showing signal waveforms of corresponding operation signals and corresponding inductor currents in a charging process and a discharging process according to an embodiment of the present invention. Please also refer to FIG. 3A. In the embodiment shown in FIG. 11A, the charging operation signal GA of the switches Q1-Q4 is at a high level during the charging process, and the discharging operation signal GB of the switches Q5-Q10 is at a high level during the discharging process. In the embodiment of FIG. 11A, the duration of the charging process is approximately 50% of the duty cycle; thus, the switch Q1 can be switched when the current flowing through the switch is at a relatively low level of its positive half-wave. , is also switched when the charging inductor current IL1 of the charging inductor L1 is zero current, so as to achieve flexible switching. In a preferred embodiment, zero current switching can be achieved.

11B and 11C are schematic diagrams showing signal waveforms of corresponding operation signals and corresponding inductor currents in a charging process and a discharging process according to another embodiment of the present invention. 3A, in the embodiment shown in FIG. 11B, the charging operation signal GA of the switches Q1-Q4 is at a high level during the charging process, and the discharging operation signal GB of the switches Q5-Q10 is at a high level during the discharging process. In the embodiment of FIG. 11B , the reference signal can be increased so that the duration of the charging process is substantially less than 50% of the duty cycle for a predetermined period T1; thus, the switches Q1-Q4 are turned off in advance. There is still a small current flowing through the charging inductor L1. Therefore, the accumulated charge of the parasitic capacitance stored in the switch Q10 can be discharged through the parasitic diode of the switch Q4, thereby reducing the cross-voltage of the switch Q10, so as to achieve Flexible switching. In a preferred embodiment, the preset period T1 is adjusted to achieve zero voltage switching. 3A, in the embodiment shown in FIG. 11C, the charging operation signal GA of the switches Q1-Q4 is at a high level during the charging process, and the discharging operation signal GB of the switches Q5-Q10 is at a high level during the discharging process. In the embodiment of FIG. 11C , the reference signal can be lowered so that the duration of the discharge process is substantially greater than 50% of the duty cycle for a predetermined period T2+T3; thereby, the non-conducting switch Q5 is delayed. - The negative current of the discharge inductor L2 after the Q10 will charge the parasitic capacitance of the switch Q1 through the parasitic diode of the switch Q5, thereby reducing the cross-voltage of the switch Q1, so as to achieve flexible switching. In a preferred embodiment, the preset periods T2 and T3 are adjusted to achieve zero voltage switching. In one embodiment, it should be noted that the embodiments of Figures 11B and 11C may be implemented together or only one of them.

The present invention provides a resonant switching power converter as described above, which can reduce the number of inductances by special circuit design, can mask the component changes due to DC bias or operating temperature, can reduce the switching frequency to improve low load high efficiency, can support output voltage regulation, can reduce voltage stress, can make all resonant capacitors have the same rated current and voltage to use smaller capacitors, can be dynamically controlled to achieve zero current switching (ZCS) or zero voltage switching (ZVS) flexible switching, can have better dynamic load transient response, can have better current-voltage balance, can have a stable resonant frequency, can more flexibly adjust the voltage conversion ratio and can Bidirectional operation.

It should be noted that the "high level" and "low level" mentioned in the foregoing embodiments are only examples, and are not intended to limit the scope of the present invention. In other embodiments, the foregoing "high level" and "low level" ”, under the same spirit of the present invention as described above, it can be adaptively at least partially adjusted or exchanged according to the actual switch type and logic basis used.

The present invention has been described above with respect to the preferred embodiments, but the above descriptions are only intended to make the content of the present invention easy for those skilled in the art to understand, and are not intended to limit the broadest scope of rights of the present invention. The described embodiments are not limited to be used alone, but can also be used in combination. For example, two or more embodiments can be used in combination, and some components in one embodiment can also be used to replace those in another embodiment. corresponding components. In addition, under the same spirit of the present invention, those skilled in the art can think of various equivalent changes and various combinations. According to the signal itself, when necessary, the signal is subjected to voltage-to-current conversion, current-to-voltage conversion, and/or ratio conversion, etc., and then processed or calculated according to the converted signal to generate an output result. It can be seen from this that under the same spirit of the present invention, those skilled in the art can think of various equivalent changes and various combinations, and there are many combinations, which are not listed and described here. Accordingly, the scope of the present invention should cover the above and all other equivalent changes.

30, 40, 50, 60, 70, 80, 90, 100: Resonant switching power converters 301, 401, 501, 601, 701, 801, 901, 1001: Controller 302, 402, 502, 602, 702, 802, 902, 1002: zero current detection circuit 3021, 4021, 5021, 6021, 7021, 8021, 9021, 10021: Current Sensing Circuit 3022, 4022, 5022, 6022, 7022, 8022, 9022, 10022: Comparator 303, 403, 503, 603, 703, 803, 903, 1003: Switch Drivers 4011, 7011: Logic circuits 4012, 7012: decision circuit 4012a, 5012a, 7012a: first latch circuit 4012b, 5012b, 7012b: second latch circuit 4013, 7013: Delay circuit 5011a, 8011a: first and gate 5011b, 8011b: Second and gate 5012, 8012: Inverter 5013, 8013: Delay circuit 8014a: First Latch 8014b: Second Latch C1~C3, C1(CR), C2(CF), C3(CR): Capacitor Co: output capacitance G1, GA: charging operation signal G2, G3, G4, GB: Discharge operation signal Iin: input current IL1: Charging inductor current (charging resonance current) IL2: Discharge inductor current (discharge resonance current) IL3: Inductor current (charge resonant current/discharge resonant current) L1: charging inductance L2: Discharge inductance L1(LR), L2(LR), L3, Lb: Inductance Q: output terminal Ǭ: Reverse output terminal Q1~Q10, Q1(S1A), Q2(S2A), Q3(S1B), Q4(S2B), Q5(S1A), Q6(S2A), Q7(S2A), Q8(S1B), Q9(S1B), Q10 (S2B), Qb: switch R: reset terminal S: setting terminal RL: load resistance T1, T2, T3: Period Vc1: DC bias voltage of capacitor C1 Vc2: Capacitor C2 DC bias Vc3: Capacitor C3 DC bias Vin: input voltage Vout: output voltage Vref1: Reference signal ZCD: zero current detection signal

FIG. 1 shows a conventional power converter.

FIG. 2 is a schematic diagram showing the change of capacitance value with DC bias.

3A is a schematic circuit diagram showing a resonant switching power converter according to an embodiment of the present invention.

3B is a schematic circuit diagram showing a resonant switching power converter according to an embodiment of the present invention.

FIG. 4 is a schematic circuit diagram showing a resonant switching power converter according to another embodiment of the present invention.

FIG. 5 is a schematic circuit diagram showing a resonant switching power converter according to yet another embodiment of the present invention.

FIG. 6 is a schematic circuit diagram showing a resonant switching power converter according to yet another embodiment of the present invention.

FIG. 7 is a schematic circuit diagram showing a resonant switching power converter according to yet another embodiment of the present invention.

8A and 8B are schematic diagrams showing signal waveforms of a circuit of a resonant switching power converter and related signals according to yet another embodiment of the present invention.

FIG. 9 is a schematic circuit diagram showing a resonant switching power converter according to yet another embodiment of the present invention.

10 is a schematic circuit diagram showing a resonant switching power converter according to yet another embodiment of the present invention.

11A , 11B and 11C are schematic diagrams showing signal waveforms of corresponding operation signals and corresponding inductor currents in a charging process and a discharging process according to an embodiment of the present invention.

30: Resonant switching power converters

301: Controller

302: Zero current detection circuit

3021: Current Sensing Circuit

3022: Comparator

303: Switch Driver

C1~C3: Capacitor

Co: output capacitance

GA: Charging operation signal

GB: Discharge operation signal

IL1: Charging inductor current

IL2: Discharge inductor current

L1: charging inductance

L2: Discharge inductance

Q1~Q10: switch

RL: load resistance

Vin: input voltage

Vout: output voltage

ZCD: zero current detection signal

Claims (24)

A resonant switching power converter for converting an input voltage into an output voltage, the resonant switching power converter comprising: complex capacitance; a complex number of switches, correspondingly coupled to the complex number of capacitors; at least one charging inductor, correspondingly connected in series with at least one of the plurality of capacitors; at least one discharge inductor, correspondingly connected in series with at least one of the complex capacitors; a controller for generating a charging operation signal and at least one discharging operation signal, respectively corresponding to a charging procedure and at least one discharging procedure, and operating the corresponding plurality of switches to switch the electrical connection relationship of the corresponding capacitors; as well as At least one zero current detection circuit for detecting a charging resonant current flowing through the at least one charging inductor during the charging process and/or detecting at least one charging resonant current flowing through the at least one discharging inductor during the at least one discharging process a discharge resonant current, when the at least one zero-current detection circuit detects that the charging resonant current and/or the at least one discharge resonant current is zero, correspondingly generates at least one zero-current detection signal to the controller; Wherein, the charging operation signal and the at least one discharging operation signal are respectively switched to a conduction level for a conduction period, and the plurality of conduction periods do not overlap each other, so that the charging process and the at least one discharging process do not overlap each other ; Wherein, in the charging procedure, the controller controls the switching of the plurality of switches by the charging operation signal, so that the plurality of capacitors and the at least one charging inductor are connected in series between the input voltage and the output voltage to form a charging path; Wherein, in the at least one discharge procedure, the controller controls the switching of the plurality of switches by the at least one discharge operation signal, so that each of the capacitors and the corresponding discharge inductance are connected in series between the output voltage and a ground potential, To form a plurality of discharge paths at the same time or in turn; Wherein, the controller determines respective start time points and end time points of the charging process and the at least one discharging process according to the at least one zero current detection signal; Wherein, the charging procedure and the at least one discharging procedure are repeatedly and alternately sequenced, so as to convert the input voltage into the output voltage. The resonant switching power converter as claimed in claim 1, wherein the controller further determines the respective starting time points and starting points of the charging process and the at least one discharging process according to the charging operation signal and/or the at least one discharging operation signal. end time. The resonant switching power converter of claim 1, wherein the at least one zero current detection circuit comprises a current sensing circuit for sensing the charging resonant current during the charging process or during the at least one discharging process The at least one discharge resonant current is sensed to generate a current sensing signal; and a comparator is used for comparing the current sensing signal with a reference signal to generate the at least one zero current detection signal. The resonant switching power converter according to claim 3, further comprising a plurality of switch drivers, respectively coupled between the controller and the corresponding switch, for the corresponding charging operation signal or the corresponding discharging operation signal to control the plurality of switches respectively. The resonant switching power converter of claim 2, wherein the controller comprises: a logic circuit, coupled to the at least one zero current detection circuit, for generating a charging judgment signal and a discharging according to the at least one zero current detection signal and the charging operation signal and/or the at least one discharging operation signal judgment signal; and a determination circuit, coupled to the logic circuit, for generating the charging operation signal and the at least one discharging operation signal according to the charging determination signal and the discharging determination signal, so as to determine the respective difference between the charging procedure and the at least one discharging procedure Start time and end time. The resonant switching power converter of claim 5, wherein the controller further comprises a delay circuit, coupled between the logic circuit and the determination circuit, for delaying the charging process and/or the at least one discharging The start point of the program is a delay time. The resonant switching power converter as claimed in claim 5, wherein the charging determination signal is used to determine a start time point of the charging process and an end time point of the at least one discharging process. The resonant switching power converter as claimed in claim 7, wherein the logic circuit performs a logic operation on the at least one zero-current detection signal and an inversion signal of the charging operation signal to generate the charging determination signal. The resonant switching power converter of claim 8, wherein the determination circuit includes a first latch circuit for setting the charging operation signal according to the charging judgment signal, and switching the charging according to the discharging judgment signal The level of the operation signal is generated, and the inversion signal of the charging operation signal is generated to input the logic circuit. The resonant switching power converter as claimed in claim 5, wherein the discharge determination signal is used to determine a start time point of the at least one discharge process and an end time point of the charging process. The resonant switching power converter as claimed in claim 10, wherein the logic circuit performs and a logic operation on the inversion signal of the at least one zero current detection signal and the at least one discharge operation signal to generate the discharge determination signal. The resonant switching power converter of claim 11, wherein the determination circuit includes a second latch circuit for setting the at least one discharge operation signal according to the discharge judgment signal, and switching according to the charge judgment signal The level of the at least one discharge operation signal is generated, and an inversion signal of the at least one discharge operation signal is generated to be input to the logic circuit. The resonant switching power converter of claim 1, wherein the at least one charging inductor is a single charging inductor, and the at least one discharging inductor is a single discharging inductor. The resonant switching power converter of claim 13, wherein the inductance value of the single charging inductor is equal to the inductance value of the single discharging inductor. The resonant switching power converter of claim 1, wherein the at least one charging inductor and the at least one discharging inductor are a single same inductor. The resonant switching power converter of claim 15, wherein the single identical inductor is a variable inductor. The resonant switching power converter of claim 1 or 13, wherein the charging process has a charging resonant frequency, and the at least one discharging process has a discharging resonant frequency, and the charging resonant frequency is the same as the discharging resonant frequency. The resonant switching power converter of 13, 14 or 15, wherein the charging process has a charging resonant frequency, and the at least one discharging process has a discharging resonant frequency, and the charging resonant frequency is different from the discharging resonant frequency. The resonant switching power converter of claim 3, wherein the level of the reference signal is adjusted to adjust the duration of the charging procedure to achieve zero-voltage switching of soft switching. The resonant switching power converter of claim 3, wherein the level of the reference signal is adjusted to adjust the duration of the at least one discharge procedure to achieve zero-voltage switching of soft switching. The resonant switching power converter described in 13, 14 or 15, wherein the resonant switching power converter is a bidirectional resonant switching power converter. The resonant switching power converter of 13, 14 or 15, wherein the voltage conversion ratio of the input voltage to the output voltage of the resonant switching power converter is 4:1, 3:1 or 2:1. The resonant switching power converter as claimed in claim 1, wherein when the at least one zero-current detection circuit detects that the charging resonant current is zero and generates the at least one zero-current detection signal with a delay of one delay time, and switch the discharge operation signal to perform the at least one discharge process at the end of the delay time. The resonant switching power converter as claimed in claim 1, wherein when the at least one zero-current detection circuit detects that the discharge resonant current is zero and generates the at least one zero-current detection signal with a delay of one delay time, and switch the charging operation signal at the end of the delay time to perform the charging process.

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