TWI755143B - Resonant switching power converter - Google Patents

Abstract

The present invention provides a resonant switching power converter including: at least one capacitor; a plurality of switches correspondingly coupled to the at least one capacitor for switching electrical connections of the corresponding capacitor according to a corresponding operation signal; at least one charging inductor; at least one discharging inductor; and a zero current estimation circuit coupled to the at least one charging inductor and/or the at least one discharging inductor, and/or the capacitor, for estimating a time point at which a charging resonant current is zero during a charging process and/or a time point at which at least one corresponding discharging resonant current is zero during at least one discharging process according to a voltage difference between two ends of the charging inductor and/or a voltage difference between two ends of the discharging inductor, and/or a voltage difference between two ends of the capacitor, to correspondingly generate a zero current estimation signal respectively, so as to generate the operation signal.

Description

Resonant Switching Power Converters

The present invention relates to a resonant switching power converter, in particular, to a resonant switching power converter capable of estimating the zero current time point.

FIG. 1 shows a conventional power converter. During the charging operation, the switches Q1, Q2, Q3, and Q4 are turned on, and the switches Q5, Q6, Q7, Q8, Q9, and Q10 are turned off, so that the capacitors C1, C2, and C3 are connected in series with each other between the input voltage Vin and the output voltage Vout. between. During the discharge operation, the switches Q5, Q6, Q7, Q8, Q9, and Q10 are turned on, and the switches Q1, Q2, Q3, and Q4 are turned off, so that the capacitors C1, C2, and C3 are connected in parallel between the ground potential and the output voltage Vout. . The capacitance of the conventional power converter has a very large inrush current when the switches Q1-Q10 are switched.

In view of this, the present invention proposes an innovative power converter aiming at the above-mentioned deficiencies of the prior art.

In one aspect, the present invention provides a resonant switching power converter for converting an input voltage into an output voltage, the resonant switching power converter comprising: at least one capacitor; and a plurality of switches corresponding to the at least one capacitor Coupling, respectively according to a corresponding operation signal, to switch the electrical connection relationship of the corresponding capacitor; at least one charging inductor, correspondingly connected in series with at least one of the at least one capacitor; at least one discharging inductor, connected with the at least one At least one of the capacitors is correspondingly connected in series; and a zero-current estimation circuit, coupled to the at least one charging inductor and/or the at least one discharging inductor, and/or the capacitor, is used for The voltage difference, and/or the voltage difference across the discharge inductor, and/or the voltage difference across the capacitor, to estimate a point in time when the charging resonant current is zero during a charging process, and/or during at least one discharging process When the corresponding at least one discharge resonant current is zero, a zero current estimation signal is correspondingly generated for generating the operation signal; wherein, the operation signal includes a charge operation signal and at least one discharge operation signal, respectively Switching to a conduction level for a conduction period, and the plurality of conduction periods do not overlap each other, so that the charging process and the at least one discharging process do not overlap each other; wherein, in the charging process, the charging operation signal is used to control The switching of the plurality of switches causes the at least one capacitor and the at least one charging inductor to be connected in series between the input voltage and the output voltage to form a charging path for resonant charging of the capacitor and the charging inductor; wherein, in In the at least one discharge procedure, the switching of the plurality of switches is controlled by the at least one discharge operation signal, so that each of the capacitors and the corresponding discharge inductance are connected in series between the output voltage and a ground potential, and are formed simultaneously or alternately. A plurality of discharge paths are used to resonantly discharge the capacitor and the charging inductor; wherein, the charging procedure and the at least one discharging procedure are repeatedly and alternately sequenced with each other, so as to convert the input voltage into the output voltage.

In one embodiment, the zero current estimation circuit includes a voltage detection circuit for generating a voltage detection signal according to the voltage difference between the two ends of the charging inductor and/or the voltage difference between the two ends of the discharging inductor to generate a voltage detection signal. indicating a positive voltage period in which the voltage difference between the two ends of the charging inductor and/or the voltage difference between the two ends of the discharging inductor exceeds zero; and a timer, coupled to the output end of the voltage detection circuit, is used for according to the voltage The detection signal generates the zero current estimation signal.

In one embodiment, the zero current estimation circuit includes a voltage detection circuit for generating a voltage detection signal according to the voltage difference between the two ends of the capacitor to indicate a peak value of the peak value of the voltage difference between the two ends of the capacitor time point, and a valley value time point of one of its valleys, and generate the zero current estimation signal accordingly.

In one embodiment, the timer includes a ramp circuit for generating a rising ramp of a ramp signal according to the voltage detection signal during the positive voltage period, and after the positive voltage period ends, according to the rising ramp a ramp for generating a descending ramp of the ramp signal; and a comparison circuit for comparing the ramp signal with a zero current threshold to generate the zero current estimation signal to determine the respective start of the charging procedure and the at least one discharging procedure start time and end time.

In one embodiment, the ramp circuit includes a boost circuit for continuously boosting the voltage across a ramp capacitor from zero during the positive voltage period to generate the rising ramp; and a step-down circuit for generating the rising ramp; After the positive voltage period ends, the voltage across the ramp capacitor is continuously reduced to generate the descending ramp; wherein the absolute values of the ascending ramp and the descending ramp are the same.

In one embodiment, the boosting circuit includes a first switch and a first current source, wherein the first switch is used for causing the first current source to be connected to the positive voltage according to the voltage detection signal during the positive voltage period. The ramp capacitor is charged.

In one embodiment, the step-down circuit includes a second switch and a second current source, wherein the second switch is used for discharging the ramp capacitor by the second current source after the positive voltage period ends.

In one embodiment, the resonant switching power converter may further include a controller coupled to the zero current estimation circuit for generating the charging operation signal and the at least one discharging operation according to the zero current estimation signal signal.

In one embodiment, the controller includes a delay circuit for maintaining the zero current estimation signal for a delay time so that the charging process and the at least one discharging process are separated from each other by the delay time.

In one embodiment, the voltage detection circuit includes at least one comparator for correspondingly comparing the voltage across the charging inductor and/or the voltage across the discharging inductor.

In one embodiment, the at least one comparator is two comparators, one of the two comparators is coupled to both ends of the charging inductor, and the other of the two comparators is coupled to the discharging both ends of the inductor.

In one embodiment, the timer further includes a reset switch connected in parallel with the ramp capacitor for discharging the voltage across the ramp capacitor to zero voltage after the zero current estimation signal is generated.

In one embodiment, the plurality of switches remain off during the delay time.

In one embodiment, the at least one charging inductor is a single charging inductor, and the at least one discharging inductor is a single discharging inductor.

In one embodiment, the inductance value of the single charging inductor is equal to the inductance value of the single discharging inductor.

In one embodiment, the at least one charging inductor and the at least one discharging inductor are a single same inductor.

In one embodiment, the single identical inductor is a variable inductor.

In one embodiment, the charging process has a charging resonant frequency, and the discharging process has a discharging resonant frequency, and the charging resonant frequency is the same as the discharging resonant frequency.

In one embodiment, the charging process has a charging resonant frequency, and the discharging process has a discharging resonant frequency, and the charging resonant frequency is different from the discharging resonant frequency.

In one embodiment, the adjustment of the level of the zero-current threshold is used to shorten a zero-voltage period during the conduction period, so that the corresponding switch can achieve zero-voltage switching of soft switching.

In one embodiment, the resonant switching power converter is a bidirectional resonant switching power converter.

In one embodiment, the voltage conversion ratio of the input voltage to the output voltage of the resonant switching power converter is 4:1, 3:1 or 2:1.

In one embodiment, the timer includes a counting circuit and a judging circuit. When the voltage detection signal is switched from a low level to a high level, the counting circuit starts counting according to a clock signal, and counts the result. output to the judgment circuit, and when the voltage detection signal is switched from a high level to a low level, the counting circuit counts down from the last count result according to the clock signal, and the judgment circuit counts down to zero or When a count threshold is reached, the zero current estimation signal is generated.

In one embodiment, after the judging circuit generates the zero current estimation signal, it outputs a reset signal to the counting circuit to reset the counting circuit.

In another aspect, the present invention provides a resonant switching power converter for converting an input voltage to an output voltage, the resonant switching power converter comprising: at least one resonant cavity, the resonant cavity has a connection in series with each other. a resonant capacitor and a resonant inductor; a plurality of switches, which are correspondingly coupled to the at least one resonant cavity, respectively switch the electrical connection of the corresponding resonant cavity according to a corresponding first resonant operation signal and a second resonant operation signal The relationship corresponds to a first resonance process and a second resonance process; at least one non-resonant capacitor is used for switching the electrical connection relationship with the at least one resonance cavity according to the first resonance operation signal and the second resonance operation signal , and the voltage across the non-resonant capacitor is maintained at a fixed ratio with the input voltage; and a zero-current estimation circuit is coupled to the resonant inductor in the at least one resonant cavity, and is used to determine the voltage difference between the two ends of the resonant inductor according to the , to estimate the time point when a first resonant current flowing through the corresponding resonant inductor is zero during the first resonant process, and/or a second resonant current flowing through the corresponding resonant inductor during the second resonant process When the current is zero, a zero-current estimation signal is correspondingly generated for generating the first resonance operation signal and the second resonance operation signal; wherein, the first resonance operation signal and the second resonance operation signal, They are respectively switched to a conduction level for one conduction period, and the plurality of conduction periods do not overlap each other, so that the first resonance process and the second resonance process do not overlap each other; wherein, the first resonance process and the second resonance process The resonant procedures are repeatedly interleaved with each other to convert the input voltage to the output voltage.

One of the advantages of the present invention is that the present invention can reduce the inrush current, can estimate the zero current from the cross-voltage of the inductor or the capacitor, so as to switch the charging and discharging process, and further achieve zero current switching (ZCS) or zero current switching. Flexible switching of voltage switching (ZVS) to improve power efficiency and eliminate the need for current sense resistors or current sense transformers.

Another advantage of the present invention is that the present invention does not need to use a current sensing resistor, which can reduce the power loss of the current sensing resistor due to high current and solve the accuracy problem of a large current sensing resistor at low current.

The following describes in detail with specific embodiments, when it is easier to understand the purpose, technical content, characteristics and effects of the present invention.

The drawings in the present invention are schematic, mainly intended to represent the coupling relationship between the circuits and the relationship between the signal waveforms, and the circuits, signal waveforms and frequencies are not drawn to scale.

FIG. 2 is a schematic circuit diagram showing a resonant switching power converter according to an embodiment of the present invention. As shown in FIG. 2 , in this embodiment, the same inductor L1 is used as the charging inductor and the discharging inductor respectively at different times, and this arrangement can further reduce the number of inductors. As shown in FIG. 2 , the resonant switching power converter 20 of the present invention includes a capacitor C1 , switches Q1 , Q2 , Q3 , Q4 , an inductor L1 , a zero current estimation circuit 201 and a controller 202 . The switch Q1 is connected in series with the capacitor C1, and the switch Q2 is connected in series with the inductor L1. It should be noted that the number of capacitors in the resonant switching power converter of the present invention is not limited to one in this embodiment, but can also be more than two. The number of components shown in this embodiment is only for illustrating the present invention and not for Limit the invention.

It should be noted that, in this embodiment, the same and single inductor L1 is used as the charging inductor and the discharging inductor at different times. During the charging process and the discharging process, the switching of the switches Q1-Q4 makes the capacitors C1 is connected in series to the same single inductor L1, but the electrical connection relationship is different. The so-called same and single inductor L1 acts as the charging inductor and the discharging inductor at different times, which means that in the charging process, the inductor current IL1 flowing through the same and single inductor L1 does not flow through other inductive elements as a charging resonance. In the discharge procedure, the inductor current IL1 flowing through the same and single inductor L1 does not flow through other inductive elements as the discharge resonant current. In one embodiment, the inductor L1 can be a variable inductor.

As shown in FIG. 2 , one end of the switch Q3 is coupled to the node between the switch Q1 and the capacitor C1, and one end of the switch Q4 is coupled to the node between the capacitor C1 and the switch Q2. As shown in FIG. 2 , the other end of the switch Q3 is coupled to the node between the switch Q2 and the inductor L1 , and the other end of the switch Q4 is coupled to the ground potential. The other end of the inductor L1 is coupled to the output voltage Vout, and the other end of the switch Q1 is coupled to the input voltage Vin.

The zero current estimation circuit 201 is coupled to the inductor L1 for estimating a time point when the charging resonant current is zero during a charging procedure and/or a discharging resonance during a discharging procedure according to the voltage difference between the two ends of the inductor L1 When the current is zero, a zero current estimation signal ZCPD is correspondingly generated for generating the charging operation signal GA and the discharging operation signal GB.

In one embodiment, the zero current estimation circuit 201 may include a voltage detection circuit 2011 and a timer 2012 . Please refer to FIGS. 2 and 4 at the same time. FIG. 4 is a schematic diagram of signal waveforms according to the embodiment shown in FIGS. 2 and 3 of the present invention. The voltage detection circuit 2011 is used for generating a voltage detection signal VD according to the voltage difference VL1 across the inductor L1 to indicate that the voltage difference VL1 across the inductor L1 exceeds a positive voltage period T1 of zero voltage. The timer 2012 is coupled to the output terminal of the voltage detection circuit 2011, and is used for generating a zero current estimation signal ZCPD according to the voltage detection signal VD to indicate the time point when the inductor current IL1 is zero. The controller 202 is coupled to the zero current estimation circuit 201 for generating the charging operation signal GA and the discharging operation signal GB according to the zero current estimation signal ZCPD, respectively, for switching the switches Q1-Q4. In one embodiment, the controller 202 may determine the respective start time and end time of the charging process and the discharging process according to the zero current estimation signal ZCPD, the charging operation signal GA and/or the discharging operation signal GB.

The switches Q1-Q4 can switch the electrical connection relationship between the capacitor C1 and the inductor L1 according to the charging operation signal GA and the discharging operation signal GB generated by the controller 202 . In a charging process, according to the charging operation signal GA, the switches Q1-Q2 are turned on, and the switches Q3-Q4 are turned off, so that the capacitor C1 and the inductor L1 are connected in series between the input voltage Vin and the output voltage Vout to form a A charging path for resonant charging of the capacitor and the charging inductor. For example, the charging process, as shown in FIG. 4, refers to the period from the time point t0 to the time point t2, the charging operation signal GA is at a high level to control the conduction of switches Q1 and Q2; and the discharging operation signal GB is at a low level, In order to control the switches Q3-Q4 not conducting. In a discharge process, according to the discharge operation signal GB, the switches Q3-Q4 are turned on, and the switches Q1-Q2 are turned off, so that the capacitor C1 is connected in series with the inductor L1 between the ground potential and the output voltage Vout to form a discharge path to The capacitor and the charging inductor are resonantly discharged. For example, the discharge process, as shown in FIG. 4, refers to the period from the time point t2 to the time point t4, the charging operation signal GA is at a low level to control the switches Q1 and Q2 not to conduct; and the discharging operation signal GB is at a high level , to control the switches Q3-Q4 to be turned on. It should be noted that, the above-mentioned charging process and the above-mentioned discharging process are repeatedly performed in different time periods, but are not performed simultaneously. In this embodiment, the DC bias voltage of the capacitor C1 is Vo (as indicated by the thick black dotted line in FIG. 4 ), which is lower than that of the prior art, so the capacitor C1 in this embodiment only needs to have a lower withstand voltage. specifications, so smaller capacitors can be used.

In one embodiment, since the zero current estimation signal ZCPD is generated when the current of the charging inductor L3 or the discharging inductor L2 approaches zero, in other words, the charging operation signal also approaches zero when the current of the charging inductor L3 or the discharging inductor L2 The level switching is performed at the time of switching, whereby the switches Q1-Q4 can be switched when the current flowing through the switches Q1-Q4 is at a relatively lower level of the positive half-wave, so as to achieve flexible switching. In a preferred embodiment, zero current switch (ZCS) can be achieved.

In one embodiment, during the charging process, the switches Q1-Q2 are not turned on for a predetermined period in advance. Due to the characteristic of the inductor L1 that resists rapid changes in current, the switches Q1 and Q2 still maintain a small current after they are turned off. The inductance L1 flows through, therefore, the accumulated charge of the parasitic capacitance stored in the switch Q4 can be taken away through the parasitic diode of the switch Q2, thereby reducing the cross-voltage of the switch Q4, so as to achieve flexible switching. In a preferred embodiment, the preset period is adjusted to achieve zero voltage switch (ZVS). In one embodiment, relatively, during the discharge process, the switches Q3-Q4 are not turned on after a predetermined period of time, that is, the switches Q3-Q4 are kept on during the predetermined period, so that the discharge current flows through the inductor L1 in the reverse direction. (negative current), the parasitic capacitance of the switch Q1 will be charged through the parasitic diode of the switch Q3, and the cross-voltage of the switch Q1 will be reduced to achieve flexible switching. In a preferred embodiment, the preset period is adjusted to achieve zero voltage switch (ZVS).

In one embodiment, the resonant switching power converter 20 can be a bidirectional resonant switching power converter. In one embodiment, the voltage conversion ratio of the input voltage Vin to the output voltage Vout of the resonant switching power converter 20 may be 2:1.

FIG. 3 is a schematic circuit diagram showing another resonant switching power converter 30 according to an embodiment of the present invention. In this embodiment, the charging procedure and the discharging procedure are the same as the embodiment shown in FIG. 2 in the operation of the switches Q1-Q4. The difference between this embodiment and the embodiment shown in FIG. 2 is that, in this embodiment, the zero current estimation circuit 301 can also be coupled to the capacitor C1 for estimating the charging process according to the voltage difference between the two ends of the capacitor C1 The time point when the charging resonant current is zero in the process and/or the time point when the discharge resonant current is zero in the discharging process corresponds to generating the zero current estimation signal ZCPD for generating the charging operation signal GA and the discharging operation signal GB. In this embodiment, the zero-current estimation circuit 301 includes a voltage detection circuit 3011 for generating a voltage detection signal according to the voltage difference between the two ends of the capacitor C1 to indicate the peak time point of the peak value of the voltage difference between the two ends of the capacitor C1 ( The time point t2 shown in FIG. 4 ), and the time point of the valley value of the valley value (the time point t4 shown in FIG. 4 ), and the zero current estimation signal ZCPD is generated accordingly. There are many different implementations for detecting the peak value and the valley value of the voltage difference, which are well known to those with ordinary skills in the art, and will not be repeated here.

5 is a schematic circuit diagram showing a timer in a resonant switching power converter according to an embodiment of the present invention. The timer 2012 in this embodiment is an embodiment of the timer 2012 in FIG. 2 . In one embodiment, the timer 2012 of FIG. 2 can be an analog timer or a digital timer. The embodiment of FIG. 5 is an example of an analog timer. In one embodiment, the timer 2012 may include a ramp circuit 20121 and a comparison circuit 20122 . Please refer to FIG. 2 and FIG. 4 at the same time, the ramp circuit 20121 is coupled to the voltage detection circuit 2011 for generating a rising ramp of the ramp signal VT during the positive voltage period T1 according to the voltage detection signal VD, and in the positive voltage period T1 After the voltage period T1 ends, according to the rising ramp, a falling ramp of the ramp signal VT is generated during the negative voltage period T2. The so-called positive voltage period T1 refers to the period during which the voltage difference VL1 across the inductor L1 exceeds zero voltage; while the negative voltage period T2 refers to the period during which the voltage difference VL1 across the inductor L1 does not exceed zero voltage. The comparison circuit 20122 is coupled to the ramp circuit 20121 for comparing the ramp signal with a zero-current threshold Vref1 to generate a zero-current estimation signal ZCPD, so as to determine the respective start time and end of the charging process and the at least one discharging process time.

In one embodiment, the ramp circuit 20121 may include a boost circuit 20121a and a step-down circuit 20121b. The boosting circuit 20121a is used to continuously boost the voltage across a ramp capacitor from zero during the positive voltage period T1 to generate a rising ramp. The step-down circuit 20121b is used to continuously step down the voltage across the ramp capacitor after the positive voltage period T1 ends to generate the down ramp. The boost circuit 20121a and the step-down circuit 20121b both output the cross-voltage VT of the ramp capacitor to the comparison circuit 20122 when the ramp capacitor is boosted or stepped down, for the comparison circuit 20122 to compare with the zero current threshold Vref1 . In one embodiment, the absolute values of the slopes of the rising ramp and the falling ramp are the same, so that as long as the positive voltage period T1 is measured, it can be estimated that twice the positive voltage period 2*T1 is the point at which zero current occurs. In one embodiment, the zero current threshold Vref1 is close to zero. In a preferred embodiment, the level of the zero current threshold Vref1 can be adjusted, such as increasing or decreasing, to adjust the preset period for advancing or delaying the non-conductive switch to achieve zero voltage switching (zero voltage switching). voltage switch, ZVS).

6 is a schematic circuit diagram showing a timer in a resonant switching power converter according to another embodiment of the present invention. The timer 3012 in this embodiment is an embodiment of the timer 2012 in FIG. 2 . The embodiment of FIG. 6 is an example of a digital timer. In one embodiment, the timer 3012 may include a counting circuit 30121 and a judging circuit 30122 . The counting circuit 30121 is coupled to the voltage detecting circuit 2011, and is used for generating a counting signal CNT according to the voltage detecting signal VD and a clock signal CLK, and the counting signal CNT represents the number currently counted. The determination circuit 30122 is coupled to the counting circuit 30121 for generating a zero current estimation signal ZCPD and a reset signal RESET according to the counting signal CNT, and generating an up-counting signal UP and a down-counting signal DN according to the voltage detection signal VD. When the judging circuit 30122 detects that the voltage detection signal VD is a high-level signal, an up-counting signal UP is generated to feed back to the counting circuit 30121, so that the counting circuit 30121 counts up from zero according to the speed of a clock signal CLK and The counted number is output to the judgment circuit 30122 as a count signal CNT. When the judging circuit 30122 detects that the voltage detection signal VD is switched to a low level signal, the judging circuit 30122 generates a digital signal DN to feed back to the counting circuit 30121, so that the number counted by the counting circuit 30121 from the last counts according to the clock signal The speed of CLK counts down. When the judging circuit 30122 detects that the counting signal CNT is zero, and when the judging circuit 30121 counts down to zero, it generates the zero current estimation signal ZCPD and at the same time generates a reset signal RESET to feed back to the counting circuit 30121 for The counter circuit 30121 is reset.

7 is a circuit schematic diagram showing a zero current estimation circuit in a resonant switching power converter according to yet another embodiment of the present invention. The zero current estimation circuit 201 of FIG. 7 is an embodiment of the zero current estimation circuit 201 of FIG. 2 . The timer 2012 of FIG. 7 is another example of an analog timer. As shown in FIG. 7 , the zero current estimation circuit 201 may include a voltage detection circuit 2011 and a timer 2012 . The voltage detection circuit 2011 is, for example, a comparator for detecting the voltage difference VL1 across the inductor L1. As shown in FIG. 7 , the timer 2012 may include a ramp circuit 20121 and a comparison circuit 20122 . The comparison circuit 20122 is used for comparing the voltage VT of the high voltage side node of the ramp capacitor C with a zero current threshold Vref1 or Vref2. The non-inverting input terminal of the comparison circuit 20122 is coupled to the zero current threshold Vref1 via the switch S3, and is coupled to the zero current threshold Vref2 via the switch S4. In one embodiment, the zero current threshold Vref1 is a positive value, and the zero current threshold is a negative value. When the signal related to the charging operation signal GA is at a high level, the switch S3 is turned on, and when the signal related to the discharging operation signal GB is at a high level, the switch S4 is turned on. When the signal related to the charging operation signal GA is at a high level and the voltage VT is less than the zero current threshold Vref1, the comparison circuit 20122 generates a zero current estimation signal ZCPD. When the signal related to the discharge operation signal GB is at a high level and the voltage VT is less than the zero current threshold Vref2, the comparison circuit 20122 generates a zero current estimation signal ZCPD.

The ramp circuit 20121 may include a boost circuit 20121a and a step-down circuit 20121b. The boost circuit 20121a may include a first switch S1 and a first current source Is1. The first switch S1 is used for charging the ramp capacitor C according to the voltage detection signal VD during the positive voltage period T1. . The step-down circuit 20121b may include a second switch S2 and a second current source Is2. The second switch S2 is used to discharge the ramp capacitor C from the second current source Is2 during the negative voltage period T2 after the positive voltage period T1 ends. . The timer 2012 may further include a reset switch Sr, which is connected in parallel with the ramp capacitor C to discharge the voltage across the ramp capacitor C to zero voltage after the zero current estimation signal ZCPD is generated. Since one end of the ramp capacitor C is coupled to the high voltage side node and the other end is coupled to the ground potential, the voltage VT of the high voltage side node is equivalent to the voltage across the ramp capacitor C. In one embodiment, the first current source Is1 and the second current source Is2 may be bias current sources.

When the voltage detection circuit 2011 detects that the voltage difference (VLa-VLb) between the left-side voltage VLa of the inductor and the right-side voltage VLb of the inductor is positive, a high-level voltage detection signal VD is generated, so that the first switch S1 is turned on, prompting the first current source Is1 to charge the ramp capacitor C, so that the voltage VT continues to rise from zero, and the high-level voltage detection signal VD generates a low-level operation result through the inverse logic operation of the flip gate 20123 , so that the second switch S2 is not turned on. When the voltage detection circuit 2011 detects that the voltage difference (VLa-VLb) between the two ends of the inductor L1 is negative, a low-level voltage detection signal VD is generated, so that the first switch S1 is not turned on, and the low-level voltage detection signal VD is generated. The test signal VD generates a high-level operation result through the inverse logic operation of the reverse gate 20123, so that the second switch S2 is turned on, and the second current source Is2 discharges the ramp capacitor C through the ground potential, thereby causing the voltage VT to continuously drop. When the comparison circuit 20122 compares that the voltage VT is less than the zero current threshold Vref1 (when the signal related to the charging operation signal GA is at a high level), a zero current estimation signal ZCPD is generated for the controller 202 to generate the charging operation signal GA and the discharging operation Signal GB. In one embodiment, the zero current threshold Vref1 or Vref2 approaches zero. In one embodiment, the level of the zero current threshold Vref1 or Vref2 can be adjusted, such as increasing or decreasing, to adjust the preset period for advancing or delaying the non-conductive switch to achieve zero voltage switching. switch, ZVS). In one embodiment, the magnitude of the current of the first current source Is1 is equal to the magnitude of the current of the second current source Is2, so that the positive voltage period T1 in FIG. 4 is equal to the negative voltage period T2.

Please refer to FIG. 4 , which is a schematic diagram of related signal waveforms according to the present invention. The inductor current IL1 , the inductor voltage VL1 , the voltage detection signal VD, the voltage VT, the zero current estimation signal ZCPD, the charging operation signal GA and the discharging operation signal GB are shown in FIG. 4 .

8A is a schematic circuit diagram showing a resonant switching power converter according to yet another embodiment of the present invention. The configurations of the zero-current estimation circuit 601 , the voltage detection circuit 6011 , and the timer 6012 in FIG. 8A are similar to those in FIG. 2 , so they are not described in detail. The difference between this embodiment and the embodiment of FIG. 2 is that the number of capacitors and switches is different, and the controller 602 includes a delay circuit 6021 for making the zero current estimation signal ZCPD last for a delay time Td, so that the charging process and the At least one discharge procedure is separated from each other by the delay time Td. As shown in FIG. 8A , the resonant switching power converter 60 of the present invention includes capacitors C1 , C2 , C3 , switches Q1 , Q2 , Q3 , Q4 , Q5 , Q6 , Q7 , Q8 , Q9 , Q10 , and an inductor L1 . The switches Q1-Q3 are respectively connected in series with the corresponding capacitors C1-C3, and the switch Q4 is connected in series with the inductor L1. It should be noted that the number of capacitors in the resonant switching power converter of the present invention is not limited to three in this embodiment, but can also be two or more than four. The number of components shown in this embodiment is only for illustration. The present invention is not intended to limit the present invention. It should be appreciated that, in one embodiment, the timer 6012 of this embodiment can also be implemented with the timer architecture of FIG. 3 , FIG. 4 or FIG. 5A . In one embodiment, the inductor L1 can be a variable inductor.

As shown in FIG. 8A , one end of the switch Q5 is coupled to the node between the switch Q1 and the capacitor C1, one end of the switch Q6 is coupled to the node between the switch Q2 and the capacitor C2, and one end of the switch Q7 is coupled to the switch Q3 and capacitor C3. One end of the switch Q8 is coupled to the node between the capacitor C1 and the switch Q2, one end of the switch Q9 is coupled to the node between the capacitor C2 and the switch Q3, and one end of the switch Q10 is coupled to the node between the capacitor C3 and the switch Q4. node. As shown in FIG. 6 , after the other ends of the switches Q5-Q7 are electrically connected to a node in common, they are coupled to the node between the switch Q4 and the inductor L1, and the other ends of the switches Q8-Q10 are commonly coupled to the ground potential. The other end of the inductor L1 is coupled to the output voltage Vout, and the other end of the switch Q1 is coupled to the input voltage Vin.

The switches Q1-Q10 can switch the electrical connection relationship between the corresponding capacitors C1-C3 and the inductor L1 according to the charging operation signal GA and the discharging operation signal GB generated by the controller 602 . In a charging process, according to the charging operation signal GA, the switches Q1-Q4 are turned on, and the switches Q5-Q10 are turned off, so that the capacitors C1-C3 are connected in series with each other and the inductor L1 is connected in series between the input voltage Vin and the output voltage Vout. to form a charging path. In a discharge process, according to the discharge operation signal GB, the switches Q5-Q10 are turned on, and the switches Q1-Q4 are turned off, so that the capacitor C1, the capacitor C2 and the capacitor C3 are connected in parallel with each other and the inductor L1 is connected in series to form a complex discharge path. It should be noted that, the above-mentioned charging process and the above-mentioned discharging process are repeatedly performed in different time periods, but are not performed simultaneously. Wherein, each of the charging process and the plurality of discharging processes are repeatedly interleaved with each other to convert the input voltage Vin into the output voltage Vout. In this embodiment, the DC bias voltage of each of the first capacitors C1, C2, and C3 is Vo, so the first capacitors C1, C2, and C3 in this embodiment need to withstand a lower rated voltage, so a relatively low voltage can be used. Small size capacitors.

In one embodiment, since the zero current estimation signal ZCPD is generated when the current of the charging inductor L3 or the discharging inductor L2 approaches zero, in other words, the charging operation signal also approaches zero when the current of the charging inductor L3 or the discharging inductor L2 Level switching is performed at the time of switching, whereby the switch can be switched when the current flowing through the switch is at a relatively low level of the positive half-wave, so as to achieve flexible switching. In a preferred embodiment, zero current switch (ZCS) can be achieved.

In one embodiment, in the charging process, by turning off the switches Q1-Q4 in advance, due to the characteristic of the inductor L1 resisting the rapid change of current, the switches Q1-Q4 still maintain a small current after they are turned off, flowing through the inductor L1, Therefore, the accumulated charges of the parasitic capacitance stored in the switch Q10 can be taken away through the parasitic diode of the switch Q4, thereby reducing the cross-voltage of the switch Q10, so as to achieve flexible switching. In a preferred embodiment, the level of the zero current threshold is adjusted to adjust the preset period to achieve zero voltage switch (ZVS). In one embodiment, relatively, during the discharge process, the switches Q5-Q10 are not turned on after a predetermined period of time, that is, the switches Q5-Q10 are kept on during the predetermined period, so that the discharge current flows in the reverse direction through the inductor L1. (negative current) will charge the parasitic capacitance of switch Q1 through the parasitic diode of switch Q5, and reduce the cross-voltage of switch Q1 to achieve flexible switching. In a preferred embodiment, the level of the zero current threshold is adjusted to adjust the preset period to achieve zero voltage switch (ZVS).

In one embodiment, the resonant switching power converter 60 can be a bidirectional resonant switching power converter. In one embodiment, the voltage conversion ratio of the input voltage Vin to the output voltage Vout of the resonant switching power converter 60 may be 4:1, 3:1 or 2:1. In one embodiment, the voltage conversion ratio of the resonant switching power converter 60 can be flexibly adjusted, for example, by selectively keeping switch Q7 on and switches Q10 and Q4 off during charging and discharging procedures. When turned on, the voltage conversion ratio of the resonant switching power converter 60 can be adjusted to 3:1. Similarly, for example, the switch Q6 can be selected to be turned on, and the switches Q9, Q3, Q7, Q10, and Q4 can be selected to be non-conductive, so that the voltage conversion ratio of the resonant switching power converter 60 can be adjusted to 2:1.

In addition, FIG. 8B shows a schematic diagram of signal waveforms of the resonant switching power converter 60 shown in FIG. 8A . As shown in FIG. 8B , the current threshold Vref1 is adjusted so that the voltage VT is less than the zero current threshold Vref1 at a preset time Tz before the time point t4 when the voltage VT drops to zero voltage, at the time point t3, and the zero current estimation signal ZCPD is generated. (That is, the zero-current estimation signal ZCPD is switched from a low level to a high level), so as to achieve the aforementioned flexible switching, thereby achieving zero-voltage switching. And starting from the time point t3 when the zero current estimation circuit 601 generates the zero current estimation signal ZCPD, the zero current estimation signal ZCPD continues for a delay time Td (that is, the zero current estimation signal ZCPD is maintained at a high level), during the delay time Td, The voltage detection signal VD is kept at a low level, and the charge operation signal GA and the discharge operation signal GB are kept at a low level, so the first switch S1 is kept off, the second switch S2 is kept on, and the switches Q1-Q10 are kept off.

In one embodiment, when the zero current estimation circuit 601 estimates the charging resonant current IL1 to be zero at the time point t4 and ahead of a predetermined time Tz, at the time point t3, the zero current estimation signal ZCPD is generated, and the zero current estimation signal ZCPD is kept at a high level. Exactly after the time point t4, a delay time Td, and at the end time point t5 of the delay time Td, the discharge operation signal GB is switched to a high level to perform the discharge process. When the zero current estimation circuit 601 estimates the discharge resonant current IL1 to be zero at the time point t7 and delays a predetermined time Ty, at the time point t8, the zero current estimation signal ZCPD is generated, and the zero current estimation signal ZCPD is kept at a high level after the time point t8 , a delay time Td, and at the end time point t9 of the delay time Td, the charging operation signal GA is switched to a high level to perform the charging process. The delay time Td can be used to prevent the overlapping of the charging process and the discharging process. As shown in FIG. 8B , since the absolute values of the slopes of the rising slope and the falling slope of the voltage VT are equal, the positive voltage period T1 is equal to the negative voltage period T2 .

FIG. 9 is a schematic circuit diagram showing a resonant switching power converter according to yet another embodiment of the present invention. The configurations of the zero current estimation circuit 701 , the voltage detection circuit 7011 , the timer 7012 , and the controller 702 in FIG. 9 are similar to those in FIG. 2 , so they are not repeated here. The difference between this embodiment and the embodiment of FIG. 2 is that the number of capacitors and switches is different, and this embodiment uses a charging inductor L3 and a discharging inductor L2, so the zero current estimation circuit 701 is respectively coupled to the charging inductor L3 and discharge inductance L2 are used to estimate a time point when the charging resonant current is zero during a charging process and/or a discharge resonance during a discharging process according to the voltage difference between the two ends of the charging inductance L3 and the discharging inductance L2, respectively. When the current is zero, a zero current estimation signal ZCPD is correspondingly generated for generating the charging operation signal GA and the discharging operation signal GB. In this embodiment, a plurality of capacitors share a charging inductor or a discharging inductor, so that no matter how many capacitors there are, only one charging inductor and one discharging inductor are needed, which can further reduce the number of inductors. As shown in FIG. 7 , the resonant switching power converter 70 of the present invention includes capacitors C1, C2, C3, switches Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, a charging inductor L3, a discharge Inductor L2. The switches Q1-Q3 are respectively connected in series with the corresponding capacitors C1-C3, and the switch Q4 is connected in series with the charging inductor L3. It should be noted that the number of capacitors in the resonant switching power converter of the present invention is not limited to three in this embodiment, but can also be two or more than four. The number of components shown in this embodiment is only for illustration. The present invention is not intended to limit the present invention. It should be appreciated that, in one embodiment, the timer 7012 of this embodiment can also be implemented in the timer structure of FIG. 3 or FIG. 4 . In one embodiment, the inductance value of the charging inductor L3 may be equal to the inductance value of the discharging inductor L2.

As shown in FIG. 9 , one end of the switch Q5 is coupled to the node between the switch Q1 and the capacitor C1, one end of the switch Q6 is coupled to the node between the switch Q2 and the capacitor C2, and one end of the switch Q7 is coupled to the switch Q3 and capacitor C3. One end of the switch Q8 is coupled to the node between the capacitor C1 and the switch Q2, one end of the switch Q9 is coupled to the node between the capacitor C2 and the switch Q3, and one end of the switch Q10 is coupled to the node between the capacitor C3 and the switch Q4. node. As shown in FIG. 7 , after the other ends of the switches Q5-Q7 are electrically connected to a node in common, they are connected in series to the discharge inductor L2. The other ends of the switches Q8-Q10 are commonly coupled to the ground potential. The other ends of the charging inductor L3 and the discharging inductor L2 are commonly coupled to the output voltage Vout, and the other end of the switch Q1 is coupled to the input voltage Vin.

The switches Q1-Q10 can switch the electrical connection relationship between the corresponding capacitors C1-C3 and the charging inductance L3 and the discharging inductance L2 according to the charging operation signal GA and the discharging operation signal GB generated by the controller 702 . In a charging process, according to the charging operation signal GA, the switches Q1-Q4 are turned on, and the switches Q5-Q10 are turned off, so that the capacitors C1-C3 are connected in series with each other and the charging inductor L3 is connected in series with the input voltage Vin and the output voltage Vout. between to form a charging path. In a discharge process, according to the discharge operation signal GB, the switches Q5-Q10 are turned on, and the switches Q1-Q4 are turned off, so that the capacitor C1, the capacitor C2 and the capacitor C3 are connected in parallel with each other and then the discharge inductor L2 is connected in series to form a complex discharge path. It should be noted that, the above-mentioned charging process and the above-mentioned discharging process are repeatedly performed in different time periods, but are not performed simultaneously. In a preferred embodiment, the duration of the charging procedure and the duration of the discharging procedure do not overlap with each other. Wherein, the charging procedure and the discharging procedure are repeatedly and alternately sequenced, so as to convert the input voltage Vin into the output voltage Vout. In this embodiment, the DC bias voltage of each of the first capacitors C1, C2, and C3 is Vo, so the first capacitors C1, C2, and C3 in this embodiment have the same input voltage and output as the prior art. In voltage applications, only lower rated voltages are required, so smaller capacitors can be used.

In one embodiment, the charging resonant frequency of the above-mentioned charging procedure is the same as the discharging resonant frequency of the above-mentioned discharging procedure. In one embodiment, the charging resonant frequency of the above-mentioned charging procedure is different from the discharging resonant frequency of the above-mentioned discharging procedure. In one embodiment, the resonant switching power converter 70 can be a bidirectional resonant switching power converter. The so-called bidirectional resonant switching power converter means that the roles of the input terminal (providing the input voltage Vin) and the output terminal (providing the output voltage Vout) are reversed, which means that in the embodiment shown in FIG. 7, the resonant switching power conversion The converter 70 may convert the output voltage Vout to the input voltage Vin. In one embodiment, the voltage conversion ratio of the input voltage Vin to the output voltage Vout of the resonant switching power converter 70 may be 4:1, 3:1 or 2:1.

In one embodiment, the duration of the charging process (Ton1) is related to the charging resonant frequency (fr1) of the charging process. In a preferred embodiment, the duration of the charging process (Ton1) is related to the positive half-wave of the charging resonant current during the charging process. For example, the on-time and off-time of the switches Q1-Q4 are substantially synchronized with the charging process. The start time and end time of the positive half-wave of a charging resonant current. In one embodiment, the duration of the discharge process (Ton2) is related to the discharge resonance frequency (fr2) of the discharge process. In a preferred embodiment, the duration of the discharge process (Ton2) is related to the positive half-wave of the discharge resonant current during the discharge process. For example, the on-time and off-time of the switches Q5-Q10 are substantially synchronized with the discharge process. The start time and end time of the positive half-wave of a discharge resonant current.

Since the zero current estimation signal ZCPD is generated when the current of the charging inductor L3 or the discharging inductor L2 approaches zero, in other words, the charging operation signal also performs level switching when the current of the charging inductor L3 or the discharging inductor L2 approaches zero. In this way, the current flowing through the switch can be switched at a relatively low level of the positive half-wave, so as to achieve flexible switching. In a preferred embodiment, zero current switch (ZCS) can be achieved.

In addition, it should be noted that due to the parasitic effect of the circuit components or the mutual matching between components is not necessarily ideal, therefore, although the duration of the charging process is intended to be equal to the duration of the discharging process (that is, in this embodiment The duration of the charging procedure is fifty percent of the duty cycle) to achieve zero-current switching for soft switching. However, the actual duty cycle may not be exactly 50%, but only close to 50% duty cycle. That is, according to the present invention, it is acceptable to make the charging procedure unsatisfactory due to circuit imperfections. There is a certain degree of error between the duration and the 50% duty cycle, which means that the aforementioned discharge to "substantially" means the 50% duty cycle. The same is true everywhere.

In one embodiment, the duration of the charging process is less than a certain percentage of the duty cycle for a predetermined period, for example, less than 50% of the duty cycle for a predetermined period; thereby the switches Q1-Q4 are not turned on in advance and still remain There is a tiny current flowing through the charging inductor L3. Therefore, the accumulated charge of the parasitic capacitance stored in the switch Q10 can be taken away through the parasitic diode of the switch Q4, thereby reducing the cross-voltage of the switch Q10 to achieve Flexible switching. In a preferred embodiment, the zero current threshold is adjusted to adjust the preset period to achieve zero voltage switch (ZVS). In one embodiment, relatively, the duration of the above-mentioned discharge process is longer than a certain proportion of the duty cycle for a predetermined period, for example, a predetermined period greater than 50% of the duty cycle; thereby, the switch Q5 is not turned on after a delay. - The negative current of the discharge inductor L2 after the Q10 will charge the parasitic capacitance of the switch Q1 through the parasitic diode of the switch Q5, thereby reducing the cross-voltage of the switch Q1, so as to achieve flexible switching. In a preferred embodiment, the zero current threshold is adjusted to adjust the preset period to achieve zero voltage switching.

10A and 10B are schematic diagrams showing circuits and signal waveforms of a zero current estimation circuit in a resonant switching power converter according to an embodiment of the present invention. The zero current estimation circuit 801 in FIG. 10A is an embodiment of the zero current detection circuit 701 in FIG. 9 . The configurations of the timer 8012 , the ramp circuit 80121 , the booster circuit 80121a , the step-down circuit 80121b , the comparison circuit 80122 , and the reverse gate 80123 in FIG. 10A are similar to those shown in FIG. 7 , so they will not be repeated. This embodiment is different from the embodiment of FIG. 7 in that in this embodiment, the voltage detection circuit 8011 includes two comparators 80111 and 80112, which are respectively coupled to both ends of the charging inductor L3 and the discharging inductor L2. The output terminals of the two comparators 80111 and 80112 are coupled to the input terminal of an OR gate 80113 .

During the charging process, when the comparator 80111 detects that the voltage difference (VL3a-VL3b) across the charging inductor L3 is positive, it will generate a high-level signal to the OR gate 80113, and the comparator 80112 detects the two ends of the discharging inductor L2 The voltage difference (the voltage on the left side of the discharge inductor VL2a - the voltage on the right side of the discharge inductor VL2b) is zero, so a low-level signal is generated to the OR gate 80113. The OR gate 80113 performs an OR logic operation according to the high-level signal received from the comparator 80111 and the low-level signal received from the comparator 80112 to generate a high-level voltage detection signal VD for output to the timer 8012 . When the comparator 80111 detects that the voltage difference (VL3a-VL3b) across the charging inductor L3 is negative, it will generate a low level signal to the OR gate 80113, and the comparator 80112 detects the voltage difference across the discharging inductor L2 (discharge When the voltage on the left side of the inductor VL2a - the voltage on the right side of the discharge inductor VL2b) is still zero, a low level signal is generated to the OR gate 80113. The OR gate 80113 generates a low-level voltage detection signal VD to output to the timer 8012 according to the low-level signal received from the comparator 80111 and the low-level signal received from the comparator 80112 .

During the discharging process, when the comparator 80111 detects that the voltage difference (VL3a-VL3b) across the charging inductor L3 is zero, a low-level signal is generated to the OR gate 80113, and the comparator 80112 detects that the two terminals of the discharging inductor L2 are zero. When the voltage difference between the terminals (the voltage on the left side of the discharge inductor VL2a - the voltage on the right side of the discharge inductor VL2b) is positive, a high-level signal is generated to the OR gate 80113. The OR gate 80113 performs an OR logic operation according to the low-level signal received from the comparator 80111 and the high-level signal received from the comparator 80112 to generate a high-level voltage detection signal VD for output to the timer 8012 . When the comparator 80111 detects that the voltage difference (VL3a-VL3b) across the charging inductor L3 is still zero, it will generate a low level signal to the OR gate 80113, and the comparator 80112 detects the voltage difference across the discharging inductor L2 ( When the voltage VL2a on the left side of the discharge inductor - the voltage on the right side of the discharge inductor VL2b) is negative, a low level signal is generated to the OR gate 80113. The OR gate 80113 generates a low-level voltage detection signal VD to output to the timer 8012 according to the low-level signal received from the comparator 80111 and the low-level signal received from the comparator 80112 .

10B is a schematic diagram showing signal waveforms of a zero current estimation circuit in a resonant switching power converter according to an embodiment of the present invention. The charging inductor current IL3, the charging inductor voltage VL3, the discharging inductor current IL2, the discharging inductor voltage VL2, the voltage detection signal VD, the voltage VT, the zero current estimation signal ZCPD, the charging operation signal GA, and the discharging operation signal GB are shown in FIG. 10B . As shown in FIG. 10B , a delay time T3 is delayed after the zero current estimation circuit 801 generates the zero current estimation signal ZCPD. During the delay time T3, the voltage detection signal VD is kept at a low level, the charging operation signal GA and the discharging operation are performed. The signal GB is also kept at a low level, so the first switch S1 is kept non-conductive, the second switch S2 is kept conductive, and the switches Q1-Q10 are kept non-conductive. In one embodiment, when the zero current estimation circuit 801 estimates the charging resonant current IL3 to be zero and generates the zero current estimation signal ZCPD, a delay time T3 is delayed after the time point, and the discharge operation signal GB is transmitted at the end of the delay time T3 Switch to high level signal for discharge procedure. Similarly, when the zero current estimation circuit 801 estimates the discharge resonant current IL2 to be zero and generates the zero current estimation signal ZCPD after a delay time T3, the charging operation signal GA is switched to a high level at the end of the delay time T3 quasi signal for charging process. The delay time T3 can be used to prevent the on-time overlap of the switches Q1-Q10. As shown in FIG. 10B , since the absolute values of the slopes of the rising slope and the falling slope of the voltage VT are equal, the positive voltage period T1 is equal to the negative voltage period T2 .

11 is a schematic diagram showing a circuit in a resonant switching power converter according to yet another embodiment of the present invention. The configurations of the zero current estimation circuit 901 , the voltage detection circuit 9011 , the timer 9012 , and the controller 902 in FIG. 11 are similar to those in FIG. 2 , so they are not described in detail. The difference between this embodiment and the embodiment of FIG. 2 is that the inductor L1 of this embodiment can be moved between the capacitor C1 and the switch Q2 , and the configurations of other components are similar to those of FIG. 2 , so they are not described in detail. It should be appreciated that, in one embodiment, the timer 9012 of this embodiment can also be implemented with the timer structure of FIG. 5 or FIG. 6 .

12A and 12B are schematic diagrams showing circuits and signal waveforms of a zero current estimation circuit in a resonant switching power converter according to an embodiment of the present invention. The zero current estimation circuit 1001 in FIG. 12A is an embodiment of the zero current detection circuit 901 in FIG. 11 . The configurations of the timer 10012 , the ramp circuit 100121 , the booster circuit 100121a , the step-down circuit 100121b , the comparison circuit 100122 , and the flip gate 100123 in FIG. 12A are similar to those shown in FIG. 7 , so they will not be repeated. This embodiment is different from the embodiment of FIG. 7 in that, in this embodiment, the voltage detection circuit 10011 includes a comparator 100111 and a logic circuit 100112 . The above logic circuit 100112 may include AND gates 100112a and 100112b, an anti-gate 100112c and an OR gate 100112d. And gate 10112a is coupled between OR gate 100112d and comparator 100111; and gate 100112b is coupled between OR gate 100112d and comparator 100111; and anti-gate 100112c is coupled between comparator 100111 and AND gate 100112b between.

During the charging process, when the comparator 100111 detects that the voltage difference (VLa-VLb) across the inductor L1 is positive, it will generate a high-level signal Vcp to the AND gate 100112a and the reverse gate 100112c. The AND gate 100112a performs and logic operation according to the high-level signal Vcp and the high-level charging operation signal GA received from the controller 902, and generates a high-level operation result to output to the OR gate 100112d, and the reverse gate 100112c is based on the high-level operation result. The quasi-signal Vcp performs an inverse logic operation to generate a low-level operation result, which is output to the AND gate 100112b. The AND gate 100112b generates a low-level signal according to the low-level operation result and the low-level discharge operation signal GB received from the controller 902 to output to the OR gate 100112d. The OR gate 100112d performs an OR logic operation according to the high-level operation result from the AND gate 100112a and the low-level signal from the AND gate 100112b to generate a high-level voltage detection signal VD for output to the timer 10012 . When the comparator 100111 detects that the voltage difference (VLa-VLb) across the inductor L1 is negative, a low level signal Vcp is generated to the AND gate 100112a and the reverse gate 100112c. The AND gate 100112a generates a low level signal according to the low level signal Vcp and the high level charging operation signal GA received from the controller 902 to output to the OR gate 100112d, and the reverse gate 100112c performs an inverse logic operation according to the low level signal Vcp, A high-level operation result is generated to output to the AND gate 100112b. The AND gate 100112b generates a low-level signal according to the high-level operation result and the low-level discharge operation signal GB received from the controller 902 to output to the OR gate 100112d. The OR gate 100112d generates a low-level voltage detection signal VD for output to the timer 10012 according to the low-level signal from the AND gate 100112a and the low-level signal from the AND gate 100112b.

During the discharging process, when the comparator 100111 detects that the voltage difference (VLa-VLb) across the inductor L1 is negative, a low-level signal Vcp is generated to the AND gate 100112a and the reverse gate 100112c. The AND gate 100112a generates a low level signal according to the low level signal Vcp and the low level charging operation signal GA received from the controller 902 to output to the OR gate 100112d, and the reverse gate 100112c performs an inverse logic operation according to the low level signal Vcp, A high-level operation result is generated to output to the AND gate 100112b. The AND gate 100112b performs AND logic operation according to the high-level operation result and the high-level discharge operation signal GB received from the controller 902 to generate a high-level operation result to output to the OR gate 100112d. The OR gate 100112d performs an OR logic operation according to the low-level signal from the AND gate 100112a and the high-level operation result from the AND gate 100112b to generate a high-level voltage detection signal VD for output to the timer 10012 . When the comparator 100111 detects that the voltage difference (VLa-VLb) across the inductor L1 is positive, a high-level signal Vcp is generated to the AND gate 100112a and the reverse gate 100112c. The AND gate 100112a generates a low level signal according to the high level signal Vcp and the low level charging operation signal GA received from the controller 902 to output to the OR gate 100112d, and the reverse gate 100112c performs an inverse logic operation according to the high level signal Vcp, A low-level operation result is generated to output to the AND gate 100112b. The AND gate 100112b generates a low-level signal according to the low-level operation result and the high-level discharge operation signal GB received from the controller 902 to output to the OR gate 100112d. The OR gate 100112d generates a low-level voltage detection signal VD for output to the timer 10012 according to the low-level signal from the AND gate 100112a and the low-level signal from the AND gate 100112b.

12B is a schematic diagram showing signal waveforms of a zero current estimation circuit in a resonant switching power converter according to an embodiment of the present invention. The inductor current IL1 , the inductor voltage VL1 , the signal Vcp, the voltage detection signal VD, the voltage VT, the zero current estimation signal ZCPD, the charging operation signal GA and the discharging operation signal GB are shown in FIG. 12B . As shown in FIG. 12B , a delay time T3 is delayed after the zero current estimation circuit 1001 generates the zero current estimation signal. During the delay time T3, the voltage detection signal VD remains at a low level, the charging operation signal GA and the discharging operation signal GB is also kept at a low level, so the first switch S1 is kept non-conductive, the second switch S2 is kept conductive, and the switches Q1-Q10 are kept non-conductive. In one embodiment, when the zero current estimation circuit 1001 estimates the charging resonant current IL1 to be zero and generates the zero current estimation signal ZCPD after a delay time t3, the discharge operation signal GB is output at the end of the delay time t3. Switch to high level signal for discharge procedure. Similarly, when the zero current estimation circuit 1001 estimates the discharge resonant current IL1 to be zero and generates the zero current estimation signal ZCPD after a delay time T3, the charging operation signal GA is switched to a high level at the end of the delay time T3 quasi signal for charging process. The delay time T3 can be used to prevent the overlapping of the on-periods of the switches Q1-Q10, and can adjust the ratio of the input voltage Vin to the output voltage Vout. As shown in FIG. 12B , since the absolute values of the slopes of the rising slope and the falling slope of the voltage VT are equal, the positive voltage period T1 is equal to the negative voltage period T2 .

13A and 13B are schematic diagrams showing circuits and signal waveforms in a resonant switching power converter according to yet another embodiment of the present invention. The configurations of capacitors C1-C3, charging inductor L3, discharging inductor L2, switches Q1-Q10, zero current estimation circuit 1101, voltage detection circuit 11011, timer 11012, and controller 1102 in FIG. 13A are similar to those shown in FIG. 9, so I won't go into details. The difference between this embodiment and the embodiment of FIG. 9 lies in that this embodiment divides the discharge process into a plurality of discharge processes to be performed in turn, and the controller 1102 is used for generating the charging operation signal GA, the discharging operation signals GB, GC, and GD to respectively Corresponding to a charging process and a complex discharging process, the corresponding complex switches Q1-Q10 are operated to switch the electrical connection relationship of the corresponding capacitors C1-C3. The zero current estimation circuit 1101 is coupled to the charging inductor L3 and the discharging inductor L2 for estimating a time point when the charging resonant current is zero during a charging process according to the voltage difference between the two ends of the charging inductor L3 and the discharging inductor L2, and /or at each discharge resonant current zero time point in each discharge process, a zero current estimation signal ZCPD is correspondingly generated for generating the charging operation signal GA and the complex discharge operation signals GB, GC, GD. In one embodiment, the controller 1102 can determine the start time and end time of the charging process and the discharging process according to the zero current estimation signal ZCPD, the charging operation signal GA and/or the discharging operation signals GB, GC and GD. It should be appreciated that, in one embodiment, the timer 11012 of this embodiment can also be implemented with the timer structure of FIG. 5 , FIG. 6 or FIG. 7 .

The switches Q1-Q10 can switch the electrical connection relationship between the corresponding capacitors C1-C3 and the charging inductance L3 and the discharging inductance L2 according to the charging operation signal GA and the discharging operation signal GB, GC, GD generated by the controller 1102 . In one embodiment, the charge operation signal GA and the discharge operation signals GB, GC, and GD are respectively switched to a conduction level for one conduction period, and the plurality of conduction periods do not overlap with each other.

For example, in a charging process, according to the charging operation signal GA, the switches Q1-Q4 are turned on, and the switches Q5-Q10 are turned off, so that the capacitors C1-C3 are connected in series with each other and the charging inductor L3 is connected in series with the input voltage Vin and the output voltage Vout to form a charging path. In the complex discharge procedure, according to the discharge operation signals GB, GC, GD, the switches Q5-Q10 are turned on in turn, and the switches Q1-Q4 are turned off, so that the capacitor C1, the capacitor C2 and the capacitor C3 are respectively connected in series to discharge the inductor L2, and A complex discharge path is formed. That is to say, a plurality of discharge procedures take turns to form corresponding discharge paths. For example, in the first discharge process, according to the discharge operation signal GB, the switches Q5 and Q8 are turned on, and the switches Q1-Q4, Q6-Q7 and Q9-Q10 are turned off, so that the capacitor C1 is connected in series with the discharge inductor L2 at the ground potential and the output A first discharge path is formed between the voltages Vout; in the second discharge process, according to the discharge operation signal GC, the switches Q6 and Q9 are turned on, and the switches Q1-Q5, Q7, Q8 and Q10 are turned off, so that the capacitor C2 The discharge inductor L2 is connected in series between the ground potential and the output voltage Vout to form a second discharge path; in the third discharge process, according to the discharge operation signal GD, the switches Q7 and Q10 are turned on, and the switches Q1-Q6 and Q8-Q9 are turned on. Not conducting, the capacitor C3 is connected in series with the discharge inductor L2 between the ground potential and the output voltage Vout to form a third discharge path.

It should be noted that, the above-mentioned charging procedure, the above-mentioned first discharging procedure, the second discharging procedure and the third discharging procedure are repeatedly performed in different time periods, but are not performed simultaneously. Wherein, the charging procedure and the above-mentioned three discharging procedures are repeatedly and interleaved with each other to convert the input voltage Vin into the output voltage Vout, that is, after one charging procedure is completed, the first discharging procedure, the second discharging procedure and the third discharging procedure are followed The procedures are executed in turn, followed by the charging procedure, and so on.

In this embodiment, the DC bias voltage of each of the first capacitors C1, C2, and C3 is Vo, so the first capacitors C1, C2, and C3 in this embodiment have the same input voltage and output as the prior art. In voltage applications, only lower rated voltages are required, so smaller capacitors can be used.

In one embodiment, the charging resonant frequency of the above-mentioned charging procedure is the same as the discharging resonant frequency of the above-mentioned complex discharging procedure. In one embodiment, the charging resonant frequency of the above-mentioned charging procedure is different from the discharging resonant frequency of the above-mentioned complex discharging procedure. In one embodiment, the resonant switching power converter 110 can be a bidirectional resonant switching power converter. In one embodiment, the voltage conversion ratio of the input voltage Vin to the output voltage Vout of the resonant switching power converter 110 may be 4:1, 3:1 or 2:1.

In the above embodiment, since the zero current estimation signal ZCPD is generated when the current of the charging inductor L3 or the discharging inductor L2 approaches zero, in other words, the charging operation signal also approaches zero when the current of the charging inductor L3 or the discharging inductor L2 approaches zero. The level switching is performed when the current flows through the switch, so that the current flowing through the switch can be switched at the time point when the positive half-wave is relatively lower, so as to achieve flexible switching. In a preferred embodiment, zero current switch (ZCS) can be achieved.

In one embodiment, during the charging process, the switches Q1-Q4 are not turned on for a predetermined period in advance. Due to the characteristic of the inductor L3 resisting the rapid change of current, the switches Q1-Q4 still maintain a small current even after they are turned off. Through the charging inductor L3, the accumulated charge of the parasitic capacitance stored in the switch Q10 can be discharged through the parasitic diode of the switch Q4, thereby reducing the cross-voltage of the switch Q10, so as to achieve flexible switching. In a preferred embodiment, by adjusting the predetermined period, zero voltage switching (ZVS) can be achieved. In one embodiment, relatively, during a plurality of discharge procedures, the switches Q7 and Q10 are not turned on after a predetermined period of time, that is, the switches Q7 and Q10 are kept turned on during the predetermined period, so that the discharge current flows in the reverse direction through the discharge. The inductance L2 (negative current) will charge the parasitic capacitance of the switch Q1 through the parasitic diode of the switch Q5, thereby reducing the cross-voltage of the switch Q1 to achieve flexible switching. In a preferred embodiment, the level of the zero current threshold can be adjusted to adjust the above-mentioned predetermined period to achieve zero voltage switching.

13B is a schematic diagram showing signal waveforms of a zero current estimation circuit in a resonant switching power converter according to an embodiment of the present invention. The charging inductor current IL3, the discharging inductor current IL2, the discharging inductor voltage VL2, the voltage VT, the zero current estimation signal ZCPD, and the discharging operation signal GB are shown in FIG. 13B.

FIG. 14 is a schematic diagram showing a circuit in a resonant switching power converter according to yet another embodiment of the present invention. The configurations of the zero current estimation circuit 1201 , the timer 12012 , the voltage detection circuit 12011 , and the controller 1202 in FIG. 14 are similar to those shown in FIG. 2 , so they will not be repeated. As shown in FIG. 14, the resonant switching power converter 120 of the present invention includes capacitors C1, C2, C3, switches Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, inductors L1, L2, L3. The switches Q1-Q3 are respectively connected in series with the corresponding capacitors C1-C3, and the capacitors C1-C3 are respectively connected in series with the corresponding inductors L1-L3. It should be noted that the number of capacitors in the resonant switching power converter of the present invention is not limited to three in this embodiment, but may also be two or more, and the number of inductors is not limited to three in this embodiment. , or more than two or four, the number of elements shown in this embodiment is only used to illustrate the present invention and not to limit the present invention. It should be appreciated that, in one embodiment, the timer 12012 of this embodiment can also be implemented with the timer structure of FIG. 5 , FIG. 6 or FIG. 7 .

As shown in FIG. 14, one end of switch Q5 is coupled to the node between switch Q1 and capacitor C1, one end of switch Q6 is coupled to the node between switch Q2 and capacitor C2, and one end of switch Q7 is coupled to switch Q3 and capacitor C3. One end of the switch Q8 is coupled to the node between the inductor L1 and the switch Q2, one end of the switch Q9 is coupled to the node between the inductor L2 and the switch Q3, and one end of the switch Q10 is coupled to the node between the inductor L3 and the switch Q4. node. As shown in FIG. 12, the other ends of the switches Q5-Q7 are commonly coupled to the output voltage Vout. The other ends of the switches Q8-Q10 are commonly coupled to the ground potential. The switch Q4 is coupled between the inductor L3 and the output voltage Vout, and one end of the switch Q1 is coupled to the input voltage Vin.

The switches Q1-Q10 can switch the electrical connection relationship between the corresponding capacitors C1-C3 and the inductors L1-L3 according to the charging operation signal GA and the discharging operation signal GB generated by the controller 1202 . In a charging process, according to the charging operation signal GA, the switches Q1-Q4 are turned on, and the switches Q5-Q10 are turned off, so that the capacitors C1-C3 and the inductors L1-L3 are connected in series with each other between the input voltage Vin and the output voltage Vout. to form a charging path. In a discharge process, according to the discharge operation signal GB, the switches Q5-Q10 are turned on, and the switches Q1-Q4 are turned off, so that the capacitor C1 and the corresponding inductor L1 are connected in series between the output voltage Vout and the ground potential, and the capacitor C2 and the corresponding The inductor L2 is connected in series between the output voltage Vout and the ground potential, and the capacitor C3 and the corresponding inductor L3 are connected in series between the output voltage Vout and the ground potential to form a complex discharge path. It should be noted that the above-mentioned charging procedure and the above-mentioned discharging procedure are performed alternately in different time periods, rather than being performed simultaneously. Wherein, the charging procedure and the discharging procedure are repeatedly and alternately sequenced, so as to convert the input voltage Vin into the output voltage Vout. In this embodiment, the DC bias voltage of each capacitor C1, C2, and C3 is Vo, so the capacitors C1, C2, and C3 in this embodiment need to withstand a lower rated voltage, so capacitors with smaller volume can be used. .

In one embodiment, since the zero current estimation signal ZCPD is generated when the current of the charging inductor L3 or the discharging inductor L2 approaches zero, in other words, the charging operation signal also approaches zero when the current of the charging inductor L3 or the discharging inductor L2 Level switching is performed at the time of switching, whereby the switch can be switched when the current flowing through the switch is at a relatively low level of the positive half-wave, so as to achieve flexible switching. In a preferred embodiment, zero current switch (ZCS) can be achieved.

In one embodiment, the charging process has a charging resonant frequency, and the discharging process has a discharging resonant frequency. In a preferred embodiment, the charging resonant frequency is the same as the discharging resonant frequency.

15A is a schematic diagram showing signal waveforms of corresponding operation signals and corresponding inductor currents in a charging process and a discharging process according to an embodiment of the present invention. Please also refer to FIG. 9. In the embodiment shown in FIG. 15A, the charging operation signal GA of the switches Q1-Q4 is at a high level during the charging process, and the discharging operation signal GB of the switches Q5-Q10 is at a high level during the discharging process. In the embodiment of FIG. 15A, since the zero current estimation signal ZCPD is generated when the current of the charging inductor L3 or the discharging inductor L2 approaches zero, in other words, the charging operation signal also approaches the current of the charging inductor L3 or the discharging inductor L2. The level switching is performed at zero time, whereby the switch Q1 can be switched when the current flowing through the switch is at a relatively low level of its positive half-wave, and it is also switched when the current of the charging inductor L3 is zero current to achieve flexible switching . In a preferred embodiment, zero current switching can be achieved.

15B and 15C are schematic diagrams showing signal waveforms of corresponding operation signals and corresponding inductor currents in a charging process and a discharging process according to another embodiment of the present invention. Please refer to FIG. 9 at the same time. In the embodiment shown in FIG. 15B, the charging operation signal GA of the switches Q1-Q4 is at a high level during the charging process, and the discharging operation signal GB of the switches Q5-Q10 is at a high level during the discharging process. In the embodiment of FIG. 15B , the duration of the charging process is substantially less than 50% of the duty cycle for a predetermined period Ta; thus, a small current still flows after the switches Q1-Q4 are turned off in advance. Therefore, the charging inductor L3 can discharge the accumulated charge of the parasitic capacitance stored in the switch Q10 through the parasitic diode of the switch Q4, thereby reducing the cross-voltage of the switch Q10 to achieve flexible switching. In a preferred embodiment, the level of the zero current threshold can be adjusted to adjust the preset period Ta to achieve zero voltage switching. Please refer to FIG. 9 at the same time. In the embodiment shown in FIG. 15C, the charging operation signal GA of the switches Q1-Q4 is at a high level during the charging process, and the discharging operation signal GB of the switches Q5-Q10 is at a high level during the discharging process. In the embodiment of FIG. 15C , the duration of the discharge process is approximately a predetermined period Tb greater than 50% of the duty cycle; thus, the negative current of the discharge inductor L2 will be reduced after the non-conducting switches Q5 - Q10 are delayed. The parasitic capacitance of the switch Q1 is charged through the parasitic diode of the switch Q5, thereby reducing the cross-voltage of the switch Q1, so as to achieve flexible switching. In a preferred embodiment, the level of the zero current threshold can be adjusted to adjust the preset period Tb to achieve zero voltage switching. In one embodiment, it should be noted that the embodiments of Figures 15B and 15C may be implemented together or only one of them.

FIG. 16 is a schematic diagram showing a circuit in a resonant switching power converter according to yet another embodiment of the present invention. In this embodiment, the resonant switching power converter 160 is used to convert the input voltage Vin into the output voltage Vout. The resonant switching power converter 160 includes resonant cavities RT1 and RT2 , switches Q1 - Q10 , a non-resonant capacitor Cf1 , a zero current estimation circuit 1601 and a controller 1602 .

The resonant cavity RT1 has a resonant capacitor Cr1 and a resonant inductor Lr1 connected in series with each other; the resonant cavity RT2 has a resonant capacitor Cr2 and a resonant inductor Lr2 connected in series with each other. The switches Q1-Q10 are correspondingly coupled to the resonator cavities RT1 and RT2, respectively, according to the corresponding first resonant operation signal G1 and the second resonant operation signal G2, to switch the electrical connection relationship between the corresponding resonator cavities RT1 and RT2 to correspond to the first resonant operation signal G1 and the second resonant operation signal G2 respectively. The resonance procedure and the second resonance procedure.

According to the first resonant operation signal G1 and the second resonant operation signal G2, the non-resonant capacitor Cf1 switches the electrical connection relationship with the resonant cavities RT1 and RT2, and the cross-voltage of the non-resonant capacitor Cf1 is maintained at a fixed ratio to the input voltage Vin, for example In this embodiment, it is half the input voltage Vin. The zero current estimation circuit 1601 is coupled to the resonant inductors Lr1 and Lr2 in the resonant cavities RT1 and RT2, and is used to estimate the flow through the corresponding resonant inductors during the first resonant process according to the voltage difference between the two ends of the resonant inductors Lr1 and Lr2 respectively. The time point when the first resonant current of Lr1 or Lr2 is zero, and/or the time point when the second resonant current flowing through the corresponding resonant inductor Lr1 or Lr2 is zero during the second resonance process, and the zero current estimation signal ZCPD is generated correspondingly, respectively, for generating the first resonance operation signal G1 and the second resonance operation signal G2. Wherein, the first resonance operation signal G1 and the second resonance operation signal G2 are respectively switched to the conduction period of the conduction level segment, and the plurality of conduction periods do not overlap each other, so that the first resonance process and the second resonance process do not overlap each other. . Wherein, the first resonant process and the second resonant process are repeatedly and alternately sequenced with each other, so as to convert the input voltage Vin into the output voltage Vout.

The operation of the resonant switching power converter 160 having the resonant cavities RT1 and RT2 shown in FIG. 16 is well known to those skilled in the art, and will not be repeated here. The zero current estimation circuit 1601 of this embodiment can also be implemented with the zero current estimation circuit structure shown in FIG. 7 , FIG. 10A or FIG. 12A . The timer 16012 of this embodiment can also be implemented with the timer structure of FIG. 5 or FIG. 6 .

The controller 1602 is coupled to the zero current estimation circuit 1601 for generating a first resonance operation signal G1 and a second resonance operation signal G2 respectively according to the zero current estimation signal ZCPD for switching the switches Q1 - Q10 . In one embodiment, the controller 1602 may determine the respective start time and end time of the first resonance process and the second resonance process according to the zero current estimation signal ZCPD, the first resonance operation signal G1 and/or the second resonance operation signal G2 .

The present invention provides a resonant switching power converter as described above, which can reduce inrush current through special circuit design, and can perform zero current estimation from inductor or capacitor to achieve zero current switching (ZCS) or zero voltage switching. (ZVS) flexible switching to improve power efficiency, eliminate the need for current sensing resistors or current sensing transformers, reduce the power loss of current sensing resistors due to high currents, and solve the problem of large current sensing resistors at low currents exact question.

It should be noted that the "high level" and "low level" mentioned in the foregoing embodiments are only examples, and are not intended to limit the scope of the present invention. In other embodiments, the foregoing "high level" and "low level" ”, under the same spirit of the present invention as described above, it can be adaptively at least partially adjusted or exchanged according to the actual switch type and logic basis used.

The present invention has been described above with respect to the preferred embodiments, but the above descriptions are only intended to make the content of the present invention easy for those skilled in the art to understand, and are not intended to limit the broadest scope of rights of the present invention. The described embodiments are not limited to be used alone, but can also be used in combination. For example, two or more embodiments can be used in combination, and some components in one embodiment can also be used to replace those in another embodiment. corresponding components. In addition, under the same spirit of the present invention, those skilled in the art can think of various equivalent changes and various combinations. According to the signal itself, when necessary, the signal is subjected to voltage-to-current conversion, current-to-voltage conversion, and/or ratio conversion, etc., and then processed or calculated according to the converted signal to generate an output result. It can be seen from this that under the same spirit of the present invention, those skilled in the art can think of various equivalent changes and various combinations, and there are many combinations, which are not listed and described here. Accordingly, the scope of the present invention should cover the above and all other equivalent changes.

20, 60, 70, 90, 110, 120, 160: Resonant Switching Power Converters 201, 301, 601, 701, 901, 1001, 1101, 1201, 1601: Zero Current Estimation Circuits 2011, 3011, 6011, 7011, 8011, 9011, 10011, 11011, 12011, 126011: Voltage detection circuit 2012, 3012, 6012, 7012, 8012, 9012, 10012, 11012, 12012, 16012: Timers 20121, 80121, 100121: Ramp circuit 20121a, 80121a, 100121a: Boost Circuits 20121b, 80121b, 100121b: Buck Circuits 20122, 80122, 100122: Comparison circuits 20123, 80123, 100112c, 100123: back gate 202, 602, 702, 902, 1102, 1202, 1602: Controllers 30121: Counting Circuit 30122: Judgment Circuit 80111, 80112, 100111: Comparator 80113, 100112d: or gate 100112: Logic Circuits 100112a, 100112b: and gate C: Ramp Capacitance C1~C3: Capacitors Cf1: non-resonant capacitor CLK: clock signal CNT: count signal Co: output capacitance Cr1, Cr2: Resonant capacitors DN: count down signal G1: The first resonance operation signal G2: Second resonance operation signal GA: Charging operation signal GB, GC, GD: Discharge operation signal IL1: Inductor current (charge resonant current/discharge resonant current) IL2: Discharge inductor current (discharge resonance current) IL3: Charging inductor current (charging resonance current) Is1: first current source Is2: second current source L1: Inductance L2: Discharge Inductance L3: charging inductor Lr1, Lr2: resonant inductance Q1~Q10: switch RESET: reset signal RL: load resistance RT1, RT2: Resonator S1: first switch S2: Second switch Sr: reset switch T1: During positive voltage T2: During negative voltage T3, Td: delay time Ta, Tb, Tc: period t0, t1, t2, t3, t4: time points UP: count up signal Vcp: signal VD: Voltage detection signal Vin: input voltage VL1: Inductor voltage (voltage difference) VL2: discharge inductor voltage VL2a: Voltage on the left side of the discharge inductor VL2b: Right side voltage of discharge inductor VL3: charging inductor voltage VL3a: Left side voltage of charging inductor VL3b: Right side voltage of charging inductor VLa: Voltage on the left side of the inductor VLb: Voltage on the right side of the inductor Vout: output voltage Vref1: zero current threshold VT: voltage (cross voltage) ZCPD: Zero Current Estimation Signal

FIG. 1 shows a conventional power converter.

FIG. 2 is a schematic circuit diagram showing a resonant switching power converter according to an embodiment of the present invention.

FIG. 3 is a schematic circuit diagram showing another resonant switching power converter according to an embodiment of the present invention.

FIG. 4 is a schematic diagram of signal waveforms according to the embodiment shown in FIGS. 2 and 3 of the present invention.

5 is a schematic circuit diagram showing a timer in a resonant switching power converter according to an embodiment of the present invention.

6 is a schematic circuit diagram showing a timer in a resonant switching power converter according to another embodiment of the present invention.

7 is a circuit schematic diagram showing a zero current estimation circuit in a resonant switching power converter according to yet another embodiment of the present invention.

8A and 8B are schematic circuit diagrams and signal waveform diagrams showing a resonant switching power converter according to still another embodiment of the present invention.

FIG. 9 is a schematic circuit diagram showing a resonant switching power converter according to yet another embodiment of the present invention.

10A and 10B are schematic diagrams showing circuits and signal waveforms of a zero current estimation circuit in a resonant switching power converter according to an embodiment of the present invention.

11 is a schematic diagram showing a circuit in a resonant switching power converter according to yet another embodiment of the present invention.

12A and 12B are schematic diagrams showing circuits and signal waveforms of a zero current estimation circuit in a resonant switching power converter according to an embodiment of the present invention.

13A and 13B are schematic diagrams showing circuits and signal waveforms in a resonant switching power converter according to yet another embodiment of the present invention.

FIG. 14 is a schematic diagram showing a circuit in a resonant switching power converter according to yet another embodiment of the present invention.

15A , 15B and 15C are schematic diagrams showing signal waveforms of corresponding operation signals and corresponding inductor currents in a charging process and a discharging process according to an embodiment of the present invention.

FIG. 16 is a schematic diagram showing a circuit in a resonant switching power converter according to yet another embodiment of the present invention.

20: Resonant Switching Power Converters 201: Zero Current Estimation Circuit 2011: Voltage Detection Circuit 2012: Timer 202: Controller C1: Capacitor Co: output capacitance GA: Charging operation signal GB: Discharge operation signal IL1: Inductor current (charge resonant current/discharge resonant current) L1: Inductance Q1~Q4: switch RL: load resistance VD: Voltage detection signal Vin: input voltage VL1: Inductor voltage (voltage difference) Vout: output voltage ZCPD: Zero Current Estimation Signal

Claims (30)

A resonant switching power converter for converting an input voltage into an output voltage, the resonant switching power converter comprising: at least one capacitor; a plurality of switches, which are correspondingly coupled to the at least one capacitor, and respectively switch the electrical connection relationship of the corresponding capacitor according to a corresponding one of the operation signals; at least one charging inductor, correspondingly connected in series with at least one of the at least one capacitor; at least one discharge inductor, correspondingly connected in series with at least one of the at least one capacitor; and a zero-current estimation circuit, coupled to the at least one charging inductor and/or the at least one discharging inductor, and/or the capacitor, and used for determining the voltage difference between the two ends of the charging inductor and/or the voltage difference between the two ends of the discharging inductor The voltage difference, and/or the voltage difference across the capacitor, to estimate the time point when a charging resonant current is zero during a charging process, and/or a corresponding time point when at least one discharging resonant current is zero during at least one discharging process , and correspondingly generate a zero current estimation signal for generating the operation signal; Wherein, the operation signal includes a charge operation signal and at least one discharge operation signal, which are respectively switched to a conduction level for a conduction period, and the plurality of conduction periods do not overlap each other, so that the charging process and the at least one discharging process are performed. do not overlap each other; Wherein, in the charging process, the switching of the plurality of switches is controlled by the charging operation signal, so that the at least one capacitor and the at least one charging inductor are connected in series between the input voltage and the output voltage to form a charging path, to resonantly charge the capacitor and the charging inductor; Wherein, in the at least one discharge procedure, the switching of the plurality of switches is controlled by the at least one discharge operation signal, so that each of the capacitors and the corresponding discharge inductance are connected in series between the output voltage and a ground potential, and simultaneously form Or alternately form complex discharge paths to resonantly discharge the capacitor and the charging inductance; Wherein, the charging procedure and the at least one discharging procedure are repeatedly and alternately sequenced with each other, so as to convert the input voltage into the output voltage. The resonant switching power converter of claim 1, wherein the zero current estimation circuit comprises: a voltage detection circuit for generating a voltage detection signal according to the voltage difference between the two ends of the charging inductor and/or the voltage difference between the two ends of the discharging inductor to indicate the voltage difference between the two ends of the charging inductor and/or The voltage difference across the discharge inductor exceeds a positive voltage period of zero voltage; and A timer, coupled to the output end of the voltage detection circuit, is used for generating the zero current estimation signal according to the voltage detection signal. The resonant switching power converter of claim 1, wherein the zero current estimation circuit includes a voltage detection circuit for generating a voltage detection signal according to the voltage difference between the two ends of the capacitor to indicate the capacitor A peak time point of the peak value of the voltage difference between the two ends, and a valley value time point of the bottom value thereof, and the zero current estimation signal is generated accordingly. The resonant switching power converter of claim 2, wherein the timer comprises: a ramp circuit for generating a rising ramp of a ramp signal during the positive voltage period according to the voltage detection signal, and generating a descending ramp of the ramp signal according to the rising ramp after the positive voltage period ends ;as well as A comparison circuit is used for comparing the ramp signal with a zero current threshold to generate the zero current estimation signal to determine the respective start time and end time of the charging process and the at least one discharging process. The resonant switching power converter of claim 4, wherein the ramp circuit comprises: a boosting circuit for continuously boosting the voltage across a ramp capacitor from zero during the positive voltage period to generate the rising ramp; and a step-down circuit for continuously reducing the voltage across the ramp capacitor after the positive voltage period ends to generate the down ramp; The absolute values of the slopes of the rising slope and the falling slope are the same. The resonant switching power converter of claim 5, wherein the boost circuit comprises a first switch and a first current source, wherein the first switch is used for detecting the signal according to the voltage during the positive voltage period The ramp capacitor is charged by the first current source. The resonant switching power converter of claim 6, wherein the step-down circuit includes a second switch and a second current source, wherein the second switch is used to enable the second switch after the positive voltage period ends. The current source discharges the ramp capacitor. The resonant switching power converter of claim 1, further comprising a controller coupled to the zero current estimation circuit for generating the charging operation signal and the at least one discharging operation according to the zero current estimation signal signal. The resonant switching power converter of claim 8, wherein the controller includes a delay circuit for maintaining the zero current estimation signal for a delay time so that the charging process and the at least one discharging process are spaced from each other by the segment delay time. The resonant switching power converter of claim 2, wherein the voltage detection circuit comprises at least one comparator for correspondingly comparing the voltage across the charging inductor and/or the voltage across the discharging inductor. The resonant switching power converter of claim 10, wherein the at least one comparator is two comparators, one of the two comparators is coupled to both ends of the charging inductor, and the two comparators are The other one is coupled to both ends of the discharge inductor. The resonant switching power converter as claimed in claim 5, wherein the timer further comprises a reset switch connected in parallel with the ramp capacitor for voltage across the ramp capacitor after the zero current estimation signal is generated , discharge to zero voltage. The resonant switching power converter of claim 9, wherein the plurality of switches remain non-conductive during the delay time. The resonant switching power converter of claim 1, wherein the at least one charging inductor is a single charging inductor, and the at least one discharging inductor is a single discharging inductor. The resonant switching power converter of claim 1, wherein the at least one charging inductor and the at least one discharging inductor are a single same inductor. The resonant switching power converter of claim 1 or 14, wherein the charging process has a charging resonant frequency, and the discharging process has a discharging resonant frequency, and the charging resonant frequency is the same as the discharging resonant frequency. The resonant switching power converter of claim 1 or 14, wherein the charging process has a charging resonant frequency, and the discharging process has a discharging resonant frequency, and the charging resonant frequency is different from the discharging resonant frequency. The resonant switching power converter as claimed in claim 4, wherein the timer adjusts the level of the zero-current threshold to shorten or extend the on-period to a zero-voltage period, so that the corresponding switch achieves flexible switching ( soft switching) zero voltage switching. The resonant switching power converter of claim 1, wherein the resonant switching power converter is a bidirectional resonant switching power converter. The resonant switching power converter of claim 1, wherein a voltage conversion ratio of the input voltage to the output voltage of the resonant switching power converter is 4:1, 3:1 or 2:1. The resonant switching power converter as claimed in claim 2, wherein the timer comprises a counting circuit and a judging circuit, and when the voltage detection signal is switched from a low level to a high level, the counting circuit according to a clock The signal starts to count, and the counted result is output to the judgment circuit, and when the voltage detection signal is switched from high level to low level, the counting circuit counts back from the last count result according to the clock signal, and the judgment The circuit generates the zero current estimation signal when the counting circuit counts down to zero or a count threshold. The resonant switching power converter as claimed in claim 21, wherein the determination circuit outputs a reset signal to the counting circuit to reset the counting circuit after generating the zero current estimation signal. A resonant switching power converter for converting an input voltage into an output voltage, the resonant switching power converter comprising: at least one resonant cavity, the resonant cavity has a resonant capacitor and a resonant inductance connected in series with each other; A plurality of switches are correspondingly coupled to the at least one resonant cavity, respectively according to a corresponding first resonant operation signal and a second resonant operation signal to switch the electrical connection relationship of the corresponding resonant cavity to correspond to a first resonant procedure and a second resonance procedure, wherein in the first resonance procedure, the corresponding resonant cavity is resonantly charged, and in the second resonance procedure, the corresponding resonant cavity is resonantly discharged; At least one non-resonant capacitor is used for switching the electrical connection relationship with the at least one resonant cavity according to the first resonant operation signal and the second resonant operation signal, and the voltage across the non-resonant capacitor is maintained to be one with the input voltage fixed scale; and a zero-current estimation circuit, coupled to the resonant inductor in the at least one resonant cavity, for estimating one of the corresponding resonant inductors flowing through the resonant inductor during the first resonant process according to the voltage difference between the two ends of the resonant inductor The time point when the first resonant current is zero, and/or the time point when a second resonant current flowing through the corresponding resonant inductor during the second resonant process is zero, and respectively generate a zero current estimation signal for use in generating the first resonance operation signal and the second resonance operation signal; Wherein, the first resonant operation signal and the second resonant operation signal are respectively switched to a conduction level for a conduction period, and the plurality of conduction periods do not overlap each other, so that the first resonance process and the second resonance process procedures do not overlap each other; Wherein, the first resonant process and the second resonant process are repeatedly and alternately sequenced with each other, so as to convert the input voltage into the output voltage. The resonant switching power converter of claim 23, wherein the zero current estimation circuit comprises: a voltage detection circuit for generating a voltage detection signal according to the voltage difference between the two ends of the resonant inductor to indicate that the voltage difference between the two ends of the resonant inductor exceeds a positive voltage period of zero voltage; and A timer is coupled to the output end of the voltage detection circuit and used for generating the zero current estimation signal according to the voltage detection signal. The resonant switching power converter of claim 24, wherein the timer comprises: a ramp circuit for generating a rising ramp of a ramp signal during the positive voltage period according to the voltage detection signal, and generating a descending ramp of the ramp signal according to the rising ramp after the positive voltage period ends ;as well as A comparison circuit is used for comparing the ramp signal with a zero current threshold to generate the zero current estimation signal to determine the respective start time and end time of the charging process and the at least one discharging process. The resonant switching power converter of claim 25, wherein the ramp circuit comprises: a boosting circuit for continuously boosting the voltage across a ramp capacitor from zero during the positive voltage period to generate the rising ramp; and a step-down circuit for continuously reducing the voltage across the ramp capacitor after the positive voltage period ends to generate the down ramp; The absolute values of the slopes of the rising slope and the falling slope are the same. The resonant switching power converter of claim 26, wherein the boost circuit comprises a first switch and a first current source, wherein the first switch is used for detecting the signal according to the voltage during the positive voltage period The ramp capacitor is charged by the first current source. The resonant switching power converter of claim 27, wherein the step-down circuit includes a second switch and a second current source, wherein the second switch is used to enable the second switch after the positive voltage period ends. The current source discharges the ramp capacitor. The resonant switching power converter of claim 23, further comprising a controller coupled to the zero-current estimation circuit for generating the first resonant operation signal and the second resonant operation signal according to the zero-current estimation signal Resonant operation signal. The resonant switching power converter of claim 29, wherein the controller includes a delay circuit for maintaining the zero current estimation signal for a delay time so that the first resonant process and the second resonant process are mutually exclusive interval of this delay time.

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