CN115765406A - Buck-boost converter and control circuit and control method thereof - Google Patents

Abstract

The invention discloses a buck-boost converter and a control circuit and a control method thereof. The control circuit includes: the current sampling circuit detects the current flowing through the inductor and generates a current sampling signal; the average current limiting circuit compares the current sampling signal with a set bias current to generate a current clamping signal; a PWM comparator comparing a feedback signal of the output voltage with a first reference voltage to generate a pulse width modulation signal; and the logic circuit controls the conduction time of the first power switch in each switching period according to the current clamping signal and the pulse width modulation signal. The logic circuit controls the first power switch to be switched on only when the pulse width modulation signal is in a logic high state and the current clamping signal is in a logic low state in each switching period, and the current in the inductor can be controlled without arranging an operational amplifier and a large RC network in the circuit for filtering and shaping, so that the response speed is higher, and the input average current can be quickly limited.

Description

Buck-boost converter and control circuit and control method thereof

Technical Field

The invention relates to the technical field of power conversion, in particular to a buck-boost converter, a control circuit and a control method thereof.

Background

Modern portable electronic devices are often provided with a power source, such as a battery, which is used as a Direct Current (DC) for various electronic components within the device. However, typically these components will have different voltage requirements, and therefore such devices typically employ one or more voltage converters that reduce the nominal voltage associated with the power supply to a voltage suitable for the different electronic components.

Existing DC/DC converters with wide input voltage include cascaded buck-boost converters, H-bridge buck-boost converters, cuk converters, and SEPIC (Single end Primary inductor Converter) structures. Among them, H-bridge buck-boost converters (single inductor or non-inverting buck-boost converters) have good performance.

Fig. 1 shows a schematic circuit diagram of a buck-boost converter according to the prior art. As shown in fig. 1, the buck-boost converter of the prior art includes a control circuit 100 and an external power circuit. Wherein the power circuit includes one or more switch and filter elements (e.g., inductors and capacitors, etc.) configured to regulate power transfer from the power converter input to the output in response to one or more switch drive signals from the control circuit 100.

As shown in fig. 1, the power circuit is configured to convert an input voltage VIN to an output voltage VOUT, and includes power switches S1-S4, an inductor L, and an output capacitor COUT. When power switches S1 and S3 are on and power switches S2 and S4 are off, inductor L stores energy. When the power switches S1 and S3 are turned off and the power switches S2 and S4 are turned on, the energy stored in the inductor L is supplied to the load connected to the output terminal.

The control circuit 100 is used to control the on and off of the switching elements S1 to S4 to control the inductor L to output energy in discontinuous pulses. The control circuit 100 includes a current sampling circuit 101, an oscillator 102, an error amplifier 103, an adder circuit 104, a slope compensation circuit 105, PWM comparators 106 and 107, a loop compensation circuit 108, a voltage source 109, and a logic and drive circuit 110.

The current sampling circuit 101 is used for sampling a current flowing through the inductor L to generate a current sampling signal ISENSE. The oscillator 102 is used to provide an internal clock for the circuit that is switched in time (e.g., by generating a plurality of narrow pulses at a constant frequency, with adjacent pulses defining a clock cycle). The error amplifier 103 is used to compare the feedback signal VFB of the output voltage VOUT with the reference voltage VREF to generate an error amplifier output signal Vea. Optionally, the error amplifier output signal Vea is connected to the loop compensation circuit 108 and provided as an input to the PWM comparator 106. The PWM comparator 106 is used to compare the error amplifier output signal Vea with the ramp signal Vsum and generate a turn-off logic signal RST1 when the two intersect, where the turn-off logic signal RST1 is used to control the duty ratio of the power switches S1 and S2 in the buck mode. For example, the slope compensation signal VSLOPE provided by the slope compensation circuit 105 and the current sampling signal ISENSE may be superimposed by the adder circuit 104 to obtain the slope signal Vsum. The error amplifier output signal Vea is also connected to a voltage source 109, and the voltage source 109 is used to provide the error amplifier output signal Vea to the PWM comparator 107 after being properly offset. The PWM comparator 107 is used to compare the signal offset by the voltage source 109 with the ramp signal Vsum, and when the two signals intersect, generate a turn-off logic signal RST2, where the turn-off logic signal RST2 is used to control the duty ratio of the power switches S3 and S4 in the boost mode. The logic and driving circuit 110 is used for implementing a logic control function of the system, processing logic signals of each module controlling the working states of the power switches S1 to S4, generating switch driving signals DRV1 to DRV4, and providing the switch driving signals DRV1 to DRV4 to the power switches S1 to S4. The logic and drive circuit 110 may include a Pulse Width Modulator (PWM) circuit or any other suitable circuit capable of controlling the duty cycle of the power switches S1-S4.

In the buck-boost converter, it is usually necessary to limit the average current input to the buck-boost converter, and in the conventional practice, a current sampling voltage signal VSENSE is obtained by passing a current sampling signal ISENSE obtained by a current sampling circuit 101 through a filter shaping circuit 111, and is provided to the input of a current-limiting operational amplifier 112. The current limiting operational amplifier 112 compares the current sampling voltage signal VSENSE with the clamp voltage Vclamp, and once the current sampling voltage signal VSENSE reaches the input average current clamp voltage, the output of the clamp error amplifier 103 limits the current in the inductor L by controlling the duty cycle of the switch, thereby achieving the purpose of limiting the input current of the circuit.

However, the conventional method has a certain limitation, and for a boost-buck converter in a COT (constant on time) control mode, because a loop error amplifier is not arranged in a system architecture, the method cannot be adopted to limit an input average current. In addition, this method requires adding a current-limiting operational amplifier in the circuit, and requires complex control logic to improve loop stability, which undoubtedly increases the difficulty of system design. Moreover, the method also needs to use a large RC network for filtering and shaping, has slow response speed and cannot realize fast input average current limitation.

Disclosure of Invention

In view of this, the present invention provides a buck-boost converter, a control circuit thereof and a control method thereof, which have a faster response speed and can achieve a fast input average current limit.

According to a first aspect of embodiments of the present invention, there is provided a control circuit of a buck-boost converter, the buck-boost converter including a first power switch coupled between an input voltage and a first switching node, a second power switch coupled between the first switching node and a reference ground, a third power switch coupled between the second switching node and the reference ground, a fourth power switch coupled between the second switching node and an output voltage, and an inductor coupled between the first switching node and the second switching node, the control circuit comprising: the current sampling circuit is used for detecting the current flowing through the inductor and generating a current sampling signal; the average current limiting circuit is used for comparing the current sampling signal with a set bias current to generate a current clamping signal; a PWM comparator for comparing a feedback signal of the output voltage with a first reference voltage to generate a pulse width modulation signal; and a logic circuit for controlling a conduction time of the first power switch in each switching cycle according to a combination of the current clamp signal and the pulse width modulation signal, wherein the logic circuit is configured to control the first power switch to conduct if the pulse width modulation signal is a logic high state and the current clamp signal is a logic low state in each switching cycle.

Optionally, the average current limiting circuit includes: a capacitor, a second terminal of the capacitor coupled to ground; the current source circuit is coupled with the first end of the capacitor and used for providing a charging current with the size equivalent to that of the current sampling signal to the capacitor; a bias current source circuit having a first terminal coupled to the first terminal of the capacitor and a second terminal coupled to ground, the bias current source circuit configured to discharge the capacitor according to the set bias current; and a comparator for comparing the voltage of the capacitor with a threshold voltage to generate the current clamp signal.

Optionally, the threshold voltage has a reference ground potential.

Optionally, the average current limiting circuit further includes: a first switch coupled between a first terminal of the capacitor and ground, the first switch to turn on shortly before the first power switch turns on to discharge charge within the capacitor.

Optionally, the bias current source circuit includes: a first transistor and a resistor coupled between the input voltage and ground; a second transistor and a third transistor coupled between the input voltage and ground; an operational amplifier, a non-inverting input terminal of which is coupled with a fourth reference voltage, an inverting input terminal of which is coupled with a common terminal of the first transistor and the resistor, and an output terminal of which is coupled with control terminals of the first transistor and the second transistor; a second switch having a first terminal coupled to the input voltage and a second terminal coupled to control terminals of the first transistor and the second transistor; a third switch having a first terminal coupled to the control terminal and the first terminal of the third transistor; a sample and hold module having an input coupled to the second terminal of the third switch; and a fourth transistor having a control terminal coupled to the output terminal of the sample-and-hold module, a second terminal coupled to ground, and a first terminal for providing the bias current.

Optionally, the second switch and the third switch are configured to conduct complementarily at different times within one switching period.

Optionally, in a first time period within one switching cycle, the second switch is turned off and the third switch is turned on, and in a second time period other than the first time period within one switching cycle, the second switch is turned on and the third switch is turned off.

Optionally, the first time period is a combination of a conduction time of the first power switch within one switching cycle and a delay time between the first power switch and the second power switch.

Optionally, the first transistor and the second transistor are PMOS transistors, and the third transistor and the fourth transistor are NMOS transistors.

Optionally, the control circuit further includes: and the on-time control circuit is used for comparing the on-time of the first power switch in one switching period with a time threshold value so as to generate an on-time control signal for controlling the off-time of the first power switch.

Optionally, the control circuit further includes: a first peak current comparator for comparing a voltage of the first switching node with a second reference voltage to generate a first peak signal for controlling a turn-off timing of the third power switch in each switching cycle.

Optionally, the control circuit further includes: a second peak current comparator for comparing a voltage of the second switching node with a third reference voltage to generate a second peak signal for controlling a turn-on time of the third power switch in each switching cycle.

According to a second aspect of embodiments of the present invention, there is provided a control method of a buck-boost converter, the buck-boost converter including a first power switch coupled between an input voltage and a first switching node, a second power switch coupled between the first switching node and a reference ground, a third power switch coupled between the second switching node and the reference ground, a fourth power switch coupled between the second switching node and an output voltage, and an inductor coupled between the first switching node and the second switching node, the control method comprising: detecting the current flowing through the inductor to generate a current sampling signal; comparing the current sampling signal with a set bias current to generate a current clamping signal; comparing a feedback signal of the output voltage with a first reference voltage to generate a pulse width modulation signal; and controlling a turn-on time of the first power switch in each switching cycle according to a combination of the current clamp signal and the pulse width modulation signal, wherein the first power switch is controlled to be turned on in a case where the pulse width modulation signal is in a logic high state and the current clamp signal is in a logic low state in each switching cycle.

Optionally, the step of comparing the current sampling signal with a set bias current to generate a current clamping signal includes: providing a capacitor; providing a charging current with a magnitude corresponding to the current sampling signal to the capacitor; providing a set bias current, and discharging the capacitor according to the bias current; and comparing the voltage of the capacitor with a threshold voltage to generate the current clamp signal.

Optionally, the step of comparing the current sampling signal with a set bias current to generate a current clamping signal further includes: discharging charge within the capacitor before the first power switch is turned on in each switching cycle.

Optionally, the control method further includes: and comparing the on-time of the first power switch in one switching period with a time threshold value to generate an on-time control signal, and controlling the turn-off time of the first power switch in one switching period according to the on-time control signal.

Optionally, the control method further includes: and comparing the voltage of the first switching node with a second reference voltage to generate a first peak signal, and controlling the turn-off time of the third power switch in one switching period according to the first peak signal.

Optionally, the control method further includes: and comparing the voltage of the second switching node with a third reference voltage to generate a second peak signal, and controlling the conduction time of the third power switch in one switching period according to the second peak signal.

According to a third aspect of the embodiments of the present invention, there is provided a buck-boost converter, including: a first power switch coupled between an input voltage and a first switch node; a second power switch coupled between the first switch node and a ground reference; a third power switch coupled between the second switch node and a reference ground; a fourth power switch coupled between the second switch node and an output voltage; and an inductor coupled between the first switching node and the second switching node; and the control circuit described above.

In summary, in the buck-boost converter, the control circuit and the control method thereof provided by the embodiments of the present invention, the control circuit is configured to control the switching of the buck-boost converter in a combination manner of the constant on-time control, the peak current mode control and the average current limit control. The control circuit comprises an average current limiting circuit, the average current limiting circuit is used for comparing a current sampling signal obtained by a current sampling circuit with a set bias current, generating a current clamping signal according to a comparison result, and then controlling the charging time of the inductor by a logic circuit according to the combination of a PWM signal and the current clamping signal in each switching period. That is, the logic circuit first determines the level state of the current clamp signal when the rising edge of the PWM signal arrives, and starts charging the inductor only when the current clamp signal is logic low, thereby realizing control of the current in the inductor and finally enabling the average current in the inductor to reach a constant value. In addition, the scheme provided by the embodiment does not need to arrange an operational amplifier and a large RC network in the circuit for filtering and shaping, so that the response speed is higher, and the input average current can be quickly limited.

Drawings

The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings.

Fig. 1 shows a schematic circuit diagram of a buck-boost converter according to the prior art.

Fig. 2 shows a schematic circuit diagram of a buck-boost converter according to an embodiment of the invention.

Fig. 3 shows a schematic circuit diagram of an average current limiting circuit according to an embodiment of the invention.

Fig. 4 is a waveform diagram illustrating an operation of an average current limiting circuit according to an embodiment of the present invention.

Fig. 5 shows a schematic circuit diagram of a bias current source according to an embodiment of the invention.

Fig. 6 shows a timing diagram of the operation of the buck-boost converter according to an embodiment of the invention.

Detailed Description

The invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by like reference numerals. For purposes of clarity, the various features in the drawings are not drawn to scale. Moreover, certain well-known elements may not be shown in the figures.

In the following description, numerous specific details are set forth, such as configurations of components, materials, dimensions, processing techniques and techniques, in order to provide a more thorough understanding of the present invention. However, as will be understood by those skilled in the art, the present invention may be practiced without these specific details.

It should be understood that in the following description, a "circuit" refers to a conductive loop formed by at least one element or sub-circuit through an electrical or electromagnetic connection. When an element or circuit is referred to as being "connected to" another element or element/circuit is referred to as being "connected between" two nodes, it may be directly coupled or connected to the other element or intervening elements may be present, and the connection between the elements may be physical, logical, or a combination thereof. In contrast, when an element is referred to as being "directly coupled" or "directly connected" to another element, it is intended that there are no intervening elements present. Further, the transistors present in pairs according to the invention are matched transistors, which are, unless otherwise specified, of the same size and/or type.

In the context of the present invention, a transistor blocks current and/or conducts substantially no current when the transistor is in an "off state" or "open". Conversely, a transistor is capable of significantly conducting current when the transistor is from an "on" state or "on". For example, in one embodiment, the high voltage transistor comprises an N-channel metal oxide semiconductor (NMOS) Field Effect Transistor (FET), wherein the high voltage is provided between a first terminal (i.e., drain) and a second terminal (i.e., source) of the transistor. In some embodiments, an integrated control circuit may be used to drive the power switch when regulating the energy provided to the load. In addition, for the purposes of this disclosure, "ground" or "ground potential" in the present disclosure refers to a reference voltage or potential relative to which all other voltages or potentials of an electronic circuit or Integrated Circuit (IC) are defined or measured.

Fig. 2 shows a schematic circuit diagram of a buck-boost converter according to an embodiment of the invention. The buck-boost converter of the present embodiment includes a control circuit 200 and an external power circuit. Wherein the power circuit includes one or more switch and filter elements (e.g., inductors and capacitors, etc.) configured to regulate power transfer from the input to the output of the power converter in response to one or more switch drive signals from the control circuit 200. In some embodiments, one or more switches in the power circuit are integrated with the control circuit 200 to form an integrated circuit chip.

As shown in fig. 2, the power circuit includes power switches S1 to S4, an inductor L, and an output capacitor COUT. The power switch S1 has a first terminal, a second terminal and a control terminal, wherein the first terminal is coupled to the input voltage VIN. The power switch S2 has a first terminal coupled to the second terminal of the power switch S1, a second terminal coupled to the ground reference, and a control terminal. The inductor L has a first terminal and a second terminal, and a common terminal of the power switches S1 and S2 forms a first switching node SW1, to which the first terminal of the inductor L is coupled. The power switch S3 has a first terminal, a second terminal and a control terminal, the second terminal of which is connected to the reference ground. The power switch S4 has a first terminal coupled to the first terminal of the power switch S3, a second terminal coupled to the output voltage VOUT, and a control terminal. The output capacitor COUT is coupled between the second terminal of the power switch S4 and ground. A common terminal of power switches S3 and S4 forms a second switch node SW2, to which a second terminal of inductor L is coupled. The power switches S1-S4 may be any controllable semiconductor switching device, such as a Metal Oxide Semiconductor Field Effect Transistor (MOSFET), an Insulated Gate Bipolar Transistor (IGBT), or the like.

The control circuit 200 is used to control the on and off of the switching elements S1 to S4 to control the inductor L to output energy in discrete pulses. Various examples of the invention provide systems and methods for controlling a buck-boost converter with a combination of constant on-time (COT) control and Peak Current Mode (PCM) control. The control circuit 200 includes a current sampling circuit 201, a PWM comparator 202, peak current comparators 203 and 204, an on-time control circuit 205, an average current limiting circuit 206, a logic circuit 207, and a driving circuit 208.

The current sampling circuit 201 samples a current flowing through the inductor L to generate a current sampling signal ISENSE. The sampling may be implemented by a sampling resistor, a current transformer, a current mirror, or the like, and the current sampling circuit 201 may also estimate the current flowing through the inductor L by sampling the current flowing through each switching element (e.g., the power switch S1) and obtain a current sampling signal ISENSE.

The PWM comparator 202 has a non-inverting input terminal receiving the first reference voltage VREF1, an inverting input terminal receiving the feedback signal VFB of the output voltage VOUT, and an output terminal, wherein the feedback signal VFB of the output voltage VOUT is obtained, for example, by a resistor divider network formed by divider resistors Ra and Rb, which are coupled in series between the output voltage VOUT and a reference ground, and the feedback signal VFB representing the output voltage VOUT is generated at a common node between the two and is coupled to the inverting input terminal of the PWM comparator 202. The PWM comparator 202 is used for comparing the feedback signal VFB with the first reference voltage VREF1 to generate the pulse width modulation signal PWM at the output terminal.

The peak current comparator 203 has a non-inverting input coupled to the first switching node SW1, an inverting input for receiving a second reference voltage VREF2, which second reference voltage VREF2 may be generated by other circuits, and an output, and the peak current comparator 203 is configured to compare the first switching node voltage VSW1 with the second reference voltage VREF2 and generate a first peak signal Ipeak1 at the output. When the first switching node voltage VSW1 is higher than the second reference voltage VREF2, the peak current comparator 203 outputs a first peak signal Ipeak1 in a first state (e.g., high level); when the first switching node voltage VSW1 is lower than the second reference voltage VREF2, the peak current comparator 203 outputs the first peak signal Ipeak1 in a second state (e.g., a low level).

The peak current comparator 204 has a non-inverting input coupled to the second switching node SW2, an inverting input for receiving a third reference voltage VREF3, for example, the third reference voltage VREF3 may be generated by other circuits, and an output, and the peak current comparator 204 is configured to compare the second switching node voltage VSW2 with the third reference voltage VREF3 and generate a second peak signal Ipeak2 at the output. When the second switching node voltage VSW2 is higher than the third reference voltage VREF3, the peak current comparator 204 outputs a second peak signal Ipeak2 in a first state (e.g., high level); when the second switching node voltage VSW2 is lower than the third reference voltage VREF3, the peak current comparator 204 outputs a second peak signal Ipeak2 of a second state (e.g., a low level).

The on-time control circuit 205 is configured to start timing when the power switch S1 is turned on for setting the on-time of the power switch S1 in each switching cycle. Illustratively, the on-time control circuit 205 is configured to compare the on-time of the power switch S1 in one switching cycle with a time threshold Ton, and to generate the on-time control signal COT at the output terminal. The time threshold Ton can be obtained by the input voltage VIN and the output voltage VOUT. In one embodiment, the time threshold Ton may be expressed as: ton = Tperiod VOUT/VIN, where Tperiod represents the desired switching period.

The input end of the average current limiting circuit 206 is coupled to the output end of the current sampling circuit 201, and the average current limiting circuit 206 is configured to compare the current sampling signal ISENSE with the set bias current Ibias, generate a current clamp signal Iclamp according to the comparison result, and further adjust the on-time of the power switches S1 and S3, so as to finally make the average current of the inductor reach a constant value.

The logic circuit 207 is configured to implement a logic control function of the system, process logic signals of each module controlling the operating states of the switching elements S1 to S4, and generate a first control signal CTRL1 for controlling the power switches S1 and S2 to be turned on and off and a second control signal CTRL2 for controlling the power switches S3 and S4 to be turned on and off, respectively.

The driving circuit 208 is coupled to an output of the logic circuit 206 and configured to generate driving signals DRV1 and DRV2 based on the first control signal CTRL1 to control the power switches S1 and S2, respectively. Typically, the drive signals DRV1 and DRV2 are complementary signals. To avoid shoot-through of switches S1 and S2, a dead-time control circuit is typically included in drive circuit 208 to introduce a dead time Tdelay between drive signals DRV1 and DRV 2. The drive circuit 208 is further configured to generate drive signals DRV3 and DRV4 based on the second control signal CTRL2 to control the power switches S3 and S4, respectively. Typically, the drive signals DRV3 and DRV4 are complementary signals. Similar to the foregoing, to avoid the switches S3 and S4 going through, a dead time control circuit is also included in the drive circuit 208 to introduce a dead time Tdelay between the drive signals DRV3 and DRV4.

In some embodiments, to prevent the occurrence of reverse current, a zero crossing detection circuit 209 is further included in the control circuit 200, and the zero crossing detection circuit 209 is coupled to the driving circuit 208. The zero-crossing detection circuit 209 is configured to detect whether the current flowing through the inductor L crosses zero, and provide a zero-crossing detection signal ZCD to the driving circuit 208 when the current flowing through the inductor L is detected to cross zero, and turn off both the power switches S2 and S4 or turn on both the power switches S2 and S3 through the driving circuit 208. In practical applications, the zero crossing detection circuit 209 may determine whether the current flowing through the inductor L crosses zero by detecting the current flowing through the switch S2 or S4.

According to the teachings of the present embodiment, the control circuit 200 controls the buck-boost converter in a combination of constant on-time (COT) control and Peak Current Mode (PCM) control. In each switching period, when the feedback signal VFB is lower than the first reference voltage VREF1, the PWM signal PWM output by the PWM comparator 202 flips to a high level, the logic circuit 207 sets the first control signal CTRL1 and the second control signal CTRL2 according to the pulse width modulation signal PWM in a high level state (for example, the first control signal CTRL1 and the second control signal CTRL2 are set to a high level), the switches S1 and S3 are turned on, and the switches S2 and S4 are turned off. When the current IL in the inductor L reaches the first current threshold, the first switch node voltage VSW1 is lower than the second reference voltage VREF2, the first peak signal Ipeak1 output by the peak current comparator 203 is inverted to a low level, and the logic circuit 207 resets the second control signal CTRL2 according to the first peak signal Ipeak1 in a low level state (for example, the second control signal CTRL2 is set to a low level) to turn off the switch S3 and turn on the switch S4. When the on-time of the power switch S1 reaches the time threshold Ton, the logic circuit 207 resets the first control signal CTRL1 (e.g., the first control signal CTRL1 flips to a low level) to turn off the power switch S1 and turn on the power switch S2. When the current IL in the inductor L reaches the second current threshold, the second switch node voltage SW2 is higher than the third reference voltage VREF3, the second peak signal Ipeak2 output by the peak current comparator 204 is inverted to a high level, and the logic circuit 207 sets the second control signal CTRL2 again according to the second peak signal Ipeak2 in a high level state to turn on the switch S3 and turn off the switch S4. The above process is repeated continuously to achieve regulation of the output voltage VOUT. Further, the control circuit of the buck-boost converter of the present embodiment is further configured to control the average current in the inductor L according to the current clamp signal Iclamp in each switching cycle, so that the average current of the system reaches a constant value. That is, the logic circuit 207 detects whether the current clamp signal Iclamp is at a low level or not before the high level state of the PWM signal PWM comes, and turns on the power switches S1 and S3 according to the rising edge of the PWM signal PWM if the current clamp signal Iclamp is at a low level, and repeats the above-mentioned control process; if the current clamp signal Iclamp is at a high level, the power switches S1 and S3 are turned on when a falling edge of the current clamp signal Iclamp is detected, and then the above-described control process is repeated. Therefore, the ripple current can be adjusted by adjusting the turn-off time of the power switch S1 in each switching period, so that the ripple current reaches a constant value, and finally, the average current of the inductor L reaches a constant value.

Fig. 3 shows a schematic circuit diagram of the average current limiting circuit 206 according to an embodiment of the present invention. As shown in fig. 3, the average current limiting circuit 206 includes a current source 261, a bias current source 262, a capacitor C1, a comparator 263, and a switch K1. The current source 261 is coupled to a first terminal of the capacitor C1, a second terminal of the capacitor C1 is coupled to ground, and the current source 261 is configured to provide a charging current having a magnitude corresponding to the current sampling signal ISENSE to the capacitor C1. For example, the current source 261 may be implemented by a current mirror, which provides the charging current to the capacitor C1 according to the current sampling signal ISENSE in a mirrored manner. The bias current source 262 has a first terminal and a second terminal, the first terminal is coupled to the first terminal of the capacitor C1, the second terminal is coupled to ground, the bias current source 262 is configured to provide a set bias current Ibias, and discharge the capacitor C1 according to the set bias current Ibias, that is, the discharge current of the capacitor C1 is equal to the bias current Ibias. The comparator 263 has a non-inverting input terminal coupled to the first terminal of the capacitor C1, an inverting input terminal coupled to a comparison threshold (e.g., a ground reference voltage), and an output terminal, and the comparator 263 is configured to compare the voltage VC of the capacitor C1 with a threshold voltage and provide the current clamp signal Iclamp at the output terminal according to the comparison result. The switch K1 has a first terminal coupled to the first terminal of the capacitor C1 and a second terminal coupled to ground. The switch K1 is used to conduct shortly before each switching cycle to discharge the charge in the capacitor C1. For example, the control signal for switch K1 may be generated using a narrow pulse circuit that may provide a narrow pulse control signal to switch K1 before the start of each switching cycle by detecting the control signal for power switch Q1.

Fig. 4 is a waveform diagram illustrating an operation of the average current limiting circuit according to the embodiment of the present invention, and fig. 4 illustrates waveforms of the inductor current IL, the current sampling signal ISENSE, the bias current Ibias, and the control signal of the switch K1, respectively. Wherein the current sampling signal ISENSE = I _VIN N, wherein I _VIN The current provided by the input voltage VIN is represented, n is a proportionality coefficient between a sampling transistor and the power switch S1 in the current sampling circuit 201, T is a switching period of the system operation, ton is an on-time of the power switch S1 in the switching period T, and then the charge amount of the current sampling signal ISENSE charging the capacitor C1 in the switching period is:

the amount of charge that the bias current Ibias discharges to the capacitor C1 in one switching cycle is:

Q2＝Ibias*T

if it is desired that the average current of the input is kept at a constant value, it is necessary to satisfy: q1= Q2, then the input average current, \9is:

as can be seen from the above equation, the average circuit error of the buck-boost converter is derived from two aspects: the current sampling precision and the bias current source precision can meet the high-precision requirement through design, so the average current limiting circuit of the embodiment can meet the high-precision requirement.

Fig. 5 shows a schematic circuit diagram of a bias current source 262 according to an embodiment of the present invention. As shown in fig. 5, the bias current source 262 of the present embodiment includes an operational amplifier 2621, PMOS transistors M1 and M2, a resistor R1, NMOS transistors M3 and M4, switches K2 and K3, and a sample-and-hold module 2622.

The PMOS transistors M1 and M2 have sources, gates, and drains, wherein the sources of the PMOS transistors M1 and M2 are coupled to the input voltage VIN, and the gates of the PMOS transistors M1 and M2 are coupled to each other. The resistor R1 has a first terminal coupled to the drain of the PMOS transistor M1 and a second terminal coupled to ground. The operational amplifier 2621 has a non-inverting input terminal receiving the fourth reference voltage VREF4, an inverting input terminal coupled to the drain of the PMOS transistor M1 and the first terminal of the resistor R1, and an output terminal coupled to the gates of the PMOS transistors M1 and M2. The NMOS transistor M3 has a source, a gate, and a drain, the drain and the gate of which are coupled to the drain of the PMOS transistor M2, and the source of which is coupled to ground. The switch K2 has a first terminal coupled to the sources of the PMOS transistors M1 and M2 and a second terminal coupled to the gates of the PMOS transistors M1 and M2. The switch K3 has a first terminal coupled to the gate and the drain of the NMOS transistor M3 and a second terminal coupled to the input terminal of the sample-and-hold module 2622. The NMOS transistor M4 has a source, a gate, and a drain, wherein the gate is coupled to the output terminal of the sample-and-hold module 2622, the source is coupled to ground, and the drain is used for outputting the bias current Ibias.

In the present embodiment, the switches K2 and K3 are non-overlapped to conduct, wherein the switch K2 is turned off and the switch K3 is turned on in a first time period (i.e., ton + Tdelay) of one switching period, wherein Ton represents the conducting time of the power switch S1 in each switching period, and Tdelay represents the time for shielding the additional increase of the interference caused by the moment the power switch S2 is turned on. In a second period (i.e., T- (Ton + Tdelay)) other than the first period in one switching cycle, the switch K2 is turned on and the switch K3 is turned off.

During the first period of time in one switching cycle, the operational amplifier 2621 generates a current I1= VREF4/R1 across the resistor R1 by clamping the gate voltage of the PMOS transistor M1. In the present embodiment, by designing so that the PMOS transistors M1 and M2 have equal size ratios, the PMOS transistor M2 mirrors the current I1 on the PMOS transistor M1 to obtain a current I2, i.e. a current I2= I1= VREF4/R1, the NMOS transistor M3 converts the current I2 into a voltage signal, and controls the gate voltage of the NMOS transistor M4 by the voltage signal, and converts it into a current signal again, i.e. a bias current Ibias = I1= VREF4/R1. In the second time period, the switch K2 is turned on and the switch K3 is turned off, so that the operational amplifier 2621 and the current mirror on the left side of the bias current source circuit 262 of this embodiment do not work any more, and therefore, the power consumption of the whole circuit drawn from the input voltage VIN during this time period is 0, which can reduce the power consumption of the circuit to the maximum extent and improve the efficiency of the circuit. In addition, since the sample-and-hold module 2622 has sample-and-hold the voltage signal converted by the NMOS transistor M3 during the first period, the bias current Ibias is still maintained at VREF4/R1 during the second period. Therefore, the bias current source circuit 262 of the present embodiment not only can generate a bias current with higher precision, but also can reduce the power consumption of the circuit to the maximum extent by a time-sharing operation, and is suitable for a buck-boost converter circuit system with ultra-low power consumption.

Fig. 6 shows a timing diagram of the operation of the buck-boost converter according to an embodiment of the invention. The horizontal axis in fig. 6 represents time intervals, where T represents one switching period. The first row represents the feedback signal VFB and the first reference voltage VREF1 fed into the PWM comparator 202, the second row represents the inductor current IL in the inductor L, the third row represents the pulse width modulation signal PWM generated by the PWM comparator 202, the fourth row represents the current clamp signal Iclamp generated by the comparator 263 in the average current limiting circuit 206, the fifth row represents the voltage VC across the capacitor C1 in the average current limiting circuit 206, the sixth and seventh rows represent the first and second peak signals Ipeak1 and Ipeak2 generated by the peak current comparators 203 and 204, respectively, the eighth and ninth rows represent the first and second control signals CTRL1 and CTRL2, respectively, generated by the logic circuit 207, and the tenth to thirteenth rows represent the drive signals DRV1 to DRV4, respectively, generated by the drive circuit 208.

The operation principle of the buck-boost converter of the present embodiment is explained with reference to fig. 2, fig. 3 and fig. 6. At time t0, the feedback signal VFB is lower than the first reference voltage VREF1. Referring back to fig. 2, the output of the pwm comparator 202 generates a logic level "1" and supplies the logic level "1" to the logic circuit 207. Meanwhile, at the time t0, the voltage VC across the capacitor C1 is not higher than the ground reference potential GND, so the output of the comparator 263 generates the current clamp signal Iclamp of logic level "0", the logic circuit 207 outputs the first control signal CTRL1 of logic level "1" according to the current clamp signal Iclamp of logic level "0" and the PWM signal of logic level "1", and the driving circuit 208 turns off the power switch S2 according to the first control signal CTRL1 of logic level "1", and turns on the power switch S1 after a suitable delay. In addition, since the second control signal CTRL2 is also at logic level "1" at time t0, the power switch S3 is turned on and the power switch S4 is turned off. Thus, from time t0 to time t1, power switches S2 and S4 are turned off, and power switches S1 and S3 are turned on. As a result of turning on the power switches S1 and S3, the current IL in the inductor L rises linearly with a first slope from time t0 to time t 1. From time t0 to time t1, the current sampling signal ISENSE charges the capacitor C1, so the voltage VC across the capacitor C1 increases in a linear manner and the current clamp signal Iclamp output by the comparator 263 has a logic high state.

At a time t1, the current IL in the inductor L reaches a first current threshold, the first peak signal Ipeak1 output by the peak current comparator 203 generates a pulse signal that flips downward and provides the pulse signal to the logic circuit 207, the logic circuit 207 resets the second control signal CTRL2 to a logic level "0" according to the pulse signal generated on the first peak signal Ipeak1, and the driving circuit 208 turns off the power switch S3 according to the second control signal CTRL2 at the logic level "0" and turns on the power switch S4 after a suitable delay. Thus, from time t1 to time t2, power switches S1 and S4 are turned on, and power switches S2 and S3 are turned off. As a result of turning off the power switch S3, the current IL in the inductor L varies linearly with a second slope, which is smaller than the first slope, from time t1 to time t 2.

At time t2, the on-time of the power switch S1 reaches the time threshold Ton, the logic circuit 207 resets the first control signal CTRL1 to the logic level "0", the driving circuit 208 turns off the power switch S1 according to the first control signal CTRL1 at the logic level "0", and turns on the power switch S2 after a suitable delay. Thus, from time t2 to time t3, power switches S1 and S3 are turned off, and power switches S2 and S4 are turned on. As a result of the conduction of the power switch S2, the current IL in the inductor L drops linearly. From time t2 to time t3, capacitor C1 is discharged by bias current source 262 due to the turning off of current sampling circuit 201, and the voltage VC across capacitor C1 drops linearly.

At time t3, the current IL in the inductor L reaches the second current threshold, an upward-flipping pulse signal appears in the second peak signal Ipeak2 output by the peak current comparator 204, and the pulse signal is provided to the logic circuit 207, the logic circuit 207 again sets the second control signal CTRL2 to logic level "1", the driving circuit 208 turns off the power switch S4 according to the second control signal CTRL2 at logic level "1", and after a suitable delay, turns on the power switch S3. Thus, from time t3 to time t4, power switches S1 and S4 are turned off, and power switches S2 and S3 are turned on.

At time t4, the feedback signal VFB is again lower than the first reference voltage VREF1, and the output of the PWM comparator 202 generates a logic level "1" and supplies the logic level "1" to the logic circuit 207. The logic circuit 207 simultaneously detects whether the current clamp signal Iclamp is in a logic low state, and as shown in the figure, the current clamp signal Iclamp is still in a logic level "0" at time t4, so that the logic circuit 207 sets the first control signal CTRL1 to a logic high state according to the PWM signal of the logic level "1" to turn on the power switch S1 and turn off the power switch S2, as can be understood, there is a certain delay time between the two switching operations, and then another switching cycle begins and the circuit repeats the process from time t0 to time t 3.

If the current clamp signal Iclamp is in a logic high state when the rising edge of the output signal of the PWM comparator 202 arrives, which indicates that the input average current of the circuit reaches the current limiting value, the logic circuit 207 does not immediately turn on the power switch S1 to charge the circuit. As shown at time t5 in fig. 6, at time t5, the output of the PWM comparator 202 generates a logic level "1" while the current clamp signal Iclamp is at a logic level "1", and the logic circuit 207 continues to maintain the first control signal CTRL1 at a logic level "0", while the circuit still keeps the power switches S1 and S4 off and the power switches S2 and S3 on. Until time t6, when the current clamp signal Iclamp is inverted to logic level "0", the logic circuit 207 will not set the first control signal CTRL1 to logic level "1", and then turn off the power switch S2, turn on the power switch S1, and then start the switching cycle of the circuit.

If the feedback signal VFB is lower than the first reference voltage VREF1 after the charging process is finished, that is, the PWM signal PWM output by the PWM comparator 202 is always in a logic high state after the charging process is finished, the logic circuit 207 controls the charging time of the next switching cycle according to the state of the current clamp signal Iclamp, and if the current clamp signal Iclamp is in a logic high state, it indicates that the input average current of the circuit is higher than the current limit value, and the switching element S1 is turned on again until the falling edge of the current clamp signal Iclamp comes, so as to start the charging process of the next switching cycle.

In summary, in the buck-boost converter, the control circuit and the control method thereof provided by the embodiments of the present invention, the control circuit is configured to control the switching of the buck-boost converter in a combination manner of the constant on-time control, the peak current mode control and the average current limit control. The control circuit comprises an average current limiting circuit, the average current limiting circuit is used for comparing a current sampling signal obtained by a current sampling circuit with a set bias current, generating a current clamping signal according to a comparison result, and then controlling the charging time of the inductor by a logic circuit according to the combination of a PWM signal and the current clamping signal in each switching period. That is, the logic circuit first determines the level state of the current clamp signal when the rising edge of the PWM signal arrives, and starts charging the inductor only when the current clamp signal is logic low, thereby realizing control of the current in the inductor and finally enabling the average current in the inductor to reach a constant value. In addition, the scheme provided by the embodiment does not need to arrange an operational amplifier and a large RC network in the circuit for filtering and shaping, so that the response speed is higher, and the input average current can be quickly limited.

Further, an embodiment of the present invention further provides a bias current source circuit used in the average current limiting circuit, where the bias current source circuit generates a bias current by combining time-sharing operation with sample-and-hold, so that not only can a bias current with higher precision be generated, but also the power consumption of the circuit can be reduced to the maximum extent by using the time-sharing operation, and the bias current source circuit is suitable for a buck-boost converter circuit system with ultra-low power consumption.

It should be noted that, in this document, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrases "comprising a," "8230," "8230," or "comprising" does not exclude the presence of additional like elements in a process, method, article, or apparatus that comprises the element.

While embodiments in accordance with the invention have been described above, these embodiments are not intended to be exhaustive or to limit the invention to the precise embodiments described. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. The invention is limited only by the claims and their full scope and equivalents.

Claims (19)

1. A control circuit of a buck-boost converter, the buck-boost converter including a first power switch coupled between an input voltage and a first switching node, a second power switch coupled between the first switching node and a reference ground, a third power switch coupled between a second switching node and a reference ground, a fourth power switch coupled between the second switching node and an output voltage, and an inductor coupled between the first switching node and the second switching node, the control circuit comprising:

the current sampling circuit is used for detecting the current flowing through the inductor and generating a current sampling signal;

the average current limiting circuit is used for comparing the current sampling signal with a set bias current to generate a current clamping signal;

a PWM comparator for comparing a feedback signal of the output voltage with a first reference voltage to generate a pulse width modulation signal; and

logic circuitry to control a turn-on time of the first power switch in each switching cycle in accordance with a combination of the current clamp signal and the pulse width modulation signal,

wherein the logic circuit is configured to control the first power switch to conduct if the pulse width modulated signal is a logic high state and the current clamp signal is a logic low state in each switching cycle.

2. The control circuit of claim 1, wherein the average current limit circuit comprises:

a capacitor, a second terminal of the capacitor coupled to ground;

the current source circuit is coupled with the first end of the capacitor and used for providing a charging current with the size equivalent to that of the current sampling signal to the capacitor;

a bias current source circuit having a first terminal coupled to the first terminal of the capacitor and a second terminal coupled to ground, the bias current source circuit configured to discharge the capacitor according to the set bias current; and

a comparator for comparing the voltage of the capacitor with a threshold voltage to generate the current clamp signal.

3. The control circuit of claim 2, the threshold voltage having a reference ground potential.

4. The control circuit of claim 2 wherein the average current limit circuit further comprises:

a first switch coupled between the first terminal of the capacitor and ground, the first switch to turn on shortly before the first power switch turns on to discharge charge in the capacitor.

5. The control circuit of claim 2, wherein the bias current source circuit comprises:

a first transistor and a resistor coupled between the input voltage and ground;

a second transistor and a third transistor coupled between the input voltage and ground;

an operational amplifier, a non-inverting input terminal of which is coupled to a fourth reference voltage, an inverting input terminal of which is coupled to a common terminal of the first transistor and the resistor, and an output terminal of which is coupled to control terminals of the first transistor and the second transistor;

a second switch having a first terminal coupled to the input voltage and a second terminal coupled to control terminals of the first transistor and the second transistor;

a third switch having a first end coupled to the control end and the first end of the third transistor;

a sample and hold module having an input coupled to the second terminal of the third switch; and

and a fourth transistor, wherein a control terminal of the fourth transistor is coupled to the output terminal of the sample-and-hold module, a second terminal of the fourth transistor is coupled to ground, and a first terminal of the fourth transistor is used for providing the bias current.

6. The control circuit of claim 5, wherein the second switch and the third switch are configured to conduct complementarily time-divided within one switching period.

7. The control circuit of claim 6 wherein the second switch is off and the third switch is on for a first period of time within one switching cycle, and the second switch is on and the third switch is off for a second period of time within one switching cycle other than the first period of time.

8. The control circuit of claim 7 wherein the first time period is a combination of a turn-on time within one switching cycle of the first power switch and a delay time between the first power switch and the second power switch.

9. The control circuit of claim 5, wherein the first and second transistors are PMOS transistors and the third and fourth transistors are NMOS transistors.

10. The control circuit of claim 1, further comprising:

and the on-time control circuit is used for comparing the on-time of the first power switch in one switching period with a time threshold value so as to generate an on-time control signal for controlling the off-time of the first power switch.

11. The control circuit of claim 1, further comprising:

a first peak current comparator for comparing a voltage of the first switching node with a second reference voltage to generate a first peak signal for controlling a turn-off timing of the third power switch in each switching cycle.

12. The control circuit of claim 1, further comprising:

a second peak current comparator for comparing a voltage of the second switching node with a third reference voltage to generate a second peak signal for controlling a turn-on time of the third power switch in each switching cycle.

13. A control method of a buck-boost converter including a first power switch coupled between an input voltage and a first switching node, a second power switch coupled between the first switching node and a reference ground, a third power switch coupled between a second switching node and a reference ground, a fourth power switch coupled between the second switching node and an output voltage, and an inductor coupled between the first switching node and the second switching node, the control method comprising:

detecting the current flowing through the inductor to generate a current sampling signal;

comparing the current sampling signal with a set bias current to generate a current clamping signal;

comparing a feedback signal of the output voltage with a first reference voltage to generate a pulse width modulation signal; and

controlling a turn-on instant of the first power switch in each switching cycle according to a combination of the current clamp signal and the pulse width modulation signal,

wherein the first power switch is controlled to be on when the pwm signal is in a logic high state and the current clamp signal is in a logic low state in each switching period.

14. The control method of claim 13, wherein the step of comparing the current sample signal with a set bias current to generate a current clamp signal comprises:

providing a capacitor;

providing a charging current with a magnitude corresponding to the current sampling signal to the capacitor;

providing a set bias current, and discharging the capacitor according to the bias current; and

comparing the voltage of the capacitor with a threshold voltage to generate the current clamp signal.

15. The method of claim 14, wherein the step of comparing the current sample signal to a set bias current to generate a current clamp signal further comprises:

discharging charge within the capacitor before the first power switch is turned on in each switching cycle.

16. The control method according to claim 13, further comprising:

and comparing the on-time of the first power switch in one switching period with a time threshold value to generate an on-time control signal, and controlling the turn-off time of the first power switch in one switching period according to the on-time control signal.

17. The control method according to claim 13, further comprising:

and comparing the voltage of the first switching node with a second reference voltage to generate a first peak signal, and controlling the turn-off time of the third power switch in one switching period according to the first peak signal.

18. The control method according to claim 13, further comprising:

and comparing the voltage of the second switching node with a third reference voltage to generate a second peak signal, and controlling the conduction time of the third power switch in one switching period according to the second peak signal.

19. A buck-boost converter comprising:

a first power switch coupled between an input voltage and a first switch node;

a second power switch coupled between the first switch node and a ground reference;

a third power switch coupled between the second switch node and a reference ground;

a fourth power switch coupled between the second switch node and an output voltage; and

an inductor coupled between the first switching node and the second switching node; and

the control circuit of any of claims 1-12.

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