TW202143256A - Composite circuit protection device capable of protecting varistor sandwiched between two PTC elements from burning in the presence of overcurrent and overvoltage - Google Patents

Abstract

A composite circuit protection device comprises a first positive-temperature-coefficient (PTC) element, a second PTC element, a varistor, a first conductive lead, a second conductive lead, and a third conductive lead. The first PTC element includes a first PTC layer, a first electrode layer, and a second electrode layer. The first PTC layer has two opposite surfaces, wherein the first and second electrode layers are respectively disposed on the two opposite surfaces of the PTC layer. The second PTC element includes a second PTC layer, a third electrode layer, and a fourth electrode layer, wherein the second PTC has two opposite surfaces, and the third and fourth electrode layers are respectively disposed on the two opposite surfaces of the first PTC layer. The varistor is connected to the second electrode layer and the third electrode layer. The first conductive lead is connected with the first electrode layer, the second conductive lead is connected with the varistor, and the third conductive lead is connected with the fourth electrode layer. The composite circuit protection device of the present invention is provided with excellent durability and may protect the varistor sandwiched between two PTC elements from burning in the presence of overcurrent and overvoltage.

Description

Composite circuit protection device

The present invention relates to a composite circuit protection device, in particular to a type comprising a voltage-dependent resistor (VDR, or varistor) sandwiched between two positive temperature coefficient (PTC) components The combined circuit protection device.

US Patent No. 8,508,328 B1 describes a plug-in polymer positive temperature coefficient (PPTC) over-current (PPTC) over-current protection device. See Figure 1. The PPTC over-current protection device includes two electrodes 30, one Solder material, conductive leads 50, 60 respectively connected to the electrodes 30, and a PTC polymer substrate 20 laminated between the electrodes 30. A hole 40 is formed on the PTC polymer substrate 20, and the hole 40 has an effective volume capable of accommodating the thermal expansion of the PTC polymer substrate 20 when the temperature increases.

Electrical characteristics [such as operating current and high-voltage surge endurability] are important factors that affect the occurrence of power surges in PPTC overcurrent protection devices. For example, increasing the thickness or area of the PTC polymer substrate 20 can increase the working current of the PPTC overcurrent protection device, which is more susceptible to damage from power surges. On the other hand, reducing the thickness or area of the PTC polymer substrate 20 can increase the high voltage tolerance of the PPTC overcurrent protection device, and the PPTC overcurrent protection device may not be less susceptible to damage from power surges.

Although a voltage-dependent resistor (VDR) can be combined with the PPTC over-current protection device to provide over-current and over-voltage (over-voltage) protection to the combined composite circuit protection device, the VDR is still only Can withstand short-term power surges (for example, 0.001 seconds). In other words, if the surge time interval exceeds a cut-off time interval, the VDR will be burned or damaged due to overcurrent and overvoltage, causing the composite circuit protection device to permanently lose its function.

Therefore, the purpose of the present invention is to provide a composite circuit protection device that can overcome at least one of the above-mentioned shortcomings of the prior art.

Therefore, the composite circuit protection device of the present invention includes a first positive temperature coefficient (PTC) element, a second PTC element, a varistor, a first conductive lead, a second conductive lead, and a third conductive lead. lead. The first PTC element includes a first PTC layer, a first electrode layer, and a second electrode layer. The first PTC layer has two opposite surfaces. The first electrode layer and the second electrode layer are respectively disposed on the first PTC layer. Two opposite surfaces of the PTC layer. The second PTC element includes a second PTC layer, a third electrode layer, and a fourth electrode layer. The second PTC layer has two opposite surfaces. The third electrode layer and the fourth electrode layer are respectively disposed on the first PTC layer. Two opposite surfaces of the PTC layer. The varistor is connected to the second electrode layer of the first PTC element and the third electrode layer of the second PTC element. The first conductive lead is connected to the first electrode layer of the first PTC element. The second conductive lead is connected to the varistor. The third conductive lead is connected to the fourth electrode layer of the second PTC element.

The effect of the present invention is that the composite circuit protection device of the present invention has excellent tolerance and reliability, and can protect the varistor sandwiched between two PTC elements from burning under the presence of overcurrent and overvoltage.

Before the present invention is described in detail, it should be noted that in the following description, similar elements are denoted by the same numbers.

2 and 3, the first embodiment of the composite circuit protection device of the present invention includes a first positive temperature coefficient (PTC) element 2, a varistor 3, a second PTC element 4, a first The conductive lead 5, a second conductive lead 6 and a third conductive lead 7.

The first PTC element 2 includes a first PTC layer 21, a first electrode layer 22, and a second electrode layer 23. The first PTC layer 21 has two opposite surfaces 211, the first electrode layer 22 and the second electrode The layers 23 are respectively arranged on two opposite surfaces 211 of the first PTC layer 21.

The second PTC element 4 includes a second PTC layer 41, a third electrode layer 42, and a fourth electrode layer 43. The second PTC layer 41 has two opposite surfaces 411, the third electrode layer 42 and the fourth electrode The layers 43 are respectively disposed on two opposite surfaces 411 of the second PTC layer 41.

The varistor 3 is connected to the second electrode layer 23 of the first PTC element 2 and the third electrode layer 42 of the second PTC element 4 by a solder.

The first conductive lead 5 is connected to the first electrode layer 22 of the first PTC element 2. The second conductive lead 6 is connected to the varistor 3. The third conductive lead 7 is connected to the fourth electrode layer 43 of the second PTC element 4.

In some specific embodiments of the present invention, the first PTC element 2 has a rated voltage, the rated voltage is between 40% and 200% of the voltage measured by the varistor 3 at 1 mA. Sensitive voltage (varistor voltage). In some specific embodiments of the present invention, the rated voltage of the first PTC element 2 is between 110% and 200% of the varistor voltage measured by the varistor 3 at 1 mA.

According to the present invention, the first PTC element 2 or the second PTC element 4 is under an overcurrent and a voltage greater than the varistor voltage of the varistor 3 and trips before the varistor 3 burns out. In other words, in the presence of the overcurrent and the voltage greater than the varistor voltage of the varistor 3, the first PTC element 2 or the second PTC element 4 quickly trips to a high resistance state to The overcurrent is restricted not to flow through the varistor 3, thereby protecting the varistor 3 from burning, and the composite circuit protection device can therefore be reused.

In this article, the terms "burnt", "sparking" and "fire" can be used interchangeably, and mean that the varistor 3 loses its function, which usually occurs above 180°C.

In some specific embodiments of the present invention, the first PTC element 2 or the second PTC element 4 is under an overcurrent and a voltage greater than the varistor voltage of the varistor 3, and the temperature is between 10 μs and 10 μs. Jump within s. In some specific embodiments of the present invention, the first PTC element 2 or the second PTC element 4 is under an overcurrent of not less than 0.5 A and a voltage greater than the varistor voltage of the varistor 3. Trip within 1 ms to 10 s. In some embodiments of the present invention, the first PTC element 2 or the second PTC element 4 is under an overcurrent of not less than 10 A and a voltage greater than the varistor voltage of the varistor 3. Trip within 1 ms to 1 s.

The first PTC element 2 may be formed with a first hole 210. In this embodiment, the first hole 210 is formed in the first PTC layer 21. The first PTC layer 21 of the first PTC element 2 has a peripheral edge 212 that defines the boundary of the first PTC layer 21 and is interconnected with two opposite surfaces 211 of the first PTC layer 21. The first hole 210 is spaced from the periphery 212 of the first PTC layer 21, and has an effective volume that can accommodate the thermal expansion of the first PTC layer 21 when the temperature rises, so as to prevent the first PTC layer 21 from being undesired. The structure is deformed.

In some embodiments of the present invention, the first hole 210 penetrates at least one of the two opposite surfaces 211 of the first PTC layer 21. In some embodiments of the present invention, the first hole 210 also penetrates at least one of the first electrode layer 22 and the second electrode layer 23. In this embodiment, the first hole 210 penetrates two opposite surfaces 211 of the first PTC layer 21 and the first electrode layer 22 and the second electrode layer 23 to form a through hole. In some embodiments of the present invention, the first hole 210 extends along a line passing through the geometric center of the first PTC layer 21 and across the two opposite surfaces 211. The first hole 210 is defined by a first hole defining wall, and the first hole defining wall has a cross section parallel to the surface 211 of the first PTC layer 21. The cross-section of the first hole-defining wall can be circular, square, elliptical, triangular, cross-shaped, and the like.

The second PTC element 4 can be formed with a second hole 410. In this embodiment, the second hole 410 is formed in the second PTC layer 41. The second PTC layer 41 of the second PTC element 4 has a peripheral edge 412 that defines the boundary of the second PTC layer 41 and is interconnected with two opposite surfaces 411 of the second PTC layer 41. The second hole 410 is spaced from the periphery 412 of the second PTC layer 41, and has an effective volume that can accommodate the thermal expansion of the second PTC layer 41 when the temperature rises, so as to prevent the second PTC layer 41 from being undesired. The structure is deformed.

In some embodiments of the present invention, the second hole 410 penetrates at least one of the two opposite surfaces 411 of the second PTC layer 41. In some embodiments of the present invention, the second hole 410 also penetrates at least one of the third electrode layer 42 and the fourth electrode layer 43. In this embodiment, the second hole 410 penetrates two opposite surfaces 411 of the second PTC layer 41 and the third electrode layer 42 and the fourth electrode layer 43 to form a through hole. In some embodiments of the present invention, the second hole 410 extends along a line passing through the geometric center of the second PTC layer 41 and across the two opposite surfaces 411. The second hole 410 is defined by a second hole defining wall, and the second hole defining wall has a cross section parallel to the surface 411 of the second PTC layer 41. The cross-section of the second hole-defining wall can be round, square, elliptical, triangular, cross-shaped, and the like.

According to the present invention, both the first PTC element 2 and the second PTC element 4 can be polymer PTC (PPTC) elements, and the first PTC layer 21 and the second PTC layer 41 can both be PTC polymer layers. The PTC polymer layer includes a polymer substrate and a conductive filler dispersed in the polymer substrate. The polymer substrate can be made of a polymer composition containing a non-grafted olefin-based polymer. In some specific embodiments of the present invention, the non-grafted olefin-based polymer is high-density polyethylene (HDPE). In some specific embodiments of the present invention, the polymer composition further includes a grafted olefin-based polymer. In some specific embodiments of the present invention, the grafted olefin-based polymer is an olefin-based polymer grafted with carboxylic anhydride. The conductive filler suitable for the present invention is selected from carbon black powder, metal powder, conductive ceramic powder or a combination of the foregoing, but is not limited thereto.

The varistor 3 may include a varistor layer 31, a fifth electrode layer 32 and a sixth electrode layer 33. The varistor layer 31 has two opposite surfaces 311, and the fifth electrode layer 32 and the sixth electrode layer 33 are respectively disposed on the two opposite surfaces 311 of the varistor layer 31. The second conductive lead 5 can be connected to the fifth electrode layer 32 or the sixth electrode layer 33 of the varistor 3. In some specific embodiments of the present invention, the varistor layer 31 is made of a metal oxide material.

In this embodiment, the fifth electrode layer 32 is connected to the second electrode layer 23 of the first PTC element 2. The second conductive lead 6 is connected and disposed between the sixth electrode layer 33 of the varistor 3 and the third electrode layer 42 of the second PTC element 4.

The varistor 3 may have a third hole 310 formed in the varistor layer 31. In this embodiment, the piezoresistor layer 31 of the piezoresistor 3 has a peripheral edge 312 that defines the boundary of the piezoresistor layer 31 and is opposite to two of the piezoresistor layer 31 The surfaces 311 are interconnected. The third hole 310 is spaced apart from the periphery 312 of the varistor layer 31.

In some embodiments of the present invention, the third hole 310 penetrates at least one of the two opposite surfaces 311 of the varistor layer 31. In some embodiments of the present invention, the third hole 310 also penetrates at least one of the fifth electrode layer 32 and the sixth electrode layer 33. In this embodiment, the third hole 310 penetrates two opposite surfaces 311 of the varistor layer 31 and the fifth electrode layer 32 and the sixth electrode layer 33 to form a through hole.

The first conductive lead 5 may have a first connecting portion 51 and a first free portion 52, the second conductive lead 6 may have a second connecting portion 61 and a free portion 62, and the third conductive lead 7 may have A third connecting portion 71 and a third free portion 72.

In this embodiment, the first connecting portion 51 of the first conductive lead 5 is connected to the outer surface of the first electrode layer 22 of the first PTC element 2 by a solder, and the first conductive lead 5 is The free portion 52 extends from the first connecting portion 51 to the first electrode layer 22 for insertion into a pin hole of a circuit board or a circuit device (not shown).

The second connecting portion 61 of the second conductive lead 6 is connected by a solder and is arranged between the sixth electrode layer 33 and the third electrode layer 42, and the second free portion 62 of the second conductive lead 6 is self-contained The second connecting portion 61 extends from the sixth electrode layer 33 and the third electrode layer 42 for insertion into a pin hole of a circuit board or a circuit device (not shown).

The third connecting portion 71 of the third conductive lead 7 is connected to the outer surface of the fourth electrode layer 43 of the second PTC element 4 by a solder, and the third free portion 72 of the third conductive lead 7 is connected to the outer surface of the fourth electrode layer 43 of the second PTC element 4 by a solder. The three connecting portions 71 extend out of the fourth electrode layer 43 for insertion into a pin hole of a circuit board or a circuit device (not shown).

4 and 5, the second embodiment of the composite circuit protection device of the present invention is similar to the first embodiment, the difference is that the second embodiment also includes a packaging material 8 that packages the first The PTC element 2, the varistor 3, the second PTC element 4, a part of the first conductive lead 5, a part of the second conductive lead 6 and a part of the third conductive lead 7. The first free part 52 of the first conductive lead 5, the second free part 62 of the second conductive lead 6 and the third free part 72 of the third conductive lead 7 are exposed outside the packaging material 8. In some specific embodiments of the present invention, the packaging material 8 is made of epoxy resin.

Referring to FIG. 6, the third embodiment of the composite circuit protection device of the present invention is similar to the second embodiment, the difference is that the third embodiment also includes a third PTC element 9 (or another varistor 9) , Connected to the third conductive lead 7. The third PTC element 9 (or the other varistor 9) includes a third PTC layer 91 (or another varistor layer 91), and the third PTC layer 91 (or the other varistor layer 91) The resistor layer 91) has two opposite surfaces 911, a seventh electrode layer 92 and an eighth electrode layer 93, and the seventh electrode layer 92 and the eighth electrode layer 93 are respectively disposed on the two opposite surfaces 911. The third conductive lead 7 is connected and disposed between the fourth electrode layer 43 and the seventh electrode layer 92. The packaging material 8 also packages the third PTC layer 91 (or the other varistor layer 91). The third PTC layer 91 (or the other varistor layer 91) may be formed with a fourth hole (not shown).

7 and 8, the fourth embodiment of the composite circuit protection device of the present invention is similar to the third embodiment, the difference is that the fourth embodiment also includes a fourth conductive lead 10, the fourth conductive lead 10 Connected to the eighth electrode layer 93, the fourth conductive lead 10 has a fourth connection portion 101 and a fourth free portion 102. The fourth connecting portion 101 of the fourth conductive lead 10 is connected to the outer surface of the eighth electrode layer 93, and the fourth free portion 102 of the fourth conductive lead 10 extends from the fourth connecting portion 101 to the eighth electrode The layer 93 is for inserting into a pin hole of a circuit board or a circuit device (not shown). In addition, the packaging material 8 packages the first PTC element 2, the varistor 3, the second PTC element 4, the third PTC element 9 (or the other varistor 9), and a part of the first PTC element The conductive lead 5, a part of the second conductive lead 6, a part of the third conductive lead 7 and a part of the fourth conductive lead 10. The first free part 52 of the first conductive lead 5, the second free part 62 of the second conductive lead 6, the third free part 72 of the third conductive lead 7, and the fourth free part of the fourth conductive lead 10 102 is exposed outside the packaging material 8.

The present invention will be further illustrated with the following examples, but it should be understood that these examples are for illustrative purposes only and should not be construed as limitations to the implementation of the present invention.

Example

＜Example 1 (E1) ＞

22 g HDPE (purchased from Taiwan Plastics Industry Co., Ltd., product model: HDPE9002) as a non-grafted olefin polymer, 22 g of HDPE grafted with maleic anhydride (purchased from DuPont, product model: MB100D) as a non-grafted olefin polymer Olefin-based polymer grafted with carboxylic anhydride, 56 g carbon black powder (purchased from Columbian Chemicals, product model: Raven 430UB) as conductive filler.

The above three ingredients are mixed in a mixer (brand: Brabender), and the ingredients are mixed for 10 minutes under the conditions of a temperature of 200°C and a stirring speed of 30 rpm to obtain the first ingredient mixture.

In addition, 21 g of HDPE, 21 g of HDPE grafted with maleic anhydride, and 58 g of carbon black powder were mixed and compounded under the same conditions as above to obtain a second compounding mixture.

The first ingredient mixture and the second ingredient mixture obtained above are respectively placed in a mold, and hot-pressed under ^{the conditions of a hot-pressing temperature of 200°C and a hot-pressing pressure of 80 kg/cm 2} for 4 minutes to form a first PTC polymer layer sheet and a second PTC polymer layer sheet. After the two sheets are taken out of the mold, the first PTC polymer layer sheet is placed between the two copper foils (as the first electrode layer and the second electrode layer respectively), and the second PTC polymer layer sheet is placed Two pieces of copper foil (as the third electrode layer and the fourth electrode layer, respectively), and ^{hot-pressed at 200 ℃ and 80 kg/cm 2} for 4 min to form the first PPTC element and the thickness of 0.42 mm respectively The second PPTC element. Then cut the first PPTC element into a plurality of circular chips (chips, hereinafter referred to as PPTC-1) with a diameter of 6.4 mm, and cut the second PPTC element into a plurality of 9.5 mm × 11.5 mm chips (chips). , Hereinafter referred to as PPTC-2), irradiate each small piece with Co-60 gamma rays with a total radiation dose of 150 kGy.

The second conductive lead is welded to one side of a metal oxide varistor (MOV, purchased from Ceramate Technical Company, product model: 07D270K), and then one of the copper foils of PPTC-1 and one of PPTC-2 The copper foil is respectively welded on the side of the MOV where the second conductive lead is welded and the opposite side of the non-welded second conductive lead (that is, the MOV is sandwiched between PPTC-1 and PPTC-2), and then the first conductive lead is welded to PPTC-1 is opposite to the copper foil of the MOV, and the third conductive lead is welded to one of the copper foils of PPTC-2 to form an E1 composite circuit protection device.

According to Underwriter Laboratories' safety standard UL 1434 for thermistor-type device (thermistor-type device), measure the holding current of each PPTC-1 and each PPTC-2 (hold current, that is, the maximum current value during normal operation) , Trip current (trip current, that is, the minimum current value required for the PPTC element to reach a high resistance state), rated voltage (ie the voltage applicable to the PPTC element when it works) and withstand voltage (that will not cause the PPTC element to malfunction Or damage the maximum voltage). In addition, according to Underwriter Laboratories’ safety standard UL 1449 for transient voltage surge suppressors, the varistor voltage (that is, the voltage at which the MOV triggers the work) and the clamping voltage (the clamping voltage) of the MOV element can be measured. Limited maximum voltage). The property measurement results of PPTC-1, PPTC-2 and MOV are shown in Table 1, respectively. 【Table 1】 Hold current Trip current Rated voltage Withstand voltage PPTC-1 0.90 A 1.80 A 30 V 30 V PPTC-2 5.00 A 8.50 A 16 V 16 V Varistor voltage ^a Clamping voltage ^b MOV 27 V 53 V a: Measured at 1 mA. b: Measured at pulse waveform (t _p ) 8/20 μs and pulse current (I _p ) 2.5 A.

＜Example 2 To 8 (E2-E8) ＞

The process conditions of the E2-E8 composite circuit protection device are similar to those of E1. The difference is that PPTC-1 is formed with a first through hole and/or PPTC-2 is formed with a second through hole and/or MOV is formed with a third through hole (such as As shown in Table 2), each first perforation, each second perforation, and each third perforation are defined by a hole-defining wall ^{having a circular cross-section (diameter of 1.5 mm, circular area of 1.77 mm 2 ).}

Specifically, in E2, after γ-ray irradiation, the first perforation is drilled in the central part of PPTC-1. In E3, before welding to PPTC-1 and PPTC-2, a third hole is drilled in the center of the MOV. In E4, the first perforation is drilled in the central part of PPTC-1 and the third perforation is drilled in the central part of the MOV. In E5, after gamma-ray irradiation, a second perforation was drilled in the central part of PPTC-2. In E6, the first perforation is drilled in the central part of PPTC-1 and the second perforation is drilled in the central part of PPTC-2. In E7, a third perforation is drilled in the central part of the MOV and a second perforation is drilled in the central part of PPTC-2. In E8, the first perforation is cut in the central part of PPTC-1, the third perforation is cut in the central part of the MOV, and the second perforation is cut in the central part of PPTC-2 (as shown in Figure 3).

＜Comparative example 1 To 2 (CE1-CE2) ＞

The process conditions of the circuit protection devices of CE1 and CE2 are similar to those of E1 and E2, respectively. The difference is that CE1 and CE2 do not contain MOV and PPTC-2, and the first conductive lead and the second conductive lead are respectively welded to the PPTC-1 Two pieces of copper foil.

＜Comparative example 3 To 4 (CE3-CE4) ＞

The process conditions of the circuit protection devices of CE3 and CE4 are similar to those of E1 and E3, respectively. The difference is that CE3 and CE4 do not contain PPTC-1 and PPTC-2, and the first conductive lead and the second conductive lead are respectively welded to the MOV On two opposite surfaces.

＜Comparative example 5 To 6 (CE5-CE6) ＞

The process conditions of the circuit protection devices of CE5 and CE6 are similar to those of E1 and E5, respectively. The difference is that CE5 and CE6 do not contain PPTC-1 and MOV, and the first conductive lead and the second conductive lead are respectively welded to the PPTC-2 Two pieces of copper foil.

＜Comparative example 7 To 10 (CE7-CE10) ＞

The process conditions of the CE7-CE10 composite circuit protection device are similar to those of E1, E5, E3, and E7. The difference is that CE7-CE10 does not contain PPTC-1, and the first conductive lead and the second conductive lead are respectively welded to On the two opposite surfaces of the MOV, the third conductive lead is soldered to one of the copper foils of PPTC-2.

The structure of E1-E8 and CE1-CE10 (composite) circuit protection devices is shown in Table 2. 【Table 2】 (Composite) Circuit Protection Device PPTC-1 First perforation MOV Third perforation PPTC-2 Second piercing E1 have - have - have - E2 have have have - have - E3 have - have have have - E4 have have have have have - E5 have - have - have have E6 have have have - have have E7 have - have have have have E8 have have have have have have CE1 have - - - - - CE2 have have - - - - CE3 - - have - - - CE4 - - have have - - CE5 - - - - have - CE6 - - - - have have CE7 - - have - have - CE8 - - have - have have CE9 - - have have have - CE10 - - have have have have "--" means there is no such component.

Performance Testing

[ Hold current test (Hold current test)]

Take 10 (composite) circuit protection devices of E1-E8 and CE1-CE10 each as test samples, and conduct a holding current test to determine the maximum holding current of the test sample.

The holding current test is to apply _{a direct current voltage of 16 V dc} at 25°C, while keeping the trip (trip), for each test sample to measure for 15 minutes. The test results are shown in Table 3 respectively.

[ Trip time test (Time-to-trip test)]

Take 10 (composite) circuit protection devices of E1-E8 and CE1-CE10 each as test samples, and conduct a trip time test to determine the trip time of the test sample.

The trip time test is to apply _{a DC voltage of 16 V dc} and a trip current of 8.5 A at 25°C to measure the trip time of each test sample. The test results are shown in Table 3 respectively. 【table 3】 Hold current test Trip time test Average maximum holding current (A) Average trip time (s) E1 6.00 24.400 E2 6.10 24.210 E3 6.10 23.950 E4 6.30 23.900 E5 6.30 23.750 E6 6.40 23.700 E7 6.30 23.500 E8 6.50 23.220 CE1 0.90 0.555 CE2 0.95 0.540 CE3 N/A N/A CE4 N/A N/A CE5 5.00 21.485 CE6 5.40 20.530 CE7 5.30 22.500 CE8 5.70 21.265 CE9 5.30 22.150 CE10 5.70 21.125

"N/A" means not applicable.

The results in Table 3 show that the average maximum holding current of the E1-E8 test samples at 16 V _dc is between 6.0 A and 6.5 A, which is higher than the CE1-CE2 and CE5-CE10 test samples.

[ Surge immunity test (Surge immunity test)]

Take 10 of the E1-E8 and CE1-CE10 composite circuit protection devices as test samples for the surge immunity test.

The surge immunity test is based on the constant voltage (38 V _dc and 44 V _dc , the varistor voltage greater than MOV) and constant current (0.5 A and 10 A) connect the first conductive lead and the second conductive lead for 60 seconds and then turn off Way to test. If neither the PPTC chip nor the MOV is burnt or damaged, the test sample has passed the surge immunity test, and the average value of the time for the PPTC chip to escape (if any) is recorded. If the PPTC chip or MOV is burned, the test sample is burned, and the average time of burning is recorded. The results are shown in Table 4, respectively. 【Table 4】 38 V/0.5 A 38 V/10 A 44 V/0.5 A 44 V/10 A result Time(s) result Time(s) result Time(s) result Time(s) E1 pass through 1.400 pass through 0.455 pass through 1.365 pass through 0.155 E2 pass through 1.375 pass through 0.450 pass through 1.285 pass through 0.150 E3 pass through 1.250 pass through 0.440 pass through 1.210 pass through 0.140 E4 pass through 1.205 pass through 0.435 pass through 1.170 pass through 0.135 E5 pass through 1.385 pass through 0.430 pass through 1.295 pass through 0.140 E6 pass through 1.350 pass through 0.420 pass through 1.250 pass through 0.125 E7 pass through 1.245 pass through 0.405 pass through 1.190 pass through 0.115 E8 pass through 1.200 pass through 0.395 pass through 1.155 pass through 0.100 CE1 pass through No jump PPTC-1 burned 0.425 pass through No jump PPTC-1 burned 0.415 CE2 pass through No jump PPTC-1 burned 0.410 pass through No jump PPTC-1 burned 0.410 CE3 MOV burned 4.700 MOV burned 2.260 MOV burned 4.310 MOV burned 1.030 CE4 MOV burned 4.435 MOV burned 2.050 MOV burned 3.885 MOV burned 1.015 CE5 pass through No jump PPTC-2 burned 0.920 pass through No jump PPTC-2 burned 0.920 CE6 pass through No jump PPTC-2 burned 0.915 pass through No jump PPTC-2 burned 0.910 CE7 MOV burned 4.850 MOV burned 2.500 MOV burned 4.445 MOV burned 1.115 CE8 MOV burned 4.450 MOV burned 2.450 MOV burned 4.405 MOV burned 1.095 CE9 MOV burned 4.350 MOV burned 2.450 MOV burned 4.105 MOV burned 1.080 CE10 MOV burned 4.340 MOV burned 2.250 MOV burned 4.035 MOV burned 1.055

The results in Table 4 show that the test samples of CE3-CE4 containing only MOV burned within 5 s at an overcurrent of 0.5 A and a voltage of at least 1.4 times the varistor voltage of the MOV (generally MOV can withstand 1.2 times its varistor voltage的voltage), or burned within 2.5 s under an overcurrent and overvoltage of 10 A, and the damage cannot be repaired. The test samples CE1-CE2 containing only PPTC-1 and the test samples CE5-CE6 containing only PPTC-2 burned down at an overcurrent of 10 A. The CE7-CE10 test samples containing MOV and PPTC-2 also burned under overvoltage.

On the contrary, all test samples E1-E8 containing a combination of PPTC-1, MOV and PPTC-2 (the rated voltage of PPTC-1 is about 111% of the varistor voltage measured by MOV at 1 mA) all pass the burst Wave immunity test without burning. In addition, compared to E1, E2-E8 PPTC chips and/or MOVs with perforated test samples have improved heat transfer, which can further shorten the time for PPTC chips to trip, and prevent overcurrent from flowing through the MOV, thereby protecting them MOV is free from burning. In other words, in the test samples of E1-E8, the small PPTC chip is under an overcurrent and a voltage greater than the varistor voltage of the MOV and trips before the MOV burns.

In summary, since the PTC element can quickly trip to a high resistance state in the presence of overcurrent and overvoltage, the present invention can protect the varistor by connecting a varistor to two PTC elements The device is prevented from being burnt due to overcurrent, and the composite circuit protection device of the present invention can be reused without damage, and exhibits its excellent endurance and reliability, so it can indeed achieve the purpose of the invention.

However, the above are only examples of the present invention, and should not be used to limit the scope of implementation of the present invention, all simple equivalent changes and modifications made in accordance with the scope of the patent application of the present invention and the content of the patent specification still belong to This invention patent covers the scope.

20: PTC polymer substrate 30: Electrode 40: Hole 50: Conductive lead pin 60: Conductive lead pin 2: The first PTC component 21: The first PTC layer 210: first hole 211: Surface 212: Perimeter 22: The first electrode layer 23: second electrode layer 3: Varistor 31: Varistor layer 310: third hole 311: Surface 312: Perimeter 32: Fifth electrode layer 33: sixth electrode layer 4: The second PTC component 41: The second PTC layer 410: second hole 411: Surface 412: Perimeter 42: third electrode layer 43: Fourth electrode layer 5: The first conductive lead 51: The first connection part 52: First Freedom 6: The second conductive lead 61: The second connecting part 62: Second Freedom 7: The third conductive lead 71: The third connecting part 72: Third Freedom 8: Packaging material 9: The third PTC element / varistor 91: the third PTC layer / varistor layer 911: Surface 92: seventh electrode layer 93: Eighth electrode layer 10: The fourth conductive lead 101: The fourth connecting part 102: The Fourth Freedom

Other features and effects of the present invention will be clearly presented in the embodiments with reference to the drawings, in which: [Figure 1] is a schematic diagram of an existing plug-in PPTC overcurrent protection device; [Figure 2] is a schematic diagram of the first specific embodiment of the composite circuit protection device of the present invention; [Figure 3] is a schematic cross-sectional view of the first specific embodiment; [Figure 4] is a schematic diagram of the second specific embodiment of the composite circuit protection device of the present invention; [Figure 5] is a schematic cross-sectional view of the second specific embodiment; [Figure 6] is a schematic cross-sectional view of the third embodiment of the composite circuit protection device of the present invention; [Figure 7] is a schematic diagram of the fourth embodiment of the composite circuit protection device of the present invention; and [Figure 8] is a schematic cross-sectional view of the fourth embodiment.

2: The first PTC component

21: The first PTC layer

210: first hole

211: Surface

22: The first electrode layer

23: second electrode layer

3: Varistor

31: Varistor layer

310: third hole

311: Surface

32: Fifth electrode layer

33: sixth electrode layer

4: The second PTC component

41: The second PTC layer

410: second hole

411: Surface

42: third electrode layer

43: Fourth electrode layer

5: The first conductive lead

51: The first connection part

52: First Freedom

6: The second conductive lead

61: The second connecting part

62: Second Freedom

7: The third conductive lead

71: The third connecting part

72: Third Freedom

Claims (24)

A composite circuit protection device, including: A first PTC component, including: A first PTC layer with two opposite surfaces, and A first electrode layer and a second electrode layer respectively disposed on two opposite surfaces of the first PTC layer; A second PTC component, including: A second PTC layer with two opposite surfaces, and A third electrode layer and a fourth electrode layer respectively disposed on two opposite surfaces of the second PTC layer; A varistor connected to the second electrode layer of the first PTC element and the third electrode layer of the second PTC element; A first conductive lead connected to the first electrode layer of the first PTC element; A second conductive lead connected to the varistor; and A third conductive lead is connected to the fourth electrode layer of the second PTC element. The composite circuit protection device according to claim 1, wherein the rated voltage of the first PTC element is between 40% and 200% of the varistor voltage measured by the varistor at 1 mA. The composite circuit protection device according to claim 2, wherein the rated voltage of the first PTC element is between 110% and 200% of the varistor voltage measured by the varistor at 1 mA. The composite circuit protection device according to claim 1, wherein the first PTC element or the second PTC element is under an overcurrent and a voltage greater than the varistor voltage, and the varistor The resistor trips before it burns out. The composite circuit protection device according to claim 1, wherein the first PTC element or the second PTC element is under an overcurrent and a voltage greater than the varistor voltage of the varistor and is within 10 μs to Trip within 10 s. The composite circuit protection device according to claim 1, wherein the first PTC element or the second PTC element is under an overcurrent of not less than 0.5 A and a voltage greater than the varistor voltage However, it trips within 1 ms to 10 s. The composite circuit protection device according to claim 1, wherein the first PTC element or the second PTC element is at an overcurrent of not less than 10 A and a voltage greater than the varistor voltage And it trips within 1 ms to 1 s. The composite circuit protection device according to claim 1, wherein the first PTC element has a first hole formed in the first PTC layer. The composite circuit protection device according to claim 8, wherein the first PTC layer of the first PTC element has a peripheral edge that defines a boundary of the first PTC layer and is opposite to two of the first PTC layer The surfaces are interconnected, and the first hole is spaced from the periphery of the first PTC layer. The composite circuit protection device according to claim 8, wherein the first hole penetrates at least one of the two opposite surfaces of the first PTC layer. The composite circuit protection device according to claim 10, wherein the first hole further penetrates at least one of the first electrode layer and the second electrode layer. The composite circuit protection device according to claim 8, wherein the second PTC element is formed with a second hole in the second PTC layer. The composite circuit protection device according to claim 12, wherein the second PTC layer of the second PTC element has a peripheral edge that defines the boundary of the second PTC layer and is opposite to two of the second PTC layer The surfaces are interconnected, and the second hole is spaced apart from the periphery of the second PTC layer. The composite circuit protection device according to claim 12, wherein the second hole penetrates at least one of the two opposite surfaces of the second PTC layer. The composite circuit protection device according to claim 14, wherein the second hole further penetrates at least one of the third electrode layer and the fourth electrode layer. The composite circuit protection device according to claim 1, wherein the varistor includes: A varistor layer with two opposite surfaces; A fifth electrode layer disposed on one of the two opposite surfaces of the varistor layer and connected to the second electrode layer of the first PTC element; and A sixth electrode layer provided on the other of the two opposite surfaces of the varistor layer, The second conductive lead is connected to the fifth electrode layer or the sixth electrode layer of the varistor. The composite circuit protection device according to claim 16, wherein the varistor has a third hole formed in the varistor layer. The composite circuit protection device according to claim 17, wherein the piezoresistor layer of the piezoresistor has a peripheral edge that defines the boundary of the piezoresistor layer and is connected to the piezoresistor layer. The two opposite surfaces are interconnected, and the third hole is spaced apart from the periphery of the varistor layer. The composite circuit protection device according to claim 18, wherein the third hole penetrates at least one of the two opposite surfaces of the varistor layer. The composite circuit protection device according to claim 19, wherein the third hole further penetrates at least one of the fifth electrode layer and the sixth electrode layer. The composite circuit protection device according to claim 1, wherein the first PTC element and the second PTC element are both polymer PTC elements, and the first PTC layer and the second PTC layer are both PTC polymer layers . The composite circuit protection device according to claim 1, further comprising a packaging material packaging the first PTC element, the varistor, the second PTC element, a part of the first conductive lead, and a part of the The second conductive lead and a part of the third conductive lead. The composite circuit protection device according to claim 1, further comprising a third PTC element or another varistor connected to the third conductive lead. The composite circuit protection device according to claim 23, further comprising a fourth conductive lead connected to the third PTC element or the other varistor opposite to the surface of the third conductive lead .

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