TW202139281A - Micro-electro mechanical system and manufacturing method thereof - Google Patents

Abstract

In a method of manufacturing bumps or pillars, an under bump conductive layer is formed over a substrate, a first photoresist layer having a first opening and a second opening is formed over the under bump conductive layer, a first conductive layer is formed in the first opening and the second opening to form a first low bump and a second low bump, the first photoresist layer is removed, a second photoresist layer having a third opening is formed over the second low bump, a second conductive layer is formed on the second low bump in the third opening to form a high bump having a greater height than the first low bump, and the second photoresist layer is removed.

Description

Microelectromechanical system and manufacturing method thereof

The embodiment of the present invention relates to a microelectromechanical system and a manufacturing method thereof.

Recently, micro-electromechanical system (MEMS) devices have been developed. MEMS devices include devices manufactured using semiconductor technology to form mechanical and electrical components. MEMS devices are implemented in pressure sensors, microphones, actuators, mirrors, heaters, and/or printer nozzles. Although existing devices and methods for forming MEMS devices are generally suitable for their intended purpose, they are not yet fully satisfactory in all respects.

An embodiment of the present invention relates to a method for manufacturing bumps or pillars, which includes: forming an under-bump conductive layer on a substrate; forming a first opening and a second opening on the under-bump conductive layer. Opening a first photoresist layer; forming a first conductive layer in the first opening and the second opening to form a first low bump and a second low bump; removing the first photoresist Agent layer; a second photoresist layer having a third opening is formed above the second low bump; a second conductive layer is formed in the third opening on the second low bump to form a A high bump with a height of the first low bump; and removing the second photoresist layer.

An embodiment of the present invention relates to a method of manufacturing bumps or pillars, which includes: forming pad electrodes on a substrate; forming an insulating layer on the pad electrodes; and patterning the insulating layer to partially expose the pads Electrodes; forming a conductive layer under bumps over the insulating layer and the exposed pad electrodes; a first photoresist layer with a first opening and a second opening formed above the conductive layer under bumps ; Form a first conductive layer in the first opening and the second opening to form a first low bump and a second low bump; remove the first photoresist layer; formed in the second low A second photoresist layer having a third opening above the bump; a second conductive layer is formed in the third opening on the second low bump to form a second photoresist layer larger than the first low bump A high bump with a height; remove the second photoresist layer; form a third photoresist layer with a fourth opening that exposes a part of the conductive layer under the bump, and the third photoresist layer covers The first low bump and the high bump; forming one or more conductive layers in the fourth opening on the exposed portion of the conductive layer under the bump to form a third low bump; removing the A third photoresist layer; and removing the portion of the conductive layer under the bump that is not covered by the first low bump, the third low bump, and the high bump.

An embodiment of the present invention relates to a semiconductor device, which includes: a substrate; and a first bump structure disposed on the substrate, wherein: the first bump structure includes a bump disposed on the substrate A first bump with a first height above the lower conductive layer and made of Au or Au alloy, and the lower conductive layer of the bump includes a lower layer made of Ti or Ti alloy and a lower layer made of Au or Au alloy As one of the upper floors.

It should be understood that the following disclosures provide many different embodiments or examples for implementing different features of the embodiments of the present invention. Specific embodiments or examples of components and configurations are described below to simplify the disclosure. Of course, these are only examples and are not intended to be limiting. For example, the size of the element is not limited to the disclosed range or value, but may depend on the process conditions and/or desired properties of the device. In addition, in the following description, a first member formed on or on a second member may include an embodiment in which the first member and the second member are formed in direct contact, and may also include an additional member may be formed An embodiment in which the first member and the second member are interposed so that the first member and the second member may not directly contact each other. For simplicity and clarity, various components can be drawn arbitrarily at different scales.

In addition, for ease of description, spatially relative terms such as "below", "below", "below", "above", "upper" and the like can be used herein to describe an element or component The relationship with another element(s) or component is as shown in the figure. Spatial relative terms are intended to cover different orientations of the device in use or operation in addition to the orientations depicted in the figures. The device can be oriented in other ways (rotated by 90 degrees or in other orientations) and the spatial relative descriptors used herein can be interpreted accordingly. In addition, the term "made of" can mean "including" or "consisting of". In this disclosure, unless otherwise indicated, at least one of A, B and C means "A", "B", "C", "A and B", "A and C", "B and C" "Or "A, B and C", and does not mean from one of A, from one of B, and from one of C. The materials, configurations, dimensions, and manufacturing processes described in one embodiment can be applied to other embodiments, and detailed descriptions thereof may be omitted. In this disclosure, the phrase "same material" or "different material" can mean that most of the elements are the same or different.

The MEMS device or semiconductor device according to the present disclosure can be an electron beam deflector, an electromagnetic beam deflector, an accelerometer, a gyroscope, a pressure sensor, a microphone, an RF resonator, an RF switch or Any of an ultrasonic transducer. In some embodiments, the MEMS device includes a beam deflector, by which one of the electronic circuits embedded in the MEMS device operates to make one or more electrons or extreme ultraviolet (EUV) light The beam is deflected.

1A and 1B show schematic cross-sectional views of a MEMS device according to an embodiment of the disclosure.

As shown in FIG. 1A, the MEMS device 10 includes a circuit substrate 20 in which an electronic circuit 25 is formed, and a support substrate 30 having a groove 35. In some embodiments, an insulating layer 40 (a bonding layer) is disposed between the circuit substrate 20 and the supporting substrate 30. In some embodiments, the insulating layer 40 is one or more of a silicon oxide layer, a silicon nitride layer, or any other metal oxide or nitride layer. In some embodiments, one or more through holes 60 are arranged to pass through the circuit substrate 20. In some embodiments, in a plan view, the through holes 60 are arranged in an n×m matrix, where n and m are integers of 2 or greater and equal to or less than 128, for example. The electronic circuit 25 includes a transistor, including a semiconductor field effect transistor such as a complementary metal oxide semiconductor (CMOS) device. In some embodiments, the circuit substrate 20 includes an electronic circuit 25, such as a signal processing circuit and/or an amplifier circuit formed by the electronic circuit. In some embodiments, the circuit substrate 20 is made of crystalline silicon or any other suitable semiconductor material.

In some embodiments, the thickness of the circuit substrate 20 is in a range from about 100 µm to about 500 µm. In some embodiments, the thickness of the support substrate 30 is in a range from about 300 µm to about 1500 µm. In some embodiments, the thickness of the insulating layer 40 is in a range from about 500 nm to about 5 µm, and in other embodiments, in a range from about 1 µm to about 2 µm. In some embodiments, the total thickness of the MEMS device is in a range from about 500 μm to about 2 mm, and in other embodiments, in a range from about 600 μm to about 1200 μm.

In some embodiments, one or more passivation films 28 are formed on the front surface of the circuit substrate 20. In some embodiments, the one or more passivation films 28 include silicon oxide, silicon nitride, or organic films.

In some embodiments, the first conductive layer 50 is formed on a front surface of the circuit substrate 20 and the second conductive layer 55 is formed on a back surface of the support substrate 30, as shown in FIG. 1A. In some embodiments, the first conductive layer 50 is also formed on at least a part of the inner wall of the through hole 60 and the passivation film 28, and the second conductive layer 55 is also formed on at least a part of the inner wall of the through hole 60. In some embodiments, the first conductive layer 50 and/or the second conductive layer 55 includes one or more layers of Au, Ti, Cu, Ag, Ni, or alloys thereof. In some embodiments, the first conductive layer 50 is a gold (Au) layer formed on the Ti layer. In other embodiments, the first and/or second conductive layer is composed of one, two, three, four, or five layers made of different materials. For example, in some embodiments, the first conductive layer 50 has A/B/C/D/E, A/B/C/D, A/B/C, A/B or A (A/B means B On A) a layered structure, where each of A, B, C, D, and E represents a metal or a metal material. In other embodiments, the first and/or second conductive layer is composed of two, three, four or five layers, wherein adjacent layers are made of different materials. In some embodiments, each of the metal or metal layer of the first conductive layer 50 has a thickness in a range from about 2 nm to about 100 nm.

In some embodiments, as shown in FIG. 1A, the insulating layer 40 is in contact with the second conductive layer 55 and in contact with the circuit substrate 20. In other embodiments, the insulating layer 40 is kept at the bottom of the cavity 35 and the second conductive layer 55 is not in contact with the circuit substrate 20.

In some embodiments, in plan view, the groove 35 has a rectangular (eg, square) shape. In some embodiments, at least one of the circuit substrate 20 and the supporting substrate 30 is made of crystalline silicon.

In some embodiments, the inner sidewall of the through hole 60 is completely covered by the first conductive layer 50 and the second conductive layer 55. In some embodiments, when a sputtering method is used to form the first and second conductive layers, the conductive layer is not uniformly formed on the inner sidewall of the through hole 60. In some embodiments, the first and/or second conductive layer has a tapered shape. In other embodiments, the thickness of the first and/or second conductive layer is substantially uniform inside the through hole 60. In some embodiments, the first conductive layer 50 partially covers the inner sidewall of the through hole 60. In other embodiments, the first conductive layer 50 completely covers the inner sidewall of the through hole 60. Since the second conductive layer 55 is formed from the back side of the circuit substrate 20, even if the first conductive layer 50 does not completely cover the inner sidewall of the through hole 60, the inner sidewall of the through hole 60 is still completely covered by a conductive material. Since the first and second conductive layers are coupled with each other and completely cover the inner sidewall of the through hole, when the MEMS device is used for electron beam lithography, the problem of electron charging can be suppressed.

In some embodiments, the second conductive layer 55 covers a part of the outer surface of the MEMS device 10, and the first conductive layer 50 is not disposed on the outer surface. In some embodiments, the distance from the bottom to the top of the second conductive layer 55 is equal to or less than the total thickness of the MEMS device from the top of the first conductive layer 50 to the bottom of the second conductive layer 55. In some embodiments, the distance from the interface between the insulating layer 40 and the circuit substrate 20 to the top of the second conductive layer 55 is greater than zero. In other words, the second conductive layer 55 completely covers the side surface of the insulating layer 40. In some embodiments, the second conductive layer 55 on the outer surface is not in contact with the first conductive layer 50 formed on the passivation layer 28. In other embodiments, the second conductive layer 55 on the outer surface is in contact with the first conductive layer 50 formed on the passivation layer 28. The second conductive layer 55 covers the outer surface of the MEMS device 10 to improve heat dissipation.

In some embodiments, as shown in FIG. 1A, the MEMS device 10 includes one or more metal pillars 90 (or metal bumps). In some embodiments, the metal pillar 90 is made of one or more of gold, gold alloy, silver, silver alloy, copper, copper alloy, or any other suitable conductive material. In some embodiments, the metal pillar 90 is electrically coupled to the circuit 25, as shown in FIG. 1B. As shown in FIG. 1B, a pad electrode 32 is formed in the circuit substrate 20, and the circuit substrate 20 is electrically connected to the electronic circuit 25. In some embodiments, one or more underlying conductive layers 50A and 50B are formed between the pad electrode 32 and the metal pillar 90. In some embodiments, the metal pillars 90 have different heights from each other. In some embodiments, the metal pillar 90 includes one or more high pillars 90H and one or more low pillars 90L, as shown in FIG. 1A. In some embodiments, the height of the pillar 90H from the top of the first conductive layer 50 is in a range from about 30 μm to about 100 μm. In some embodiments, the height of the low pillar 90L from the top of the first conductive layer 50 is in a range from about 20 μm to about 50 μm. In some embodiments, the width of the pillar 90 is in a range from about 5 µm to about 10 µm.

In some embodiments, the MEMS device 10 includes a second metal pillar 95 having one or more conductive layers formed on the first conductive layer 50 formed at a periphery of the MEMS device 10. In some embodiments, the underlying conductive layers 50A and 50B are used as the first conductive layer 50.

FIG. 2 shows a use of the MEMS device 10 according to an embodiment of the present disclosure. In some embodiments, the MEMS device 10 is used for an electron beam or an electromagnetic wave lithography. In some embodiments, the electron beam (or EUV ray) 500 is input to the MEMS device 10 from the front side of the circuit substrate 20. The electronic circuit 25 formed in the circuit substrate 20 independently controls the voltage applied to the conductive layer (for example, the first conductive layer 50) formed on the inner wall of each of the holes 60. By adjusting the voltage applied to the conductive layer in the hole 60, a part of the electron beam 500 passes through one or more of the holes 60 and a part of the electron beam 500 does not pass through the hole 60. The portion of the electron beam passing through the hole is guided to a wafer or a substrate on which a photoresist layer is formed. In some embodiments, the wafer is a semiconductor wafer. In some embodiments, the substrate is used for a light shield (such as a transparent substrate or a reflective substrate). By controlling the electronic circuit, the position of the hole through which the electron beam passes is controlled, and therefore a desired shape can be drawn on the photoresist pattern.

In some embodiments, the pillar 90H having a larger height is used as an electrode for removing excess charges and filtering noise. In some embodiments, a column 90L having a smaller height is used to guide (deflect) the electron beam. In some embodiments, the second post 95 serves as an electrode for providing electrical connection with one of one or more other devices.

3A-7B show schematic cross-sectional views of various stages of a fabrication operation for a MEMS device according to an embodiment of the present disclosure. It should be understood that additional operations may be provided before, during, and after the processes shown in FIGS. 3A to 7B, and some operations described below are replaced or eliminated for additional embodiments of the method. The sequence of operations/processes can be interchangeable. The materials, configurations, dimensions, and manufacturing processes described in FIGS. 1A to 1B and FIG. 2 can be applied to the following embodiments, and detailed descriptions thereof may be omitted.

As shown in FIG. 3A, after the circuit substrate 20 with an electronic circuit is formed, one or more planar electrodes 100 are formed on the circuit substrate and one or more passivation layers 110 are formed. The electrode 100 is electrically connected to an electronic circuit formed in the circuit substrate 20. In some embodiments, the circuit substrate 20 includes a crystalline silicon substrate. In some embodiments, one or more openings are formed in one or more passivation layers 110 above the electrode 100. In some embodiments, the electrode 100 is made of one or more layers of Cu, Al, Au, Ni, Ag or other suitable conductive materials. The passivation layer 110 includes silicon nitride, SiON, silicon oxide, aluminum nitride, or organic materials.

Next, one or more holes 120 for through-silicon-via (TSV) are formed in the area other than the electrode 100. The TSV hole 120 corresponds to the hole 60 of FIG. 1A. The TSV hole 120 is formed by one or more lithography and etching operations. In some embodiments, in a plan view, the TSV holes 120 are arranged in an n×m matrix (see FIG. 7A), where n and m are 2 or greater and equal to or less than an integer of 128, for example. In some embodiments, the depth of the TSV from the top of the passivation layer 110 is in a range from about 20 μm to about 100 μm. In some embodiments, the depth is determined so that the bottom of the TSV hole 120 is exposed after a thinning process of the back side of the circuit substrate is subsequently performed. In some embodiments, in plan view, the shape of the TSV hole 120 is circular or rectangular (for example, square). In some embodiments, the TSV hole 120 is wedge-shaped and has an opening larger than a bottom. In some embodiments, a diameter (or a length of a side) of the TSV hole 120 at the opening is in a range from about 100 nm to about 10,000 nm.

Then, a first conductive layer 130 is formed on the electrode 100, the passivation layer 110 and inside the TSV hole 120. Next, a filling layer 140 is formed to fill the TSV hole 120, as shown in FIG. 3B. The first conductive layer 130 has the same or similar functionality as the first conductive layer 50 shown in FIGS. 1A and 1B. In some embodiments, the first conductive layer 130 includes one or more layers of Au, Ti, Cu, Ag, and Ni. In some embodiments, a gold layer formed on the Ti layer is used as the first conductive layer 130. In some embodiments, the thickness of the Ti layer is in a range from about 50 nm to about 200 nm, and in other embodiments, in a range from about 80 nm to about 120 nm. In some embodiments, the thickness of the gold (Au) layer is in a range from about 10 nm to about 400 nm, and in other embodiments, in a range from about 150 nm to about 250 nm. In some embodiments, the filling layer 140 includes silicon oxide or any other suitable insulating material. In some embodiments, a blanket layer of a filling material is formed on the first conductive layer 130, and then a planarization operation (such as a chemical mechanical polishing process or an etch-back process) is performed to only inside the TSV hole 120 Leave the filling material, as shown in Figure 3B. In other embodiments, the filling material also remains in a concave portion above the electrode 100.

Next, as shown in FIG. 3C, the conductive layer 130 is patterned to form one or more openings above the passivation layer 110 near the TSV hole 120 to partially expose the passivation layer. Next, an insulating layer is formed and patterned to form an island-shaped insulating pattern 150 covering the opening. In some embodiments, the insulating pattern 150 includes silicon nitride.

Further, as shown in FIG. 3D, a first carrier bonding layer 160 is formed on the front surface of the circuit substrate 20 (on which the conductive layer 130 and the pattern 150 are formed), and then a first carrier substrate 165 is attached. In some embodiments, the first carrier substrate 165 is a glass substrate, a ceramic substrate, a semiconductor substrate, or a resin substrate. In some embodiments, the first carrier bonding layer 160 includes organic materials, silicon oxide, or any other suitable materials.

Then, the back side of the circuit substrate 20 is thinned by a grinding or a polishing (for example, CMP) operation. In some embodiments, after thinning, the circuit substrate 20 has a remaining thickness in a range from about 20 µm to about 100 µm, and in other embodiments, the remaining thickness is from about 40 µm to about 100 µm. Within a range of 60 µm. As shown in FIG. 3D, the bottom of the filling material layer 140 filled in the TSV hole 120 is exposed. In other embodiments, after the thinning operation, a first carrier substrate 165 is attached to the front surface of the circuit substrate 20.

Further, as shown in FIG. 3E, a bonding layer 170 is formed on the thinned back surface of the circuit substrate 20. The bonding layer 170 has the same or similar functionality as the bonding layer 40 shown in FIG. 1A. In some embodiments, the bonding layer 170 includes silicon oxide formed by, for example, a CVD process.

Next, as shown in FIG. 4A, a support substrate 30 is prepared and bonded to the circuit substrate 20 through the bonding layer 170 (oxide fusion bonding). In some embodiments, the support substrate 30 is made of crystalline silicon. After the oxide fusion bonding, the first carrier substrate 165 and the first carrier bonding layer 160 are removed, as shown in FIG. 4B. When the first carrier bonding layer 160 is made of an organic material, the first carrier substrate 165 and the first carrier bonding layer 160 are removed by a wet process. As shown in FIG. 4A, the bonding layer 170 is connected to the filling material layer 140 in the TSV hole 120. In some embodiments, the bonding layer 170 and the filling material layer 140 are made of the same material.

In other embodiments, the bonding layer 170 is formed on the support substrate 30 or on both the support substrate 30 and the circuit substrate 20. In some embodiments, without the bonding layer, the thickness of the support substrate 30 ranges from about 200 µm to about 1.8 mm, and in other embodiments, it ranges from about 500 µm to about 750 µm. Within a range.

Then, as shown in FIG. 4C, a first hard mask layer 180 is formed over the front surface of the circuit substrate 20 and then a second hard mask layer 190 is formed. In some embodiments, the first hard mask layer 180 includes silicon oxide and the second hard mask layer 190 includes polysilicon or amorphous silicon. In some embodiments, the silicon oxide hard mask layer 180 is formed by a CVD process, and then a planarization operation (such as a CMP operation) is performed. Similarly, in some embodiments, the polysilicon hard mask layer 190 is formed by chemical vapor deposition (CVD), and then a CMP operation is performed as appropriate. In some embodiments, the thickness of the polysilicon hard mask layer 190 is in a range from about 30 µm to about 70 µm.

Then, by using one or more lithography and etching operations, the second hard mask layer 190 and the first hard mask layer 180 are patterned to form one or more openings 200 above the electrode 100, as shown in FIG. 4D exhibit. In some embodiments, the size of the opening 200 is larger than the size of the opening formed above the electrode 100 in the passivation layer 110. In addition, in some embodiments, the insulating pattern 150 is partially exposed in the opening 200, as shown in FIG. 4D.

Next, as shown in FIG. 5A, one or more conductive layers 210 (pillars 90) are formed in the opening 200. In some embodiments, the conductive layer includes gold or gold alloy (for example, AuCu and AuNi) formed by a plating operation (electroplating or electroless plating). In some embodiments, the thickness of the plated conductive layer 210 is in a range from about 20 µm to about 50 µm. In some embodiments, the thickness (height) of the plated conductive layer 210 is smaller than the top of the second hard mask layer 190, as shown in FIG. 5A.

Further, as shown in FIG. 5B, a mask pattern 220 covers the plating layer 210 above the one or more electrodes 100. In some embodiments, the mask pattern 220 includes a photoresist pattern. Next, an additional conductive layer 215 (pillar 90H) is formed on the conductive plating layer 210. In some embodiments, the additional conductive layer 215 is formed by a plating operation (electroplating or electroless plating). In some embodiments, the additional conductive layer 215 is made of the same material as the plated conductive layer 210, and includes gold or a gold alloy (for example, AuCu, AuNi). In other embodiments, the additional conductive layer 215 is made of a material different from the plated conductive layer 210. Next, the photoresist pattern 220 is removed, as shown in FIG. 5C.

In some embodiments, the thickness of the additional conductive layer 215 is in a range from about 10 µm to about 30 µm. In some embodiments, the total thickness (height) of the plated conductive layer 210 and the additional conductive layer 215 is less than the top of the second hard mask layer 190, as shown in FIG. 5C. The plated conductive layer 210 corresponds to the low pillar 90L shown in FIG. 1A, and the combination of layers 210 and 215 corresponds to the high pillar 90H in FIG. 1A.

Next, as shown in FIG. 6A, a second carrier bonding layer 305 is formed above the front side of the circuit substrate 20, and then a second carrier substrate 300 is attached to the front side of the circuit substrate 20 via the second carrier bonding layer 305. In some embodiments, the second carrier substrate 300 is a glass substrate, a ceramic substrate, a semiconductor substrate, or a resin substrate. In some embodiments, the second carrier bonding layer 305 includes organic material, silicon oxide, or any other suitable material.

Next, the entire substrate is vertically inverted, and then the back side of the support substrate 30 is patterned to form a groove 35. In some embodiments, the groove 35 is formed by one or more lithography and etching operations using a mask pattern 310. In some embodiments, the mask pattern 310 is made of a photoresist.

In some embodiments, the etching operation includes plasma dry etching or wet etching. In some embodiments, the bonding layer 170 serves as an etch stop layer for forming the groove 35. When a plasma dry etching process is used to form the groove 35, the plasma etching substantially stops at the bonding layer 170, and thus the plasma can prevent damage to the electronic circuit formed in the circuit substrate 20.

In some embodiments, after the groove etching stops at the bonding layer 170, the bonding layer 170 is further etched by one or more dry etching or wet etching operations. In some embodiments, the etching of the bonding layer has a high selectivity relative to the circuit substrate 20 (for example, Si). For example, the etching rate of the bonding layer is 10 times or more the etching rate of the circuit substrate 20. In some embodiments, when the bonding layer 170 is made of silicon oxide, a wet etching process using HF or buffered HF is performed to prevent damage to the electronic circuits formed in the circuit substrate 20. When the bonding layer 170 is removed, when the filling material layer 140 is made of the same material as the bonding layer 170 (for example, silicon oxide), the filling material layer 140 in the TSV hole 120 is also removed. When the filling material layer 140 is made of a material different from the bonding layer 170 (for example, silicon nitride), an additional etching operation (such as a wet etching operation) is performed to remove the filling material layer 140.

After removing the filling material layer 140 from the TSV hole 120, a second conductive layer 320 is formed inside the groove 35, as shown in FIG. 6B.

In some embodiments, as shown in FIG. 6B, the second conductive layer 320 is formed to contact the first conductive layer 130 formed on the inner wall of each of the TSV holes 120. In some embodiments, the second conductive layer 320 is also formed on the inner wall of the TSV hole 120 in which the first conductive layer 130 has been formed. In some embodiments, the second conductive layer 320 is made of the same or different material as the first conductive layer 130, and includes one or more layers of Au, Ti, Cu, Ag, and Ni. In some embodiments, a gold layer formed on the Ti layer is used as the second conductive layer 320. In some embodiments, the thickness of the Ti layer is in a range from about 50 nm to about 200 nm, and in other embodiments, in a range from about 80 nm to about 120 nm. In some embodiments, the thickness of the gold (Au) layer is in a range from about 10 nm to about 400 nm, and in other embodiments, in a range from about 150 nm to about 250 nm.

In some embodiments, a plurality of MEMS devices are formed on a Si wafer, and the wafer is cut into individual MEMS devices (wafers) by sawing at the dicing path (a cutting operation). In some embodiments, the cutting operation does not completely cut the supporting second carrier bonding layer 305, as shown in FIG. 6B. By removing the second carrier bonding layer 305 and thus the second carrier substrate 300, a separate MEMS device is released. In some embodiments, the cutting operation is performed before the second conductive layer 320 is formed, and the second conductive layer 320 is also formed at the side of the MEMS device.

In some embodiments, after removing the second carrier substrate 300 and the second carrier bonding layer 305, individual MEMS devices are attached to a frame 400, as shown in FIG. 6C. As shown in FIG. 6C, by removing the second carrier substrate 300 and the second carrier bonding layer 305, the TSV hole 120 is exposed so that an electron beam or a light can pass.

FIG. 7A shows a plan view of the MEMS device, and FIG. 7B shows a cross-sectional view of a pad structure at the peripheral region PR. As shown in the plan view of FIG. 7A, the MEMS device has a central area CR and a peripheral area PR surrounding the central area. The TSV hole 120 and the conductive layer 210/215 are arranged in the central region CR. In the peripheral region PR, one or more bump under-bump electrodes 250 are formed to connect the electronic circuit formed in the circuit substrate 20 to one or more circuits outside the MEMS device. In some embodiments, in a plan view, the peripheral region PR does not overlap the groove 35. In other embodiments, the peripheral region PR partially overlaps the groove 35 in a plan view.

Next, an under bump electrode 250 is formed on the front side of the circuit substrate 20, as shown in FIGS. 7A and 7B. In some embodiments, the under-bump pad electrodes 250 are arranged in a matrix in the peripheral region PR. In some embodiments, a ball bump 260 is disposed on each of the under-bump pad electrodes 250. In some embodiments, the under-bump electrode 250 is formed before the recess etching, as shown in FIG. 6A. In some embodiments, the under-bump electrode 250 is formed after attaching the support substrate 30 to the circuit substrate 20 via oxide fusion bonding (as shown in FIGS. 4A and 4B).

In some embodiments, the under-bump pad electrode 250 is formed on a metal pad 225. The metal pad 225 is embedded in the interlayer dielectric layer 230 and is formed by the uppermost metal layer of the electronic circuit (for example, the 8th to the 12th metal Hierarchy) formed. In some embodiments, the metal pad 225 includes one or more layers of conductive materials. In some embodiments, the metal pad 225 includes Cu or Cu alloy.

In addition, as shown in FIG. 7B, the under-bump electrode 250 includes multiple layers of conductive material. In some embodiments, the under-bump pad electrode 250 includes a first metal layer 252, a second metal layer 254, a third metal layer 256, and a fourth metal layer 258. In some embodiments, the first metal layer is a TiW layer, the second metal layer is a Cu layer, the third metal layer is a Ni layer, and the fourth metal layer is a Sn layer.

In some embodiments, the thickness of the TiW layer 252 is in a range from about 50 nm to about 1000 nm, and in other embodiments, in a range from about 100 nm to about 500 nm. In some embodiments, the thickness of the Cu layer 254 is in a range from about 10 nm to about 2000 nm, and in other embodiments, in a range from about 500 nm to about 1000 nm. In some embodiments, the thickness of the Ni layer 256 is in a range from about 1000 nm to about 5000 nm, and in other embodiments, in a range from about 2500 nm to about 3500 nm. In some embodiments, the thickness of the Sn layer 258 is in a range from about 500 nm to about 4000 nm, and in other embodiments, in a range from about 1500 nm to about 2500 nm. The metal layer is formed by one or more of CVD, physical vapor deposition (PVD) including sputtering, plating, or any other suitable film formation method, and lithography and etching operations.

In some embodiments, the surface of the electronic circuit is covered by one or more passivation layers. In some embodiments, the passivation layer includes a first passivation layer 242, a second passivation layer 244, and a third passivation layer 246. An under bump electrode 250 is formed in one of the openings formed in the passivation layer, as shown in FIG. 7B. In some embodiments, the first passivation layer 242 is a SiC layer, the second passivation layer 244 is a silicon oxide layer, and the third passivation layer 246 is a silicon nitride layer.

8A-11B show cross-sectional views of various stages of a sequential fabrication operation of a MEMS device according to an embodiment of the present disclosure. In some embodiments, a sequential fabrication operation is used for the MEMS device 10 according to FIG. 1. It should be understood that additional operations may be provided before, during, and after the processes shown in FIGS. 8A to 11B, and some operations described below are replaced or eliminated for additional embodiments of the method. The sequence of operations/processes can be interchangeable. The materials, configurations, dimensions, and manufacturing processes described in FIGS. 1A to 7B can be applied to the following embodiments, and detailed descriptions thereof may be omitted.

The structure shown in FIG. 8A corresponds to the structure shown in FIG. 4C. As shown in FIG. 8A, a pad electrode 100 is formed in an insulating layer 110 such as a passivation layer. A portion of the upper surface of the pad electrode 100 is exposed from the insulating layer 110, and one or more under-bump conductive layers (corresponding to the first conductive layer 50) are formed over the upper surfaces of the exposed pad electrode 100 and the insulating layer 110. In some embodiments, similar to FIG. 4C, a TSV hole is formed between the pad electrodes.

In some embodiments, the under-bump conductive layer includes a lower conductive layer 50A (such as a Ti or Ti alloy (eg, TiN) layer) and an upper conductive layer 50B (such as a gold or gold alloy (eg, AuCu, AuNi) layer) . In some embodiments, each of the metal or metal layer of the first conductive layer 50 has a thickness in a range from about 2 nm to about 100 nm. In some embodiments, the thickness ratio of the Ti layer to the Au layer Ti:Au ranges from about 1:1.5 to about 1:6, and in other embodiments from about 1:2 to about 1:4 Within the range. In some embodiments, the total thickness of the Ti/Au under layer is about 50% smaller than a conventional Ti/Cu under bump conductive layer.

In some embodiments, the lower and upper conductive layers 50 are formed by CVD, PVD including sputtering, ALD, plating, or any other suitable film deposition method.

Next, as shown in FIG. 8B, a first photoresist layer 400 including one of the openings 405 above the pad electrode 100 is formed over the under-bump conductive layer.

After forming the first photoresist layer 400, a first conductive layer 210 is formed in the opening 405 by electroplating or any other suitable metal film forming method, as shown in FIG. 8C. In some embodiments, the first conductive layer 210 is a gold layer or a gold alloy layer. In some embodiments, the thickness of the first conductive layer 210 is in a range from about 20 μm to about 50 μm. Subsequently, the first photoresist layer 400 is removed by a suitable resist removal operation, as shown in FIG. 9A.

Next, as shown in FIG. 9B, a second photoresist layer 410 including an opening 415 above the one or more pad electrodes 100 is formed over the under-bump conductive layer and the one or more first conductive layers 210. As shown in FIG. 9B, the opening 415 exposes one or more of the first conductive layer 210. Next, a second conductive layer 215 is formed in the opening 415 on the first conductive layer 210 by electroplating or any other suitable metal film forming method, as shown in FIG. 9C. In some embodiments, the first conductive layer 210 is a gold layer or a gold alloy layer. In some embodiments, the thickness of the second conductive layer 215 is in a range from about 10 µm to about 30 µm. Subsequently, as shown in FIG. 10A, the second photoresist layer 410 is removed by a suitable resist removal operation, thereby forming one or more high pillars and one or more low pillars.

Further, as shown in FIG. 10B, a third photoresist layer 420 including an opening 425 above the peripheral area is formed above the conductive layer under bumps and the high pillars and the low pillars. Next, one or more third conductive layers are formed on the conductive layer 50B above the under bump conductive layer by electroplating or any other suitable metal film forming method, as shown in FIG. 10C. In some embodiments, the third conductive layer includes a bottom layer 95A and a top layer 95B. In some embodiments, the bottom layer 95A is a Ni layer or a Ni alloy layer, and the top layer 95B is a tin (Sn) layer or a tin alloy layer. In some embodiments, the tin alloy layer includes solder, such as AgSn, SnAgCu, PbSn, and CuSn. In some embodiments, each of the metal or metal layer of the third conductive layer 95 has a thickness in a range from about 100 nm to about 10 μm. The total thickness of the third conductive layer 95 is smaller than the thickness of the high pillars and the low pillars.

Next, the third photoresist layer 420 is removed, as shown in FIG. 11A. Subsequently, the exposed portions of the under-bump conductive layers 50A, 50B are removed by etching (eg, wet etching), as shown in FIG. 11B. In some embodiments, the Ti/Au underlayer is removed by a wet etching operation using an appropriate etchant that is selective to the Ti/Au underlayer.

By using gold, the oxidation of the column (specifically, the low column) can be avoided.

FIG. 12 shows a cross-sectional view of a MEMS device according to an embodiment of the disclosure. In some embodiments, the one or more high posts 92 are made of a different material than the low posts 90L. In some embodiments, the low post 90L is made of gold or a gold alloy, and the high post 92 is made of copper or a copper alloy (for example, AlCu).

FIGS. 13A to 16B show cross-sectional views of various stages of a sequential fabrication operation of the MEMS device shown in FIG. 12 according to an embodiment of the present disclosure. It should be understood that additional operations may be provided before, during, and after the processes shown in FIGS. 13A to 16B, and some operations described below are replaced or eliminated for additional embodiments of the method. The sequence of operations/processes can be interchangeable. The materials, configurations, dimensions, and manufacturing processes described in FIGS. 1A to 11B can be applied to the following embodiments, and detailed descriptions thereof may be omitted.

After forming the structure shown in FIG. 8A, by using one or more lithography and etching operations, a portion of the upper layer 50B of the under-bump conductive layer is removed, and then by using one or more films to form, micro Shadow and etching operation to form a second upper conductive layer 50C. In some embodiments, the second upper conductive layer 50C is made of copper or copper alloy. In some embodiments, the thickness of the second upper conductive layer 50C is greater than the thickness of the upper conductive layer 50B. In some embodiments, the second upper conductive layer has a thickness in a range from about 5 nm to about 150 nm.

Next, as shown in FIG. 13B, a first photoresist layer 402 including an opening 407 above the pad electrode 100 covered by the upper conductive layer 50B is formed over the under-bump conductive layer. After forming the first photoresist layer 402, a first conductive layer 210 is formed in the opening 407 by electroplating or any other suitable metal film forming method, as shown in FIG. 13C. In some embodiments, the first conductive layer 210 is a gold layer or a gold alloy layer. In some embodiments, the thickness of the first conductive layer 210 is in a range from about 20 μm to about 50 μm. Subsequently, the first photoresist layer 402 is removed by a suitable photoresist removal operation, as shown in FIG. 14A.

Next, as shown in FIG. 14B, an opening including an opening above one or more pad electrodes 100 covered by the second upper conductive layer 50C is formed over the under-bump conductive layer and the one or more first conductive layers 210 A second photoresist layer 412. Next, a conductive layer 92 is formed in the opening on the second upper conductive layer 50C by electroplating or any other suitable metal film forming method, as shown in FIG. 14B. In some embodiments, the conductive layer 92 is a copper layer or a copper alloy layer. In some embodiments, the thickness of the conductive layer 92 is in a range from about 30 µm to about 100 µm. Subsequently, as shown in FIG. 14C, the second photoresist layer 412 is removed by a suitable resist removal operation, thereby forming one or more high pillars 92 and one or more low pillars 210.

Further, as shown in FIG. 15A, a third photoresist layer 422 including one of the openings 427 above the peripheral region is formed above the conductive layer under bumps and the high pillars and the low pillars. Next, one or more third conductive layers are formed on the conductive layer 50B above the conductive layer under bump by electroplating or any other suitable metal film forming method, as shown in FIG. 15B. In some embodiments, the third conductive layer includes a bottom layer 95A and a top layer 95B. In some embodiments, the bottom layer 95A is a Ni layer or a Ni alloy layer, and the top layer 95B is a tin (Sn) layer or a tin alloy layer. In some embodiments, the tin alloy layer includes SnAg, SnAgCu, PbSn, and/or CuSn. In some embodiments, each of the metal or metal layer of the third conductive layer 95 has a thickness in a range from about 100 nm to about 10 μm. The total thickness of the third conductive layer 95 is smaller than the thickness of the high pillars and the low pillars.

Next, the third photoresist layer 422 is removed, as shown in FIG. 16A. Subsequently, the exposed portions of the under-bump conductive layers 50A, 50B, and 50C are removed by one or more etching operations (eg, wet etching), as shown in FIG. 16B. In some embodiments, the Ti/Au underlayer and/or Cu layer are removed by a wet etching operation using a suitable etchant.

FIG. 17 shows a cross-sectional view of a MEMS device according to an embodiment of the disclosure. In some embodiments, one or more low pillars 90L are also formed on the peripheral area to replace the second metal pillars 95. In some embodiments, all pillars are made of gold or gold alloy.

18A to 20B show cross-sectional views of various stages of a sequential manufacturing operation of the MEMS device shown in FIG. 17 according to an embodiment of the present disclosure. It should be understood that additional operations may be provided before, during, and after the processes shown in FIGS. 18A to 20B, and some operations described below are replaced or eliminated for additional embodiments of the method. The sequence of operations/processes can be interchangeable. The materials, configurations, dimensions, and manufacturing processes described in FIGS. 1A to 16B can be applied to the following embodiments, and detailed descriptions thereof may be omitted.

Figure 18A is the same as Figure 8A. Next, as shown in FIG. 18B, a first photoresist layer 414 including an opening 408 above the pad electrode 100 covered by the upper conductive layer 50B and an opening 409 above the peripheral area is formed above the conductive layer under bumps . After forming the first photoresist layer 414, a first conductive layer 210 is formed in the openings 407 and 409 by electroplating or any other suitable metal film forming method, as shown in FIG. 18C. In some embodiments, the first conductive layer 210 is a gold layer or a gold alloy layer. In some embodiments, the thickness of the first conductive layer 210 is in a range from about 20 μm to about 50 μm. Subsequently, the first photoresist layer 414 is removed by a suitable photoresist removal operation, as shown in FIG. 19A.

Next, as shown in FIG. 19B, a second photoresist layer 424 including an opening 417 is formed over one or more pad electrodes 100 on which the first conductive layer 210 is formed. Next, a second conductive layer 215 is formed in the opening 417 on the first conductive layer 210 by electroplating or any other suitable metal film forming method, as shown in FIG. 19C. In some embodiments, the conductive layer 92 is a copper layer or a copper alloy layer. Subsequently, as shown in FIG. 20A, the second photoresist layer 424 is removed by a suitable resist removal operation, thereby forming one or more high pillars and low pillars.

Subsequently, the exposed portions of the under-bump conductive layers 50A, 50B are removed by one or more etching operations (for example, wet etching), as shown in FIG. 20B. In some embodiments, the Ti/Au underlayer is removed by a wet etching operation using a suitable etchant.

The MEMS device of the semiconductor device according to the embodiment of the present disclosure includes a Ti/Au bottom layer under the Au bumps for guiding an electron beam (e-beam). The Ti/Au underlayer provides increased conductivity, and Au bumps have fewer oxidation problems. In addition, Au bumps have better bonding and shearing force than Cu bumps. Although the above embodiments are described with respect to a MEMS device, the techniques disclosed herein can be applied to any device with bumps or pillars.

The various embodiments or examples described herein provide several advantages over the prior art, as explained above. It will be understood that not all advantages have been discussed herein, not all embodiments or examples require specific advantages, and other embodiments or examples may provide different advantages.

According to one aspect of the present disclosure, in a method of manufacturing bumps or pillars, a conductive layer under bump is formed on a substrate; a first opening and a second opening are formed on the conductive layer under bump A first photoresist layer; forming a first conductive layer in the first opening and the second opening to form a first low bump and a second low bump; removing the first photoresist Layer; a second photoresist layer having a third opening is formed above the second low bump; a second conductive layer is formed in the third opening on the second low bump to form a A high bump with a height of the first low bump; and removing the second photoresist layer. In one or more of the foregoing and following embodiments, the under bump conductive layer includes a lower layer made of Ti or Ti alloy and an upper layer made of Au or Au alloy, and the first conductive layer is made of Made of Au or Au alloy. In one or more of the foregoing and following embodiments, the second conductive layer is made of Au or Au alloy. In one or more of the foregoing and following embodiments, the ratio of the thickness of the lower layer to the one of the upper layer is in the range from 1:2 to 1:4. In one or more of the foregoing and following embodiments, after removing the second photoresist layer, the portion of the conductive layer under bump that is not covered by the first low bump and the high bump is removed . In one or more of the foregoing and following embodiments, a third photoresist layer having a third opening that exposes a portion of the conductive layer under bump is formed. The third photoresist layer covers the first low bump and the high bump. One or more conductive layers are formed on the exposed portion of the under-bump conductive layer to form a third low bump, and the third photoresist layer is removed. In one or more of the foregoing and following embodiments, the one or more conductive layers include a lower layer and an upper layer, and both the lower layer and the upper layer are different from the bump lower conductive layer, the high bump and The first low bump is made of material. In one or more of the foregoing and following embodiments, the lower layer is made of Ni or Ni alloy, and the upper layer is made of Sn alloy. In one or more of the foregoing and following embodiments, the Sn alloy is at least one selected from the group consisting of AgSn, SnAgCu, PbSn, and CuSn. In one or more of the foregoing and following embodiments, after removing the third photoresist layer, the first low bump, the third low bump, and the high bump are not covered by the The part of the conductive layer under the bump.

According to another aspect of the present disclosure, in a method of manufacturing bumps or pillars, pad electrodes are formed on a substrate; an insulating layer is formed on the pad electrodes; the insulating layer is patterned to partially expose the pads Electrodes; forming a conductive layer under bumps over the insulating layer and the exposed pad electrodes; a first photoresist layer with a first opening and a second opening formed above the conductive layer under bumps ; Form a first conductive layer in the first opening and the second opening to form a first low bump and a second low bump; remove the first photoresist layer; formed in the second low A second photoresist layer having a third opening above the bump; a second conductive layer is formed in the third opening on the second low bump to form a second photoresist layer larger than the first low bump A high bump of one height; removing the second photoresist layer; forming a third photoresist layer having a fourth opening that exposes a portion of the conductive layer under the bump, wherein the third photoresist layer Covering the first low bump and the high bump; forming one or more conductive layers in the fourth opening on the exposed portion of the conductive layer under the bump to form a third low bump; removing The third photoresist layer; and removing the portion of the under-bump conductive layer that is not covered by the first low bump, the third low bump, and the high bump. In one or more of the foregoing and following embodiments, the thickness of one of the third low bumps starting from the top of the conductive layer under bump is smaller than the thickness of the first bump starting from the top of the conductive layer under bump One of the thickness of the low bump. In one or more of the foregoing and following embodiments, a thickness of the first low bump from the top of the conductive layer under bump is in a range from 20 µm to 50 µm. In one or more of the foregoing and following embodiments, a thickness of the high bump from the top of the conductive layer under the bump is in a range from 30 µm to 100 µm. In one or more of the foregoing and following embodiments, the under bump conductive layer includes a lower layer made of Ti or Ti alloy and an upper layer made of Au or Au alloy, and the first conductive layer and the The second conductive layer is made of Au or Au alloy. In one or more of the foregoing and following embodiments, the first conductive layer and the second conductive layer are formed by electroplating.

According to another aspect of the present disclosure, in a method of manufacturing bumps or pillars, pad electrodes are formed on a substrate; an insulating layer is formed on the pad electrodes; the insulating layer is patterned to partially expose the pads Electrode; forming a conductive layer under the bump over the insulating layer and the exposed pad electrodes; a first opening, a second opening and a third opening formed above the conductive layer under the bump A photoresist layer; forming a first conductive layer in the first opening, the second opening and the third opening to form a first low bump, a second low bump and a third low bump Removing the first photoresist layer; forming a second photoresist layer with a fourth opening above the second low bump; forming on the second low bump in the fourth opening A second conductive layer to form a high bump having a height greater than a height of the first low bump; removing the second photoresist layer; and removing the first low bump and the third low bump The bump and the portion of the conductive layer under the bump covered by the high bump. In one or more of the foregoing and following embodiments, the lower bump conductive layer includes a lower layer made of Ti or Ti alloy and an upper layer made of Au or Au alloy. In one or more of the foregoing and following embodiments, the ratio of the thickness of the lower layer to the one of the upper layer is in the range from 1:2 to 1:4. In one or more of the foregoing and following embodiments, the first and second conductive layers are made of Au or Au alloy.

According to another aspect of the present disclosure, in a method of fabricating a semiconductor device, a Ti/Au underlayer is formed on a substrate; a first photoresist layer is formed on the Ti/Au underlayer; and the first photoresist layer is patterned. A resist layer to form a plurality of openings exposing the substrate; depositing Au in the plurality of openings to form a plurality of Au bumps; removing the first photoresist layer; over the substrate and the plurality of Au bumps Forming a second photoresist layer; patterning the second photoresist layer to form one of the openings exposing one of the Au bumps; depositing in the openings exposing one of the Au bumps Au to increase the height of the Au bumps; remove the second photoresist layer; form a third photoresist layer on the substrate and the plurality of Au bumps; pattern the third photoresist layer to Forming an opening exposing the Ti/Au underlayer; forming a different metal in the opening exposing the Ti/Au underlayer to form a bump having a height smaller than that of the other bumps; and removing the third bump Photoresist layer. In one or more of the foregoing and following embodiments, depositing a different metal includes forming a Ni layer above the Ti/Au underlayer and forming a SnAg layer above the Ni layer. In one or more of the foregoing and following embodiments, the exposed portion of the Ti/Au underlayer is removed.

According to another aspect of the present disclosure, in a method of fabricating a semiconductor device, a Ti layer is formed on a substrate; Au and Cu layers are selectively formed on the Ti layer; and the Au, Cu, and Ti layers A first photoresist layer is formed above; the first photoresist layer is patterned to form an opening that exposes a portion of the Au layer; Au is formed above the exposed portion of the Au layer to form Au bumps; Remove the first photoresist layer; form a second photoresist layer over the Au, Cu and Ti layers and the Au bumps; pattern the second photoresist layer to form one of the Cu layers exposed Opening; depositing Cu over the Cu layer to form Cu bumps; removing the second photoresist layer; forming a third photoresist layer over the substrate and the Au and Cu bumps; patterning the second photoresist layer Three photoresist layers to form an opening exposing another part of the Au layer; forming a different metal in the opening exposing the other part of the Au layer to form a bump of the different metal; and removing the second Three photoresist layers. In one or more of the foregoing and following embodiments, depositing a different metal includes: forming a Ni layer on the Au layer and forming a SnAg layer on the Ni layer. In one or more of the foregoing and following embodiments, the exposed portion of the Ti/Au underlayer is removed. In one or more of the foregoing and following embodiments, the Cu bump has a height greater than that of the Au bump, and the Au bump has a height greater than that of the bump of a different metal.

According to another aspect of the present disclosure, in a method of fabricating a semiconductor device, a Ti/Au underlayer is formed on a substrate; a first photoresist layer is formed on the Ti/Au underlayer; and the first photoresist layer is patterned A photoresist layer to form a plurality of openings exposing the substrate; depositing Au in the plurality of openings to form a plurality of Au bumps; removing the first photoresist layer; on the substrate and the plurality of Au bumps A second photoresist layer is formed above; the second photoresist layer is patterned to form an opening that exposes one of the first bumps of the plurality of Au bumps; the one where one of the first bumps is exposed Deposit Au in the opening to increase the height of the first Au bump; remove the second photoresist layer; form a third photoresist layer on the substrate and the plurality of Au bumps; pattern the third The photoresist layer is used to form an opening that exposes a second Au bump; Au is deposited in the opening that exposes the second Au bump to increase the height of a second Au bump, so that the second Au bump A height greater than a height of the first Au bump; and removing the third photoresist layer. In one or more of the foregoing and following embodiments, the exposed portion of the Ti/Au underlayer is removed. In one or more of the foregoing and following embodiments, the plurality of Au bumps include a third Au bump having a height smaller than the height of the first Au bump. In one or more of the foregoing and following embodiments, the Ti/Au underlayer includes a Ti layer disposed above the substrate and an Au layer disposed above the Ti layer. In one or more of the foregoing and following embodiments, the ratio (Ti:Au) of the thickness of the Ti layer to the Au layer is in the range from 1:2 to 1:4.

According to another aspect of the present disclosure, a semiconductor device includes a substrate and a first bump structure disposed on the substrate. The first bump structure includes a first bump with a first height and made of Au or Au alloy disposed above an under bump conductive layer, and the under bump conductive layer includes Ti or Ti alloy A lower layer is made and an upper layer is made of Au or Au alloy. In one or more of the foregoing and following embodiments, the under-bump conductive layer is disposed above a pad electrode. In one or more of the foregoing and following embodiments, the ratio of the thickness of the lower layer in the bottom layer to the thickness of the upper layer is in the range from 1:2 to 1:4. In one or more of the foregoing and following embodiments, the semiconductor device further includes a second bump structure. The second bump structure includes a second bump having a second height, and the second height is greater than the first height. In one or more of the foregoing and following embodiments, the semiconductor device further includes a third bump structure. The third bump structure includes a third bump having a third height, and the third height is equal to or less than the first height. In one or more of the foregoing and following embodiments, the third bump is made of a material different from the first and second bumps, and the third height is smaller than the first height. In one or more of the foregoing and following embodiments, the third bump includes a tin alloy layer disposed on the Ni or Ni alloy layer. In one or more of the foregoing and following embodiments, the third bump is made of the same material as the first and second bumps, and the third height is equal to the first height. In one or more of the foregoing and following embodiments, the second bump is made of a material different from the first bump. In one or more of the foregoing and following embodiments, the semiconductor device further includes a third bump structure. The third bump structure includes a third bump having a third height, and the third height is equal to or less than the first height. In one or more of the foregoing and following embodiments, the third bump is made of a material different from the first and second bumps, and the third height is smaller than the first height. In one or more of the foregoing and following embodiments, the third bump includes a tin alloy layer disposed on the Ni or Ni alloy layer.

According to another aspect of the present disclosure, a micro-electromechanical system (MEMS) device includes: a circuit substrate including an electronic circuit; a supporting substrate having a groove; and a bonding layer disposed on the circuit substrate and the Between the supporting substrates; through holes, which pass through the circuit substrate to the opening; a plurality of pad electrodes, which are arranged above the circuit substrate; and a plurality of bump structures. The plurality of bump structures includes a first bump structure, the first bump structure includes a first bump having a first height, and the first bump is disposed above a first under-bump conductive layer and Made of Au or Au alloy, the first under-bump conductive layer is disposed on one of the pad electrodes, and the first under-bump conductive layer includes a lower layer made of Ti or Ti alloy and a lower layer made of Au Or an upper layer made of Au alloy. In one or more of the foregoing and following embodiments, the ratio of the thickness of the lower layer in the bottom layer to the thickness of the upper layer is in the range from 1:2 to 1:4. In one or more of the foregoing and following embodiments, the plurality of bump structures further include a second bump structure, and the second bump structure includes a second bump structure disposed above a second under bump conductive layer. A second bump of one of two heights, the conductive layer under the second bump is disposed on one of the pad electrodes, and the second height is greater than the first height. In one or more of the foregoing and following embodiments, the first height measured from the top of a conductive layer under the first bump is in a range from 30 µm to 100 µm, and the first height measured from the second bump The second height measured on the top of one of the conductive layers under the block is in a range from 20 µm to 50 µm. In one or more of the foregoing and the following embodiments, the first bump is made of the same material as the second bump, and the first under-bump conductive layer has the same material as the second under-bump. Layer configuration with the same conductive layer. In one or more of the foregoing and following embodiments, the first bump is made of a material different from that of the second bump, and the conductive layer under the first bump has a different material from that of the second bump. The layer configuration of the lower conductive layer.

According to another aspect of the present disclosure, a micro-electromechanical system (MEMS) device includes: a circuit substrate including electronic circuits; a plurality of pad electrodes; a passivation layer disposed on the circuit substrate and having a plurality of openings, A corresponding one of the plurality of pad electrodes is exposed through the plurality of openings; a supporting substrate having a groove; a through hole that passes through the circuit substrate to the opening; and a plurality of bump structures. The plurality of bump structures includes: a first bump structure including a first bump having a first height, the first bump being disposed on a first under bump conductive layer, the first bump The under-block conductive layer is disposed on one of the pad electrodes; a second bump structure includes a second bump having a second height greater than the first height, and the second bump is disposed on a Above the second under-bump conductive layer, the second under-bump conductive layer is disposed on one of the pad electrodes; and a third bump structure including a third bump having a third height, The first bump is arranged above a third under-bump conductive layer, and the third under-bump conductive layer is not arranged above the pad electrode. In one or more of the foregoing and following embodiments, the first, second, and third bumps are made of different materials.

According to another aspect of the present disclosure, a semiconductor device includes a substrate, and at least one bump structure disposed on the substrate. The at least one bump structure includes Au bumps with a first height disposed above a bottom layer, and the bottom layer includes an Au layer disposed above the Ti layer. In one or more of the foregoing and following embodiments, the bottom layer is disposed above a metal pad. In one or more of the foregoing and following embodiments, the ratio of the thickness of the Ti layer to the thickness of the Au layer in the bottom layer (Ti:Au) is in the range from 1:2 to 1:4 . In one or more of the foregoing and following embodiments, the at least one bump structure includes a second bump structure, the second bump structure includes a second Au bump having a second height, and the first bump structure The second height is greater than the first height. In one or more of the foregoing and following embodiments, the at least one bump structure includes a third bump structure, the third bump structure includes a third bump having a third height, and the third bump structure The height is smaller than the first height. In one or more of the foregoing and following embodiments, the third bump is made of a material different from the first and second bumps. In one or more of the foregoing and following embodiments, the third bump is made of SnAg disposed on the Ni layer. In one or more of the foregoing and following embodiments, the at least one bump structure includes a second bump structure, and the second bump structure includes a second bump made of Cu. In one or more of the foregoing and following embodiments, the second bump has a second height, and the second height is greater than the first height. In one or more of the foregoing and following embodiments, the at least one bump structure includes a third bump structure, the third bump structure includes a third bump having a third height, and the third bump structure The height is smaller than the first height. In one or more of the foregoing and following embodiments, the third bump is made of a material different from the first and second bumps. In one or more of the foregoing and following embodiments, the third bump is made of SnAg disposed on the Ni layer.

The foregoing summarizes the characteristics of several embodiments or examples, so that those familiar with the art can better understand the aspect of the present disclosure. Those who are familiar with this technology should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for implementing the same purpose and/or achieving the same advantages of the embodiments or examples introduced herein. . Those familiar with the technology should also realize that these equivalent structures do not depart from the spirit and scope of this disclosure, and various changes, substitutions and alterations can be made in this article without departing from the spirit and scope of this disclosure.

10: Micro-Electro-Mechanical System (MEMS) device 20: Circuit board 25: Electronic circuit/circuit 28: Passivation film/passivation layer 30: Support substrate 32: Pad electrode 35: Groove/cavity 40: Insulation layer / bonding layer 50: The first conductive layer / lower and upper conductive layers 50A: Underlying conductive layer/lower conductive layer/bump lower conductive layer 50B: Underlying conductive layer/Upper conductive layer/Bump lower conductive layer 50C: second upper conductive layer/bump lower conductive layer 55: second conductive layer 60: Through hole/hole 90: metal column/column 90H: high column/column 90L: low column/column 92: high column / conductive layer 95: second metal pillar/second pillar/third conductive layer 95A: bottom layer 95B: top layer 100: Planar electrode/electrode/pad electrode 110: passivation layer/insulation layer 120: Hole/Through Silicon Via (TSV) Hole 130: first conductive layer/conductive layer 140: Filling layer/filling material layer 150: Insulation pattern/pattern 160: first carrier bonding layer 165: first carrier substrate 170: Bonding layer 180: The first hard mask layer / silicon oxide hard mask layer 190: second hard mask layer/polysilicon hard mask layer 200: opening 210: conductive layer/plated conductive layer/plated layer/conductive plating layer/first conductive layer/low pillar 215: additional conductive layer/second conductive layer 220: mask pattern/photoresist pattern 225: Metal pad 230: Interlayer dielectric layer 242: first passivation layer 244: second passivation layer 246: third passivation layer 250: pad electrode under bump 252: first metal layer/TiW layer 254: second metal layer/Cu layer 256: third metal layer/Ni layer 258: Fourth metal layer/Sn layer 260: Ball Bump 300: second carrier substrate 305: second carrier bonding layer 310: Mask pattern 320: second conductive layer 400: Frame (Figure 6C)/First photoresist layer (Figure 8B and Figure 8C) 402: first photoresist layer 405: open 407: open 408: open 409: open 410: second photoresist layer 412: second photoresist layer 414: first photoresist layer 415: open 417: open 420: third photoresist layer 422: third photoresist layer 424: second photoresist layer 425: open 427: open 500: electron beam CR: Central area PR: Peripheral area

This disclosure is best understood from the following [Embodiments] when read in conjunction with the drawings. It should be emphasized that according to standard practice in the industry, various components are not drawn to scale and are used for illustration purposes only. In fact, for clear discussion, the size of various components can be increased or decreased arbitrarily.

1A and 1B show schematic cross-sectional views of a MEMS device according to an embodiment of the disclosure.

Figure 2 shows the use of a MEMS device according to an embodiment of the present disclosure.

3A, 3B, 3C, 3D, and 3E show schematic cross-sectional views of various stages of a sequential manufacturing operation for a MEMS device according to an embodiment of the present disclosure.

4A, 4B, 4C, and 4D show schematic cross-sectional views of various stages of a sequential fabrication operation for a MEMS device according to an embodiment of the present disclosure.

5A, 5B, and 5C show schematic cross-sectional views of various stages of a sequential fabrication operation for a MEMS device according to an embodiment of the present disclosure.

6A, 6B, and 6C show schematic cross-sectional views of various stages of a sequential fabrication operation for a MEMS device according to an embodiment of the present disclosure.

FIG. 7A shows a plan view of a MEMS device according to an embodiment of the disclosure, and FIG. 7B shows a cross-sectional view of a pad structure device according to an embodiment of the disclosure.

8A, 8B, and 8C show cross-sectional views of various stages of a sequential manufacturing operation of a MEMS device according to an embodiment of the present disclosure.

9A, 9B, and 9C show cross-sectional views of various stages of a sequential manufacturing operation of a MEMS device according to an embodiment of the present disclosure.

10A, 10B, and 10C show cross-sectional views of various stages of a sequential manufacturing operation of a MEMS device according to an embodiment of the present disclosure.

11A and 11B show cross-sectional views of various stages of a sequential manufacturing operation of a MEMS device according to an embodiment of the disclosure.

FIG. 12 shows a cross-sectional view of a MEMS device according to an embodiment of the disclosure.

13A, 13B, and 13C show cross-sectional views of various stages of a sequential manufacturing operation of a MEMS device according to an embodiment of the disclosure.

14A, 14B, and 14C show cross-sectional views of various stages of a sequential fabrication operation of a MEMS device according to an embodiment of the disclosure.

15A and 15B show cross-sectional views of various stages of a sequential manufacturing operation of a MEMS device according to an embodiment of the present disclosure.

16A and 16B show cross-sectional views of various stages of a sequential manufacturing operation of a MEMS device according to an embodiment of the present disclosure.

FIG. 17 shows a cross-sectional view of a MEMS device according to an embodiment of the disclosure.

18A, 18B, and 18C show cross-sectional views of various stages of a sequential manufacturing operation of a MEMS device according to an embodiment of the present disclosure.

19A, 19B, and 19C show cross-sectional views of various stages of a sequential manufacturing operation of a MEMS device according to an embodiment of the present disclosure.

20A and 20B show cross-sectional views of various stages of a sequential manufacturing operation of a MEMS device according to an embodiment of the present disclosure.

10: Micro-Electro-Mechanical System (MEMS) device

20: Circuit board

25: Electronic circuit/circuit

28: Passivation film/passivation layer

30: Support substrate

35: Groove/cavity

40: Insulation layer / bonding layer

50: The first conductive layer / lower and upper conductive layers

55: second conductive layer

60: Through hole/hole

90: metal column/column

90H: high column/column

90L: low column/column

95: second metal pillar/second pillar/third conductive layer

Claims (20)

A method of manufacturing bumps or pillars, which includes: Forming an under-bump conductive layer on a substrate; Forming a first photoresist layer having a first opening and a second opening on the conductive layer under the bump; Forming a first conductive layer in the first opening and the second opening to form a first low bump and a second low bump; Removing the first photoresist layer; Forming a second photoresist layer with a third opening on the second low bump; Forming a second conductive layer in the third opening on the second low bump to form a high bump having a height greater than a height of the first low bump; and Remove the second photoresist layer. Such as the method of claim 1, where: The under bump conductive layer includes a lower layer made of Ti or Ti alloy and an upper layer made of Au or Au alloy, and The first conductive layer is made of Au or Au alloy. The method of claim 2, wherein the second conductive layer is made of Au or Au alloy. Such as the method of claim 2, wherein the ratio of one of the thicknesses of the lower layer to the upper layer is in the range from 1:2 to 1:4. The method of claim 1, further comprising, after removing the second photoresist layer, removing a portion of the under-bump conductive layer that is not covered by the first low bump and the high bump. Such as the method of claim 1, which further includes: Forming a third photoresist layer with a third opening that exposes a portion of the conductive layer under the bump, the third photoresist layer covering the first low bump and the high bump; Forming one or more conductive layers on the exposed portion of the under-bump conductive layer to form a third low bump; and The third photoresist layer is removed. Such as the method of claim 6, wherein the one or more conductive layers include a lower layer and an upper layer, and both the lower layer and the upper layer are different from the bump lower conductive layer, the high bump and the first low bump Made of block material. Such as the method of claim 7, wherein the lower layer is made of Ni or Ni alloy, and the upper layer is made of Sn alloy. The method of claim 8, wherein the Sn alloy is at least one selected from the group consisting of AgSn, SnAgCu, PbSn, and CuSn. The method of claim 6, further comprising, after removing the third photoresist layer, removing the bumps that are not covered by the first low bump, the third low bump, and the high bump The part of the lower conductive layer. A method of manufacturing bumps or pillars, which includes: Forming pad electrodes on a substrate; Forming an insulating layer above the pad electrodes; Patterning the insulating layer to partially expose the pad electrodes; Forming an under-bump conductive layer over the insulating layer and the exposed pad electrodes; Forming a first photoresist layer having a first opening and a second opening on the conductive layer under the bump; Forming a first conductive layer in the first opening and the second opening to form a first low bump and a second low bump; Removing the first photoresist layer; Forming a second photoresist layer with a third opening on the second low bump; Forming a second conductive layer in the third opening on the second low bump to form a high bump having a height greater than a height of the first low bump; Removing the second photoresist layer; Forming a third photoresist layer having a fourth opening that exposes a part of the conductive layer under the bump, the third photoresist layer covering the first low bump and the high bump; Forming one or more conductive layers in the fourth opening on the exposed portion of the under-bump conductive layer to form a third low bump; Removing the third photoresist layer; and Removing the portion of the conductive layer under the bump that is not covered by the first low bump, the third low bump, and the high bump. The method of claim 11, wherein the thickness of one of the third low bumps starting from the top of the under-bump conductive layer is less than the thickness of one of the first low bumps starting from the top of the under-bump conductive layer thickness. The method of claim 12, wherein a thickness of the first low bump from the top of the conductive layer under the bump is in a range from 20 µm to 50 µm. The method of claim 12, wherein a thickness of the high bump from the top of the conductive layer under the bump is in a range from 30 µm to 100 µm. Such as the method of claim 11, where: The under bump conductive layer includes a lower layer made of Ti or Ti alloy and an upper layer made of Au or Au alloy, and The first conductive layer and the second conductive layer are made of Au or Au alloy. The method of claim 11, wherein the first conductive layer and the second conductive layer are formed by electroplating. A semiconductor device including: A substrate; and A first bump structure, which is arranged above the substrate, in which: The first bump structure includes a first bump with a first height and made of Au or Au alloy disposed above a conductive layer under bump, and The under-bump conductive layer includes a lower layer made of Ti or Ti alloy and an upper layer made of Au or Au alloy. The semiconductor device of claim 17, wherein the under-bump conductive layer is disposed above a pad electrode. The semiconductor device of claim 17, wherein the ratio of the thickness of the lower layer in the bottom layer to the thickness of the upper layer is in the range from 1:2 to 1:4. The semiconductor device of claim 17, which further includes a second bump structure, wherein: The second bump structure includes a second bump having a second height, and The second height is greater than the first height.

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