TW202137551A - High voltage integrated circuit structure - Google Patents

Abstract

A high voltage integrated circuit structure including: a substrate having a first conductive type; an epitaxial layer disposed on the substrate, wherein the epitaxial layer has a second conductive type different from the first conductive type; a source and a drain region disposed in the epitaxial layer, having the second conductive type; a first isolation structure and a second isolation structure disposed on the epitaxial layer on opposite sides of the drain region, respectively, wherein the first isolation structure is between the source region and the drain region; a first conductive type isolation region disposed in the epitaxial layer under the second isolation structure and includes: a slot region disposed on the center area of the first conductive type isolation region constituted by the epitaxial layer, and a high voltage first conductive type well region disposed on opposite sides of the slot region.

Description

High-voltage integrated circuit structure

The present invention relates to a semiconductor device, in particular to a high-voltage integrated circuit structure.

High voltage integrated circuit (HVIC) technology is suitable for high voltage and high power integrated circuits. Traditional high-voltage semiconductor devices, such as vertical diffused metal oxide semiconductor (VDMOS) transistors and laterally diffused metal oxide semiconductor (LDMOS) transistors, are mainly used in component applications above 12V . The advantages of high-voltage device technology are that it is cost-effective and easily compatible with other manufacturing processes. It has been widely used in display driver IC components, power supplies, power management, communications, automotive electronics, or industrial control.

Although the existing high-voltage integrated circuits have generally met their original purposes, they are not satisfactory in all respects. For example, the breakdown voltage and the lateral punch-through voltage need to be further improved. Therefore, there are still some problems to be overcome with regard to high-voltage integrated circuits and manufacturing technology.

A high-voltage integrated circuit structure includes: a substrate having a first conductivity type; an epitaxial layer is arranged on the substrate, wherein the epitaxial layer has a second conductivity type different from the first conductivity type; a source region and a drain region, It is arranged in the epitaxial layer and has the second conductivity type; the first isolation structure and the second isolation structure are arranged on the epitaxial layer and are respectively located on opposite sides of the drain region, wherein the first isolation structure is located at the source Between the pole region and the drain region; the first conductivity type isolation region is located in the epitaxial layer under the second isolation structure, including: an empty trench region, which is set in the central region of the first conductivity type isolation region, and is epitaxial And the first conductivity type high-voltage well region is arranged on opposite sides of the empty slot region; the first buried layer is arranged in the substrate and has the first conductivity type, wherein the first buried layer is located in the isolation of the first conductivity type And a second buried layer disposed in the substrate and having the second conductivity type, wherein the second buried layer is located between the drain region and the isolation region of the first conductivity type, and the first buried layer Separate from the second buried layer.

The following disclosure provides many embodiments or examples for implementing different components of the present invention. Specific examples of components and configurations are described below to simplify the embodiments of the present invention. Of course, these are only examples and are not intended to limit the embodiments of the present invention. For example, the description mentioned that the first part is formed on the second part may include an embodiment in which the first and second parts are in direct contact, or an additional part is formed between the first and second parts. , So that the first and second components do not directly contact an embodiment. In addition, the present invention may repeat component symbols and/or letters in various examples. Unless otherwise specified, similar element symbols are quoted on similar elements, and are formed with the same or similar materials and using the same or similar methods.

Furthermore, spatially related terms can be used here, such as "below", "below", "below", "above", "above" and similar terms can be used here for description The diagram shows the relationship between one element or component and other elements or components. These spatial terms are intended to include the different orientations of the device in use or operation. When the device is turned to other orientations (rotated by 90° or other orientations), the relative description of the space used here can also be interpreted according to the rotated orientation.

The present invention provides embodiments of high-voltage semiconductor devices, especially embodiments of laterally diffused metal oxide semiconductor (LDMOS) transistors. In the prior art, usually by adjusting the doping concentration of the well region of the horizontally diffused metal oxide semiconductor during the manufacturing process, the horizontally diffused metal oxide semiconductor generates a specific breakdown voltage to meet the requirements of different product applications. However, in actual manufacturing processes, such as the integrated bipolar complementary metal oxide semiconductor-double diffused metal oxide semiconductor (BCD) process, the adjustment well The doping concentration of the region will need to add an additional mask in the process, so that the overall process cost will also increase.

In order to increase the breakdown voltage and lateral punch-through voltage of the horizontally diffused metal oxide semiconductor transistor, the embodiment of the present invention uses the horizontally diffused metal oxide semiconductor transistor to move away from the source in the drain region. One side of the region is provided with a first conductivity type isolation region, a first buried layer and a second buried layer, wherein the first conductivity type isolation region, the first buried layer and the second buried layer are connected to form an L-shaped structure, and the L-shaped The horizontal part extends in the direction of the source region. With the arrangement of the L-shaped structure, a vertical assisted depletion layer (VADL) and a laterally assisted depletion layer (LADL) can be added at the same time, thereby increasing the breakdown voltage and lateral breakdown voltage of the device. The horizontal diffusion MOS transistor with high breakdown voltage and lateral breakdown voltage can also be widely used as a level shifter in lighting, flat panel display, audio, switch mode power supply, power control and other fields.

FIG. 1 is a schematic cross-sectional view of a high voltage integrated circuit (HVIC) structure 10 according to some embodiments of the present invention. The high-voltage integrated circuit structure 10 may include a substrate 100. The substrate 100 may be a semiconductor substrate, such as doped or undoped silicon, or an active layer of a semiconductor-on-insulator (SOI) substrate. The substrate 100 may include other semiconductor materials, such as germanium. In some embodiments, the substrate 100 may include compound semiconductors such as silicon carbide, gallium arsenide, gallium phosphide, gallium nitride, and indium phosphide. ), indium arsenide and/or indium antimonide. In some embodiments, the substrate 100 may include alloy semiconductors including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP, or a combination thereof. Other substrates can also be used, such as multilayer or gradient substrates.

In some embodiments, the substrate 100 may be a lightly doped first conductivity type substrate or a second conductivity type substrate, wherein the doping concentration of the substrate 100 is between about 1×10 ¹⁴ atoms/cm ³ and 1×10 ¹⁶ atoms /cm ³ , for example, between about 5×10 ¹⁴ atoms/cm ³ and 5×10 ¹⁵ atoms/cm ³ . In the following embodiments, the first conductivity type is P-type and the second conductivity type is N-type as an example for description. Those with ordinary knowledge in the technical field of the present invention can also use the first conductivity type as N-type. , And the second conductivity type is P-type. In an embodiment of the present invention, the substrate 100 is of the first conductivity type (for example, P-type), and has P-type dopants (for example, boron) inside. In the embodiment of the present invention, the high-voltage semiconductor device 10 subsequently formed on the substrate 100 may include a horizontally diffused metal oxide semiconductor transistor of the second conductivity type (for example, N-type).

The high-voltage integrated circuit structure 10 may include an epitaxial layer 102 disposed on the substrate 100. In the embodiment of the present invention, the epitaxial layer 102 is of the second conductivity type (for example, N-type) that has the opposite type to that of the substrate 100. The material used for the epitaxial layer 102 may include silicon, silicon germanium, silicon carbide, and the doping concentration of the epitaxial layer 102 is in a range between about 5×10 ¹⁴ atoms/cm ³ and 5×10 ¹⁶ atoms/cm ³ , For example, between about 7×10 ¹⁴ atoms/cm ³ and 7×10 ¹⁵ atoms/cm ³ .

In addition, as shown in FIG. 1, the high-voltage integrated circuit structure 10 includes a plurality of buried layers disposed in the substrate 100 and the epitaxial layer 102, such as a first buried layer 104, a second buried layer 106, The third buried layer 108, the fourth buried layer 110, and the fifth buried layer 150. Since the buried layers with the same conductivity type can be formed in the same layer by the same mask and the same process, the multiple buried layer configurations will not affect the process cost or cycle. In the embodiment of the present invention, the first buried layer 104 and the third buried layer 108 have the first conductivity type (for example, P type), and the second buried layer 106, the fourth buried layer 110, and the fifth buried layer 150 have the first conductivity type. Two conductivity types (such as N-type). According to some embodiments, during the operation of the integrated circuit, the charges between the P-type component and the N-type component will compensate each other to achieve a state of charge balance. By cross-arranging the P-type buried layer and the N-type buried layer between the substrate 100 and the epitaxial layer 102, the state of charge balance can be further improved, and the expected depletion region (depletion region) will be "depleted" More complete. According to some embodiments, a more complete depletion region can reduce the leakage current and increase the breakdown voltage and the lateral breakdown voltage of the integrated circuit. According to some embodiments, the doping concentration of the first buried layer 104, the second buried layer 106, the third buried layer 108, the fourth buried layer 110, and the fifth buried layer 150 is between about 1×10 ¹⁶ atoms/cm ³ and The range between 1×10 ²⁰ atoms/cm ³ is, for example, between about 1×10 ¹⁷ atoms/cm ³ and 1×10 ¹⁹ atoms/cm ³ .

In some embodiments, the method for forming the first buried layer 104, the second buried layer 106, the third buried layer 108, the fourth buried layer 110, and the fifth buried layer 150 may include forming the epitaxial layer 102 in the substrate P-type dopants (for example, boron) or N-type dopants (for example, phosphorus or arsenic) are ion implanted in 100, and heat treatment is performed to drive the implanted ions into the substrate 100 , And then the epitaxial layer 102 is formed on the substrate 100. In some embodiments, since the epitaxial layer 102 is formed under high temperature conditions, the implanted ions will diffuse into the epitaxial layer 102. As shown in Figure 1, the first buried layer 104, the second buried layer 106, the third buried layer 108, the fourth buried layer 110, and the fifth buried layer 150 are located near the interface between the substrate 100 and the epitaxial layer 102, and have One part is in the substrate 100 and the other part is in the epitaxial layer 102.

Continuing to refer to FIG. 1, the high-voltage integrated circuit structure 10 may include a first conductive type isolation region 112, a first high-voltage well region 120, a second high-pressure well region 122, and a third high-pressure well region 152 in the epitaxial layer 102. According to an embodiment of the present invention, the first conductivity type isolation region 112 is placed on the first buried layer 104. According to an embodiment of the present invention, the first conductivity type isolation region 112 further includes an empty trench region 114, a first conductivity type high-voltage well region 116, and a second conductivity type micro-well region 118. In the embodiment of the present invention, the empty slot region 114 is disposed in the central region of the first conductivity type isolation region 112, and the slot region 114 is adjacent to the first buried layer 104 below. According to the embodiment of the present invention, the empty trench region 114 is formed by the epitaxial layer 102; that is, no additional implantation process is performed on the region of the epitaxial layer 102 where the empty trench region 114 is scheduled to be formed, so the empty trench The region 114 has the same second conductivity type (for example, N-type) and doping concentration as the epitaxial layer 102. In a specific embodiment, the empty groove region 114 has a horizontal length of at least about 2 μm, for example, a range between about 2 μm and 10 μm. Adjusting the empty slot area 114 to an appropriate horizontal length does not affect the performance of the overall high-voltage integrated circuit. However, increasing the empty slot area 114 will make the overall high-voltage integrated circuit structure 10 more bulky. In today's market, an excessively large integrated circuit structure will affect the flexibility of application, so it is not appropriate. The above-mentioned dimensions will vary with the difference in process technology, so the embodiment of the present invention is not limited to this.

According to the embodiment of the present invention, the first conductivity type high-voltage well region 116 is formed on opposite sides of the empty slot region 114. In a specific embodiment, the first conductivity type high-voltage well regions 116 on both sides of the empty trench region 114 may each have a horizontal length of about 2 μm. Therefore, in a specific embodiment, the overall structure of the first conductive type isolation region 112 has a total horizontal length of about 6 μm. The first conductivity type high voltage well region 116 has the same conductivity type as the first buried layer 104, for example, P type. The formation method of the first conductivity type high voltage well region 116 includes an ion implantation process and a thermal drive in process. In some embodiments, the doping concentration of the first conductivity type high-voltage well region 116 is in a range between about 5×10 ¹⁵ atoms/cm ³ and 5×10 ¹⁸ atoms/cm ³ , for example, about 5×10 ¹⁶ atoms/cm 3 cm ³ and 1×10 ¹⁸ atoms/cm ³ .

By arranging the N-type empty slot regions 114 between the P-type first conductivity type high-voltage well regions 116, the number and total area of heterojunctions can be increased. The heterogeneous junction promotes the mutual compensation of the charges between the P-type components and the N-type components to achieve a more balanced state of charge. The equivalent charge balance makes the formed depletion region more complete, which can avoid the generation of leakage current, thereby increasing the breakdown voltage and the lateral breakdown voltage. Therefore, in the embodiment of the present invention, arranging the empty slot region 114 in the middle of the first conductivity type high-voltage well region 116 (for example, the central region of the first conductivity type isolation region 112) can make the first conductivity type isolation region 112 Get uniform "exhaustion". For example, if the empty slot area 114 of the first conductivity type isolation area 112 is excessively biased to one side, the other side may be "depleted" and not complete enough, so that the depleted area may cause leakage current and affect the high voltage. The performance of the breakdown voltage and lateral breakdown voltage of the integrated circuit.

As mentioned above, the first buried layer 104 is disposed under the first conductive type isolation region 112 and adjacent to the empty trench region 114. The first buried layer 104 (P-type) can compensate for each other with the second buried layer 106 (N-type), and can also be charged with the empty trench region 114 (N-type). In addition, since the first buried layer 104 is located at the bottom of the epitaxial layer 102, between the bottom surface of the epitaxial layer 102 and the top surface of the substrate 100, the configuration of the first buried layer 104 can make the depletion region close to the epitaxial layer 102 The part of the bottom surface is "depleted" more completely, thereby improving the leakage current problem at the bottom of the epitaxial layer 102.

According to the embodiment of the present invention, the second conductivity type micro-well region 118 can be formed in the first conductivity type isolation region 112 to complete the overall structure of the first conductivity type isolation region 112. The second conductivity type micro-well region 118 is adjacent to the empty slot region 114 below, and adjacent to the first conductivity type high-voltage well region 116 on the left and right sides. In a specific embodiment, the second conductivity type microwell region 118 may have a horizontal length of about 2 μm. In a specific embodiment, the second conductivity type microwell region 118 is N-type, and its doping concentration is in a range between about 1×10 ¹⁶ atoms/cm ³ and 1×10 ¹⁹ atoms/cm ³ , for example, about 1×10 16 atoms/cm 3 and 1×10 19 atoms/cm 3. Between 1×10 ¹⁷ atoms/cm ³ and 5×10 ¹⁸ atoms/cm ^3.

According to some embodiments, since the doping concentration (P-type) of the first conductivity type high-voltage well region 116 is higher than the doping concentration of the empty trench region 114 (N-type), the second conductivity type microwell on the empty trench region 114 Setting the region 118 to be N-type (rather than P-type) can make the portion of the depletion region located in the isolation region 112 of the first conductivity type "depleted" in a more balanced manner. In addition, since the top surfaces of the second conductivity type microwell region 118 and the epitaxial layer 102 are substantially at the same level, the configuration of the second conductivity type microwell region 118 can make the depletion region close to the part of the top surface of the epitaxial layer 102. "Depleted" is more complete, thereby improving the leakage current problem on the surface of the epitaxial layer 102.

With continued reference to FIG. 1, the epitaxial layer 102 may additionally include a first high-pressure well region 120, a second high-pressure well region 122, and a third high-pressure well region 152. The first high-voltage well region 120 has the same conductivity type as the second buried layer 106, the fourth buried layer 110, and the fifth buried layer 150, while the second high-voltage well region 122 has the same conductivity type as the first buried layer 104 and the third buried layer 108. The same conductivity type. In the embodiment of the present invention, the first high-pressure well area 120 and the third high-pressure well area 152 are N-type, and the second high-pressure well area 122 is P-type. In some embodiments, the doping concentration of the first high pressure well region 120, the second high pressure well region 122, and the third high pressure well region 152 may be lower than or equal to the doping concentration of the first conductivity type high pressure well region 116, for example That is, it may be in a range between about 1×10 ¹⁵ atoms/cm ³ and 5×10 ¹⁷ atoms/cm ³ , for example, between about 1×10 ¹⁶ atoms/cm ³ and 5×10 ¹⁷ atoms/cm ³ .

After the first high-pressure well area 120 is formed, the first well area 124 is formed in the first high-pressure well area 120. The first well area 124 and the first high voltage well area 120 have the same conductivity type. In the embodiment of the present invention, the first well area 124 is N-type. The formation method of the first well region 124 includes an ion implantation process and a thermal drive process. In some embodiments, the doping concentration of the first well region 124 is higher than the doping concentration of the first conductivity type high-voltage well region 116, for example, may be between about 1×10 ¹⁶ atoms/cm ³ and 5×10 ^{The range between 18} atoms/cm ³ is, for example, between about 1×10 ¹⁷ atoms/cm ³ and 5×10 ¹⁸ atoms/cm ³ .

After the second high-pressure well area 122 is formed, a second well area 126 and a third well area 128 are formed in the second high-pressure well area 122. The second well area 126 and the third well area 128 and the second high pressure well area 122 have the same conductivity type. In the embodiment of the present invention, the second well area 126 and the third well area 128 are P-type. The formation methods of the second well region 126 and the third well region 128 include an ion implantation process and a thermal drive process. In some embodiments, the doping concentration of the second well region 126 and the third well region 128 is higher than the doping concentration of the first conductivity type high-voltage well region 116, for example, it may be about 1×10 ¹⁶ atoms/ The range between cm ³ and 5×10 ¹⁸ atoms/cm ³ is, for example, between about 1×10 ¹⁷ atoms/cm ³ and 5×10 ¹⁸ atoms/cm ³ .

Continuing to refer to FIG. 1, the high-voltage integrated circuit structure 10 may include a first isolation structure 130a, a second isolation structure 130b, a third isolation structure 130c, a fourth isolation structure 130d, and a fifth isolation structure disposed on the epitaxial layer 102 130e. Specifically, a portion of the first isolation structure 130a, the second isolation structure 130b, the third isolation structure 130c, the fourth isolation structure 130d, and the fifth isolation structure 130e are embedded in the epitaxial layer 102. In some embodiments, the first isolation structure 130a, the second isolation structure 130b, the third isolation structure 130c, the fourth isolation structure 130d, and the fifth isolation structure 130e may be made of silicon oxide, and are formed by thermal oxidation Local oxidation of silicon (LOCOS) isolation structure. In other embodiments, the first isolation structure 130a, the second isolation structure 130b, the third isolation structure 130c, the fourth isolation structure 130d, and the fifth isolation structure 130e may be shallow trenches formed by etching, oxidation, and deposition processes Shallow trench isolation (STI) structure.

In some embodiments, after forming the first isolation structure 130a, the second isolation structure 130b, the third isolation structure 130c, the fourth isolation structure 130d, and the fifth isolation structure 130e, a gate structure 132 is formed on the epitaxial layer 102 . As shown in Figure 1, the gate structure 132 extends from the second well region 126 to the first isolation structure 130a, and the gate structure 132 covers the second well region 126, a part of the second high pressure well region 122 and the first high pressure Part of the well area 120.

The gate structure 132 includes a gate dielectric layer (not shown) and a gate electrode (not shown) disposed on the gate dielectric layer. According to some embodiments, a dielectric material layer and a conductive material layer on the dielectric material layer may be sequentially blanket deposited on the epitaxial layer 102 to form the gate dielectric layer and the conductive material layer, respectively. The gate electrode on the gate dielectric layer. Then, the dielectric material layer and the conductive material layer are respectively patterned by a lithography process and an etching process to form a gate structure 132 including a gate dielectric layer and a gate electrode.

The material used in the above-mentioned dielectric material layer (that is, the material of the gate dielectric layer) may include silicon oxide, silicon nitride, silicon oxynitride, high-k dielectric materials, combinations of the above, or other materials. The right material. In some embodiments, the dielectric material layer may be formed by chemical vapor deposition (CVD) or spin-on coating. The material of the conductive material layer (that is, the material of the gate electrode) can be amorphous silicon, polysilicon, one or more metals, metal nitrides, metal silicides, conductive metal oxides, combinations of the above, or other suitable materials.

As shown in FIG. 1, the high-voltage integrated circuit structure 10 may include a plurality of doped regions, such as a drain region 134, a source region 136, a doped region 138, and a high-voltage doped region 154. According to an embodiment of the present invention, the drain region 134 is between the first isolation structure 130 a and the second isolation structure 130 b, and is located in the first well region 124. The drain region 134 and the first well region 124 may have the same conductivity type. In the embodiment of the present invention, the drain region 134 is N-type. The formation method of the drain region 134 includes an ion implantation process and a thermal drive process. In some embodiments, the doping concentration of the drain region 134 may be higher than the doping concentration of the first well region 124, for example, it may be between about 1×10 ¹⁹ atoms/cm ³ and 5×10 ²⁰ atoms/cm. The range between cm ³ is, for example, between about 5×10 ¹⁹ atoms/cm ³ and 5×10 ²⁰ atoms/cm ³ .

According to an embodiment of the present invention, the source region 136 is between the gate structure 132 and the third isolation structure 130c, and is located in the second well region 126. The source region 136 and the second well region 126 may have different conductivity types. In the embodiment of the present invention, the source region 136 is N-type. The method for forming the source region 136 includes an ion implantation process and a thermal drive process. In some embodiments, the doping concentration of the source region 136 may be higher than the doping concentration of the second well region 126, for example, it may be between about 1×10 ¹⁹ atoms/cm ³ and 5×10 ²⁰ atoms/cm. The range between cm ³ is, for example, between about 5×10 ¹⁹ atoms/cm ³ and 5×10 ²⁰ atoms/cm ³ .

According to an embodiment of the present invention, the doped region 138 is between the third isolation structure 130c and the fourth isolation structure 130d, and is located in the third well region 128. The doped region 138 and the third well region 128 may have the same conductivity type. In the embodiment of the present invention, the doped region 138 is P-type. The formation method of the doped region 138 includes an ion implantation process and a thermal drive process. In some embodiments, the doping concentration of the doping region 138 may be higher than the doping concentration of the third well region 128, for example, may be between about 1×10 ¹⁹ atoms/cm 3 and 5×10 ²⁰ atoms/ ^{cm 3.} The range between cm ³ is, for example, between about 5×10 ¹⁹ atoms/cm ³ and 5×10 ²⁰ atoms/cm ³ .

According to an embodiment of the present invention, the high-voltage doped region 154 is between the second isolation structure 130b and the fifth isolation structure 130e, and is located in the third high-voltage well region 152. The high-voltage doped region 154 and the third high-voltage well region 152 may have the same conductivity type. In the embodiment of the present invention, the high-voltage doped region 154 is N-type. The formation method of the high-voltage doped region 154 includes an ion implantation process and a thermal drive process. In some embodiments, the doping concentration of the high-voltage doped region 154 may be higher than that of the third high-voltage well region 152, for example, it may be between about 1×10 ¹⁹ atoms/cm ³ and 5×10 ^20. The range between atoms/cm ³ is, for example, between about 5×10 ¹⁹ atoms/cm ³ and 5×10 ²⁰ atoms/cm ³ . In some embodiments, after the gate structure 132 is formed, the drain region 134, the source region 136, the doped region 138, and the high-voltage doped region 154 are formed.

Continuing to refer to FIG. 1, the high-voltage integrated circuit structure 10 may include an interlayer dielectric (ILD) 140 disposed on the epitaxial layer 102. According to some embodiments, for example, silicon oxide, silicon nitride, silicon carbonitride, silicon carbide, titanium nitride, tetraethyl orthosilicate oxide (TEOS oxide) can be used as a precursor, Phospho-silicate glass (PSG), boro-silicate glass (BSG), boron-doped phospho-silicate glass (BPSG) or other similar materials Interlayer dielectric layer 140.

The high-voltage integrated circuit structure 10 may include a plurality of vias, such as vias 142a, 142b, 142c, and 142d, disposed on the epitaxial layer 102 and in the interlayer dielectric layer 140. In addition, the high-voltage integrated circuit structure 10 may also include a drain electrode 144 disposed on the via hole 142a, a source electrode 146 on the via hole 142b, a base electrode 148 on the via hole 142c, and a drain electrode 148 on the via hole 142d. High-voltage isolation electrode 156. In the embodiment of the present invention, the drain electrode 144 is electrically connected to the drain region 134 through the via hole 142a, the source electrode 146 is electrically connected to the source region 136 via the via hole 142b, and the base electrode 148 is electrically connected via the conductive hole 142b. The hole 142c is electrically connected to the doped region 138, and the high-voltage isolation electrode 156 is electrically connected to the high-voltage doped region 154 through the via 142d.

In some embodiments, the vias 142a, 142b, 142c, 142d, the drain electrode 144, the source electrode 146, the base electrode 148, and the high-voltage isolation electrode 156 may include aluminum (Al), copper (Cu), and tungsten (W) , Titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), nickel silicide (NiSi), cobalt silicide (CoSi), tantalum carbide (TaC), tantalum silicon nitride (TaSiN) , Tantalum Carbonitride (TaCN), Titanium Aluminide (TiAl), Titanium Aluminum Nitride (TiAlN), the above combination or other suitable materials. In some embodiments, photolithography processes (such as photoresist coating, soft baking, exposure, post-exposure baking, development, other suitable techniques or combinations of the above) and etching processes (such as wet etching processes) can be used. , A dry etching process, other suitable methods, or a combination of the above), other suitable processes, or a combination thereof, form a plurality of openings (not shown) in the interlayer dielectric layer 140. Next, the above-mentioned materials are filled in the openings to form via holes 142a, 142b, 142c, and 142d.

In some embodiments, before filling the via holes 142a, 142b, 142c, and 142d with the above-mentioned material, a barrier layer (not shown) may be formed on the sidewalls and bottom of the opening to prevent the vias 142a, 142b, The conductive materials of 142c and 142d diffuse into the interlayer dielectric layer 140. The material of the barrier layer can be titanium nitride (TiN), titanium (Ti), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), other suitable materials or combinations thereof . In some embodiments, physical vapor deposition, atomic layer deposition, electroplating, other suitable processes, or a combination thereof may be used to form the barrier layer.

In some embodiments, a photolithography process (such as photoresist coating, soft baking, exposure, post-exposure baking, development, other suitable techniques, or a combination of the above) may be used to form a patterned light on the interlayer dielectric layer 140. Resistance (not shown). Then, the same material as the via holes 142a, 142b, 142c, and 142d can be formed by using physical vapor deposition, atomic layer deposition, electroplating, other suitable processes, or a combination thereof to form the drain electrode 144, the source electrode 146, The base electrode 148 and the high-voltage isolation electrode 156. According to some embodiments, the formation of the high-voltage isolation electrode 156 may allow a high-voltage voltage to be applied in the isolation structure. According to some embodiments, the formation of the substrate electrode 148 may allow the high-voltage integrated circuit structure 10 to be grounded from the top or from the bottom. According to the embodiment of the present invention, after the drain electrode 144, the source electrode 146, the base electrode 148 and the high voltage isolation electrode 156 are formed, the manufacturing process of the high voltage integrated circuit structure 10 is completed. According to some embodiments, the high-voltage integrated circuit structure 10 can be divided into a first area 10A and a second area 10B. The first region 10A extends from the first conductive type isolation region 112 to the first high-voltage well region 120 to the second high-voltage well region 122. The second region 10B extends from the first conductive type isolation region 112 to a direction opposite to the first high-voltage well region 120 to the third high-voltage well region 152. According to some embodiments, the first region 10A can be used as a potential converter of the high-voltage integrated circuit structure 10, and the second region 10B can be used as a high-side region of the high-voltage integrated circuit structure 10.

As shown in FIG. 1, according to some embodiments, the high-voltage integrated circuit structure 10 of the present invention includes a substrate 100 having a first conductivity type (for example, P-type), and an epitaxial layer 102 is disposed on the substrate 100, wherein the epitaxial layer 102 has a second conductivity type (such as N-type) that is different from the first conductivity type, and a source region 136 and a drain region 134 are provided in the epitaxial layer 102, which have the second conductivity type, and are provided on the epitaxial layer 102 The first isolation structure 130a and the second isolation structure 130b are respectively located on opposite sides of the drain region 134, wherein the first isolation structure 130a is located between the source region 136 and the drain region 134, and the first conductivity type isolation region 112 is located in the epitaxial layer 102 under the second isolation structure 130b, including: an empty trench region 114 is provided in the central area of the first conductivity type isolation region 112, and is formed by the epitaxial layer 102, and the empty trench region 114 The first conductivity type high voltage well regions 116 are provided on opposite sides, and the first buried layer 104 is provided in the substrate 100, which has the first conductivity type. The first buried layer 104 is located under the first conductivity type isolation region 112 and is adjacent to the space. The trench region 114, and a second buried layer 106 is provided in the substrate 100, which has a second conductivity type, wherein the second buried layer 106 is located between the drain region 134 and the first conductivity type isolation region 112, and the first buried layer 104 and the second buried layer 106 are separated from each other. According to some embodiments, the high-voltage integrated circuit structure 10 further includes a second conductivity type micro-well region 118, which is disposed on the empty slot region 114 and adjacent to the second isolation structure 130b. According to some embodiments, a first high-voltage well region 120 is provided in the epitaxial layer 102, which has the second conductivity type, wherein the drain region 134 is provided in the first high-voltage well region 120, and the first high-voltage well region 120 is adjacent to the first high-voltage well region 120. A conductive type isolation region 112 and a second buried layer 106.

According to some embodiments, a first well region 124 is provided in the first high-pressure well region 120, which has the second conductivity type, wherein the first well region 124 is located between the first isolation structure 130a and the second isolation structure 130b, and is drained. The polar region 134 is located in the first well region 124. According to some embodiments, a third buried layer 108 is provided in the substrate 100, which has the first conductivity type, wherein the third buried layer 108 is located under the first high voltage well region 120, and is located in the source region 136 and the second buried layer 106 , And the second buried layer 106 and the third buried layer 108 are separated from each other. According to some embodiments, a second high-voltage well region 122 is disposed in the epitaxial layer 102, which has the first conductivity type, wherein the source region 136 is disposed in the second high-voltage well region 122, and the second high-voltage well region 122 is adjacent to the second high-voltage well region 122. A high pressure well area 120. According to some embodiments, a second well region 126 is provided in the second high voltage well region 122 and has the first conductivity type, wherein the source region 136 is located in the second well region 126. According to some embodiments, a fourth buried layer 110 is provided in the substrate 100, which has the second conductivity type, wherein the fourth buried layer 110 is located under the second high-voltage well region 122, and the third buried layer 108 and the fourth buried layer 110 Separate from each other. According to some embodiments, a gate structure 132 is provided on the epitaxial layer 102, which extends from the second well region 126 to the first isolation structure 130a. According to some embodiments, a third isolation structure 130c is disposed on the epitaxial layer 102, wherein the source region 136 is located between the first isolation structure 130a and the third isolation structure 130c. According to some embodiments, a third well region 128 and a doped region 138 are provided in the second high voltage well region 122, which have the first conductivity type, wherein the doped region 138 is located in the third well region 128, and the third isolation structure 130c Located between the doped region 138 and the source region 136, and the doped region 138 is electrically connected to the substrate 100. According to some embodiments, a third high-voltage well region 152 is provided in the epitaxial layer 102, which has the second conductivity type, and the third high-voltage well region 152 is adjacent to the isolation region 112 of the first conductivity type relative to the first high-voltage well region 120. The other side. According to some embodiments, a fifth buried layer 150 is provided in the substrate 100, which has the second conductivity type, wherein the fifth buried layer 150 is located under the third high voltage well region 152, wherein the first buried layer 104 and the fifth buried layer 150 Separate from each other. According to some embodiments, a high-voltage doped region 154 is provided in the third high-voltage well region 152, which has the second conductivity type. According to some embodiments, the high-voltage integrated circuit structure 10 is a potential converter and a high-side region.

According to some embodiments, the top surfaces of the first conductive type isolation region 112 and the second conductive type microwell region 118 may abut the bottom surface of the second isolation structure 130b. The second isolation structure 130b may completely cover the first conductivity type isolation region 112 and the second conductivity type microwell region 118. Furthermore, the second buried layer 106 may be disposed under the first high-pressure well region 120 and under the projection range of the second isolation structure 130b. According to an embodiment of the present invention, the first buried layer 104 and the second buried layer 106 may be separated from each other. The third buried layer 108 can also be disposed under the first high-pressure well region 120, and can extend from below the projection range of the second isolation structure 130b to the projection of the first well region 124, the first isolation structure 130a, and the gate structure 132 Below the range. In other embodiments, the third buried layer 108 may not be located below the projection range of the second isolation structure 130b, or the third buried layer 108 may not extend to the projection range of the first isolation structure 130a and/or the gate structure 132 Below. According to an embodiment of the present invention, the second buried layer 106 and the third buried layer 108 may be separated from each other. According to an embodiment of the present invention, the fourth buried layer 110 may be disposed under the second high-pressure well region 122, and may extend from below the projection range of the gate structure 132 to the second well region 126 and the third isolation structure 130c. Below the projection range. In other embodiments, the fourth buried layer 110 may not be located below the projection range of the third isolation structure 130c. According to an embodiment of the present invention, the third buried layer 108 and the fourth buried layer 110 may be separated from each other. According to an embodiment of the present invention, the fifth buried layer 150 may be disposed under the third high pressure well region 152, wherein the first buried layer 104 and the fifth buried layer 150 may be separated from each other.

In order to increase the breakdown voltage and the lateral breakdown voltage of the high-voltage integrated circuit structure 10, the embodiment of the present invention arranges the first conductivity type isolation region 112 and the first buried region 134 on the side of the drain region 134 away from the source region 136. Layer 104 and the second buried layer 106. The first conductive type isolation region 112, the first buried layer 104, and the second buried layer 106 are configured into an L-shaped structure, and the horizontal portion of the L-shaped extends toward the source region 136. With the arrangement of the L-shaped structure, when a reverse voltage is applied to the drain terminal of the horizontally diffused metal oxide semiconductor transistor, the size and integrity of the depletion region can be increased, thereby increasing the breakdown voltage and lateral breakdown voltage of the device. Compared with the embodiment in which the empty slot region 114 and the second conductivity type micro-well region 118 are not arranged in the first conductivity type isolation region 112, the breakdown voltage and the lateral impact of the high voltage integrated circuit structure 10 of the embodiment of the present invention are The through voltage can be increased by 10% to 15% and 2% to 5%, respectively. The horizontal diffusion metal oxide semiconductor transistor with high breakdown voltage and high lateral breakdown voltage can be widely used in potential converters of high-voltage integrated circuits. According to the embodiment of the present invention, since the reduced surface field region (RESURF region) is located in the N-type first high-voltage well region 120 under the gate structure 132, the first part of the high-voltage integrated circuit structure 10 The area 10A can be an N-channel potential converter.

Fig. 2 is a graph 20 showing the correlation between the voltage of the high-voltage integrated circuit and the distance between the buried layers. According to the embodiment of the present invention, the separation distance G is the separation distance between the second buried layer 106 and the third buried layer 108. When the separation distance G is 0 μm (that is, when the second buried layer 106 is adjacent to the third buried layer 108), the breakdown voltage and the lateral breakdown voltage measured are lower than the breakdown voltage measured when the separation distance G is 2 μm Voltage and lateral breakdown voltage. However, if the separation distance G continues to be increased, the overall high-voltage integrated circuit structure 10 will become more bulky. In today's market, an excessively large integrated circuit structure will affect the flexibility of application, so it is not appropriate. Therefore, in an embodiment, the predetermined separation distance G can be set to about 2 μm.

Figure 3 shows a graph 30 of the correlation between the voltage of the high-voltage integrated circuit and the length of the buried layer. According to the embodiment of the present invention, the buried layer length L is the horizontal length of the second buried layer 106. When the buried layer length L increases, the breakdown voltage of the high-voltage integrated circuit structure 10 can be further increased. However, while the breakdown voltage increases, the lateral breakdown voltage decreases at the same time. Therefore, the buried layer length L has opposite effects on the breakdown voltage and the lateral breakdown voltage. When the buried layer length L reaches 6 μm or longer, the measured lateral punch-through voltage is even lower than the implementation of the empty trench region 114 and the second conductivity type micro-well region 118 in the first conductivity type isolation region 112 that are not configured Example of the measured lateral punch-through voltage. Therefore, in an embodiment, the predetermined buried layer length L can be set to about 4 μm to 6 μm.

The components of several embodiments are summarized above, so that those with ordinary knowledge in the technical field of the present invention can better understand the viewpoints of the present invention. Those with ordinary knowledge in the technical field of the present invention should understand that they can easily design or modify other manufacturing processes and structures based on the embodiments of the present invention to achieve the same purposes and/or advantages as the embodiments described herein. . Those with ordinary knowledge in the technical field to which the present invention belongs should also understand that such equivalent structures do not depart from the spirit and scope of the present invention, and they can do various things without departing from the spirit and scope of the present invention. Such changes, substitutions and replacements.

10: High-voltage integrated circuit structure 100: base 10A: The first area 10B: second area 102: epitaxial layer 104: first buried layer 106: second buried layer 108: third buried layer 110: fourth buried layer 112: Isolation area of the first conductivity type 114: empty slot area 116: The first conductivity type high voltage well area 118: Second conductivity type micro-well area 120: The first high-pressure well area 122: The second high-pressure well area 124: The first well area 126: The second well area 128: The third well area 130a: the first isolation structure 130b: Second isolation structure 130c: third isolation structure 130d: Fourth isolation structure 130e: Fifth isolation structure 132: Gate structure 134: Drain Area 136: Source Region 138: doped area 140: Interlayer dielectric layer 142a, 142b, 142c, 142d: pilot hole 144: Drain electrode 146: Source electrode 148: Base electrode 150: Fifth Buried Layer 152: The third high-pressure well area 154: High voltage doped area 156: high voltage isolation electrode 20: High-voltage integrated circuit voltage-separation distance curve 30: High voltage integrated circuit voltage-length graph G: separation distance L: Buried layer length

Various aspects of the disclosure will be described in detail below in conjunction with the accompanying drawings. It should be noted that, according to standard practices in the industry, the various features are not drawn to scale. In fact, the size of the element can be arbitrarily enlarged or reduced to clearly show the features of the present disclosure. FIG. 1 is a schematic cross-sectional view showing the structure of a high-voltage semiconductor integrated circuit according to some embodiments of the present invention. FIG. 2 is a graph showing the correlation between the voltage of the high-voltage integrated circuit and the spacing distance of the buried layer according to some embodiments of the present invention. FIG. 3 is a graph showing the correlation between the voltage of the high-voltage integrated circuit and the length of the buried layer according to some embodiments of the present invention.

10: High-voltage integrated circuit structure

10A: The first area

10B: second area

100: base

102: epitaxial layer

104: first buried layer

106: second buried layer

108: third buried layer

110: fourth buried layer

112: Isolation area of the first conductivity type

114: empty slot area

116: The first conductivity type high voltage well area

118: Second conductivity type micro-well area

120: The first high-pressure well area

122: The second high-pressure well area

124: The first well area

126: The second well area

128: The third well area

130a: the first isolation structure

130b: Second isolation structure

130c: third isolation structure

130d: Fourth isolation structure

130e: Fifth isolation structure

132: Gate structure

134: Drain Area

136: Source Region

138: doped area

140: Interlayer dielectric layer

142a, 142b, 142c, 142d: pilot hole

144: Drain electrode

146: Source electrode

148: Base electrode

150: Fifth Buried Layer

152: The third high-pressure well area

154: High voltage doped area

156: high voltage isolation electrode

G: separation distance

L: Buried layer length

Claims (15)

A high-voltage integrated circuit structure, including: A substrate having a first conductivity type; An epitaxial layer disposed on the substrate, wherein the epitaxial layer has a second conductivity type different from the first conductivity type; A source region and a drain region are arranged in the epitaxial layer and have the second conductivity type; A first isolation structure and a second isolation structure are disposed on the epitaxial layer and are respectively located on opposite sides of the drain region, wherein the first isolation structure is located between the source region and the drain region between; A first conductivity type isolation region located in the epitaxial layer under the second isolation structure includes: An empty slot area, which is arranged in the central area of the first conductivity type isolation area and is formed by the epitaxial layer; and A first conductivity type high-voltage well area, arranged on opposite sides of the empty slot area; A first buried layer disposed in the substrate and having the first conductivity type, wherein the first buried layer is located under the first conductivity type isolation region and adjacent to the empty trench region; and A second buried layer is disposed in the substrate and has the second conductivity type, wherein the second buried layer is located between the drain region and the first conductivity type isolation region, and the first buried layer and the second conductivity type The two buried layers are separated from each other. Such as the high-voltage integrated circuit structure of claim 1, wherein the first conductivity type isolation region further includes a second conductivity type microwell region, wherein the second conductivity type microwell region is disposed on the empty slot region and adjacent to the The second isolation structure. For example, the high-voltage integrated circuit structure of claim 1, further comprising a first high-voltage well region disposed in the epitaxial layer and having the second conductivity type, wherein the drain region is disposed in the first high-voltage well region , Wherein the first high-voltage well region is adjacent to the first conductive type isolation region and the second buried layer. For example, the high-voltage integrated circuit structure of claim 3 further includes a first well area, which is disposed in the first high-voltage well area and has the second conductivity type, wherein the first well area is located between the first isolation structure and the Between the second isolation structures, and the drain region is located in the first well region. For example, the high-voltage integrated circuit structure of claim 3 further includes a third buried layer disposed in the substrate and having the first conductivity type, wherein the third buried layer is located under the first high-voltage well region and located in the Between the source region and the second buried layer, and the second buried layer and the third buried layer are separated from each other. For example, the high-voltage integrated circuit structure of claim 5 further includes a second high-voltage well region disposed in the epitaxial layer and having the first conductivity type, wherein the source region is disposed in the second high-voltage well region , Wherein the second high-pressure well area is adjacent to the first high-pressure well area. For example, the high-voltage integrated circuit structure of claim 6 further includes a second well region, which is disposed in the second high-voltage well region and has the first conductivity type, wherein the source region is located in the second well region. For example, the high-voltage integrated circuit structure of claim 6, further comprising a fourth buried layer disposed in the substrate and having the second conductivity type, wherein the fourth buried layer is located in the second high-voltage well region, and the third The buried layer and the fourth buried layer are separated from each other. For example, the high-voltage integrated circuit structure of claim 7 further includes a gate structure disposed on the epitaxial layer and extending from the second well region to the first isolation structure. For example, the high-voltage integrated circuit structure of claim 6 further includes a third isolation structure disposed on the epitaxial layer, wherein the source region is located between the first isolation structure and the third isolation structure. For example, the high-voltage integrated circuit structure of claim 10 further includes a third well region and a doped region, which are arranged in the second high-voltage well region and have the first conductivity type, wherein the doped region is located in the third In the well region, the third isolation structure is located between the doped region and the source region, and the doped region is electrically connected to the substrate. For example, the high-voltage integrated circuit structure of claim 3 further includes a third high-voltage well region disposed in the epitaxial layer and having the second conductivity type, wherein the third high-voltage well region is adjacent to the first conductivity type isolation The zone is opposite to the other side of the first high-pressure well zone. For example, the high-voltage integrated circuit structure of claim 12 further includes a fifth buried layer disposed in the substrate and having the second conductivity type, wherein the fifth buried layer is located under the third high-voltage well region, and the first A buried layer and the fifth buried layer are separated from each other. For example, the high-voltage integrated circuit structure of claim 12 further includes a high-voltage doped region disposed in the third high-voltage well region and having the second conductivity type. Such as the high-voltage integrated circuit structure of claim 1, wherein the high-voltage integrated circuit structure is a level shifter and a high-side region.

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