TW202129850A - Semiconductor device assemblies including stacked individual modules - Google Patents

Semiconductor device assemblies including stacked individual modules Download PDF

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Publication number
TW202129850A
TW202129850A TW109145322A TW109145322A TW202129850A TW 202129850 A TW202129850 A TW 202129850A TW 109145322 A TW109145322 A TW 109145322A TW 109145322 A TW109145322 A TW 109145322A TW 202129850 A TW202129850 A TW 202129850A
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Taiwan
Prior art keywords
individual
individual module
module
substrate
semiconductor device
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TW109145322A
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Chinese (zh)
Inventor
布萊 Ｊ 蘇葛
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美商美光科技公司
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Publication of TW202129850A publication Critical patent/TW202129850A/en

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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
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Abstract

A semiconductor device assembly can include a substrate including a plurality of external connections. The assembly can include a first individual module and a first bond pad. The first individual module can be disposed on the substrate such that the first side of the first individual module faces the substrate. In some embodiments, the first individual module electrically is coupled to an external connection of the substrate via the first bond pad. The assembly can include a second individual module comprising a plurality of lateral sides. The second individual module can be disposed over the first individual module. In some embodiments, a first lateral side of the second individual module includes a first step forming a first overhang portion and a first recess. In some embodiments, the first bond pad is vertically aligned with the first recess of the second individual module.

Description

包括堆疊式個別模組之半導體裝置總成Semiconductor device assembly including stacked individual modules

本揭示大體上涉及半導體裝置，且更具體地涉及包括個別模組之多個堆疊(例如，個別可測試模組(ITM's))的半導體裝置總成。The present disclosure relates generally to semiconductor devices, and more specifically to semiconductor device assemblies including multiple stacks of individual modules (eg, individual testable modules (ITM's)).

封裝之半導體裝置(包括記憶體晶片、微處理器晶片及成像器晶片)通常包括一或多個安裝在基板上的個別模組，此等模組被封閉在塑膠保護罩中或被導熱蓋覆蓋。接合襯墊可電連接至保護罩外部之端子，以允許個別模組連接至更高級別之電路。Packaged semiconductor devices (including memory chips, microprocessor chips, and imager chips) usually include one or more individual modules mounted on a substrate, and these modules are enclosed in a plastic protective cover or covered by a thermally conductive cover . Bonding pads can be electrically connected to terminals outside the protective cover to allow individual modules to be connected to higher-level circuits.

為了提供附加功能，可向半導體裝置總成添加附加之個別模組。一種包括附加之個別模組的方法涉及在基板上方堆疊個別模組。圖1展示了半導體裝置總成100，其中間隔帶及/或其他材料用於將個別模組彼此垂直間隔開(例如，在垂直於間隔帶之平面的方向上)，以提供對個別模組104上之接合襯墊(例如，接觸襯墊)的近接。如圖所示，間隔帶之寬度W1/橫截面積(平行於間隔帶之平面量測)小於個別模組104之寬度W2/橫截面積，從而留下個別模組之曝露之一或多個接合襯墊108，用於藉由一或多個焊線121引線接合連接至基板101(例如，接合至基板101之接合點120)，個別模組104定位在該基板上。如圖所示，間隔帶105之使用導致一或多個個別模組104具有寬範圍之高度H1。In order to provide additional functions, additional individual modules can be added to the semiconductor device assembly. One method of including additional individual modules involves stacking individual modules above a substrate. FIG. 1 shows a semiconductor device assembly 100 in which spacer tapes and/or other materials are used to vertically space individual modules apart (for example, in a direction perpendicular to the plane of the spacer tape) to provide a pair of individual modules 104 Proximity of the upper bonding pad (for example, the contact pad). As shown in the figure, the width W1/cross-sectional area of the spacer (measured parallel to the plane of the spacer) is smaller than the width W2/cross-sectional area of the individual module 104, leaving one or more of the individual modules exposed The bonding pad 108 is used for wire bonding connection to the substrate 101 (for example, to the bonding point 120 of the substrate 101) by one or more bonding wires 121, on which the individual modules 104 are positioned. As shown in the figure, the use of spacers 105 results in one or more individual modules 104 having a wide range of height H1.

一種促進個別模組至基板之電連接且減少間隔物可能需要之垂直空間的方法係將個別模組配置在一或多個疊瓦堆疊中，其中每個個別模組自下面的個別模組水平偏移，以留下個別模組之曝露之接觸襯墊，該接觸襯墊可接合(例如，用焊線)至基板上之對應接合點(例如，接合指、接合襯墊或其他接合點)。此種疊瓦堆疊方法之缺點為，由於添加至堆疊中之每個附加個別模組之懸垂量增加，且在平行於基板之方向上的尺寸對應增加，因此可以此種方式堆疊之個別模組的數目受到限制。One way to facilitate the electrical connection of individual modules to the substrate and reduce the vertical space that may be required by spacers is to arrange individual modules in one or more shingled stacks, where each individual module is leveled from the individual module below Offset to leave the exposed contact pads of the individual modules, which can be bonded (for example, with bonding wires) to corresponding joints on the substrate (for example, bonding fingers, bonding pads, or other joints) . The disadvantage of this shingled stacking method is that the overhang of each additional individual module added to the stack increases, and the size in the direction parallel to the substrate increases correspondingly, so the individual modules can be stacked in this way The number is limited.

為了解決此種限制，個別模組之疊瓦堆疊可包括以疊瓦方式配置之多組個別模組，且在相同之方向上偏移(例如，如圖2中所示)或在相反之方向上偏移(如圖3中所示)。就此而言，圖2展示了半導體裝置總成200，其中基板201上之個別模組之疊瓦堆疊210包括兩組202及203之個別模組204，它們在相同之偏移方向上疊瓦，且藉由焊線221電連接至基板201上之接合點220。如參照圖2可看出，第一組202之個別模組204的焊線221位於第二組203之懸垂區域211的下方，且因此可能需要在第二組203之個別模組204堆疊在第一組202上方之前形成第一組之個別模組的焊線。此外，第二組203之最底部的個別模組204可能需要在第一組202之最頂部的個別模組204上面間隔足夠距離(例如，由較厚之晶粒附接材料層205提供)以允許焊線221至其上。因此，此種配置之缺點包括由於疊瓦式配置而由個別模組204之疊瓦堆疊佔據的大覆蓋區(例如，在平行於基板201之表面的方向上)。In order to solve this limitation, the shingled stack of individual modules can include multiple sets of individual modules arranged in a shingled manner and offset in the same direction (for example, as shown in Figure 2) or in the opposite direction Up offset (as shown in Figure 3). In this regard, FIG. 2 shows a semiconductor device assembly 200 in which the shingled stack 210 of individual modules on the substrate 201 includes two sets of individual modules 204 of 202 and 203, which are shingled in the same offset direction. And it is electrically connected to the junction 220 on the substrate 201 by the bonding wire 221. As can be seen with reference to FIG. 2, the bonding wires 221 of the individual modules 204 of the first group 202 are located below the overhanging area 211 of the second group 203, and therefore it may be necessary to stack the individual modules 204 of the second group 203 in the first group 203. The bonding wires of the individual modules of the first group are formed above one group 202. In addition, the individual modules 204 at the bottom of the second group 203 may need to be spaced a sufficient distance above the individual modules 204 at the top of the first group 202 (for example, provided by a thicker die attach material layer 205). Allow wire 221 to be soldered to it. Therefore, the disadvantages of this configuration include the large footprint (for example, in a direction parallel to the surface of the substrate 201) occupied by the stack of tiles of the individual modules 204 due to the tiled configuration.

在形成圖3中所示之半導體裝置總成中亦存在類似之挑戰，其中各組個別模組以相反的偏移方向疊瓦。就此而言，圖3展示了半導體裝置總成300，其中基板301上之個別模組之疊瓦堆疊310包括兩組302及303之個別模組304，它們在相反的偏移方向上疊瓦，且藉由焊線321電連接至基板301上的接合點320。如參照圖3可看出，第一組302之個別模組304的至少一些焊線321位於第二組303之懸垂區域311的下方，且因此可能需要在第二組303之個別模組304堆疊在第一組302上方之前形成第一組之個別模組的焊線。因此，此種配置之缺點還包括由於疊瓦式配置而由個別模組304之疊瓦堆疊佔據的大覆蓋區(例如，在平行於基板301之表面的方向上)。A similar challenge also exists in forming the semiconductor device assembly shown in FIG. 3, where the individual modules of each group are stacked in opposite offset directions. In this regard, FIG. 3 shows a semiconductor device assembly 300, in which the shingled stack 310 of individual modules on the substrate 301 includes two sets of individual modules 304 of 302 and 303, which are shingled in opposite offset directions. The bonding wire 321 is electrically connected to the junction 320 on the substrate 301. As can be seen with reference to FIG. 3, at least some of the bonding wires 321 of the individual modules 304 of the first group 302 are located below the overhanging area 311 of the second group 303, and therefore may need to be stacked on the individual modules 304 of the second group 303 The bonding wires of the individual modules of the first group are formed before above the first group 302. Therefore, the disadvantages of this configuration also include the large footprint (for example, in a direction parallel to the surface of the substrate 301) occupied by the stack of tiles of the individual modules 304 due to the tiled configuration.

本揭示之一個態樣提供一種半導體裝置總成，其中該半導體裝置總成包含：基板，該基板包括複數個外部連接；第一個別模組，該第一個別模組包含第一側；第二側，該第二側與該第一側相對；複數個晶粒，該複數個晶粒位於該第一側與該第二側之間；以及第一接合襯墊，該第一接合襯墊位於該第二側上，該第一個別模組設置在該基板上，使得該第一個別模組之該第一側朝向該基板，該第一個別模組藉由該第一接合襯墊電耦接至該複數個外部連接的一個外部連接；以及第二個別模組，該第二個別模組包含第一側；第二側，該第二側與該第一側相對；複數個晶粒，該複數個晶粒位於該第一側與該第二側之間；以及複數個側向側，該複數個側向側在該第一側與該第二側之間延伸，該第二個別模組設置在該第一個別模組上方，使得該第二個別模組之該第一側朝向該第一個別模組之該第二側；其中該第二個別模組之第一側向側包括第一懸垂部分及第一凹槽；該第一接合襯墊與該第二個別模組之該第一凹槽垂直對準。One aspect of the present disclosure provides a semiconductor device assembly, wherein the semiconductor device assembly includes: a substrate including a plurality of external connections; a first individual module, the first individual module including a first side; and a second individual module. Side, the second side is opposite to the first side; a plurality of dies, the plurality of dies are located between the first side and the second side; and a first bonding pad, the first bonding pad is located On the second side, the first individual module is disposed on the substrate such that the first side of the first individual module faces the substrate, and the first individual module is electrically coupled by the first bonding pad An external connection connected to the plurality of external connections; and a second individual module, the second individual module including a first side; a second side, the second side opposite to the first side; a plurality of dies, The plurality of dies are located between the first side and the second side; and a plurality of lateral sides, the plurality of lateral sides extend between the first side and the second side, the second individual mold The group is arranged above the first individual module so that the first side of the second individual module faces the second side of the first individual module; wherein the first lateral side of the second individual module includes The first overhanging portion and the first groove; the first bonding pad is vertically aligned with the first groove of the second individual module.

本揭示之另一態樣提供一種半導體裝置總成，其中該半導體裝置總成包含：基板，該基板包含頂面及位於該頂面上的複數個接合點；個別模組之堆疊，該個別模組之堆疊設置在該基板上方且電耦接至該複數個接合點中之至少一者，每個該個別模組包含位於其中之複數個晶粒；以及密封劑，該密封劑至少部分地封裝該基板及該個別模組之堆疊；其中當在垂直於該基板之該頂面的平面中觀察時，該個別模組之堆疊的上部個別模組之周邊的至少一部分具有階梯狀輪廓。Another aspect of the present disclosure provides a semiconductor device assembly, wherein the semiconductor device assembly includes: a substrate including a top surface and a plurality of joints on the top surface; a stack of individual modules, the individual modules The stack of groups is disposed above the substrate and electrically coupled to at least one of the plurality of bonding points, each of the individual modules includes a plurality of dies located therein; and a sealant, the sealant at least partially encapsulates The stack of the substrate and the individual module; wherein when viewed in a plane perpendicular to the top surface of the substrate, at least a part of the periphery of the upper individual module of the stack of the individual module has a stepped profile.

本揭示之另一態樣提供一種製造半導體裝置總成之方法，該方法包含：提供基板，該基板具有至少一個接合點；在該基板上堆疊複數個個別模組；在至少一個該等個別模組之周邊的至少一部分中形成階梯狀輪廓，使得至少一個個別模組之至少一個接合襯墊與另一個別模組之該階梯狀輪廓的凹槽垂直對準；將該至少一個接合襯墊引線接合至該基板的該至少一個接合點。Another aspect of the present disclosure provides a method of manufacturing a semiconductor device assembly. The method includes: providing a substrate, the substrate having at least one joint; stacking a plurality of individual modules on the substrate; A stepped profile is formed in at least a part of the periphery of the group, so that at least one bonding pad of at least one individual module is vertically aligned with the groove of the stepped profile of another individual module; the at least one bonding pad leads The at least one bonding point bonded to the substrate.

在下面之描述中，討論了許多具體細節，以提供對本技術之實施例的全面且可行描述。然而，相關領域之技術人員將認識到，本揭示可在沒有一或多個具體細節之情況下實施。在其他情形下，通常沒有展示(或沒有詳細描述)與半導體裝置相關聯之公知結構或操作，以避免模糊本技術之其他態樣。一般而言，應當理解，除了本文揭示之彼等具體實施例之外，各種其他裝置、系統及方法亦可在本技術之範疇內。In the following description, many specific details are discussed to provide a comprehensive and feasible description of the embodiments of the present technology. However, those skilled in the relevant art will recognize that the present disclosure can be implemented without one or more specific details. In other situations, generally known structures or operations associated with the semiconductor device are not shown (or not described in detail) to avoid obscuring other aspects of the technology. Generally speaking, it should be understood that in addition to the specific embodiments disclosed herein, various other devices, systems, and methods may also fall within the scope of the present technology.

如上所述，在半導體裝置總成中增加堆疊中之個別模組的數目帶來了製造挑戰，克服此等挑戰(例如，多次反覆堆疊及引線接合操作、改變模組至模組之間隔、寬範圍之高度等)之成本很高。因此，根據本技術之半導體裝置總成的幾個實施例可提供具有設計成克服此等挑戰之周邊輪廓的半導體裝置總成。As mentioned above, increasing the number of individual modules in the stack in a semiconductor device assembly brings manufacturing challenges to overcome these challenges (for example, multiple repeated stacking and wire bonding operations, changing the module-to-module interval, The cost of a wide range of heights, etc.) is very high. Therefore, several embodiments of the semiconductor device assembly according to the present technology can provide a semiconductor device assembly having a peripheral profile designed to overcome these challenges.

就此而言，本技術之幾個實施例針對包括基板之半導體裝置總成，該基板包括複數個外部連接。第一個別模組可連接至基板及/或堆疊在基板上。第一個別模組可包括第一側、與第一側相對之第二側以及位於第二側上之第一接合襯墊。第一個別模組可設置在基板上，使得第一個別模組之第一側朝向基板。在一些實施例中，第一個別模組藉由第一接合襯墊電耦接至基板之外部連接。總成可包括第二個別模組，該第二個別模組具有第一側、與第一側相對之第二側以及在第一側與第二側之間延伸的複數個側向側。在一些實施例中，第二個別模組設置在第一個別模組上方，使得第二個別模組之第一側朝向第一個別模組之第二側。在一些實施例中，第二個別模組之第一側向側包括形成第一懸垂部分及第一凹槽之第一階梯。在一些實施例中，第一接合襯墊與第二個別模組之第一凹槽垂直對準。In this regard, several embodiments of the present technology are directed to a semiconductor device assembly including a substrate including a plurality of external connections. The first individual modules can be connected to the substrate and/or stacked on the substrate. The first individual module may include a first side, a second side opposite to the first side, and a first bonding pad on the second side. The first individual module can be arranged on the substrate such that the first side of the first individual module faces the substrate. In some embodiments, the first individual module is electrically coupled to the external connection of the substrate through the first bonding pad. The assembly may include a second individual module having a first side, a second side opposite to the first side, and a plurality of lateral sides extending between the first side and the second side. In some embodiments, the second individual module is disposed above the first individual module such that the first side of the second individual module faces the second side of the first individual module. In some embodiments, the first lateral side of the second individual module includes a first step forming a first overhanging portion and a first groove. In some embodiments, the first bonding pad is vertically aligned with the first groove of the second individual module.

個別模組總成之幾個實施例包括基板，該基板包含頂面及位於頂面上之複數個接合點。總成可包括個別模組之堆疊，該個別模組之堆疊設置在基板上方且電耦接至複數個接合點中之至少一者。在一些實施例中，總成包括至少部分地封裝基板及個別模組之堆疊的密封劑。在一些實施例中，當在垂直於基板之頂面的平面中觀察時，個別模組之堆疊的上部個別模組之周邊的至少一部分具有階梯狀輪廓。Several embodiments of individual module assemblies include a substrate including a top surface and a plurality of bonding points on the top surface. The assembly may include a stack of individual modules, the stack of individual modules being disposed above the substrate and electrically coupled to at least one of a plurality of bonding points. In some embodiments, the assembly includes an encapsulant that at least partially encapsulates the substrate and the stack of individual modules. In some embodiments, when viewed in a plane perpendicular to the top surface of the substrate, at least a part of the periphery of the upper individual module of the stack of individual modules has a stepped profile.

製造個別模組總成之方法可包括提供具有至少一個接合點之基板，以及在基板上堆疊複數個個別模組。個別模組之一或多者可包括由密封劑材料封裝之一或多個個晶粒。密封劑內之個別晶粒可堆疊及/或側向分佈(例如，在平行於基板之方向上)。在一些實施例中，方法包括在至少一個個別模組之周邊的至少一部分中形成階梯狀輪廓，使得至少一個個別模組之至少一個接合襯墊與另一個別模組之階梯狀輪廓的凹槽垂直對準及/或定位在該凹槽內。方法可包括將至少一個接合襯墊引線接合至基板之至少一個接合點。The method of manufacturing the individual module assembly may include providing a substrate with at least one bonding point, and stacking a plurality of individual modules on the substrate. One or more of the individual modules may include one or more dies encapsulated by an encapsulant material. The individual dies in the encapsulant can be stacked and/or distributed laterally (for example, in a direction parallel to the substrate). In some embodiments, the method includes forming a stepped profile in at least a portion of the periphery of at least one individual module, so that at least one of the at least one individual module engages with a groove of the stepped profile of another individual module Vertically aligned and/or positioned in the groove. The method may include wire bonding at least one bonding pad to at least one bonding point of the substrate.

下面描述半導體裝置之幾個實施例的具體細節。術語「半導體裝置」通常指包括半導體材料之固態裝置。例如，半導體裝置可包括個別模組、半導體基板、晶圓或自晶圓或基板分割之晶粒。貫穿本揭示內容，半導體裝置通常在個別模組之背景中描述；然而，半導體裝置並不限於個別模組。The specific details of several embodiments of the semiconductor device are described below. The term "semiconductor device" generally refers to solid-state devices that include semiconductor materials. For example, semiconductor devices may include individual modules, semiconductor substrates, wafers, or dies separated from wafers or substrates. Throughout this disclosure, semiconductor devices are generally described in the context of individual modules; however, semiconductor devices are not limited to individual modules.

術語「半導體裝置封裝」可指將一或多個半導體裝置接合至公共封裝中之配置。半導體封裝可包括部分地或完全地封裝至少一個半導體裝置之外殼或殼體。半導體裝置封裝亦可包括插入基板，該插入基板承載一或多個半導體裝置，且附接至或以其他方式接合至殼體中。術語「半導體裝置總成」可指一或多個半導體裝置、半導體裝置封裝及/或基板(例如，插入物、支撐物或其他合適基板)之總成。例如，半導體裝置總成可以離散封裝形式、條帶或矩陣形式及/或晶圓面板形式製造。如本文所使用，術語「垂直」、「側向」、「上部」及「下部」可指自圖中所示之取向來看，半導體裝置或裝置總成中之特徵的相對方向或位置。例如，「上部」或「最上部」可分別指比另一特徵或相同特徵之部分更靠近或最靠近頁面之頂部的特徵。然而，此等術語應被廣義地解釋為包括具有其他取向之半導體裝置，諸如倒置或傾斜取向，其中頂部/底部、上方/下方、上面/下面、上部/下部及左/右可依據取向互換。The term "semiconductor device package" can refer to a configuration in which one or more semiconductor devices are bonded into a common package. The semiconductor package may include a housing or housing that partially or completely encapsulates at least one semiconductor device. The semiconductor device package may also include an interposer substrate that carries one or more semiconductor devices and is attached or otherwise bonded to the housing. The term "semiconductor device assembly" can refer to an assembly of one or more semiconductor devices, semiconductor device packages, and/or substrates (eg, interposers, supports, or other suitable substrates). For example, the semiconductor device assembly can be manufactured in discrete package form, strip or matrix form, and/or wafer panel form. As used herein, the terms "vertical", "lateral", "upper" and "lower" can refer to the relative direction or position of features in a semiconductor device or device assembly from the orientation shown in the figure. For example, "top" or "topmost" may refer to the feature closer to or closest to the top of the page than another feature or part of the same feature, respectively. However, these terms should be broadly interpreted to include semiconductor devices with other orientations, such as inverted or oblique orientations, where top/bottom, top/bottom, top/bottom, top/bottom, and left/right are interchangeable depending on the orientation.

圖4為根據本技術實施例之半導體裝置總成的簡化橫截面圖，該半導體裝置總成包括個別模組之堆疊。半導體裝置總成400包括基板401及至少部分被密封劑430圍繞之複數個個別模組404之堆疊。如參照圖4可看出，個別模組之堆疊包括四個個別模組404。堆疊之最底部的個別模組直接耦接至基板401，且除了最底部的之外，堆疊之每個個別模組404藉由晶粒附著膜或其他附著膜412在約相同之方向上自其下面的個別模組404偏移約相同之距離。4 is a simplified cross-sectional view of a semiconductor device assembly according to an embodiment of the present technology. The semiconductor device assembly includes a stack of individual modules. The semiconductor device assembly 400 includes a substrate 401 and a stack of a plurality of individual modules 404 at least partially surrounded by an encapsulant 430. As can be seen with reference to FIG. 4, the stack of individual modules includes four individual modules 404. The individual modules at the bottom of the stack are directly coupled to the substrate 401, and except for the bottom module, each individual module 404 in the stack is separated from it in about the same direction by a die attach film or other attach film 412. The individual modules 404 below are offset by approximately the same distance.

一或多個個別模組404包括連接至包覆模製部分418之基板部分406。基板部分406可包括主動電路(例如，提供諸如儲存單元、處理器電路及/或成像器裝置之功能特徵)及/或被動特徵(例如，電容器、電阻器等)以及電連接至電路之接合襯墊408。包覆模製部分418可封裝或部分地封裝基板部分406之一或多個特徵(例如，主動或被動特徵)。在一些實施例中，包覆模製部分418由諸如樹脂、塑膠、矽、氧化物、聚合物、介電材料或其他合適材料之密封劑材料製成。包覆模製部分418可形成為單個結構(例如，整個包覆模製部分418可以同時模製或以其他方式形成)，或形成為藉由多個模製/形成步驟彼此連接之多個結構。包覆模製部分418可封裝一或多個個別晶粒。封裝在包覆模製部分418中之晶粒可堆疊配置及/或可側向分佈在基板部分上。在一些實施例中，每個個別模組404之總高度H3大於個別晶粒之典型高度。例如，個別模組404之高度H3可為包覆模製部分418內之個別晶粒的高度之至少三倍、至少四倍、至少八倍及/或至少二十倍。包覆模製部分418可封裝或至少部分地封裝其他離散部件。此類離散部件可包括主動或被動部件，諸如但不限於電容器、電阻器、電感器、控制器晶粒、矽間隔物等。在所示實施例中，每個個別模組404之基板部分406定位在個別模組404之包覆模製部分418上面。One or more individual modules 404 include a substrate portion 406 connected to an overmolded portion 418. The substrate portion 406 may include active circuits (for example, providing functional features such as storage units, processor circuits, and/or imager devices) and/or passive features (for example, capacitors, resistors, etc.) and bonding pads that are electrically connected to the circuit.垫408. The overmolded portion 418 may encapsulate or partially encapsulate one or more features of the substrate portion 406 (eg, active or passive features). In some embodiments, the overmolded portion 418 is made of a sealant material such as resin, plastic, silicon, oxide, polymer, dielectric material, or other suitable materials. The overmolded portion 418 may be formed as a single structure (for example, the entire overmolded portion 418 may be molded at the same time or formed in other ways), or formed as multiple structures connected to each other by multiple molding/forming steps . The overmolded portion 418 can encapsulate one or more individual dies. The die encapsulated in the overmolding part 418 may be stacked and/or may be laterally distributed on the substrate part. In some embodiments, the total height H3 of each individual module 404 is greater than the typical height of the individual die. For example, the height H3 of the individual module 404 may be at least three times, at least four times, at least eight times, and/or at least twenty times the height of the individual die in the overmolded portion 418. The overmolded portion 418 may encapsulate or at least partially encapsulate other discrete components. Such discrete components may include active or passive components, such as, but not limited to, capacitors, resistors, inductors, controller dies, silicon spacers, and the like. In the illustrated embodiment, the substrate portion 406 of each individual module 404 is positioned above the overmolded portion 418 of the individual module 404.

半導體裝置總成400進一步包括將每個個別模組404連接至基板401之焊線421。更具體地，堆疊中之每個個別模組404連接至基板401上的一或多個接合點420。在一些實施例中，每個個別模組404之接合襯墊408藉由焊線421直接連接至基板401上的一或多個接合點420。在一些其他實施例中，接合襯墊408與兩個或更多個個別模組404彼此串聯連接。在一些此類實施例中，單個焊線421連接至接合點420(例如，與連接至圖4中所示之接合點420的複數個焊線421形成對比)。The semiconductor device assembly 400 further includes a bonding wire 421 connecting each individual module 404 to the substrate 401. More specifically, each individual module 404 in the stack is connected to one or more bonding points 420 on the substrate 401. In some embodiments, the bonding pads 408 of each individual module 404 are directly connected to one or more bonding points 420 on the substrate 401 by bonding wires 421. In some other embodiments, the bonding pad 408 and two or more individual modules 404 are connected to each other in series. In some such embodiments, a single bond wire 421 is connected to the junction 420 (e.g., in contrast to a plurality of bond wires 421 connected to the junction 420 shown in FIG. 4).

在一些實施例中，當垂直於焊線421所附接之各部接合襯墊408量測時，焊線421之高度大於用於將個別模組404彼此連接之晶粒附著膜412或其他黏合劑的厚度。例如，焊線421之高度可為晶粒附著膜412之厚度的至少110%、至少130%、至少150%、至少175%、至少200%及/或至少300%。In some embodiments, when measured perpendicular to the bonding pads 408 attached to the bonding wires 421, the height of the bonding wires 421 is greater than the die attach film 412 or other adhesives used to connect the individual modules 404 to each other thickness of. For example, the height of the bonding wire 421 may be at least 110%, at least 130%, at least 150%, at least 175%, at least 200%, and/or at least 300% of the thickness of the die attach film 412.

根據本主題技術之一個態樣，一或多個個別模組404在半導體裝置440之第一端440a及第二端440b中之一或多者上包括階梯狀幾何形狀。更具體地，個別模組404之階梯狀幾何形狀可包括上部懸垂部分432及下部凹槽部分434。下部凹槽434可在平行於基板之方向上相對於懸垂部分432之側向邊緣凹陷。在一些實施例中，並非所有個別模組404皆包括階梯狀部分。在一些實施例中，半導體堆疊之每個個別模組404包括在個別模組404之至少一側/端上的階梯狀部分。According to one aspect of the subject technology, the one or more individual modules 404 include stepped geometric shapes on one or more of the first end 440a and the second end 440b of the semiconductor device 440. More specifically, the stepped geometry of the individual module 404 may include an upper overhanging portion 432 and a lower recessed portion 434. The lower groove 434 may be recessed relative to the lateral edge of the overhanging portion 432 in a direction parallel to the substrate. In some embodiments, not all individual modules 404 include stepped portions. In some embodiments, each individual module 404 of the semiconductor stack includes a stepped portion on at least one side/end of the individual module 404.

個別模組404之階梯狀部分可藉由模製製程(例如，注射模製或其他模製製程)、使用研磨輪、藉由切割工具或藉由一些其他製造方式來形成。例如，研磨輪可用於自包覆模製部分418或自個別模組404之一些其他部分移除材料(例如，以形成凹槽434)。較佳地，個別模組404之階梯狀部分之懸垂部分432定位在凹槽434上面。然而，在一些實施例中，個別模組404之一或多個階梯狀部分具有定位在凹槽下方的下部懸垂部分。在一些實施例中，一或多個接合襯墊408定位在凹槽434內及/或與凹槽垂直對準(例如，在垂直於基板401及/或垂直於個別模組404之第一側444的方向上對準)，各部個別模組404之凹槽直接定位在其中/其上形成有各部接合襯墊408之個別模組上面。例如，一或多個接合襯墊408可定位在接合襯墊408上面的個別模組404之凹槽部分434的外部側向邊緣與內部側壁之間。The stepped portion of the individual module 404 can be formed by a molding process (for example, injection molding or other molding processes), using a grinding wheel, by a cutting tool, or by some other manufacturing method. For example, an abrasive wheel can be used to remove material from the overmolded portion 418 or from some other portion of the individual module 404 (eg, to form the groove 434). Preferably, the overhanging portion 432 of the stepped portion of the individual module 404 is positioned on the groove 434. However, in some embodiments, one or more of the stepped portions of the individual modules 404 has a lower overhanging portion positioned below the groove. In some embodiments, one or more bonding pads 408 are positioned in the groove 434 and/or vertically aligned with the groove (eg, on the first side perpendicular to the substrate 401 and/or perpendicular to the individual module 404 444), the grooves of the individual modules 404 are directly positioned on the individual modules in/on which the bonding pads 408 are formed. For example, one or more bonding pads 408 may be positioned between the outer lateral edge and the inner sidewall of the groove portion 434 of the individual module 404 above the bonding pad 408.

圖5展示了在第一端440a及第二端440b上皆具有階梯狀部分的個別模組404中之一者的底部平面圖。在個別模組404之第一端440a及第二端440b上皆包括階梯狀部分可導致個別模組404具有第一側444(例如，下側)，其寬度W3小於個別模組404之第二側446(例如，如圖4中所示之上側)的寬度W4。在一些實施例中，個別模組404之第一側444之寬度W3在個別模組404之第二側446的寬度W4之大約70%-85%、大約75%-95%、大約80%-90%及/或大約65%-80%之間。在一些實施例中，個別模組404之第一側444的寬度W3大約為個別模組404之第二側446的寬度W4之85%。當平行於寬度W3、W4量測時，在個別模組404之端440a、440b處的各部凹槽部分434之深度D1、D2可彼此相等。在一些實施例中，深度D1、D2中之一者大於深度D2、D1中之另一者。FIG. 5 shows a bottom plan view of one of the individual modules 404 having stepped portions on both the first end 440a and the second end 440b. Including stepped portions on both the first end 440a and the second end 440b of the individual module 404 may result in the individual module 404 having a first side 444 (for example, the lower side), the width W3 of which is smaller than the second side of the individual module 404 The width W4 of the side 446 (e.g., the upper side as shown in FIG. 4). In some embodiments, the width W3 of the first side 444 of the individual module 404 is about 70%-85%, about 75%-95%, or about 80% of the width W4 of the second side 446 of the individual module 404- 90% and/or approximately 65%-80%. In some embodiments, the width W3 of the first side 444 of the individual module 404 is approximately 85% of the width W4 of the second side 446 of the individual module 404. When measured parallel to the widths W3 and W4, the depths D1 and D2 of the groove portions 434 at the ends 440a, 440b of the individual modules 404 can be equal to each other. In some embodiments, one of the depths D1, D2 is greater than the other of the depths D2, D1.

再參照圖4，凹槽部分434之高度H2(垂直於基板401量測)在個別模組404之總高度H3的大約10%-60%、大約20%-65%、大約30%-55%、大約50%-70%及/或大約25%-45%之間。較佳地，凹槽部分434之高度H2足以允許出於引線接合之目的而接近定位在凹槽部分434內之個別模組404的接合襯墊408。較佳地，晶粒附著膜412具有與個別模組404之第一表面444相同的尺寸及形狀。在一些此類實施例中，晶粒附著膜412藉由將懸垂部分432與定位在凹槽部分434下面的個別模組404或基板401隔開來增加凹槽部分434之高度。4 again, the height H2 of the groove portion 434 (measured perpendicular to the substrate 401) is about 10%-60%, about 20%-65%, and about 30%-55% of the total height H3 of the individual modules 404 , About 50%-70% and/or about 25%-45%. Preferably, the height H2 of the groove portion 434 is sufficient to allow access to the bonding pads 408 of the individual modules 404 positioned in the groove portion 434 for wire bonding purposes. Preferably, the die attach film 412 has the same size and shape as the first surface 444 of the individual module 404. In some such embodiments, the die attach film 412 increases the height of the recessed portion 434 by separating the overhanging portion 432 from the individual module 404 or the substrate 401 positioned under the recessed portion 434.

根據本主題技術之一個態樣，與使用間隔帶或疊瓦式配置之總成相比，在個別模組404之外部邊緣上使用階梯狀特徵可減小半導體裝置總成400的整體高度、寬度及/或深度。減小半導體裝置總成之尺寸可允許在給定應用內更緊湊且更有效地分佈總成。限制間隔帶之使用亦可降低半導體裝置總成404之製造成本。According to one aspect of the subject technology, the use of stepped features on the outer edge of the individual module 404 can reduce the overall height and width of the semiconductor device assembly 400 compared to an assembly using a spacer or shingle configuration. And/or depth. Reducing the size of the semiconductor device assembly may allow for a more compact and more efficient distribution of the assembly within a given application. Restricting the use of spacing bands can also reduce the manufacturing cost of the semiconductor device assembly 404.

圖6展示了半導體裝置總成500之實施例，其具有許多與上面描述之半導體裝置總成400相似或一致的特徵。相似之附圖標記用於標識總成400與500之間的相似特徵。例如，兩個總成皆可包括基板401、501、晶粒附著膜412、512及焊線421、521。FIG. 6 shows an embodiment of the semiconductor device assembly 500, which has many similar or identical features to the semiconductor device assembly 400 described above. Similar reference numerals are used to identify similar features between assemblies 400 and 500. For example, both assemblies may include substrates 401, 501, die attach films 412, 512, and bonding wires 421, 521.

雖然上文關於半導體裝置總成400描述了階梯狀特徵，但由階梯狀輪廓提供之許多或所有優勢皆可藉由圓角狀輪廓來實現。例如，如圖6中所示，一或多個端540a、540b可包括圓角狀輪廓，該圓角狀輪廓導致懸垂部分532及下部凹槽534。例如，圓角狀輪廓可在一或多個個別模組504之包覆模製部分518中形成。Although the stepped feature is described above with respect to the semiconductor device assembly 400, many or all of the advantages provided by the stepped profile can be realized by the rounded profile. For example, as shown in FIG. 6, one or more ends 540 a, 540 b may include a rounded contour that results in the overhang 532 and the lower groove 534. For example, a rounded contour can be formed in the overmolded portion 518 of one or more individual modules 504.

個別模組504之下部凹槽534的高度H4可與個別模組404之下部凹槽434的高度H2類似或相同。類似地，個別模組504之總高度H5可與個別模組404之總高度H3類似或相同。當平行於基板501量測時，下部凹槽534之各部深度可與下部凹槽434之深度D1、D2類似或相同。在一些實施例中，總尺寸及圖5中所示尺寸與上文描述之尺寸之間的比率同樣適用於圖6中所示之個別模組504。The height H4 of the lower groove 534 of the individual module 504 may be similar to or the same as the height H2 of the lower groove 434 of the individual module 404. Similarly, the total height H5 of the individual module 504 may be similar or the same as the total height H3 of the individual module 404. When measured parallel to the substrate 501, the depth of each part of the lower groove 534 can be similar or the same as the depths D1 and D2 of the lower groove 434. In some embodiments, the overall dimensions and the ratio between the dimensions shown in FIG. 5 and the dimensions described above are also applicable to the individual modules 504 shown in FIG. 6.

下部凹槽534之曲率半徑可為恆定的或自下部凹槽534之上部端至凹槽534的下部端係可變的。較佳地，選擇下部凹槽534之曲率半徑、高度H6及深度，使得下部凹槽534之尺寸及形狀允許個別模組504之接合襯墊508與基板501之間容易引線接合。可實現其他凹槽形狀。例如，給定個別模組之凹槽可包括彎曲部分及平坦部分。在一些實施例中，凹槽之形狀可為自個別模組之側向邊緣延伸至該個別模組之第二(例如，下部)側的傾斜表面。The radius of curvature of the lower groove 534 may be constant or variable from the upper end of the lower groove 534 to the lower end of the groove 534. Preferably, the radius of curvature, height H6 and depth of the lower groove 534 are selected so that the size and shape of the lower groove 534 allow easy wire bonding between the bonding pad 508 of the individual module 504 and the substrate 501. Other groove shapes can be realized. For example, the groove of a given individual module may include a curved portion and a flat portion. In some embodiments, the shape of the groove may be an inclined surface extending from the lateral edge of the individual module to the second (eg, lower) side of the individual module.

圖7為展示製造半導體裝置總成之方法的流程圖。方法包括提供基板(方塊704)，在複數個個別模組之至少一端上形成懸垂及凹槽(方塊706)，且將個別模組堆疊至基板上(方塊708)。在個別模組之端的凹槽中形成懸垂可包括將個別模組模製成具有凹槽及懸垂之形狀，及/或將凹槽切割/研磨成個別模組。例如，一或多個個別模組之包覆模製部分可模製成階梯形狀或其他懸垂形狀。在一些實施例中，美國專利申請案第16/237,051號(於2018年12月31日提交，且標題為用於形成半導體切割/修整刀片之系統及方法(Systems and Methods for Forming Semiconductor Cutting/Trimming Blades)，其全部揭示內容藉由引用整體併入本文)中描述之研磨輪或切割刀片，可用於在半導體裝置中形成階梯狀、斜面狀、圓角狀及/或其他形狀之凹槽。較佳地，個別模組垂直堆疊且彼此對準，使得當自上面觀察時，只有最頂部之個別模組可見。在一些實施例中，給定堆疊中之個別模組彼此對準，使得當自上面觀察時，每個個別模組佔據基本上相同的覆蓋區。方法進一步包括將個別模組引線接合至基板(方塊710)，此可在堆疊個別模組之後進行，且提供密封劑以至少部分地封裝基板及個別模組之堆疊(方塊712)。引線接合可在單次操作中進行，不受任何堆疊之干擾。在一些實施例中，製造半導體裝置總成之方法包括形成(例如，模製及/或切割)一或多個個別模組之包覆模製部分。FIG. 7 is a flowchart showing a method of manufacturing a semiconductor device assembly. The method includes providing a substrate (block 704), forming overhangs and grooves on at least one end of a plurality of individual modules (block 706), and stacking the individual modules on the substrate (block 708). Forming the overhangs in the grooves at the ends of the individual modules may include molding the individual modules into a shape having grooves and overhangs, and/or cutting/grinding the grooves into individual modules. For example, the overmolded parts of one or more individual modules can be molded into a stepped shape or other overhanging shapes. In some embodiments, U.S. Patent Application No. 16/237,051 (filed on December 31, 2018, and titled Systems and Methods for Forming Semiconductor Cutting/Trimming Blades) Blades), the entire disclosure of which is incorporated herein by reference in its entirety. The grinding wheel or cutting blade described in) can be used to form stepped, beveled, rounded and/or other shaped grooves in semiconductor devices. Preferably, the individual modules are stacked vertically and aligned with each other so that when viewed from above, only the individual modules at the top are visible. In some embodiments, the individual modules in a given stack are aligned with each other such that when viewed from above, each individual module occupies substantially the same footprint. The method further includes wire bonding the individual modules to the substrate (block 710), which may be performed after stacking the individual modules, and providing an encapsulant to at least partially encapsulate the substrate and the stack of the individual modules (block 712). Wire bonding can be performed in a single operation without any interference from stacking. In some embodiments, a method of manufacturing a semiconductor device assembly includes forming (eg, molding and/or cutting) one or more overmolded portions of individual modules.

在一些實施例中，方法不包括在個別模組之凹槽中形成懸垂，因為個別模組具有此類特徵。附加地，在一些實施例中，在將個別模組之堆疊定位至基板上之前，執行引線接合的一些部分。例如，個別模組之間的一或多個焊線可預先形成。方法可包括使用晶粒附著膜或其他膜或黏合劑將個別模組彼此附接。In some embodiments, the method does not include forming an overhang in the groove of the individual module because the individual module has such characteristics. Additionally, in some embodiments, some portions of wire bonding are performed before positioning the stack of individual modules on the substrate. For example, one or more bonding wires between individual modules can be formed in advance. Methods may include attaching individual modules to each other using die attach films or other films or adhesives.

具有上面描述之特徵(例如，參考圖4至圖8)的任意一個半導體裝置總成可被接合至無數更大及/或更複雜之系統中的任意一者中，其代表性實例為圖8中示意性展示之系統1000。系統1000可包括處理器1002、記憶體1004(例如，SRAM、DRAM、快閃記憶體及/或其他記憶體裝置)、輸入/輸出裝置1005及/或其他子系統或部件1008。上文描述之個別模組及個別模組總成可包括在圖8中所示之任意元件中。所得到之系統1000可被組態為執行多種合適之計算、處理、儲存、感測、成像及/或其他功能中之任意一種。因此，系統1000之代表性實例包括但不限於電腦及/或其他資料處理器，諸如桌上型電腦、膝上型電腦、網際網路器具、手持裝置(例如，掌上電腦、可穿戴電腦、蜂巢式或行動電話、個人數位助理、音樂播放器等)、平板電腦、多處理器系統、基於處理器或可程式化消費電子產品、網路電腦及小型電腦。系統1000之其他代表性實例包括燈、相機、車輛等。關於此等及其他實例，系統1000可容納在單個單元中或例如藉由通信網路分佈在多個互連之單元上。系統1000之部件可相應地包括本端及/或遠端記憶體儲存裝置以及多種合適之電腦可讀媒體中之任意一種。Any semiconductor device assembly having the features described above (for example, refer to FIGS. 4 to 8) can be joined to any one of countless larger and/or more complex systems, a representative example of which is shown in FIG. 8. System 1000 shown schematically in. The system 1000 may include a processor 1002, a memory 1004 (for example, SRAM, DRAM, flash memory, and/or other memory devices), an input/output device 1005, and/or other subsystems or components 1008. The individual modules and individual module assemblies described above can be included in any of the components shown in FIG. 8. The resulting system 1000 can be configured to perform any of a variety of suitable calculations, processing, storage, sensing, imaging, and/or other functions. Therefore, representative examples of the system 1000 include, but are not limited to, computers and/or other data processors, such as desktop computers, laptop computers, Internet appliances, handheld devices (for example, palmtop computers, wearable computers, cellular Mobile phones, personal digital assistants, music players, etc.), tablet computers, multi-processor systems, processor-based or programmable consumer electronics, network computers and small computers. Other representative examples of the system 1000 include lights, cameras, vehicles, and so on. Regarding these and other examples, the system 1000 can be housed in a single unit or distributed across multiple interconnected units, for example, via a communication network. The components of the system 1000 may correspondingly include a local and/or remote memory storage device and any one of a variety of suitable computer-readable media.

如上所述，將會理解，出於說明之目的，本文已經描述了本發明之具體實施例，但在不脫離本發明之範疇的情況下，可進行各種修改。因此，除了受所附申請專利範圍限制之外，本發明不受限制。As described above, it will be understood that, for illustrative purposes, specific embodiments of the present invention have been described herein, but various modifications can be made without departing from the scope of the present invention. Therefore, the present invention is not limited except by the scope of the attached patent application.

100:半導體裝置總成 101:基板 104:個別模組 105:間隔帶 108:接合襯墊 120:接合點 121:焊線 200:半導體裝置總成 201:基板 202:第一組 203:第二組 204:個別模組 205:晶粒附接材料層 210:個別模組之疊瓦堆疊 211:懸垂區域 220:接合點 221:焊線 300:半導體裝置總成 301:基板 302:第一組 303:第二組 304:個別模組 310:個別模組之疊瓦堆疊 311:懸垂區域 320:接合點 321:焊線 400:半導體裝置總成 401:基板 404:個別模組 406:基板部分 408:接合襯墊 412:晶粒附著膜或其他附著膜 418:包覆模製部分 420:接合點 421:焊線 430:密封劑 432:上部懸垂部分 434:下部凹槽部分 440:半導體裝置 440a:第一端 440b:第二端 444:第一側 446:第二側 500:半導體裝置總成 501:基板 504:個別模組 508:接合襯墊 512:晶粒附著膜 518:包覆模製部分 521:焊線 532:懸垂部分 534:下部凹槽 540a:端 540b:端 704:方塊 706:方塊 708:方塊 710:方塊 712:方塊 1000:系統 1002:處理器 1004:記憶體 1005:輸入/輸出裝置 1008:其他子系統或部件 D1:深度 D2:深度 H1:高度 H2:高度 H3:總高度 H4:高度 H5:總高度 H6:高度 W1:寬度 W2:寬度 W3:寬度 W4:寬度100: Semiconductor device assembly 101: substrate 104: Individual modules 105: Spacer 108: Bonding pad 120: Joint 121: Welding wire 200: Semiconductor device assembly 201: Substrate 202: first group 203: The second group 204: Individual modules 205: die attach material layer 210: Shingled stacking of individual modules 211: Overhanging Area 220: junction 221: Welding Wire 300: Semiconductor device assembly 301: Substrate 302: The first group 303: The second group 304: Individual modules 310: Shingled stacking of individual modules 311: Overhanging area 320: junction 321: Welding Wire 400: Semiconductor device assembly 401: substrate 404: Individual modules 406: Substrate part 408: Bonding pad 412: Die adhesion film or other adhesion film 418: Overmolded part 420: Joint 421: Welding Wire 430: Sealant 432: Upper overhanging part 434: Lower groove part 440: Semiconductor device 440a: first end 440b: second end 444: first side 446: second side 500: Semiconductor device assembly 501: substrate 504: Individual modules 508: Bonding pad 512: die attach film 518: Overmolded part 521: Welding Wire 532: Overhanging part 534: Lower groove 540a: end 540b: end 704: Block 706: Block 708: Block 710: Block 712: Block 1000: System 1002: processor 1004: memory 1005: input/output device 1008: other subsystems or components D1: depth D2: depth H1: height H2: height H3: total height H4: height H5: total height H6: height W1: width W2: width W3: width W4: width

圖1展示了半導體裝置總成，其包括由間隔帶隔開之個別模組之堆疊。Figure 1 shows a semiconductor device assembly that includes a stack of individual modules separated by spacer tapes.

圖2展示了半導體裝置總成，其包括個別模組之疊瓦堆疊。Figure 2 shows a semiconductor device assembly including a shingled stack of individual modules.

圖3展示了半導體裝置總成，其包括個別模組之疊瓦堆疊。Figure 3 shows the semiconductor device assembly, which includes a shingled stack of individual modules.

圖4展示了根據本技術實施例之半導體裝置總成的簡化橫截面圖，該半導體裝置總成包括具有階梯狀外部輪廓之個別模組的堆疊。FIG. 4 shows a simplified cross-sectional view of a semiconductor device assembly according to an embodiment of the present technology, the semiconductor device assembly including a stack of individual modules having a stepped outer profile.

圖5展示了圖4之半導體裝置總成的個別模組之底部平面圖。FIG. 5 shows a bottom plan view of individual modules of the semiconductor device assembly of FIG. 4. FIG.

圖6展示了根據本技術實施例之半導體裝置總成的簡化橫截面圖，該半導體裝置總成包括具有圓角狀外部輪廓之個別模組的堆疊。FIG. 6 shows a simplified cross-sectional view of a semiconductor device assembly according to an embodiment of the present technology. The semiconductor device assembly includes a stack of individual modules having rounded outer contours.

圖7為展示根據本技術之一個實施例的製造半導體裝置總成之方法的流程圖。FIG. 7 is a flowchart showing a method of manufacturing a semiconductor device assembly according to an embodiment of the present technology.

圖8為展示包括根據本技術實施例組態之半導體裝置總成的系統之示意圖。FIG. 8 is a schematic diagram showing a system including a semiconductor device assembly configured according to an embodiment of the present technology.

400:半導體裝置總成 400: Semiconductor device assembly

401:基板 401: substrate

404:個別模組 404: Individual modules

406:基板部分 406: Substrate part

408:接合襯墊 408: Bonding pad

412:晶粒附著膜或其他附著膜 412: Die adhesion film or other adhesion film

418:包覆模製部分 418: Overmolded part

420:接合點 420: Joint

421:焊線 421: Welding Wire

430:密封劑 430: Sealant

432:上部懸垂部分 432: Upper overhanging part

434:下部凹槽部分 434: Lower groove part

440a:第一端 440a: first end

440b:第二端 440b: second end

444:第一側 444: first side

446:第二側 446: second side

H2:高度 H2: height

H3:總高度 H3: total height

Claims (23)

一種半導體裝置總成，包含： 一基板，該基板包括複數個外部連接； 一第一個別模組，該第一個別模組包含- 一第一側； 一第二側，該第二側與該第一側相對； 複數個晶粒，該複數個晶粒位於該第一側與該第二側之間；以及 一第一接合襯墊，該第一接合襯墊位於該第二側上，該第一個別模組設置在該基板上，使得該第一個別模組之該第一側朝向該基板，該第一個別模組藉由該第一接合襯墊電耦接至該複數個外部連接之一外部連接；以及 一第二個別模組，該第二個別模組包含 一第一側； 一第二側，該第二側與該第一側相對； 複數個晶粒，該複數個晶粒位於該第一側與該第二側之間；以及 複數個側向側，該複數個側向側在該第一側與該第二側之間延伸，該第二個別模組設置在該第一個別模組上方，使得該第二個別模組之該第一側朝向該第一個別模組之該第二側； 其中 該第二個別模組之一第一側向側包括一第一懸垂部分及一第一凹槽； 該第一接合襯墊與該第二個別模組之該第一凹槽垂直對準。A semiconductor device assembly, including: A substrate, the substrate including a plurality of external connections; A first individual module, the first individual module contains- A first side A second side, the second side being opposite to the first side; A plurality of crystal grains, the plurality of crystal grains are located between the first side and the second side; and A first bonding pad, the first bonding pad is located on the second side, the first individual module is disposed on the substrate such that the first side of the first individual module faces the substrate, the first A separate module is electrically coupled to an external connection of the plurality of external connections through the first bonding pad; and A second individual module, the second individual module contains A first side A second side, the second side being opposite to the first side; A plurality of crystal grains, the plurality of crystal grains are located between the first side and the second side; and A plurality of lateral sides, the plurality of lateral sides extend between the first side and the second side, and the second individual module is disposed above the first individual module so that the second individual module The first side faces the second side of the first individual module; in A first lateral side of the second individual module includes a first overhanging portion and a first groove; The first bonding pad is vertically aligned with the first groove of the second individual module. 如請求項1之半導體裝置總成，其中該第一個別模組包括一第二接合襯墊，該第二個別模組之一第二側向側包括一第二懸垂部分及一第二凹槽，且該第二接合襯墊定位在該第二凹槽內。The semiconductor device assembly of claim 1, wherein the first individual module includes a second bonding pad, and a second lateral side of the second individual module includes a second overhanging portion and a second groove , And the second bonding pad is positioned in the second groove. 如請求項1之半導體裝置總成，其進一步包含一第三個別模組，該第三個別模組包含： 一第一側； 一第二側，該第二側與該第一側相對； 複數個晶粒，該複數個晶粒位於該第一側與該第二側之間；以及 複數個側向側，該複數個側向側在該第一側與該第二側之間延伸，該第三個別模組設置在該第二個別模組上方，使得該第三個別模組之該第一側朝向該第二個別模組之該第二側；且 其中 該第二個別模組包含位於該個別模組之該第二側上的一第三接合襯墊； 該第二個別模組藉由該第三接合襯墊電耦接至該基板之一外部連接； 該第三個別模組之一第三側向側包含一第三懸垂部分及一第三凹槽；且 該第三接合襯墊定位在該第三凹槽內。For example, the semiconductor device assembly of claim 1, which further includes a third individual module, and the third individual module includes: A first side A second side, the second side being opposite to the first side; A plurality of crystal grains, the plurality of crystal grains are located between the first side and the second side; and A plurality of lateral sides, the plurality of lateral sides extend between the first side and the second side, the third individual module is disposed above the second individual module, so that the third individual module The first side faces the second side of the second individual module; and in The second individual module includes a third bonding pad on the second side of the individual module; The second individual module is electrically coupled to an external connection of the substrate through the third bonding pad; A third lateral side of the third individual module includes a third overhanging portion and a third groove; and The third bonding pad is positioned in the third groove. 如請求項3之半導體裝置總成，其中該第一個別模組及該第二個別模組分別藉由該第一接合襯墊及該第二接合襯墊電耦接至該基板之一相同外部連接。For example, the semiconductor device assembly of claim 3, wherein the first individual module and the second individual module are electrically coupled to the same exterior of the substrate through the first bonding pad and the second bonding pad, respectively connect. 如請求項1之半導體裝置總成，其進一步包含位於該第一個別模組與該第二個別模組之間的一附著膜。Such as the semiconductor device assembly of claim 1, which further includes an adhesive film located between the first individual module and the second individual module. 如請求項1之半導體裝置總成，其中該第一個別模組之該第二側具有與該第二個別模組之該第二側相同的一形狀及尺寸，且其中當自垂直於該第二個別模組之該第二側的一視角觀察時，該第一個別模組及該第二個別模組之該等第二側對準。Such as the semiconductor device assembly of claim 1, wherein the second side of the first individual module has the same shape and size as the second side of the second individual module, and when it is perpendicular to the first side When the second side of the two individual modules is viewed from a viewing angle, the second sides of the first individual module and the second individual module are aligned. 如請求項1之半導體裝置總成，其中該第二個別模組之該第二側的尺寸小於該第一個別模組之該第一側的尺寸。The semiconductor device assembly of claim 1, wherein the size of the second side of the second individual module is smaller than the size of the first side of the first individual module. 如請求項1之半導體裝置總成，其中該第一個別模組及該第二個別模組具有相同之一尺寸及幾何形狀。For example, the semiconductor device assembly of claim 1, wherein the first individual module and the second individual module have the same size and geometric shape. 如請求項1之半導體裝置總成，其進一步包含一密封劑，該密封劑至少部分封裝該基板、該第一個別模組及該第二個別模組。According to claim 1, the semiconductor device assembly further includes a sealant at least partially encapsulating the substrate, the first individual module, and the second individual module. 如請求項1之半導體裝置總成，其中一接合線延伸至該第二個別模組之該第一凹槽中，以連接至該第一接合襯墊。According to the semiconductor device assembly of claim 1, one of the bonding wires extends into the first groove of the second individual module to be connected to the first bonding pad. 一種半導體裝置總成，包含： 一基板，該基板包含一頂面及位於該頂面上的複數個接合點； 一個別模組之堆疊，該個別模組之堆疊設置在該基板上方且電耦接至該複數個接合點中之至少一者，每個該等個別模組包含位於其中之複數個晶粒；以及 一密封劑，該密封劑至少部分地封裝該基板及該個別模組之堆疊； 其中 當在垂直於該基板之該頂面的一平面中觀察時，該個別模組之堆疊的一上部個別模組之一周邊的至少一部分具有一階梯狀輪廓。A semiconductor device assembly, including: A substrate including a top surface and a plurality of joints on the top surface; A stack of individual modules, the stack of individual modules is disposed above the substrate and electrically coupled to at least one of the plurality of bonding points, each of the individual modules includes a plurality of dies located therein; as well as A sealant that at least partially encapsulates the substrate and the stack of the individual modules; in When viewed in a plane perpendicular to the top surface of the substrate, at least a part of a periphery of an upper individual module of the stack of individual modules has a stepped profile. 如請求項11之半導體裝置總成，其中該階梯狀輪廓形成一上部懸垂部分及一下部凹槽。The semiconductor device assembly of claim 11, wherein the stepped profile forms an upper overhanging portion and a lower groove. 如請求項12之半導體裝置總成，其中該上部個別模組下方之一個別模組包括一接合襯墊，該接合襯墊與該下部凹槽垂直對準。The semiconductor device assembly of claim 12, wherein an individual module below the upper individual module includes a bonding pad that is vertically aligned with the lower groove. 如請求項13之半導體裝置總成，其中該上部個別模組下方之該個別模組的一周邊之至少一部分具有一階梯狀輪廓，該階梯狀輪廓形成一上部懸垂部分及一下部凹槽。For example, the semiconductor device assembly of claim 13, wherein at least a part of a periphery of the individual module below the upper individual module has a stepped profile, and the stepped profile forms an upper overhanging portion and a lower groove. 如請求項11之半導體裝置總成，其中該個別模組之堆疊包括至少三個個別模組，且其中當在垂直於該基板之該頂面的一平面中觀察時，該至少三個個別模組中之每一者的該周邊之一部分具有一階梯狀輪廓。The semiconductor device assembly of claim 11, wherein the stack of the individual modules includes at least three individual modules, and wherein when viewed in a plane perpendicular to the top surface of the substrate, the at least three individual modules A portion of the periphery of each of the groups has a stepped profile. 如請求項15之半導體裝置總成，其中該個別模組之堆疊中之每個個別模組包括一模組基板及一模組包覆模製，該模組包覆模製連接至該模組基板之一下表面，且其中該階梯狀輪廓形成在該模組包覆模製中。For example, the semiconductor device assembly of claim 15, wherein each individual module in the stack of the individual modules includes a module substrate and a module overmolding, and the module overmolding is connected to the module A lower surface of the substrate, and the stepped contour is formed in the overmolding of the module. 如請求項16之半導體裝置總成，其中該個別模組之堆疊中之每個個別模組包括複數個個別晶粒，該複數個個別晶粒封裝在該模組包覆模製中。For example, the semiconductor device assembly of claim 16, wherein each individual module in the stack of the individual modules includes a plurality of individual dies, and the plurality of individual dies are packaged in the module overmolding. 一種製造一半導體裝置總成之方法，該方法包含： 提供一基板，該基板具有至少一個接合點； 在該基板上堆疊複數個個別模組； 在至少一個該等個別模組之周邊的至少一部分中形成一階梯狀輪廓，使得至少一個個別模組之至少一個接合襯墊與另一個別模組之該階梯狀輪廓的一凹槽垂直對準； 將該至少一個接合襯墊引線接合至該基板之該至少一個接合點。A method of manufacturing a semiconductor device assembly, the method comprising: Providing a substrate, the substrate having at least one bonding point; Stack a plurality of individual modules on the substrate; A stepped profile is formed in at least a part of the periphery of at least one of the individual modules, so that at least one bonding pad of at least one individual module is vertically aligned with a groove of the stepped profile of another individual module ； Wire bonding the at least one bonding pad to the at least one bonding point of the substrate. 如請求項18之方法，其進一步包含將該基板之至少一部分與複數個個別模組封裝在一密封劑中。The method of claim 18, further comprising encapsulating at least a part of the substrate and a plurality of individual modules in an encapsulant. 如請求項18之方法，其中形成一階梯狀輪廓包含：在一階梯狀模具中模製至少一個個別模組之一部分。The method of claim 18, wherein forming a stepped profile includes: molding a part of at least one individual module in a stepped mold. 如請求項18之方法，其中形成一階梯狀輪廓包含：使用一切割工具來切掉一個別模組之該周邊的一部分。Such as the method of claim 18, wherein forming a stepped contour includes: using a cutting tool to cut off a part of the periphery of a separate module. 如請求項18之方法，其中在至少一個該等個別模組之該周邊的至少一部分中形成一階梯狀輪廓包含：在該至少一個個別模組之整個周邊中形成該階梯狀輪廓。The method of claim 18, wherein forming a stepped contour in at least a part of the periphery of at least one of the individual modules includes: forming the stepped contour in the entire periphery of the at least one individual module. 如請求項18之方法，其中形成一階梯狀輪廓包含：在一階梯狀模具中模製至少一個該等個別模組之一包覆模製部分。The method of claim 18, wherein forming a stepped profile includes: molding at least one overmolded part of one of the individual modules in a stepped mold.
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