TW202129664A - Composite electric circuit protection device characterized in that the composite electric circuit protection device has excellent tolerance and reliability and in the presence of overcurrent and overvoltage, the PTC component can protect the voltage-dependent resistor from burning - Google Patents

Composite electric circuit protection device characterized in that the composite electric circuit protection device has excellent tolerance and reliability and in the presence of overcurrent and overvoltage, the PTC component can protect the voltage-dependent resistor from burning Download PDF

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TW202129664A
TW202129664A TW109101887A TW109101887A TW202129664A TW 202129664 A TW202129664 A TW 202129664A TW 109101887 A TW109101887 A TW 109101887A TW 109101887 A TW109101887 A TW 109101887A TW 202129664 A TW202129664 A TW 202129664A
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varistor
protection device
circuit protection
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voltage
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TWI816013B (en
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陳繼聖
江長鴻
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富致科技股份有限公司
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Abstract

Disclosed is a composite electric circuit protection device including a positive temperature coefficient (PTC) component, a voltage-dependent resistor, a first conductive lead and a second conductive lead. The PTC component includes a PTC layer, a first electrode layer and a second electrode layer. The PTC layer is provided with two opposite surfaces. The first electrode layer and the second electrode layer are respectively disposed on the two opposite surfaces of the PTC layer. The voltage-dependent resistor is connected to the second electrode layer. The first conductive lead is connected to the first electrode layer, and the second conductive lead is connected to the voltage-dependent resistor. The PTC component is provided with a rated voltage that is between 40% and 200% of the voltage-dependent voltage measured by the voltage-dependent resistor at 1 mA. The present composite electric circuit protection device has excellent tolerance. In the presence of overcurrent and overvoltage, the PTC component can protect the voltage-dependent resistor from burning.

Description

複合式電路保護裝置Composite circuit protection device

本發明是有關於一種複合式電路保護裝置,特別是指一種包含一正溫度係數(positive temperature coefficient, PTC)元件其額定電壓介於40%至200%一壓敏電阻器(voltage-dependent resistor, VDR,或varistor)在1 mA下量測的壓敏電壓的複合式電路保護裝置。The present invention relates to a composite circuit protection device, in particular to a voltage-dependent resistor (voltage-dependent resistor, VDR, or varistor) is a composite circuit protection device for varistor voltage measured at 1 mA.

美國專利US 8,508,328 B1記載一種插入式的聚合物正溫度係數(polymer positive temperature coefficient, PPTC)過電流(over-current)保護裝置,參閱圖1,該PPTC過電流保護裝置包含兩個電極30、一焊料(solder material)、分別與該等電極30連接的導電引線50, 60,及層壓在該等電極30間的PTC聚合物基材20。該PTC聚合物基材20上形成一孔洞40,該孔洞40具有能容納該PTC聚合物基材20在溫度升高時之熱膨脹的有效體積。United States Patent US 8,508,328 B1 describes a plug-in polymer positive temperature coefficient (PPTC) over-current (PPTC) over-current protection device. See Figure 1. The PPTC over-current protection device includes two electrodes 30, one Solder material, conductive leads 50, 60 respectively connected to the electrodes 30, and a PTC polymer substrate 20 laminated between the electrodes 30. A hole 40 is formed in the PTC polymer substrate 20, and the hole 40 has an effective volume capable of accommodating the thermal expansion of the PTC polymer substrate 20 when the temperature rises.

電氣特性[例如工作電流(operating current)和高壓突波耐受性(high-voltage surge endurability)]是影響在PPTC過電流保護裝置中發生電力突波(power surge)的重要因素。當通過增加該PTC聚合物基材20的厚度或面積來增加該PPTC過電流保護裝置的工作電流時,其更容易受到電力突波的損害。另一方面,當通過減少該PTC聚合物基材20的厚度或面積來增加該PPTC過電流保護裝置的高壓耐受性時,該PPTC過電流保護裝置也未必較不易受到電力突波的損害。Electrical characteristics [such as operating current and high-voltage surge endurability] are important factors that affect the occurrence of power surges in PPTC overcurrent protection devices. When the working current of the PPTC overcurrent protection device is increased by increasing the thickness or area of the PTC polymer substrate 20, it is more susceptible to damage from power surges. On the other hand, when the high voltage tolerance of the PPTC overcurrent protection device is increased by reducing the thickness or area of the PTC polymer substrate 20, the PPTC overcurrent protection device may not be less susceptible to damage from power surges.

雖然一壓敏電阻器(voltage-dependent resistor, VDR)可與該PPTC過電流保護裝置結合以對於組合得到的複合式電路保護裝置賦予過電流及過電壓(over-voltage)保護,但是VDR仍只能短暫承受電力突波(例如0.001秒)。也就是說,若突波時間超過一截止時間區間,VDR即會因為過電流或過電壓而燒燬或損壞,造成複合式電路保護裝置永久喪失功能。Although a voltage-dependent resistor (VDR) can be combined with the PPTC over-current protection device to provide over-current and over-voltage (over-voltage) protection to the combined composite circuit protection device, the VDR is still only Can withstand short-term power surges (for example, 0.001 seconds). In other words, if the surge time exceeds a cut-off time interval, the VDR will be burned or damaged due to overcurrent or overvoltage, causing the composite circuit protection device to permanently lose its function.

因此,本發明之目的,即在提供一種複合式電路保護裝置,可以克服上述先前技術的至少一個缺點。Therefore, the purpose of the present invention is to provide a composite circuit protection device that can overcome at least one of the above-mentioned shortcomings of the prior art.

於是,本發明的複合式電路保護裝置包含一正溫度係數(PTC)元件、一壓敏電阻器、一第一導電引線及一第二導電引線。該PTC元件包括一PTC層、第一電極層及第二電極層,該PTC層具有兩個相反表面,該第一電極層及該第二電極層分別設置在該PTC層的兩個相反表面。該壓敏電阻器連接於該第二電極層。該第一導電引線連結於該第一電極層。該第二導電引線連結於該壓敏電阻器。該PTC元件具有一額定電壓(rated voltage),該額定電壓介於40%至200%該壓敏電阻器在1 mA下量測的壓敏電壓(varistor voltage)。Therefore, the composite circuit protection device of the present invention includes a positive temperature coefficient (PTC) element, a varistor, a first conductive lead, and a second conductive lead. The PTC element includes a PTC layer, a first electrode layer and a second electrode layer. The PTC layer has two opposite surfaces. The first electrode layer and the second electrode layer are respectively disposed on the two opposite surfaces of the PTC layer. The varistor is connected to the second electrode layer. The first conductive lead is connected to the first electrode layer. The second conductive lead is connected to the varistor. The PTC element has a rated voltage, and the rated voltage is between 40% and 200% of the varistor voltage measured by the varistor at 1 mA.

本發明之功效在於:本發明複合式電路保護裝置具有優異的耐受性及可靠性,在過電流及過電壓存在下,該PTC元件可保護該壓敏電阻器免於燒燬。The effect of the present invention is that the composite circuit protection device of the present invention has excellent tolerance and reliability. In the presence of overcurrent and overvoltage, the PTC element can protect the varistor from burning.

在本發明被詳細描述之前,應當注意在以下的說明內容中,類似的元件是以相同的編號來表示。Before the present invention is described in detail, it should be noted that in the following description, similar elements are denoted by the same numbers.

參閱圖2及圖3,本發明的複合式電路保護裝置之第一實施例包含一正溫度係數(PTC)元件2、一壓敏電阻器3、一第一導電引線4及一第二導電引線5。2 and 3, the first embodiment of the composite circuit protection device of the present invention includes a positive temperature coefficient (PTC) element 2, a varistor 3, a first conductive lead 4, and a second conductive lead 5.

該PTC元件2包括一PTC層21、第一電極層22及第二電極層23,該PTC層21具有兩個相反表面211,該第一電極層22及該第二電極層23分別設置在該PTC層21的兩個相反表面211。The PTC element 2 includes a PTC layer 21, a first electrode layer 22, and a second electrode layer 23. The PTC layer 21 has two opposite surfaces 211. The first electrode layer 22 and the second electrode layer 23 are respectively disposed on the Two opposite surfaces 211 of the PTC layer 21.

該壓敏電阻器3藉由一焊料連接於該第二電極層23。The varistor 3 is connected to the second electrode layer 23 by a solder.

該第一導電引線4連結於該第一電極層22。該第二導電引線5連結於該壓敏電阻器3。The first conductive lead 4 is connected to the first electrode layer 22. The second conductive lead 5 is connected to the varistor 3.

該PTC元件2具有一額定電壓,該額定電壓介於40%至200%該壓敏電阻器3在1 mA下量測的壓敏電壓(varistor voltage)。在本發明的某些具體實施例中,該PTC元件2具有的額定電壓介於45%至100%該壓敏電阻器3在1 mA下量測的壓敏電壓。在本發明的某些具體實施例中,該PTC元件2具有的額定電壓介於45%至70%該壓敏電阻器3在1 mA下量測的壓敏電壓。The PTC element 2 has a rated voltage that is between 40% and 200% of the varistor voltage measured by the varistor 3 at 1 mA. In some embodiments of the present invention, the rated voltage of the PTC element 2 is between 45% and 100% of the varistor voltage measured by the varistor 3 at 1 mA. In some specific embodiments of the present invention, the rated voltage of the PTC element 2 is between 45% and 70% of the varistor voltage measured by the varistor 3 at 1 mA.

根據本發明,該PTC元件2處於一過電流及一大於該壓敏電阻器3的壓敏電壓之電壓下而在該壓敏電阻器3燒燬之前跳脫。換句話說,在該過電流及該大於該壓敏電阻器3的壓敏電壓之電壓存在下,該PTC元件2快速地跳脫至一高電阻狀態,以使該過電流被限制不流經該壓敏電阻器3,因此保護該壓敏電阻器3免於燒燬,該複合式電路保護裝置因而得以重複使用。According to the present invention, the PTC element 2 is under an overcurrent and a voltage greater than the varistor voltage of the varistor 3 and trips before the varistor 3 burns. In other words, in the presence of the overcurrent and the voltage greater than the varistor voltage of the varistor 3, the PTC element 2 quickly trips to a high resistance state, so that the overcurrent is restricted from flowing through The varistor 3 therefore protects the varistor 3 from burning, and the composite circuit protection device can be reused.

在本文中,術語“燒燬”、“冒火花”及“著火”可相互替換使用,且是指該壓敏電阻器失去功能,通常發生在180℃以上。In this article, the terms "burnt", "sparking" and "fire" can be used interchangeably and refer to the loss of function of the varistor, which usually occurs above 180°C.

在本發明的某些具體實施例中,該PTC元件2處於一大於0.1 A的過電流及一大於該壓敏電阻器3的壓敏電壓之電壓下而在1 μs至100 s之內跳脫。在本發明的某些具體實施例中,該PTC元件2處於一大於0.1 A的過電流及一大於該壓敏電阻器3的壓敏電壓之電壓下而在10 μs至10 s之內跳脫。在本發明的某些具體實施例中,該PTC元件2處於一大於0.1 A的過電流及一大於該壓敏電阻器3的壓敏電壓之電壓下而在0.1 ms至1 s之內跳脫。In some embodiments of the present invention, the PTC element 2 is at an overcurrent greater than 0.1 A and a voltage greater than the varistor voltage of the varistor 3 and trips within 1 μs to 100 s. . In some specific embodiments of the present invention, the PTC element 2 is under an overcurrent greater than 0.1 A and a voltage greater than the varistor voltage of the varistor 3 and trips within 10 μs to 10 s. . In some specific embodiments of the present invention, the PTC element 2 is under an overcurrent greater than 0.1 A and a voltage greater than the varistor voltage of the varistor 3 and trips within 0.1 ms to 1 s .

在本發明的某些具體實施例中,該PTC元件2處於一大於0.5 A的過電流及一大於該壓敏電阻器3的壓敏電壓之電壓下而在1 ms至10 s之內跳脫。在本發明的某些具體實施例中,該PTC元件2處於一大於0.5 A的過電流及一大於該壓敏電阻器3的壓敏電壓之電壓下而在1 ms至1 s之內跳脫。In some embodiments of the present invention, the PTC element 2 is under an overcurrent greater than 0.5 A and a voltage greater than the varistor voltage of the varistor 3 and trips within 1 ms to 10 s . In some specific embodiments of the present invention, the PTC element 2 is under an overcurrent greater than 0.5 A and a voltage greater than the varistor voltage of the varistor 3 and trips within 1 ms to 1 s .

在本發明的某些具體實施例中,該PTC元件2處於一大於10 A的過電流及一大於該壓敏電阻器3的壓敏電壓之電壓下而在1 ms至1 s之內跳脫。在本發明的某些具體實施例中,該PTC元件2處於一大於10 A的過電流及一大於該壓敏電阻器3的壓敏電壓之電壓下而在1 ms至0.1 s之內跳脫。In some embodiments of the present invention, the PTC element 2 is under an overcurrent greater than 10 A and a voltage greater than the varistor voltage of the varistor 3 and trips within 1 ms to 1 s . In some specific embodiments of the present invention, the PTC element 2 is under an overcurrent greater than 10 A and a voltage greater than the varistor voltage of the varistor 3 and trips within 1 ms to 0.1 s .

該PTC元件2可形成有一第一孔洞210。在本實施例中,該第一孔洞210形成在該PTC層21中。該PTC元件2的PTC層21具有一周緣212,該周緣212定義該PTC層21的邊界並與該PTC層21的兩個相反表面211互連。該第一孔洞210與該PTC層21的周緣212相間隔,且具有能容納該PTC層21在溫度升高時之熱膨脹的有效體積,以避免該PTC層21發生不欲的結構變形。The PTC element 2 can be formed with a first hole 210. In this embodiment, the first hole 210 is formed in the PTC layer 21. The PTC layer 21 of the PTC element 2 has a peripheral edge 212 that defines the boundary of the PTC layer 21 and is interconnected with two opposite surfaces 211 of the PTC layer 21. The first hole 210 is spaced from the periphery 212 of the PTC layer 21 and has an effective volume capable of accommodating the thermal expansion of the PTC layer 21 when the temperature increases, so as to prevent the PTC layer 21 from undesired structural deformation.

在本發明的某些具體實施例中,該第一孔洞210貫穿該PTC層21的兩個相反表面211中的至少其中一者。在本發明的某些具體實施例中,該第一孔洞210還貫穿該第一電極層22及該第二電極層23中的至少其中一者。在本實施例中,該第一孔洞210貫穿該PTC層21的兩個相反表面211及該第一電極層22、該第二電極層23,以形成一穿孔。在本發明的某些具體實施例中,該第一孔洞210沿著一穿過該PTC層21的幾何中心且橫過該兩個相反表面211的線延伸。該第一孔洞210是由一孔洞定義壁所定義,該孔洞定義壁具有平行於該PTC層21的表面211之橫截面。該孔洞定義壁的橫截面可為圓形、方形、橢圓形、三角形、十字形等。In some embodiments of the present invention, the first hole 210 penetrates at least one of the two opposite surfaces 211 of the PTC layer 21. In some embodiments of the present invention, the first hole 210 also penetrates at least one of the first electrode layer 22 and the second electrode layer 23. In this embodiment, the first hole 210 penetrates two opposite surfaces 211 of the PTC layer 21 and the first electrode layer 22 and the second electrode layer 23 to form a through hole. In some embodiments of the present invention, the first hole 210 extends along a line passing through the geometric center of the PTC layer 21 and across the two opposite surfaces 211. The first hole 210 is defined by a hole defining wall, and the hole defining wall has a cross section parallel to the surface 211 of the PTC layer 21. The cross-section of the hole-defining wall can be round, square, oval, triangle, cross, etc.

根據本發明,該PTC元件2可為一聚合物PTC (PPTC)元件,且該PTC層21可為一PTC聚合物層。該PTC聚合物層包括聚合物基材及分散在該聚合物基材中的導電填料。該聚合物基材可由含有非接枝的烯烴系聚合物(non-grafted olefin-based polymer)的聚合物組成物所製得。在本發明的某些具體實施例中,該非接枝的烯烴系聚合物為高密度聚乙烯(HDPE)。在本發明的某些具體實施例中,該聚合物組成物還包括經接枝的烯烴系聚合物(grafted olefin-based polymer)。在本發明的某些具體實施例中,該經接枝的烯烴系聚合物為經羧酸酐接枝的烯烴系聚合物。本發明適用的導電填料是選自於碳黑(carbon black)粉末、金屬粉末、導電陶瓷粉末或前述的組合,但不限於此。According to the present invention, the PTC device 2 may be a polymer PTC (PPTC) device, and the PTC layer 21 may be a PTC polymer layer. The PTC polymer layer includes a polymer substrate and a conductive filler dispersed in the polymer substrate. The polymer substrate can be made of a polymer composition containing a non-grafted olefin-based polymer. In some specific embodiments of the present invention, the non-grafted olefin-based polymer is high-density polyethylene (HDPE). In some specific embodiments of the present invention, the polymer composition further includes a grafted olefin-based polymer. In some specific embodiments of the present invention, the grafted olefin-based polymer is an olefin-based polymer grafted with carboxylic anhydride. The conductive filler suitable for the present invention is selected from carbon black powder, metal powder, conductive ceramic powder or a combination of the foregoing, but is not limited thereto.

根據本發明,該壓敏電阻器3可包括一壓敏電阻器層31、一第三電極層32及一第四電極層33。該壓敏電阻器層31具有兩個相反表面311。該第二導電引線5連結於該壓敏電阻器3的第三電極層32及第四電極層33的其中一者。在本發明的某些具體實施例中,該壓敏電阻器層31是由金屬氧化物材料所製得。According to the present invention, the varistor 3 may include a varistor layer 31, a third electrode layer 32 and a fourth electrode layer 33. The varistor layer 31 has two opposite surfaces 311. The second conductive lead 5 is connected to one of the third electrode layer 32 and the fourth electrode layer 33 of the varistor 3. In some specific embodiments of the present invention, the varistor layer 31 is made of a metal oxide material.

在本實施例中,該第三電極層32設置在該壓敏電阻器層31的兩個相反表面311的其中一者,並連接該PTC元件2的第二電極層23;該第四電極層33設置在該壓敏電阻器層31的兩個相反表面311的另一者。該第二導電引線5連結並設置於該第二電極層23與該第三電極層32之間。In this embodiment, the third electrode layer 32 is disposed on one of the two opposite surfaces 311 of the varistor layer 31, and is connected to the second electrode layer 23 of the PTC element 2; the fourth electrode layer 33 is provided on the other of the two opposite surfaces 311 of the varistor layer 31. The second conductive lead 5 is connected and disposed between the second electrode layer 23 and the third electrode layer 32.

該壓敏電阻器3可在該壓敏電阻器層31中形成有一第二孔洞310。在本實施例中,該壓敏電阻器3的壓敏電阻器層31具有一周緣312,該周緣312定義該壓敏電阻器層31的邊界並與該壓敏電阻器層31的兩個相反表面311互連。該第二孔洞310與該壓敏電阻器層31的周緣312相間隔。The varistor 3 may have a second hole 310 formed in the varistor layer 31. In this embodiment, the piezoresistor layer 31 of the piezoresistor 3 has a peripheral edge 312 that defines the boundary of the piezoresistor layer 31 and is opposite to two of the piezoresistor layer 31 The surfaces 311 are interconnected. The second hole 310 is spaced apart from the periphery 312 of the varistor layer 31.

在本發明的某些具體實施例中,該第二孔洞310貫穿該壓敏電阻器層31的兩個相反表面311中的至少其中一者。在本發明的某些具體實施例中,該第二孔洞310還貫穿該第三電極層32及該第四電極層33中的至少其中一者。在本實施例中,該第二孔洞310貫穿該壓敏電阻器層31的兩個相反表面311及該第三電極層32、該第四電極層33,以形成一穿孔。In some embodiments of the present invention, the second hole 310 penetrates at least one of the two opposite surfaces 311 of the varistor layer 31. In some embodiments of the present invention, the second hole 310 also penetrates at least one of the third electrode layer 32 and the fourth electrode layer 33. In this embodiment, the second hole 310 penetrates two opposite surfaces 311 of the varistor layer 31 and the third electrode layer 32 and the fourth electrode layer 33 to form a through hole.

根據本發明,該第一導電引線4具有一連接部41及一自由部42,而該第二導電引線5具有一連接部51及一自由部52。該第一導電引線4的連接部41藉由一焊料連結於該第一電極層22的外表面,且該第一導電引線4的自由部42自該連接部41延伸出該第一電極層22以供插入一電路板或一電路裝置的接腳孔(圖未示)。在本實施例中,該第二導電引線5的連接部51藉由一焊料連結並設置於該第二電極層23與該第三電極層32之間,且該第二導電引線5的自由部52自該連接部51延伸出該第二電極層23及該第三電極層32以供插入一電路板或一電路裝置的接腳孔(圖未示)。According to the present invention, the first conductive lead 4 has a connecting portion 41 and a free portion 42, and the second conductive lead 5 has a connecting portion 51 and a free portion 52. The connecting portion 41 of the first conductive lead 4 is connected to the outer surface of the first electrode layer 22 by a solder, and the free portion 42 of the first conductive lead 4 extends from the connecting portion 41 to the first electrode layer 22 For inserting into a circuit board or a pin hole of a circuit device (not shown). In this embodiment, the connecting portion 51 of the second conductive lead 5 is connected by a solder and is arranged between the second electrode layer 23 and the third electrode layer 32, and the free portion of the second conductive lead 5 52 extends from the connecting portion 51 to the second electrode layer 23 and the third electrode layer 32 to be inserted into the pin holes of a circuit board or a circuit device (not shown).

參閱圖4及圖5,本發明的複合式電路保護裝置之第二實施例與第一實施例相似,差異之處在於在第二實施例中,該第二導電引線5的連接部51藉由一焊料連結於該第四電極層33的外表面,且該第二導電引線5的自由部52自該連接部51延伸出該第四電極層33以供插入一電路板或一電路裝置的接腳孔(圖未示)。此外,第二實施例還包含一封裝材7,該封裝材7包裝該PTC元件2、該壓敏電阻器3、一部分該第一導電引線4及一部分該第二導電引線5。該第一導電引線4的自由部42及該第二導電引線5的自由部52暴露在該封裝材7外。在本發明的某些具體實施例中,該封裝材7是由環氧樹脂所製得。4 and 5, the second embodiment of the composite circuit protection device of the present invention is similar to the first embodiment, the difference is that in the second embodiment, the connecting portion 51 of the second conductive lead 5 is A solder is connected to the outer surface of the fourth electrode layer 33, and the free portion 52 of the second conductive lead 5 extends from the connection portion 51 out of the fourth electrode layer 33 for insertion into a circuit board or a circuit device. Foot hole (not shown). In addition, the second embodiment further includes a packaging material 7 that packages the PTC element 2, the varistor 3, a part of the first conductive lead 4 and a part of the second conductive lead 5. The free portion 42 of the first conductive lead 4 and the free portion 52 of the second conductive lead 5 are exposed outside the packaging material 7. In some specific embodiments of the present invention, the packaging material 7 is made of epoxy resin.

參閱圖6及圖7,本發明的複合式電路保護裝置之第三實施例與第二實施例相似,差異之處在於第三實施例還包含一第三導電引線6,該第三導電引線6連結並設置於該第二電極層23與該第三電極層32之間。該第三導電引線6具有一連接部61及一自由部62。該第三導電引線6的連接部61連接於該第二電極層23及該第三電極層32,該第三導電引線6的自由部62自該連接部61延伸出該第二電極層23及該第三電極層32以供插入一電路板或一電路裝置的接腳孔(圖未示)。6 and 7, the third embodiment of the composite circuit protection device of the present invention is similar to the second embodiment, the difference is that the third embodiment also includes a third conductive lead 6, the third conductive lead 6 It is connected and arranged between the second electrode layer 23 and the third electrode layer 32. The third conductive lead 6 has a connecting portion 61 and a free portion 62. The connecting portion 61 of the third conductive lead 6 is connected to the second electrode layer 23 and the third electrode layer 32, and the free portion 62 of the third conductive lead 6 extends from the connecting portion 61 to the second electrode layer 23 and The third electrode layer 32 is for inserting into a pin hole of a circuit board or a circuit device (not shown).

在本實施例中,該封裝材7包裝該PTC元件2、該壓敏電阻器3、一部分該第一導電引線4、一部分該第二導電引線5及一部分該第三導電引線6。該第一導電引線4的自由部42、該第二導電引線5的自由部52及一部分該第三導電引線6的自由部62暴露在該封裝材7外。In this embodiment, the packaging material 7 packages the PTC element 2, the varistor 3, a part of the first conductive lead 4, a part of the second conductive lead 5 and a part of the third conductive lead 6. The free portion 42 of the first conductive lead 4, the free portion 52 of the second conductive lead 5 and a part of the free portion 62 of the third conductive lead 6 are exposed outside the packaging material 7.

本發明將就以下實施例來作進一步說明,但應瞭解的是,該等實施例僅為例示說明之用,而不應被解釋為本發明實施之限制。The present invention will be further described with reference to the following examples, but it should be understood that these examples are for illustrative purposes only and should not be construed as limitations to the implementation of the present invention.

實施例Example

<實施例1 (E1)<Example 1 (E1)

21 g HDPE(購自台灣塑膠工業股份有限公司,產品型號:HDPE9002)作為非接枝的烯烴系聚合物,21 g經馬來酸酐接枝的HDPE (購自杜邦公司,產品型號:MB100D)作為經羧酸酐接枝的烯烴系聚合物,58 g碳黑粉末(購自Columbian Chemicals公司,產品型號:Raven 430UB)作為導電填料。21 g HDPE (purchased from Taiwan Plastics Industry Co., Ltd., product model: HDPE9002) as a non-grafted olefin polymer, 21 g of HDPE grafted with maleic anhydride (purchased from DuPont, product model: MB100D) as An olefin-based polymer grafted with carboxylic anhydride, 58 g of carbon black powder (purchased from Columbian Chemicals, product model: Raven 430UB) was used as a conductive filler.

將上述三種配料在一混煉機(廠牌:Brabender)中混合,以溫度為200℃、攪拌轉速為30 rpm的條件混合配料10 min。The above three ingredients were mixed in a mixer (brand: Brabender), and the ingredients were mixed for 10 minutes under the conditions of a temperature of 200°C and a stirring speed of 30 rpm.

將上述得到配料混合物置於模具中,以熱壓溫度為200℃及熱壓壓力為80 kg/cm2 的條件進行熱壓4 min,以形成一PTC聚合物層薄片。將薄片從模具中取出並置於兩片銅箔(分別作為第一電極層及第二電極層)之間,並在200℃及80 kg/cm2 下進行熱壓4 min,以形成一厚度為0.42 mm的PPTC元件。再將該PPTC元件裁切成多個9.5 mm × 11 mm的小片(chip,下稱PPTC-1)後,用Co-60 γ射線以總輻射劑量150 kGy照射每一小片。將第一導電引線及第二導電引線分別焊接在每一小片的兩片銅箔上,接著焊接一金屬氧化物壓敏電阻器(MOV,購自Ceramate Technical公司,產品型號:07D270K,下稱MOV-1)至該兩片銅箔的其中一片上,以形成E1的複合式電路保護裝置。The above-obtained ingredient mixture is placed in a mold, and hot-pressed for 4 minutes under the conditions of a hot- pressing temperature of 200° C. and a hot-pressing pressure of 80 kg/cm 2 to form a PTC polymer layer sheet. The sheet was taken out of the mold and placed between two pieces of copper foil (respectively as the first electrode layer and the second electrode layer), and hot-pressed at 200 ℃ and 80 kg/cm 2 for 4 min to form a thickness of 0.42 mm PPTC element. After cutting the PPTC element into multiple 9.5 mm × 11 mm chips (hereinafter referred to as PPTC-1), each chip was irradiated with Co-60 γ rays with a total radiation dose of 150 kGy. Weld the first conductive lead and the second conductive lead on the two copper foils of each small piece respectively, and then weld a metal oxide varistor (MOV, purchased from Ceramate Technical Company, product model: 07D270K, hereinafter referred to as MOV) -1) To one of the two copper foils to form an E1 composite circuit protection device.

根據Underwriter Laboratories公司對於熱敏電阻類型的裝置(thermistor-type device)的安全標準UL 1434測量PPTC小片的保持電流(hold current,即正常操作時的最大電流值)、跳脫電流(trip current,即PPTC元件達到高電阻狀態所需的最小電流值)、額定電壓(即PPTC元件工作時適用的電壓)及耐受電壓(withstand voltage,即不會造成PPTC元件故障或損壞的最大電壓)。此外,根據Underwriter Laboratories公司對於瞬間電壓突波抑制器(transient voltage surge suppressor)的安全標準UL 1449測量MOV元件的壓敏電壓(即MOV觸發工作的電壓)及箝制電壓(clamping voltage,即MOV可提供限制的最大電壓)。PPTC-1及MOV-1的性質測量結果分別如表1所示。 【表1】   保持電流 跳脫電流 額定電壓 耐受電壓 PPTC-1 5.00 A 8.50 A 16 V 16 V     壓敏電壓 a 箝制電壓 b MOV-1   27 V 53 V a:在1 mA下量測。 b:在脈波波形(tp ) 8/20 μs及脈波電流(Ip ) 2.5 A下量測。According to Underwriter Laboratories' safety standard UL 1434 for thermistor-type device (thermistor-type device), the holding current (hold current, the maximum current value during normal operation) and trip current (trip current) of the PPTC chip are measured The minimum current value required for the PPTC element to reach a high resistance state), the rated voltage (that is, the voltage applicable to the PPTC element when it works), and the withstand voltage (that is, the maximum voltage that will not cause the PPTC element to malfunction or damage). In addition, according to Underwriter Laboratories' safety standard UL 1449 for transient voltage surge suppressors, the varistor voltage (ie, the voltage at which the MOV triggers the work) and the clamping voltage (MOV can provide Limited maximum voltage). The property measurement results of PPTC-1 and MOV-1 are shown in Table 1, respectively. 【Table 1】 Hold current Trip current Rated voltage Withstand voltage PPTC-1 5.00 A 8.50 A 16 V 16 V Varistor voltage a Clamping voltage b MOV-1 27 V 53 V a: Measured at 1 mA. b: Measured at pulse waveform (t p ) 8/20 μs and pulse current (I p ) 2.5 A.

<實施例2<Example 2 至4 (E2-E4)To 4 (E2-E4)

E2-E4的複合式電路保護裝置的製程條件與E1相似,差異之處在於PPTC小片形成有第一穿孔及/或MOV形成有第二穿孔(如表3所示),每一第一穿孔及每一第二穿孔是由具有圓形截面(直徑為1.5 mm,圓面積為1.77 mm2 )的孔洞定義壁所定義。The process conditions of the E2-E4 composite circuit protection device are similar to those of E1. The difference is that the PPTC chip is formed with a first perforation and/or the MOV is formed with a second perforation (as shown in Table 3). Each first perforation and Each second perforation is defined by a hole-defining wall with a circular cross-section (diameter of 1.5 mm and circular area of 1.77 mm 2 ).

在E2中,於γ射線照射之後,在PPTC小片的中央部分鑿出第一穿孔。在E3中,於焊接上銅箔之前,在MOV的中央部分鑿出第二穿孔。在E4中,在PPTC小片的中央部分鑿出第一穿孔並在MOV的中央部分鑿出第二穿孔(如圖3所示)。In E2, after γ-ray irradiation, the first perforation is drilled in the central part of the PPTC chip. In E3, before soldering the copper foil, a second hole is drilled in the center of the MOV. In E4, the first perforation is drilled in the central part of the PPTC chip and the second perforation is drilled in the central part of the MOV (as shown in Figure 3).

<比較例1<Comparative example 1 至4 (CE1-CE4)To 4 (CE1-CE4)

CE1-CE4的複合式電路保護裝置的製程條件分別與E1-E4相似,差異之處在於CE1和CE2中不含PPTC小片,CE3和CE4中不含MOV。The process conditions of CE1-CE4 composite circuit protection devices are similar to those of E1-E4. The difference is that CE1 and CE2 do not contain small PPTC chips, and CE3 and CE4 do not contain MOV.

<實施例5<Example 5 至8 (E5-E8)To 8 (E5-E8)

E5-E8的複合式電路保護裝置的製程條件分別與E1-E4相似,差異之處在於形成E5-E8的PTC聚合物層薄片的配料為10 g HDPE、10 g經馬來酸酐接枝的HDPE、15 g碳黑粉末及15 g氫氧化鎂(購自MagChem公司,產品型號:MH 10),且E5-E8的PPTC小片(下稱PPTC-2)是被裁切成厚度為2.2 mm的圓形(直徑為3.1 mm)。此外,E5-E8的MOV是購自Ceramate Technical公司,產品型號:20D361K (下稱MOV-2)。PPTC-2及MOV-2的性質測量結果分別如表2所示。 【表2】   保持電流 跳脫電流 額定電壓 耐受電壓 PPTC-2 0.08 A 0.16 A 250 V 250 V     壓敏電壓 a 箝制電壓 b MOV-2   360 V 595 V a:在1 mA下量測。 b:在脈波波形(tp ) 8/20 μs及脈波電流(Ip ) 2.5 A下量測。The process conditions of the E5-E8 composite circuit protection device are similar to those of E1-E4, but the difference is that the ingredients for forming the PTC polymer layer sheet of E5-E8 are 10 g HDPE and 10 g HDPE grafted with maleic anhydride. , 15 g of carbon black powder and 15 g of magnesium hydroxide (purchased from MagChem company, product model: MH 10), and E5-E8 PPTC small pieces (hereinafter referred to as PPTC-2) are cut into a circle with a thickness of 2.2 mm Shape (3.1 mm in diameter). In addition, the MOV of E5-E8 is purchased from Ceramate Technical Company, product model: 20D361K (hereinafter referred to as MOV-2). The property measurement results of PPTC-2 and MOV-2 are shown in Table 2, respectively. 【Table 2】 Hold current Trip current Rated voltage Withstand voltage PPTC-2 0.08 A 0.16 A 250 V 250 V Varistor voltage a Clamping voltage b MOV-2 360 V 595 V a: Measured at 1 mA. b: Measured at pulse waveform (t p ) 8/20 μs and pulse current (I p ) 2.5 A.

<比較例5<Comparative example 5 至8 (CE5-CE8)To 8 (CE5-CE8)

CE5-CE8的複合式電路保護裝置的製程條件分別與E5-E8相似,差異之處在於CE5和CE6中不含PPTC小片,CE7和CE8中不含MOV。The process conditions of CE5-CE8 composite circuit protection devices are similar to those of E5-E8. The difference is that CE5 and CE6 do not contain PPTC chips, and CE7 and CE8 do not contain MOV.

<實施例9<Example 9 至12 (E9-E12)To 12 (E9-E12)

E9-E12的複合式電路保護裝置的製程條件分別與E5-E8相似,差異之處在於形成E9-E12的MOV是購自Ceramate Technical公司,產品型號:20D511K (下稱MOV-3)。MOV-3的壓敏電壓為510 V(在1 mA下量測),其箝制電壓為845 V[在脈波波形(tp ) 8/20 μs及脈波電流(Ip ) 2.5 A下量測]。The process conditions of the E9-E12 composite circuit protection device are similar to those of the E5-E8, but the difference is that the MOV forming the E9-E12 is purchased from Ceramate Technical Company, product model: 20D511K (hereinafter referred to as MOV-3). The varistor voltage of MOV-3 is 510 V (measured at 1 mA), and its clamping voltage is 845 V [measured at pulse waveform (t p ) 8/20 μs and pulse current (I p ) 2.5 A Measurement].

<比較例9<Comparative Example 9 至12 (CE9-CE12)To 12 (CE9-CE12)

CE9-CE12的複合式電路保護裝置的製程條件分別與E9-E12相似,差異之處在於CE9和CE10中不含PPTC小片,CE11和CE12中不含MOV。 【表3】   複合式電路保護裝置 PPTC小片 第一穿孔 MOV 第二穿孔 E1 PPTC-1 -- MOV-1 -- E2 PPTC-1 MOV-1 -- E3 PPTC-1 -- MOV-1 E4 PPTC-1 MOV-1 CE1 -- -- MOV-1 -- CE2 -- -- MOV-1 CE3 PPTC-1 -- -- -- CE4 PPTC-1 -- -- E5 PPTC-2 -- MOV-2 -- E6 PPTC-2 MOV-2 -- E7 PPTC-2 -- MOV-2 E8 PPTC-2 MOV-2 CE5 -- -- MOV-2 -- CE6 -- -- MOV-2 CE7 PPTC-2 -- -- -- CE8 PPTC-2 -- -- E9 PPTC-2 -- MOV-3 -- E10 PPTC-2 MOV-3 -- E11 PPTC-2 -- MOV-3 E12 PPTC-2 MOV-3 CE9 -- -- MOV-3 -- CE10 -- -- MOV-3 CE11 PPTC-2 -- -- -- CE12 PPTC-2 -- -- 「--」表示無此元件。The process conditions of the CE9-CE12 composite circuit protection device are similar to those of E9-E12. The difference is that CE9 and CE10 do not contain PPTC chips, and CE11 and CE12 do not contain MOV. 【table 3】 Composite circuit protection device PPTC small piece First perforation MOV Second perforation E1 PPTC-1 - MOV-1 - E2 PPTC-1 Have MOV-1 - E3 PPTC-1 - MOV-1 Have E4 PPTC-1 Have MOV-1 Have CE1 - - MOV-1 - CE2 - - MOV-1 Have CE3 PPTC-1 - - - CE4 PPTC-1 Have - - E5 PPTC-2 - MOV-2 - E6 PPTC-2 Have MOV-2 - E7 PPTC-2 - MOV-2 Have E8 PPTC-2 Have MOV-2 Have CE5 - - MOV-2 - CE6 - - MOV-2 Have CE7 PPTC-2 - - - CE8 PPTC-2 Have - - E9 PPTC-2 - MOV-3 - E10 PPTC-2 Have MOV-3 - E11 PPTC-2 - MOV-3 Have E12 PPTC-2 Have MOV-3 Have CE9 - - MOV-3 - CE10 - - MOV-3 Have CE11 PPTC-2 - - - CE12 PPTC-2 Have - - "--" means there is no such component.

性能測試Performance Testing

[[ 突波免疫測試Surge immunity test (Surge immunity test)](Surge immunity test)]

對於E1-E12與CE1-CE12的複合式電路保護裝置各取10個作為測試樣品,進行突波免疫測試。Take 10 of E1-E12 and CE1-CE12 composite circuit protection devices as test samples for surge immunity test.

對於E1-E4及CE1-CE4的複合式電路保護裝置,每個測試樣品的突波免疫測試是在大於MOV-1的壓敏電壓之電壓(包括38 V及44 V)下和0.5 A、PPTC-1的過電流(即10 A)之電流下以先接通60秒後再關閉的方式進行測試。如果PPTC小片和MOV都沒有燒燬或損壞,該測試樣品即為通過突波免疫測試,並記錄PPTC小片發生跳脫的時間的平均值(若有跳脫)。如果PPTC小片和MOV中的其中一者燒燬,該測試樣品即為燒燬,並記錄其發生燒燬的時間的平均值。結果分別如表4所示。 【表4】 38 V/0.5 A 38 V/10 A 44 V/0.5 A 44 V/10 A 結果 時間(s) 結果 時間(s) 結果 時間(s) 結果 時間(s) E1 通過 2.438 通過 0.551 通過 2.255 通過 0.146 E2 通過 2.425 通過 0.532 通過 2.200 通過 0.134 E3 通過 2.372 通過 0.530 通過 2.180 通過 0.130 E4 通過 2.345 通過 0.525 通過 2.165 通過 0.125 CE1 MOV燒燬 4.706 MOV燒燬 2.264 MOV燒燬 4.319 MOV燒燬 1.033 CE2 MOV燒燬 4.432 MOV燒燬 2.055 MOV燒燬 3.887 MOV燒燬 1.018 CE3 通過 無跳脫 PPTC燒燬 0.922 通過 無跳脫 PPTC燒燬 0.922 CE4 通過 無跳脫 PPTC燒燬 0.918 通過 無跳脫 PPTC燒燬 0.913 For E1-E4 and CE1-CE4 composite circuit protection devices, the surge immunity test of each test sample is at a voltage greater than MOV-1 varistor voltage (including 38 V and 44 V) and 0.5 A, PPTC Under the current of -1 overcurrent (ie 10 A), the test is performed by turning on for 60 seconds and then turning off. If neither the PPTC chip nor the MOV is burnt or damaged, the test sample has passed the surge immunity test, and the average value of the time for the PPTC chip to escape (if any) is recorded. If one of the PPTC chip and the MOV is burned, the test sample is burned, and the average of the burning time is recorded. The results are shown in Table 4, respectively. 【Table 4】 38 V/0.5 A 38 V/10 A 44 V/0.5 A 44 V/10 A result Time(s) result Time(s) result Time(s) result Time(s) E1 pass through 2.438 pass through 0.551 pass through 2.255 pass through 0.146 E2 pass through 2.425 pass through 0.532 pass through 2.200 pass through 0.134 E3 pass through 2.372 pass through 0.530 pass through 2.180 pass through 0.130 E4 pass through 2.345 pass through 0.525 pass through 2.165 pass through 0.125 CE1 MOV burned 4.706 MOV burned 2.264 MOV burned 4.319 MOV burned 1.033 CE2 MOV burned 4.432 MOV burned 2.055 MOV burned 3.887 MOV burned 1.018 CE3 pass through No jump PPTC burned 0.922 pass through No jump PPTC burned 0.922 CE4 pass through No jump PPTC burned 0.918 pass through No jump PPTC burned 0.913

表4結果顯示,CE1及CE2只含有MOV-1的測試樣品處於0.5 A之電流和至少1.4倍MOV-1的壓敏電壓之電壓下在5 s之內燒燬(一般MOV可耐受1.2倍其壓敏電壓之電壓),或處於10 A之過電流和過電壓下在2.5 s之內燒燬,且該損壞無法修復。而CE3及CE4只含有PPTC-1的測試樣品在10 A之過電流下燒燬。相反地,E1-E4含有PPTC-1及MOV-1的組合的所有測試樣品(其中PPTC-1的額定電壓約為MOV-1的壓敏電壓的59%)皆通過突波免疫測試而沒有燒燬。此外,相較於E1,E2-E4的PPTC-1及/或MOV-1形成有穿孔的測試樣品提升了熱量傳遞,可進一步縮短PPTC-1發生跳脫的時間,並防止過電流流經MOV-1,因此保護其MOV-1免於燒燬。換句話說,在E1-E4的測試樣品中,PPTC-1處於一過電流及一大於MOV-1的壓敏電壓之電壓下而在MOV-1燒燬之前跳脫。The results in Table 4 show that the test samples of CE1 and CE2 containing only MOV-1 burned within 5 s at a current of 0.5 A and a voltage of at least 1.4 times the varistor voltage of MOV-1 (generally, MOV can withstand 1.2 times the voltage. The voltage of the varistor voltage), or it burns within 2.5 s under an overcurrent and overvoltage of 10 A, and the damage cannot be repaired. The test samples of CE3 and CE4 that only contained PPTC-1 burned down at an overcurrent of 10 A. On the contrary, all test samples containing a combination of PPTC-1 and MOV-1 in E1-E4 (where the rated voltage of PPTC-1 is about 59% of the varistor voltage of MOV-1) have passed the surge immunity test without burning . In addition, compared with E1, E2-E4 PPTC-1 and/or MOV-1 formed with perforated test samples, the heat transfer is improved, which can further shorten the time of PPTC-1 tripping and prevent overcurrent from flowing through the MOV. -1, so protect its MOV-1 from burning. In other words, in the test samples of E1-E4, PPTC-1 was at an overcurrent and a voltage greater than MOV-1 and tripped before MOV-1 burned.

對於E5-E8及CE5-CE8的複合式電路保護裝置,每個測試樣品的突波免疫測試與上述相似,差異之處在於施加的電壓是大於MOV-2的壓敏電壓(包括400 V及500 V)且施加的電流是PPTC-2的過電流(即0.5A或10 A)。結果分別如表5所示。 【表5】 400 V/0.5 A 400 V/10 A 500 V/0.5 A 500 V/10 A 結果 時間(s) 結果 時間(s) 結果 時間(s) 結果 時間(s) E5 通過 4.464 通過 0.058 通過 0.864 通過 0.056 E6 通過 4.400 通過 0.058 通過 0.860 通過 0.055 E7 通過 4.355 通過 0.056 通過 0.852 通過 0.050 E8 通過 4.350 通過 0.055 通過 0.834 通過 0.048 CE5 MOV燒燬 19.575 MOV燒燬 1.396 MOV燒燬 10.585 MOV燒燬 0.463 CE6 MOV燒燬 19.422 MOV燒燬 1.375 MOV燒燬 10.440 MOV燒燬 0.455 CE7 PPTC 燒燬 0.113 PPTC 燒燬 0.060 PPTC 燒燬 0.105 PPTC 燒燬 0.058 CE8 PPTC 燒燬 0.1100 PPTC 燒燬 0.058 PPTC 燒燬 0.102 PPTC 燒燬 0.056 For E5-E8 and CE5-CE8 composite circuit protection devices, the surge immunity test of each test sample is similar to the above. The difference is that the applied voltage is a varistor voltage greater than MOV-2 (including 400 V and 500 V). V) and the applied current is the overcurrent of PPTC-2 (ie 0.5A or 10 A). The results are shown in Table 5, respectively. 【table 5】 400 V/0.5 A 400 V/10 A 500 V/0.5 A 500 V/10 A result Time(s) result Time(s) result Time(s) result Time(s) E5 pass through 4.464 pass through 0.058 pass through 0.864 pass through 0.056 E6 pass through 4.400 pass through 0.058 pass through 0.860 pass through 0.055 E7 pass through 4.355 pass through 0.056 pass through 0.852 pass through 0.050 E8 pass through 4.350 pass through 0.055 pass through 0.834 pass through 0.048 CE5 MOV burned 19.575 MOV burned 1.396 MOV burned 10.585 MOV burned 0.463 CE6 MOV burned 19.422 MOV burned 1.375 MOV burned 10.440 MOV burned 0.455 CE7 PPTC burned 0.113 PPTC burned 0.060 PPTC burned 0.105 PPTC burned 0.058 CE8 PPTC burned 0.1100 PPTC burned 0.058 PPTC burned 0.102 PPTC burned 0.056

表5結果顯示,CE5及CE6只含有MOV-2的測試樣品處於0.5 A之過電流和大於MOV-2的壓敏電壓之過電壓下在20 s之內燒燬,或處於10 A之過電流和過電壓下在1.5 s之內燒燬,且該損壞無法修復。而CE7及CE8只含有PPTC-2的測試樣品在0.5 A及10 A之過電流下燒燬。相反地,E5-E8含有PPTC-2及MOV-2的組合的所有測試樣品(其中PPTC-2的額定電壓約為MOV-2的壓敏電壓的69%)皆通過突波免疫測試而沒有燒燬。此外,相較於E5,E6-E8的PPTC-2及/或MOV-2形成有穿孔的測試樣品提升了熱量傳遞,可進一步縮短PPTC-2發生跳脫的時間,並防止過電流流經MOV-2,因此保護其MOV-2免於燒燬。換句話說,在E5-E8的測試樣品中,PPTC-2處於一過電流及一大於MOV-2的壓敏電壓之電壓下而在MOV-2燒燬之前跳脫。The results in Table 5 show that the test samples of CE5 and CE6 containing only MOV-2 burned within 20 s at an overcurrent of 0.5 A and an overvoltage of a varistor voltage greater than MOV-2, or were at an overcurrent of 10 A. It burns within 1.5 s under overvoltage, and the damage cannot be repaired. The CE7 and CE8 test samples containing only PPTC-2 burned down at 0.5 A and 10 A overcurrent. On the contrary, all test samples containing a combination of PPTC-2 and MOV-2 in E5-E8 (where the rated voltage of PPTC-2 is about 69% of the varistor voltage of MOV-2) have passed the surge immunity test without burning . In addition, compared to E5, E6-E8’s PPTC-2 and/or MOV-2 are formed with perforated test samples to improve heat transfer, which can further shorten the time for PPTC-2 to trip and prevent overcurrent from flowing through the MOV. -2, so protect its MOV-2 from burning. In other words, in the test samples of E5-E8, PPTC-2 was at an overcurrent and a voltage greater than MOV-2's varistor voltage and tripped before MOV-2 burned.

對於E9-E12及CE9-CE12的複合式電路保護裝置,每個測試樣品的突波免疫測試與上述相似,差異之處在於施加的電壓是大於MOV-3的壓敏電壓(包括600 V及700 V)。結果分別如表6所示。 【表6】 600 V/0.5 A 600 V/10 A 700 V/0.5 A 700 V/10 A 結果 時間(s) 結果 時間(s) 結果 時間(s) 結果 時間(s) E9 通過 1.244 通過 0.055 通過 0.856 通過 0.050 E10 通過 1.230 通過 0.054 通過 0.845 通過 0.048 E11 通過 1.225 通過 0.050 通過 0.834 通過 0.046 E12 通過 1.198 通過 0.047 通過 0.827 通過 0.045 CE9 MOV燒燬 17.881 MOV燒燬 0.975 MOV燒燬 9.875 MOV燒燬 0.385 CE10 MOV燒燬 17.650 MOV燒燬 0.968 MOV燒燬 9.762 MOV燒燬 0.376 CE11 PPTC 燒燬 0.100 PPTC燒燬 0.058 PPTC 燒燬 0.098 PPTC 燒燬 0.055 CE12 PPTC 燒燬 0.985 PPTC燒燬 0.056 PPTC 燒燬 0.095 PPTC 燒燬 0.054 For the E9-E12 and CE9-CE12 composite circuit protection devices, the surge immunity test of each test sample is similar to the above. The difference is that the applied voltage is a varistor voltage greater than MOV-3 (including 600 V and 700 V). V). The results are shown in Table 6, respectively. 【Table 6】 600 V/0.5 A 600 V/10 A 700 V/0.5 A 700 V/10 A result Time(s) result Time(s) result Time(s) result Time(s) E9 pass through 1.244 pass through 0.055 pass through 0.856 pass through 0.050 E10 pass through 1.230 pass through 0.054 pass through 0.845 pass through 0.048 E11 pass through 1.225 pass through 0.050 pass through 0.834 pass through 0.046 E12 pass through 1.198 pass through 0.047 pass through 0.827 pass through 0.045 CE9 MOV burned 17.881 MOV burned 0.975 MOV burned 9.875 MOV burned 0.385 CE10 MOV burned 17.650 MOV burned 0.968 MOV burned 9.762 MOV burned 0.376 CE11 PPTC burned 0.100 PPTC burned 0.058 PPTC burned 0.098 PPTC burned 0.055 CE12 PPTC burned 0.985 PPTC burned 0.056 PPTC burned 0.095 PPTC burned 0.054

表6結果顯示,CE9及CE10只含有MOV-3的測試樣品處於0.5 A之過電流和大於MOV-3的壓敏電壓之過電壓下在18 s之內燒燬,或處於10 A之過電流和過電壓下在1 s之內燒燬,且該損壞無法修復。而CE11及CE12只含有PPTC-2的測試樣品在0.5 A及10 A之過電流下燒燬。相反地,E9-E12含有PPTC-2及MOV-3的組合的所有測試樣品(其中PPTC-2的額定電壓約為MOV-3的壓敏電壓的49%)皆通過突波免疫測試而沒有燒燬。此外,相較於E9,E10-E12的PPTC-2及/或MOV-3形成有穿孔的測試樣品提升了熱量傳遞,可進一步縮短PPTC-2發生跳脫的時間,並防止過電流流經MOV-3,因此保護其MOV-3免於燒燬。換句話說,在E9-E12的測試樣品中,PPTC-2處於一過電流及一大於MOV-3的壓敏電壓之電壓下而在MOV-3燒燬之前跳脫。The results in Table 6 show that the test samples of CE9 and CE10 containing only MOV-3 burned within 18 s at an overcurrent of 0.5 A and an overvoltage of a varistor voltage greater than MOV-3, or were at an overcurrent of 10 A. It burns within 1 s under overvoltage, and the damage cannot be repaired. The test samples of CE11 and CE12 containing only PPTC-2 burned down at 0.5 A and 10 A overcurrent. On the contrary, all test samples of E9-E12 containing a combination of PPTC-2 and MOV-3 (where the rated voltage of PPTC-2 is about 49% of the varistor voltage of MOV-3) all passed the surge immunity test without burning . In addition, compared to E9, E10-E12’s PPTC-2 and/or MOV-3 are formed with perforated test samples to improve heat transfer, which can further shorten the time for PPTC-2 to trip and prevent overcurrent from flowing through the MOV. -3, so protect its MOV-3 from burning. In other words, in the test samples of E9-E12, PPTC-2 was at an overcurrent and a voltage greater than MOV-3 and tripped before MOV-3 burned.

綜上所述,藉由包含具有所欲額定電壓(例如40%至200%該壓敏電阻器在1 mA下量測的壓敏電壓)的PTC元件,在該過電流及該過電壓存在下,該PTC元件快速地跳脫至一高電阻狀態,以保護該壓敏電阻器免於因過電流而燒燬,本發明複合式電路保護裝置因而得以重複使用,而顯現其優異的耐受性及可靠性,故確實能達成本發明之目的。To sum up, by including a PTC element with a desired rated voltage (for example, 40% to 200% of the varistor voltage measured at 1 mA), in the presence of the overcurrent and the overvoltage , The PTC element quickly trips to a high resistance state to protect the varistor from being burnt due to overcurrent. The composite circuit protection device of the present invention can therefore be used repeatedly, and exhibits its excellent endurance and performance. Reliability, so it can indeed achieve the purpose of the invention.

惟以上所述者,僅為本發明之實施例而已,當不能以此限定本發明實施之範圍,凡是依本發明申請專利範圍及專利說明書內容所作之簡單的等效變化與修飾,皆仍屬本發明專利涵蓋之範圍內。However, the above are only examples of the present invention. When the scope of implementation of the present invention cannot be limited by this, all simple equivalent changes and modifications made in accordance with the scope of the patent application of the present invention and the content of the patent specification still belong to This invention patent covers the scope.

20:PTC聚合物基材 30:電極 40:孔洞 50:導電引線接腳 60:導電引線接腳 2:PTC元件 21:PTC層 210:第一孔洞 211:表面 212:周緣 22:第一電極層 23:第二電極層 3:壓敏電阻器 31:壓敏電阻器層 310:第二孔洞 311:表面 312:周緣 32:第三電極層 33:第四電極層 4:第一導電引線 41:連接部 42:自由部 5:第二導電引線 51:連接部 52:自由部 6:第三導電引線 61:連接部 62:自由部 7:封裝材20: PTC polymer substrate 30: Electrode 40: Hole 50: Conductive lead pin 60: Conductive lead pin 2: PTC component 21: PTC layer 210: first hole 211: Surface 212: Perimeter 22: The first electrode layer 23: second electrode layer 3: Varistor 31: Varistor layer 310: second hole 311: Surface 312: Perimeter 32: third electrode layer 33: Fourth electrode layer 4: The first conductive lead 41: Connection part 42: Ministry of Freedom 5: The second conductive lead 51: connecting part 52: Ministry of Freedom 6: The third conductive lead 61: Connection part 62: Ministry of Freedom 7: Packaging material

本發明之其他的特徵及功效,將於參照圖式的實施方式中清楚地呈現,其中: [圖1]是一現有插入式的PPTC過電流保護裝置的示意圖; [圖2]是本發明複合式電路保護裝置的第一具體實施例的示意圖; [圖3]是該第一具體實施例的剖視示意圖; [圖4]是本發明複合式電路保護裝置的第二具體實施例的示意圖; [圖5]是該第二具體實施例的剖視示意圖; [圖6]是本發明複合式電路保護裝置的第三具體實施例的示意圖; [圖7]是該第三具體實施例的剖視示意圖。Other features and effects of the present invention will be clearly presented in the embodiments with reference to the drawings, in which: [Figure 1] is a schematic diagram of an existing plug-in PPTC overcurrent protection device; [Figure 2] is a schematic diagram of the first specific embodiment of the composite circuit protection device of the present invention; [Figure 3] is a schematic cross-sectional view of the first specific embodiment; [Figure 4] is a schematic diagram of the second specific embodiment of the composite circuit protection device of the present invention; [Figure 5] is a schematic cross-sectional view of the second specific embodiment; [Figure 6] is a schematic diagram of the third specific embodiment of the composite circuit protection device of the present invention; [Figure 7] is a schematic cross-sectional view of the third embodiment.

2:PTC元件2: PTC components

21:PTC層21: PTC layer

210:第一孔洞210: first hole

211:表面211: Surface

22:第一電極層22: The first electrode layer

23:第二電極層23: second electrode layer

3:壓敏電阻器3: Varistor

31:壓敏電阻器層31: Varistor layer

310:第二孔洞310: second hole

311:表面311: Surface

32:第三電極層32: third electrode layer

33:第四電極層33: Fourth electrode layer

4:第一導電引線4: The first conductive lead

41:連接部41: Connection part

42:自由部42: Ministry of Freedom

5:第二導電引線5: The second conductive lead

51:連接部51: connecting part

52:自由部52: Ministry of Freedom

Claims (20)

一種複合式電路保護裝置,包含: 一PTC元件,包括: 一PTC層,具有兩個相反表面,及 分別設置在該PTC層的兩個相反表面的第一電極層及第二電極層; 一壓敏電阻器,連接於該第二電極層; 一第一導電引線,連結於該第一電極層;及 一第二導電引線,連結於該壓敏電阻器, 其中該PTC元件具有一額定電壓,該額定電壓介於40%至200%該壓敏電阻器在1 mA下量測的壓敏電壓。A composite circuit protection device, including: A PTC component, including: A PTC layer with two opposite surfaces, and The first electrode layer and the second electrode layer respectively disposed on two opposite surfaces of the PTC layer; A varistor connected to the second electrode layer; A first conductive lead connected to the first electrode layer; and A second conductive lead connected to the varistor, The PTC component has a rated voltage, and the rated voltage is between 40% and 200% of the varistor voltage measured by the varistor at 1 mA. 如請求項1所述的複合式電路保護裝置,其中,該PTC元件具有的額定電壓介於45%至100%該壓敏電阻器在1 mA下量測的壓敏電壓。The composite circuit protection device according to claim 1, wherein the rated voltage of the PTC element is between 45% and 100% of the varistor voltage measured by the varistor at 1 mA. 如請求項1所述的複合式電路保護裝置,其中,該PTC元件具有的額定電壓介於45%至70%該壓敏電阻器在1 mA下量測的壓敏電壓。The composite circuit protection device according to claim 1, wherein the rated voltage of the PTC element is between 45% and 70% of the varistor voltage measured by the varistor at 1 mA. 如請求項1所述的複合式電路保護裝置,其中,該PTC元件處於一過電流及一大於該壓敏電阻器的壓敏電壓之電壓下而在該壓敏電阻器燒燬之前跳脫。The composite circuit protection device of claim 1, wherein the PTC element is under an overcurrent and a voltage greater than the varistor voltage and trips before the varistor burns. 如請求項4所述的複合式電路保護裝置,其中,該PTC元件處於一大於0.1 A的過電流及一大於該壓敏電阻器的壓敏電壓之電壓下而在1 μs至100 s之內跳脫。The composite circuit protection device of claim 4, wherein the PTC element is under an overcurrent greater than 0.1 A and a voltage greater than the varistor voltage within 1 μs to 100 s Jump off. 如請求項4所述的複合式電路保護裝置,其中,該PTC元件處於一大於0.5 A的過電流及一大於該壓敏電阻器的壓敏電壓之電壓下而在1 ms至10 s之內跳脫。The composite circuit protection device according to claim 4, wherein the PTC element is under an overcurrent greater than 0.5 A and a voltage greater than the varistor voltage within 1 ms to 10 s Jump off. 如請求項4所述的複合式電路保護裝置,其中,該PTC元件處於一大於10 A的過電流及一大於該壓敏電阻器的壓敏電壓之電壓下而在1 ms至1 s之內跳脫。The composite circuit protection device according to claim 4, wherein the PTC element is under an overcurrent greater than 10 A and a voltage greater than the varistor voltage within 1 ms to 1 s Jump off. 如請求項1所述的複合式電路保護裝置,其中,該PTC元件在該PTC層中形成有一第一孔洞。The composite circuit protection device according to claim 1, wherein the PTC element has a first hole formed in the PTC layer. 如請求項8所述的複合式電路保護裝置,其中,該PTC元件的PTC層具有一周緣,該周緣定義該PTC層的邊界並與該PTC層的兩個相反表面互連,該第一孔洞與該PTC層的周緣相間隔。The composite circuit protection device according to claim 8, wherein the PTC layer of the PTC element has a peripheral edge, the peripheral edge defines the boundary of the PTC layer and is interconnected with two opposite surfaces of the PTC layer, and the first hole Spaced from the periphery of the PTC layer. 如請求項8所述的複合式電路保護裝置,其中,該第一孔洞貫穿該PTC層的兩個相反表面中的至少其中一者。The composite circuit protection device according to claim 8, wherein the first hole penetrates at least one of the two opposite surfaces of the PTC layer. 如請求項10所述的複合式電路保護裝置,其中,該第一孔洞還貫穿該第一電極層及該第二電極層中的至少其中一者。The composite circuit protection device according to claim 10, wherein the first hole further penetrates at least one of the first electrode layer and the second electrode layer. 如請求項1所述的複合式電路保護裝置,其中,該壓敏電阻器形成有一第二孔洞。The composite circuit protection device according to claim 1, wherein the varistor is formed with a second hole. 如請求項1所述的複合式電路保護裝置,其中,該壓敏電阻器包括: 一壓敏電阻器層,具有兩個相反表面; 一第三電極層,設置在該壓敏電阻器層的兩個相反表面的其中一者,並連接該PTC元件的第二電極層;及 一第四電極層,設置在該壓敏電阻器層的兩個相反表面的另一者, 其中該第二導電引線連結於該壓敏電阻器的第三電極層及第四電極層的其中一者。The composite circuit protection device according to claim 1, wherein the varistor includes: A varistor layer with two opposite surfaces; A third electrode layer disposed on one of the two opposite surfaces of the varistor layer and connected to the second electrode layer of the PTC element; and A fourth electrode layer provided on the other of the two opposite surfaces of the varistor layer, The second conductive lead is connected to one of the third electrode layer and the fourth electrode layer of the varistor. 如請求項13所述的複合式電路保護裝置,還包含一第三導電引線,該第二導電引線連結於該第四電極層,該第三導電引線連結並設置於該第二電極層與該第三電極層之間。The composite circuit protection device according to claim 13, further comprising a third conductive lead, the second conductive lead is connected to the fourth electrode layer, and the third conductive lead is connected and disposed on the second electrode layer and the Between the third electrode layer. 如請求項13所述的複合式電路保護裝置,其中,該壓敏電阻器在該壓敏電阻器層中形成有一第二孔洞。The composite circuit protection device according to claim 13, wherein the varistor has a second hole formed in the varistor layer. 如請求項15所述的複合式電路保護裝置,其中,該壓敏電阻器的壓敏電阻器層具有一周緣,該周緣定義該壓敏電阻器層的邊界並與該壓敏電阻器層的兩個相反表面互連,該第二孔洞與該壓敏電阻器層的周緣相間隔。The composite circuit protection device according to claim 15, wherein the piezoresistor layer of the piezoresistor has a peripheral edge that defines the boundary of the piezoresistor layer and is connected to the piezoresistor layer. The two opposite surfaces are interconnected, and the second hole is spaced from the periphery of the varistor layer. 如請求項15所述的複合式電路保護裝置,其中,該第二孔洞貫穿該壓敏電阻器層的兩個相反表面中的至少其中一者。The composite circuit protection device according to claim 15, wherein the second hole penetrates at least one of the two opposite surfaces of the varistor layer. 如請求項17所述的複合式電路保護裝置,其中,該第二孔洞還貫穿該第三電極層及該第四電極層中的至少其中一者。The composite circuit protection device according to claim 17, wherein the second hole further penetrates at least one of the third electrode layer and the fourth electrode layer. 如請求項1所述的複合式電路保護裝置,其中,該PTC元件是一聚合物PTC元件,該PTC層是一PTC聚合物層。The composite circuit protection device according to claim 1, wherein the PTC element is a polymer PTC element, and the PTC layer is a PTC polymer layer. 如請求項1所述的複合式電路保護裝置,還包含一封裝材,該封裝材包裝該PTC元件、該壓敏電阻器、一部分該第一導電引線及一部分該第二導電引線。The composite circuit protection device according to claim 1, further comprising a packaging material packaging the PTC element, the varistor, a part of the first conductive lead and a part of the second conductive lead.
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