TW202125963A - Driver of power converter and driving method thereof - Google Patents
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Abstract
Description
本發明的實施例是關於一種驅動器及其驅動方法。更具體而言,本發明的實施例是關於一種電源轉換器之驅動器及其驅動方法。 The embodiment of the present invention relates to a driver and a driving method thereof. More specifically, the embodiment of the present invention relates to a driver of a power converter and a driving method thereof.
在驅動器以及電源轉換器的電源裝置之間,會因佈線而產生寄生電感,而這樣的寄生電感會造成驅動器開啟或關斷電源轉換器的電源裝置的瞬間,產生很大的電壓突波(Voltage spike),進而損壞電源裝置。有鑑於此,如何避免上述電壓突波的產生,將是本發明所屬技術領域中極需被解決的問題。 Between the driver and the power supply device of the power converter, parasitic inductance will be generated due to wiring, and such parasitic inductance will cause the moment when the driver turns on or off the power supply device of the power converter, a large voltage surge (Voltage spike), thereby damaging the power supply device. In view of this, how to avoid the occurrence of the above-mentioned voltage surge will be a problem that needs to be solved in the technical field of the present invention.
為了解決至少上述的問題,本發明的實施例提供了一種電源轉換器之驅動器。該驅動器可包含一多級放大電路以及一電流抑制電路。該多級放大電路包含彼此串接的一前級放大組與一後級放大組,且該前級放大組與該後級放大組共同提供一第一驅動電流至該電源轉換器的一電源裝置。該電流抑制電路,設置在該前級放大組與該後級放大組之間,且用以判斷該電源裝置的一啟動電壓是否大於一預設門檻值。當判斷該啟動電壓大於該預設門檻值時,該電流抑制電路將抑制該後級放大組提供電流至該電 源裝置,使得該前級放大組單獨提供小於該第一驅動電流的一第二驅動電流至該電源裝置。 In order to solve at least the above-mentioned problems, an embodiment of the present invention provides a driver for a power converter. The driver may include a multi-stage amplifying circuit and a current suppression circuit. The multi-stage amplifying circuit includes a pre-amplification group and a post-amplification group connected in series, and the pre-amplification group and the post-amplification group jointly provide a first driving current to a power supply device of the power converter . The current suppression circuit is arranged between the pre-amplification group and the post-amplification group, and is used to determine whether a starting voltage of the power supply device is greater than a preset threshold. When it is judged that the starting voltage is greater than the preset threshold value, the current suppression circuit will inhibit the post-amplification group from providing current to the circuit. The source device allows the pre-amplifier group to separately provide a second drive current smaller than the first drive current to the power source device.
為了解決至少上述的問題,本發明的實施例還提供了一種電源轉換器的驅動器的驅動方法。該驅動方法包含:該驅動器提供一第一驅動電流至該電源轉換器的一電源裝置;該驅動器判斷該電源裝置的一啟動電壓是否大於一預設門檻值;以及當判斷該啟動電壓大於該預設門檻值時,該驅動器提供小於該第一驅動電流的一第二驅動電流至該電源裝置。 In order to solve at least the above-mentioned problems, an embodiment of the present invention also provides a driving method of a driver of a power converter. The driving method includes: the driver provides a first driving current to a power device of the power converter; the driver determines whether a startup voltage of the power device is greater than a predetermined threshold; and when it is determined that the startup voltage is greater than the predetermined threshold When the threshold is set, the driver provides a second driving current smaller than the first driving current to the power supply device.
在本發明的實施例中,每當電源轉換器的電源裝置的啟動電壓到達一預設門檻值時,額外設置的電流抑制電路將自動抑制驅動器提供給電源轉換器的驅動電流,這使得電源裝置被開啟或關斷之前,電源裝置的啟動電壓的上升速度可被減緩,進而避免電壓突波的產生。另一方面,在本發明的實施例中,除了額外在驅動器內設置電流抑制電路之外,並不需要在驅動器的外部增設其他元件,故也不用考慮外部元件的散熱以及損耗等問題,可減少電路設計上的困難。 In the embodiment of the present invention, whenever the startup voltage of the power supply device of the power converter reaches a preset threshold, the additional current suppression circuit will automatically suppress the driving current provided by the driver to the power converter, which makes the power supply device Before being turned on or off, the rising speed of the starting voltage of the power supply device can be slowed down, thereby avoiding the generation of voltage surges. On the other hand, in the embodiment of the present invention, in addition to an additional current suppression circuit in the driver, there is no need to add other components outside the driver, so there is no need to consider the heat dissipation and loss of external components, which can reduce Difficulties in circuit design.
以上內容並非為了限制本發明,而只是概括地敘述了本發明可解決的技術問題、可採用的技術手段以及可達到的技術功效,以讓本發明所屬技術領域中具有通常知識者初步地瞭解本發明。根據檢附的圖式及以下的實施方式所記載的內容,本發明所屬技術領域中具有通常知識者便可進一步瞭解本發明的各種實施例的細節。 The above content is not intended to limit the present invention, but only briefly describes the technical problems that can be solved by the present invention, the technical means that can be adopted, and the technical effects that can be achieved, so that those with ordinary knowledge in the technical field to which the present invention belongs can have a preliminary understanding of the present invention. invention. According to the attached drawings and the content described in the following embodiments, those with ordinary knowledge in the technical field to which the present invention belongs can further understand the details of the various embodiments of the present invention.
如下所示: As follows:
1‧‧‧驅動器 1‧‧‧Drive
11‧‧‧第一多級放大電路 11‧‧‧The first multi-stage amplifier circuit
111‧‧‧前級放大組 111‧‧‧Pre-amplification group
112‧‧‧電流抑制電路 112‧‧‧Current suppression circuit
113‧‧‧後級放大組 113‧‧‧Post-amplification group
13‧‧‧第二多級放大電路 13‧‧‧Second multi-stage amplifier circuit
15‧‧‧電壓位準移位器 15‧‧‧Voltage level shifter
17‧‧‧固定停滯時間調變器 17‧‧‧Fixed dead time modulator
2‧‧‧電源轉換器 2‧‧‧Power converter
ST‧‧‧級 ST‧‧‧level
PE1‧‧‧第一電源裝置 PE1‧‧‧First power supply unit
PE2‧‧‧第二電源裝置 PE2‧‧‧Second power supply unit
C11、C13、C1、C2‧‧‧驅動電流 C11, C13, C1, C2‧‧‧Drive current
PM1、PM2‧‧‧P型電晶體 PM1, PM2‧‧‧P type transistor
NM1、NM4、NM5‧‧‧N型電晶體 NM1, NM4, NM5‧‧‧N type transistor
PM40‧‧‧P型電晶體 PM40‧‧‧P type transistor
NM40、NM41‧‧‧N型電晶體 NM40, NM41‧‧‧N type transistor
CP、CPa、CPb‧‧‧比較器 CP, CPa, CPb‧‧‧Comparator
NG‧‧‧反閘 NG‧‧‧Reverse gate
OG‧‧‧或閘 OG‧‧‧or gate
V1、V2、V3、V4‧‧‧電壓源 V1, V2, V3, V4‧‧‧Voltage source
N1、N2、N3‧‧‧節點 N1, N2, N3‧‧‧node
t1、t2、t3‧‧‧時間點 t1, t2, t3‧‧‧time point
v(V1)、v(V2)‧‧‧電位值 v(V1), v(V2)‧‧‧Potential value
vt‧‧‧預設門檻電壓值 vt‧‧‧Preset threshold voltage value
i1、i2‧‧‧電流值 i1, i2‧‧‧current value
5‧‧‧驅動方法 5‧‧‧Drive method
51、53、55‧‧‧步驟
第1圖例示了根據某些實施例之電源轉換器及其驅動器。 Figure 1 illustrates a power converter and its driver according to some embodiments.
第2圖例示了第1圖所示的驅動器中的第一多級放大電路與第二多級放大電路以及電源轉換器的內部結構。 Fig. 2 illustrates the internal structure of the first multi-stage amplifying circuit and the second multi-stage amplifying circuit and the power converter in the driver shown in Fig. 1.
第3圖例示了第2圖所示的第一多級放大電路的運作時序圖。 Fig. 3 illustrates the operation timing chart of the first multi-stage amplifier circuit shown in Fig. 2.
第4圖例示了第2圖所示的第一多級放大電路的比較器的兩種電路架構。 Fig. 4 illustrates two circuit structures of the comparator of the first multi-stage amplifier circuit shown in Fig. 2.
第5圖例示了根據某些實施例之電源轉換器的驅動器的驅動方法。 Figure 5 illustrates the driving method of the driver of the power converter according to some embodiments.
以下將透過多個實施例來說明本發明,惟這些實施例並非用以限制本發明只能根據所述操作、環境、應用、結構、流程或步驟來實施。與本發明非直接相關的元件並未繪示於圖式中,但可隱含於圖式中。於圖式中,各元件(element)的尺寸以及各元件之間的比例僅是範例,而非用以限制本發明。除了特別說明之外,在以下內容中,相同(或相近)的元件符號可對應至相同(或相近)的元件。在可被實現的情況下,如未特別說明,以下所述的每一個元件的數量可以是一個或多個。 Hereinafter, the present invention will be described through a number of embodiments, but these embodiments are not intended to limit the present invention to only be implemented according to the operation, environment, application, structure, process, or steps. Elements that are not directly related to the present invention are not shown in the drawings, but may be implicit in the drawings. In the drawings, the size of each element and the ratio between each element are only examples, and are not intended to limit the present invention. Except for special instructions, in the following content, the same (or similar) component symbols may correspond to the same (or similar) components. In the case of being realized, the number of each element described below may be one or more unless otherwise specified.
本揭露使用之用語僅用於描述實施例,並不意圖限制本發明。除非上下文另有明確說明,否則單數形式「一」也旨在包括複數形式。「包括」、「包含」等用語指示所述特徵、整數、步驟、操作、元素及/或元件的存在,但並不排除一或多個其他特徵、整數、步驟、操作、元素、元件及/或前述之組之存在。用語「及/或」包含一或多個相關所列項目的任何及所有的組。 The terms used in this disclosure are only used to describe the embodiments and are not intended to limit the present invention. Unless the context clearly dictates otherwise, the singular form "one" is also intended to include the plural form. Terms such as "including" and "including" indicate the existence of the features, integers, steps, operations, elements, and/or elements, but do not exclude one or more other features, integers, steps, operations, elements, elements, and/or Or the existence of the aforementioned group. The term "and/or" includes any and all groups of one or more related listed items.
第1圖例示了根據某些實施例之電源轉換器及其驅動器。第1圖所示內容僅是為了舉例說明本發明的實施例,而非為了限制本發明。 Figure 1 illustrates a power converter and its driver according to some embodiments. The content shown in Figure 1 is only for illustrating the embodiments of the present invention, not for limiting the present invention.
參照第1圖,一種電源轉換器2之驅動器1可實作為晶片、積體電路或電路模組,且可基本上包含第一多級放大電路11、第二多級放大電路13、電壓位準移位器(voltage level shifter)15、以及固定停滯時間調變器(fixed dead time modulator)17。電源轉換器2同樣可實作為晶片、積體電路或電路模組,且其可包含第一電源裝置PE1以及第二電源裝置PE2。固定停滯時間調變器17的一個輸出端連接到電壓位準移位器15的輸入端,且固定停滯時間調變器17的另一個輸出端連接到第二多級放大電路13的輸入端。電壓位準移位器15的輸出端連接到第一多級放大電路11的輸入端。第一多級放大電路11的輸出端與第二多級放大電路13的輸出端分別連接到第一電源裝置PE1與第二電源裝置PE2。
Referring to Figure 1, a driver 1 of a power converter 2 can be implemented as a chip, an integrated circuit or a circuit module, and can basically include a first multi-stage amplifying
為了便於說明,驅動器1或電源轉換器2中與本發明之實施例無直接關係的元件或已知其功能與結構的元件將不特別在於本文或圖式中詳加敘述與表示。 For ease of description, the components of the driver 1 or the power converter 2 that are not directly related to the embodiments of the present invention or components whose functions and structures are known will not be described and shown in detail in the text or the drawings.
驅動器1是一種功率放大器,其包含的第一多級放大電路11和第二多級放大電路13可分別用以將小功率訊號放大成足以驅動電源轉換器2中的第一電源裝置PE1和第二電源裝置PE2的驅動訊號。固定停滯時間調變器17可用以將驅動第一電源裝置PE1的驅動訊號和驅動第二電源裝置PE2的驅動訊號在時間上錯開。電壓位準移位器15可用來調整第一多級放大電路11的輸入訊號的電壓位準(例如,將原本高電位為「5」伏特且與低電位為「0」伏特的方波訊號,調整成高電位為「12」伏特且與低電位為「7」伏特的方波訊號,其中調整前後的高電位與低電位皆維持「5」伏特的電位差)。在驅動器1中,第一多級放大電路11所產生的驅動訊號可以提供驅動電流
C11至電源轉換器2的第一電源裝置PE1,而第二多級放大電路13所產生的驅動訊號可以提供驅動電流C13至電源轉換器2的第二電源裝置PE2。
The driver 1 is a power amplifier. The first
第2圖例示了第1圖所示的驅動器1中的第一多級放大電路11與第二多級放大電路13以及電源轉換器2的內部結構,而第3圖例示了第2圖所示的第一多級放大電路11的運作時序圖。第2-3圖所示內容僅是為了舉例說明本發明的實施例,而非為了限制本發明。
Figure 2 illustrates the internal structure of the first
首先參照第2圖,第一多級放大電路11可包含彼此串接的一前級放大組111與一後級放大組113,且該前級放大組111與該後級放大組113共同提供一第一驅動電流C1至該電源轉換器的第一電源裝置PE1。在該前級放大組111與該後級放大組113之間還額外設置了一個電流抑制電路112,且電流抑制電路112可用來判斷電源裝置PE1的啟動電壓是否大於一預設門檻值。在電流抑制電路112判斷該啟動電壓大於該預設門檻值時,電流抑制電路112將抑制該後級放大組113提供電流至第一電源裝置PE1,使得前級放大組111單獨提供小於該第一驅動電流C1的一第二驅動電流C2至該第一電源裝置PE1。
First, referring to FIG. 2, the first
在第2圖所例示的實施例中,第一電源裝置PE1是一個N型電晶體NM4,第二電源裝置PE2是一個N型電晶體NM5。本文中所提及的電晶體,在不同的應用中,可以是各種場效電晶體,例如但不限於:接面場效電晶體(Junction Gate Field-Effect Transistor,JFET)、絕緣閘極場效電晶體(Insulated Gate Field Effect Transistor,IGFET)、金屬氧化物半導體場效電晶體(Metal-Oxide-Semiconductor Field-Effect Transistor,MOSFET)等。電源裝置PE1的啟動電壓是指N型電晶體NM4的閘級-源級電壓,而電源裝置 PE2的啟動電壓是指N型電晶體NM5的閘級-源級電壓。 In the embodiment illustrated in Figure 2, the first power supply device PE1 is an N-type transistor NM4, and the second power supply device PE2 is an N-type transistor NM5. The transistors mentioned in this article can be various field-effect transistors in different applications, such as but not limited to: Junction Gate Field-Effect Transistor (JFET), insulated gate field-effect transistor Transistor (Insulated Gate Field Effect Transistor, IGFET), Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), etc. The starting voltage of the power supply device PE1 refers to the gate-source voltage of the N-type transistor NM4, and the power supply device The starting voltage of PE2 refers to the gate-source voltage of the N-type transistor NM5.
繼續參照第2圖,N型電晶體NM4的汲極連接到電壓源V4,其閘極連接到節點N1,以在不同的時間點接收來自第一多級放大電路11的第一驅動電流C1或第二驅動電流C2,且其源極連接到N型電晶體NM4的汲極以及電壓源V2。相似地,N型電晶體NM5的閘極用以接收來自第二多級放大電路13的驅動電流C13,且源極連接到一接地端GND。在某些實施例中,N型電晶體NM4與N型電晶體NM5各自可以是一氮化鎵(GaN)電晶體,而因氮化鎵電晶體的跨閘級-源級最大電壓小於矽電晶體的跨閘級-源級最大電壓,故電壓突波也更容易發生在氮化鎵電晶體上。因此,在使用氮化鎵電晶體的這些實施例中,本發明的有益效果將更明顯。
Continuing to refer to Figure 2, the drain of the N-type transistor NM4 is connected to the voltage source V4, and its gate is connected to the node N1 to receive the first driving current C1 or The second driving current C2 has its source connected to the drain of the N-type transistor NM4 and the voltage source V2. Similarly, the gate of the N-type transistor NM5 is used to receive the driving current C13 from the second
在第2圖所例示的實施例中,電源轉換器2還可包含一電感、一電容、以及一電流源。以電源轉換器2為一降壓轉換器為例,該電感的其中一端連接到N型電晶體NM4的源極與N型電晶體NM5的汲極,而該電感的另外一端(節點N3)作為電源轉換器2的輸出端,且其連接到彼此並聯的該電容與該電流源的一端。另外,該電容與該電流源的另一端皆連接到N型電晶體NM5的源極與接地端GND。 In the embodiment illustrated in FIG. 2, the power converter 2 may also include an inductor, a capacitor, and a current source. Taking the power converter 2 as a buck converter as an example, one end of the inductor is connected to the source of the N-type transistor NM4 and the drain of the N-type transistor NM5, and the other end of the inductor (node N3) is used as The output terminal of the power converter 2 is connected to one end of the capacitor and the current source in parallel with each other. In addition, the other ends of the capacitor and the current source are connected to the source of the N-type transistor NM5 and the ground GND.
在其他的實施例中,第一電源裝置PE1與第二電源裝置PE2亦可以是P型電晶體,而本發明所屬技術領域具通常知識者可根據上述說明而直接理解如何實現這些其他實施例。 In other embodiments, the first power supply device PE1 and the second power supply device PE2 may also be P-type transistors. Those skilled in the art to which the present invention belongs can directly understand how to implement these other embodiments based on the above description.
在其他實施例中,電源轉換器2也可以是一升壓轉換器,且本發明所屬技術領域具通常知識者可根據上述說明而直接理解如何實現這些其他實施例。 In other embodiments, the power converter 2 may also be a boost converter, and those skilled in the art to which the present invention pertains can directly understand how to implement these other embodiments based on the above description.
前級放大組111可包含一或串接的多個級ST。每一個級ST可包含P型電晶體PM1與N型電晶體NM1,且P型電晶體PM1的汲極與N型電晶體NM1的汲極連接,中間的級ST的P型電晶體PM1的閘極與N型電晶體NM1的閘極連接到前一個級ST,P型電晶體PM1的源極連接到電壓源V1,N型電晶體NM1的源極連接到電壓源V2。另外,第一個級ST的P型電晶體PM1的閘極與N型電晶體NM1的閘極連接到電壓位準移位器15,而最後一個級ST的P型電晶體PM1的汲極與N型電晶體NM1的汲極連接到電流抑制電路112。電壓源V1的電位高於電壓源2的電位,故以下針對第一多級放大電路11的說明中所描述的高電位指的是電壓源V1的電位值v(V1)(例如,「12」伏特),而低電位指的是電壓源V2的電位值v(V2)(例如,「7」伏特)。
The
在前級放大組111中,若P型電晶體PM1的閘極與N型電晶體NM1的閘極同時接收到一個低電位的電壓,則P型電晶體PM1將導通,也就是將有一電流從P型電晶體PM1的源極流至其汲極,使得其汲極的電位將趨近電壓源V1的電位(假設其導通電阻為零),而N型電晶體NM1則不導通。反之,若P型電晶體PM1的閘極與N型電晶體NM1的閘極同時接收到一個高電位的電壓,則N型電晶體NM1將導通,也就是將有一電流從N型電晶體NM1的源極流至其汲極,使得其汲極的電位將趨近電壓源V2的電位(假設其導通電阻為零),而此時P型電晶體PM1不導通。
In the
後級放大組113可包含P型電晶體PM2。P型電晶體PM2的源極連接到電壓源V1以及P型電晶體PM1的源極,且P型電晶體PM2的汲極、P型電晶體PM1的汲極以及N型電晶體NM4的閘級彼此連接。
The
電流抑制電路112可包含比較器CP、反閘NG與或閘OG。比
較器CP的輸入端連接到N型電晶體NM4的閘級與或閘OG的第一輸入端(也就是第2圖中的節點N1),該比較器CP的輸出端連接到該反閘NG的輸入端(也就是第2圖中的節點N2),該反閘NG的輸出端連接到該或閘OG的第二輸入端,該或閘OG的輸出端連接到該P型電晶體PM2的閘極。
The
參照第2-3圖,第一多級放大電路11將在其驅動週期內(時間點t0到時間點t3的區間)驅動第一電源裝置PE1。首先,從時間點t1開始直到時間點t2,前級放大組111與後級放大組113會共同提供驅動電流C1(具有電流值i1)至第一電源裝置PE1,以對第一電源裝置PE1進行充電。更具體而言,在時間點t0到時間點t2之間,因比較器CP的輸入端的訊號(亦即,第一電源裝置PE1的啟動電壓)不大於(未超出)一預設門檻值vt,該比較器CP的輸出端會輸出高電位訊號至反閘NG的輸入端(節點N2),而反閘NG接著會輸出低電位訊號至或閘OG的第二輸入端。此時,或閘OG的第二輸入端的電壓與第一輸入端(節點N1)的訊號皆為低電位,所以或閘OG的輸出端輸出低電位訊號至P型電晶體PM2,以使P型電晶體PM2導通。因P型電晶體PM2導通,故由其源極流至其汲極的電流將會提供給第一電源裝置PE1。此時,前級放大組111與後級放大組113會共同提供驅動電流C1至第一電源裝置PE1,以使電源裝置PE1的啟動電壓將從低電位v(V2)開始上升。預設門檻值vt的數值可以根據不同的需要來設定,例如但不限於:電源裝置PE1的臨界電壓的80%、70%、或90%等。
Referring to FIGS. 2-3, the first
在時間點t2之後,將由前級放大組111單獨提供驅動電流C2(具有電流值i2)至第一電源裝置PE1,其中驅動電流C2小於驅動電流C1。詳言之,在時間點t2之後,因比較器CP的輸入端的訊號(亦即,第一電源裝
置PE1的啟動電壓)大於(超出)預設門檻值vt,該比較器CP的輸出端會輸出低電位訊號至反閘NG的輸入端(節點N2),而反閘NG接著會輸出高電位訊號至或閘OG的第二輸入端。此時,或閘OG的輸出端會輸出高電位訊號至P型電晶體PM2,以使P型電晶體PM2不導通(斷開)。因P型電晶體PM2不導通,故其源極至汲極的電流將無法提供給第一電源裝置PE1。此時,將由前級放大組111單獨提供驅動電流C2至第一電源裝置PE1,藉以減緩電源裝置PE1的啟動電壓的上升速度,而因減緩了電源裝置PE1的啟動電壓的上升速度,故可避免在第一電源裝置PE1上產生電壓突波。
After the time point t2, the
繼續參照第2圖,第二多級放大電路13的內部結構與第一多級放大電路11的內部結構相似,而差別僅在於電壓源V1被以電壓源V3來取代,且電壓源V2被以接地端GND來取代。在某些實施例中,第二多級放大電路13可以包含電流抑制電路112,而在某些實施例中,第二多級放大電路13也可以不包含電流抑制電路112(即,不具抑制電流功能的單純放大電路)。在第二多級放大電路13包含電流抑制電路112的實施例中,將如同第一多級放大電路11般,可以判斷第二電源裝置PE2的啟動電壓是否大於某一預設門檻值,且在第二電源裝置PE2的啟動電壓大於該預設門檻值時,抑制且減少提供給第二電源裝置PE2的驅動電流C13,以避免在第二電源裝置PE2上產生電壓突波。
Continuing to refer to Figure 2, the internal structure of the second
第4圖例示了第2圖所示的第一多級放大電路的比較器的兩種電路架構。第4圖所示內容僅是為了舉例說明本發明的實施例,而非為了限制本發明。在不同的實施例中,比較器CP可以具備不同的架構,為了作為說明,第4圖提供了某些實施例的比較器CPa之電路架構以及某些其他實 施例的比較器CPb之電路架構。 Fig. 4 illustrates two circuit structures of the comparator of the first multi-stage amplifier circuit shown in Fig. 2. The content shown in Figure 4 is only for illustrating the embodiments of the present invention, not for limiting the present invention. In different embodiments, the comparator CP may have different architectures. For illustration, Figure 4 provides the circuit architecture of the comparator CPa of some embodiments and some other implementations. The circuit structure of the comparator CPb of the embodiment.
比較器CPa可包含串接的一P型電晶體PM40與一N型電晶體NM40。P型電晶體PM40的源極連接到電壓源V1,閘極連接到N型電晶體NM40的閘極以及節點N1(即,比較器CPa的輸入端)。P型電晶體PM40的汲極連接到N型電晶體NM40的汲極以及節點N2(即,比較器CPa的輸出端)。N型電晶體NM40的源極連接到電壓源V2。在比較器CPa的輸入端的訊號超過預設門檻電壓值vt時,P型電晶體PM40不導通,且N型電晶體NM40導通,這使得比較器CPa的輸出端的輸出為低電位(例如,趨近於電壓源V2的電位)。反之,比較器CPa的輸出端的輸出為高電位(例如,趨近於電壓源V1的電位)。 The comparator CPa may include a P-type transistor PM40 and an N-type transistor NM40 connected in series. The source of the P-type transistor PM40 is connected to the voltage source V1, and the gate is connected to the gate of the N-type transistor NM40 and the node N1 (ie, the input terminal of the comparator CPa). The drain of the P-type transistor PM40 is connected to the drain of the N-type transistor NM40 and the node N2 (ie, the output terminal of the comparator CPa). The source of the N-type transistor NM40 is connected to the voltage source V2. When the signal at the input terminal of the comparator CPa exceeds the preset threshold voltage value vt, the P-type transistor PM40 is not turned on, and the N-type transistor NM40 is turned on, which makes the output of the comparator CPa output to a low potential (for example, approaching At the potential of the voltage source V2). Conversely, the output of the output terminal of the comparator CPa is at a high potential (for example, close to the potential of the voltage source V1).
除了僅包含串接一P型電晶體PM40與一N型電晶體的態樣(比較器CPa),可以在比較器CP中額外串接其他N型電晶體(比較器CPb),以調整偵測的預設門檻電壓值vt的大小。詳言之,比較器CPb可包含串接的一P型電晶體PM40與彼此串接的多個N型電晶體NM41。P型電晶體PM40的源極連接到電壓源V1,其閘極連接到每一個N型電晶體NM41的閘極以及節點N1(即,比較器CPb的輸入端)。P型電晶體PM40的汲極連接到多個N型電晶體NM41中的前頭電晶體的汲極以及節點N2(即,比較器CPb的輸出端)。各個N型電晶體NM41的源極連接到下一個N型電晶體的汲極,而最後一個N型電晶體NM44的源極連接到電壓源V2。在比較器CPb的輸入端的訊號超過預設門檻電壓值vt時,P型電晶體PM40不導通,且多個N型電晶體NM41導通,這使得比較器CPb的輸出端的輸出為低電位(例如,趨近於電壓源V2的電位)。反之,比較器CPb的輸出端的輸出為高電位(例如,趨近 於電壓源V1的電位)。 In addition to only including a P-type transistor PM40 and an N-type transistor in series (comparator CPa), other N-type transistors (comparator CPb) can be connected in series in the comparator CP to adjust the detection The size of the preset threshold voltage vt. In detail, the comparator CPb may include a P-type transistor PM40 connected in series and a plurality of N-type transistors NM41 connected in series. The source of the P-type transistor PM40 is connected to the voltage source V1, and its gate is connected to the gate of each N-type transistor NM41 and the node N1 (ie, the input terminal of the comparator CPb). The drain of the P-type transistor PM40 is connected to the drain of the leading transistor among the plurality of N-type transistors NM41 and the node N2 (ie, the output terminal of the comparator CPb). The source of each N-type transistor NM41 is connected to the drain of the next N-type transistor, and the source of the last N-type transistor NM44 is connected to the voltage source V2. When the signal at the input terminal of the comparator CPb exceeds the preset threshold voltage vt, the P-type transistor PM40 is not turned on, and the multiple N-type transistors NM41 are turned on, which makes the output of the comparator CPb's output terminal to be a low potential (for example, Approaching the potential of the voltage source V2). Conversely, the output of the output terminal of the comparator CPb is high (for example, approaching At the potential of the voltage source V1).
第3圖中所例示的比較器CPb中所串接的N型電晶體NM41的數量並非限制,使用者可以根據需要來設計該數量。須說明,比較器CPb中所串接的N型電晶體NM41的數量會影響能使每一個N型電晶體NM41皆導通的臨界電壓大小,進而調整比較器CPb所能偵測預設門檻電壓值vt的大小。舉例而言,若比較器CPb中串接的N型電晶體NM41的數量越多,預設門檻電壓值vt將越高,若比較器CPb中串接的N型電晶體NM41的數量越少,預設門檻電壓值vt將越低。 The number of N-type transistors NM41 connected in series in the comparator CPb illustrated in FIG. 3 is not limited, and the user can design the number according to needs. It should be noted that the number of N-type transistors NM41 connected in series in the comparator CPb will affect the threshold voltage that enables each N-type transistor NM41 to be turned on, thereby adjusting the preset threshold voltage that the comparator CPb can detect The size of vt. For example, if the number of N-type transistors NM41 connected in series in the comparator CPb is larger, the preset threshold voltage value vt will be higher. If the number of N-type transistors NM41 connected in series in the comparator CPb is smaller, The preset threshold voltage value vt will be lower.
第5圖例示了根據某些實施例之電源轉換器的驅動器的驅動方法。第5圖所示內容僅是為了舉例說明本發明的實施例,而非為了限制本發明。 Figure 5 illustrates the driving method of the driver of the power converter according to some embodiments. The content shown in FIG. 5 is only for illustrating the embodiment of the present invention, not for limiting the present invention.
參照第5圖,一種電源轉換器的驅動器的驅動方法5可包含以下步驟:該驅動器提供一第一驅動電流至該電源轉換器的一電源裝置(標示為步驟51);該驅動器判斷該電源裝置的一啟動電壓是否大於一預設門檻值(標示為步驟53);以及當判斷該啟動電壓大於該預設門檻值時,該驅動器提供小於該第一驅動電流的一第二驅動電流至該電源裝置(標示為步驟55)。
Referring to FIG. 5, a
在某些實施例中,該驅動器可包含一多級放大電路與一電流抑制電路。該多級放大電路可包含彼此串接的一前級放大組與一後級放大組,該前級放大組與該後級放大組可共同提供該第一驅動電流至該電源轉換器的該電源裝置。該電流抑制電路可設置在該前級放大組與該後級放大組之間,且用以判斷該電源裝置的該啟動電壓是否大於該預設門檻值。 In some embodiments, the driver may include a multi-stage amplifier circuit and a current suppression circuit. The multi-stage amplifying circuit may include a pre-amplification group and a post-amplification group connected in series, and the pre-amplification group and the post-amplification group can jointly provide the first driving current to the power supply of the power converter Device. The current suppression circuit can be arranged between the pre-amplification group and the post-amplification group, and is used to determine whether the startup voltage of the power supply device is greater than the preset threshold.
在某些實施例中,該電源裝置是一N型電晶體,且該後級放大組連接到該N型電晶體的閘級。 In some embodiments, the power supply device is an N-type transistor, and the post-amplification group is connected to the gate stage of the N-type transistor.
在某些實施例中,該電源裝置是一氮化鎵N型電晶體,且該後級放大組連接到該N型電晶體的閘級。 In some embodiments, the power supply device is a gallium nitride N-type transistor, and the post-amplification group is connected to the gate stage of the N-type transistor.
驅動方法5基本上包含了與驅動器1的上述所有實施例相對應的實施例。因此,除了驅動方法5的上述實施例之外,驅動方法5還可以包含其他實施例,而因本發明所屬技術領域中具有通常知識者可以根據上文針對驅動器1的說明而直接瞭解這些其他實施例,故不再贅述。
The
上述實施例只是舉例來說明本發明,而非為了限制本發明。任何針對上述實施例進行修飾、改變、調整、整合而產生的其他實施例,只要是本發明所屬技術領域中具有通常知識者不難思及的,都涵蓋在本發明的保護範圍內。本發明的保護範圍以申請專利範圍為準。 The above-mentioned embodiments are only examples to illustrate the present invention, but not to limit the present invention. Any other embodiments resulting from modification, change, adjustment, and integration of the above-mentioned embodiments, as long as those with ordinary knowledge in the technical field of the present invention are not difficult to think of, are covered by the protection scope of the present invention. The scope of protection of the present invention is subject to the scope of the patent application.
11‧‧‧第一多級放大電路 11‧‧‧The first multi-stage amplifier circuit
111‧‧‧前級放大組 111‧‧‧Pre-amplification group
112‧‧‧電流抑制電路 112‧‧‧Current suppression circuit
113‧‧‧後級放大組 113‧‧‧Post-amplification group
13‧‧‧第二多級放大電路 13‧‧‧Second multi-stage amplifier circuit
ST‧‧‧級 ST‧‧‧level
PE1‧‧‧第一電源裝置 PE1‧‧‧First power supply unit
PE2‧‧‧第二電源裝置 PE2‧‧‧Second power supply unit
C11、C13、C1、C2‧‧‧驅動電流 C11, C13, C1, C2‧‧‧Drive current
PM1、PM2‧‧‧P型電晶體 PM1, PM2‧‧‧P type transistor
NM1、NM4、NM5‧‧‧N型電晶體 NM1, NM4, NM5‧‧‧N type transistor
CP‧‧‧比較器 CP‧‧‧Comparator
NG‧‧‧反閘 NG‧‧‧Reverse gate
OG‧‧‧或閘 OG‧‧‧or gate
V1、V2、V3、V4‧‧‧電壓源 V1, V2, V3, V4‧‧‧Voltage source
N1、N2、N3‧‧‧節點 N1, N2, N3‧‧‧node
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