TW202123466A - Gate drive interposer with integrated passives for wide band gap semiconductor devices - Google Patents

Abstract

An improved electronic assembly is provided. The electronic assembly comprises a ceramic interposer comprising multiple layers. The active layers of the multiple layers form an embedded capacitor comprising parallel electrodes with a dielectric between adjacent electrodes wherein adjacent electrodes have opposite polarity. A wide band gap device is also on the multilayered ceramic interposer.

Description

Gate drive intermediary with integrated passive component for wide band gap semiconductor device

[0001] The present invention is a partial continuation application of U.S. Patent Application No. 16/531,255 filed on August 5, 2019, and the U.S. patent application is a request for a U.S. provisional application filed on February 21, 2019 Priority No. 62/808,493. [0002] The present invention relates to an improved gate drive intermediary. More specifically, the present invention relates to an improved gate drive intermediary with integrated passive components, which are particularly suitable for use with wide band gap semiconductor devices.

公式1 其中: C =電容量(F); P_load =功率(W); U_ripple =漣波電壓(V); U_max =最大電壓(V);和 f =開關頻率(Hz) [0007]   使用公式1，可以估計給定功率負載所需的電容量，如圖1和2所示。圖1和2顯示，增加電壓進一步減小了所需的電容量，但是隨著功率負載的增加，需要更高的電容量。增大開關頻率也會減小緩衝電容器所需的電容量。為了減小尺寸，需要較低的電容值，但是在較高的頻率下，電磁干擾(EMI)成為一個問題。 [0008]   如圖1和2所示，在低頻下，高功率和較低電壓須要很大的DC鏈路電容器。在20kHz的開關頻率下，例如典型的Si基半導體，所需的大電容量係由薄膜和電解電容器供給。然而，採用基於SiC和GaN的寬帶隙半導體裝置，因為它們支持高轉換效率和更小的尺寸，故可以在更高的頻率和電壓切換。 [0009]   低溫共燒陶瓷(LTCC)已用於將半導體與其他被動組件一起封裝。但是，所用的玻璃陶瓷材料的介電常數小於10，並且主要用於高頻和低壓能量轉換以及控制電子裝置。低介電常數的結果是只能得到原有的低電容，並且必須通過表面黏著將低壓獨立電容器的更高電容值併入這些封裝中。 [0010]   本文提供一種功率模組，該功率模組適用於高電壓和高開關頻率。此外，本文提供了用於高壓和高開關頻率的功率模組，其允許功率模組的進一步小型化，並且特別適合與寬帶隙器件一起使用。[0003] Reducing the size of electronic components is an ongoing demand. The effort called miniaturization in the art is manifested in two main ways. Among them, one of the main points is the level of components. By continuously inspecting the structural or functional deficiencies of each component in detail, it is hoped that higher-level functions can be realized in a smaller volume. Another main focus is on the level of modules or electronic equipment, how to assemble electronic components together to form functional modules or functional devices. The present invention specifically relates to the miniaturization of modules, particularly power modules, and more specifically to power modules that are particularly suitable for use in wide band gap semiconductor devices preferably having a band gap of about 2 to about 4 eV. [0004] Wide band gap (WBG) semiconductor devices provide designers of power electronic components with higher switching frequencies and higher power densities. The isolated gate driver is located between the control circuit and the WBG device, and provides the necessary voltage and current to achieve the best performance. Due to the limitation of parasitic inductance and resistance commonly referred to as equivalent series inductance or ESL and equivalent series resistance or ESR in the art, the improvement is limited to some extent. [0005] WBG devices are widely used in equipment such as light-emitting diodes, lasers, certain radio frequency applications such as radar, large industrial motors, large-scale high-efficiency data centers, etc., and are suitable for, for example, wind energy and solar energy systems, transportation systems, and satellite communications. Inverters in DC energy generation systems used by other applications. WBG devices can operate at higher switching frequencies, higher voltages, and higher temperatures, thereby contributing to more efficient energy conversion in smaller devices. Integrating low-loss capacitors under the operating conditions of these devices and systems has continued demand. [0006] Wide band gap semiconductors such as SiC and GaN based can operate at higher switching frequencies and higher voltages. At higher switching frequencies, the required capacitance is smaller, thus reducing the space occupied by the capacitor. For example, the required capacitance of a DC link capacitor in Hz at a given frequency can be calculated using Equation 1:

Equation 1 where: C = capacitance (F); P _load = power (W); U _ripple = ripple voltage (V); U _max = maximum voltage (V); and f = switching frequency (Hz) [0007] Using formula 1, the capacitance required for a given power load can be estimated, as shown in Figures 1 and 2. Figures 1 and 2 show that increasing the voltage further reduces the required capacitance, but as the power load increases, higher capacitance is required. Increasing the switching frequency will also reduce the required capacitance of the snubber capacitor. In order to reduce the size, a lower capacitance value is required, but at higher frequencies, electromagnetic interference (EMI) becomes a problem. [0008] As shown in FIGS. 1 and 2, at low frequencies, high power and low voltage require large DC link capacitors. At a switching frequency of 20kHz, such as a typical Si-based semiconductor, the large capacitance required is supplied by film and electrolytic capacitors. However, wide band gap semiconductor devices based on SiC and GaN are used because they support high conversion efficiency and smaller size, so they can be switched at higher frequencies and voltages. [0009] Low-temperature co-fired ceramics (LTCC) have been used to package semiconductors with other passive components. However, the glass ceramic material used has a dielectric constant of less than 10, and is mainly used for high-frequency and low-voltage energy conversion and control electronic devices. As a result of the low dielectric constant, only the original low capacitance can be obtained, and the higher capacitance value of the low-voltage stand-alone capacitor must be incorporated into these packages through surface adhesion. [0010] This document provides a power module suitable for high voltage and high switching frequency. In addition, this article provides a power module for high voltage and high switching frequency, which allows further miniaturization of the power module and is particularly suitable for use with wide band gap devices.

[0011] The present invention relates to an improved ceramic intermediary, which is particularly suitable for use as a gate drive intermediary for wide band gap semiconductor devices. [0012] The specific feature of the present invention is to reduce the total volume, which meets the continuous demand in circuit design. [0013] More specifically, the present invention relates to a layered ceramic interposer, the active layer of the layered ceramic interposer includes parallel electrodes with alternating polarities and a dielectric between adjacent electrodes. [0014] In addition to incorporating DC link capacitors, the present invention also allows other types of capacitors to be incorporated into the intermediary for decoupling, filtering, timing, and buffering. The present invention also allows other functions to be incorporated in a part of the intermediary and allows heat dissipation. These advantages will be described in the following description. [0015] As will be appreciated, these and other embodiments are provided in an electronic assembly that includes a ceramic interposer that includes multiple layers. The active layer of multiple layers forms an embedded capacitor including parallel electrodes having a dielectric between adjacent electrodes, wherein the adjacent electrodes have opposite polarities. Wide band gap devices are also on multilayer ceramic interposers. [0016] Another embodiment provided in an electronic component includes a ceramic interposer with multiple layers. The multi-layer active layer forms an embedded capacitor. The capacitor includes parallel electrodes with a dielectric between adjacent electrodes, wherein the adjacent electrodes have opposite polarities, and wherein the dielectric has a relative dielectric constant of 10 or more and a dielectric constant between the adjacent electrodes. Paraelectric ceramic dielectrics below 300. Wide band gap devices are also on multilayer ceramic interposers.

[0018] The present invention relates to an improved power module, and more particularly to a power module particularly suitable for wide bandgap devices, wherein the power module includes an interposer with embedded or integrated capacitors. More specifically, the present invention relates to an improved package of high-power electronic equipment using an embedded multilayer ceramic capacitor structure to effectively integrate the capacitor body embedded in or integrated in the interposer of a module or a microprocessor. Together, not as separate components. [0019] In the embodiments of the present invention, especially as the switching frequency increases, low parasitic ESR and ESL decoupling capacitors are provided to reduce transient currents and improve the performance of the gate driver. In certain embodiments, soft switches such as zero voltage switching (ZVS), high voltage snubber capacitors, etc. are connected across the WBG switching devices to minimize the area of the induction loop from the WBG switch to the snubber capacitor, so as to increase with the switching frequency The increase in the buffer performance improves. [0020] As described herein, the gate driver of the WBG switch intermediary with integrated decoupling capacitors and buffer capacitors minimizes harmful parasitics of the circuit layout and increases power density by packaging the devices together. Encapsulation also reduces the volume of interconnections. [0021] The interposer of the present invention provides a high-voltage ceramic layer capable of isolating the gate driver input from the gate driver output. The integrated input filter can improve the anti-electrical noise performance and minimize the driver ringing caused by the quality of the input control signal. A timing capacitor is preferably integrated to control the cut-off time between WBG switching. [0022] Typical driver decoupling capacitors (D-Caps), switched snubber capacitors inductance loop area and power package volume form parasitic inductance ESL and resistance ESR related problems, usually using an intermediary including integrated capacitors to connect the gate The pole driver is connected to a WBG switch device for relief. [0023] A special problem in the prior art is the risk of accidentally turning on when the ringing exceeds the threshold voltage. The interposer of the present invention reduces the distance between the gate driver and the input gate of the switch. The decrease in distance can reduce the tendency of ringing. The integrated input filter capacitor of the intermediary can reduce the ringing caused by the quality of the input signal, thereby improving the anti-noise ability. It is best to provide an integrated timing capacitor that can control the cut-off time between WBG switching. [0024] Another advantage of the interposer of the present invention is to alleviate the problem of electrical isolation between the control input of the driver and the output of the WBG device and between the output channels of the gate driver. The intermediary provides a high-voltage electrical insulation area within the intermediary. [0025] The interposer integrated capacitor of the present invention can be combined with a shield electrode and a gap to provide further electrical isolation. The buffer can be integrated into the interposer to reduce the inductive loop using a wide band gap device, thereby helping to achieve zero voltage switching (ZVS). Another advantage is that the thermal buffer can be integrated into the interposer. [0026] Hereinafter, the present invention will be described with reference to the drawings of the integrated assembly disclosed herein, but it is not limited thereto. In each figure, similar elements will be labeled with corresponding numbers. [0027] Hereinafter, an embodiment of the present invention will be described with reference to FIG. 3, which shows the input, insulator, output, and buffer of a ceramic interposer in the form of a block diagram. In FIG. 3, the intermediary 300 is in electrical communication with a gate driver 302. The gate driver requires electrical isolation between input and output. There is an electrical isolation region 304 between at least one integrated buffer capacitor 306. The electrically isolated region 304 may also include a thermal buffer 316. An input filter resistor 308 is electrically connected to at least one integrated functional area 310, and preferably includes an integrated input filter and at least one decoupling capacitor. An integrated output area 312 is electrically connected to a gate drive current control resistor 314, wherein the integrated output area includes at least one output decoupling capacitor. [0028] Hereinafter, an embodiment of the present invention will be described with reference to FIG. 4, which shows an intermediary and a WBG switch in the form of a schematic circuit diagram. Most of the electrical functions are commercially available isolated dual-channel gate drivers using discrete surface mount capacitors. For example, a commercial driver UCC21530-Q1 from Texas Instruments can be used as an example, but is not limited to this. The circuit diagram shown in FIG. 4 is known to those skilled in the art, and therefore, there is no need for further elaboration except for the changes in the circuit design mentioned herein. [0029] FIG. 4 schematically shows a mediator input circuit 320. The intermediary input circuit includes a plurality of filter capacitors 322, which may be the same or different, to provide filtering out unwanted frequencies known in the art. In a particularly preferred embodiment, at least one filter capacitor, and more preferably all filter capacitors, is embedded in the interposer and uses a paradielectric capacitor (PDC) as described further in the following description. It is particularly preferred that the decoupling capacitor is embedded in the interposer. In a particularly preferred embodiment, any decoupling capacitor in the input circuit of the intermediary uses PDC. There is at least one decoupling capacitor 324 in the intermediary input circuit. As is known in the art, a timing capacitor 336 generally connected in parallel with a resistor controls the cut-off time between WBG switching. In a preferred embodiment, the timing capacitor is a PDC, which is preferably embedded in the intermediary. [0030] In FIG. 4, a mediator output circuit 338 is schematically shown. The mediator output circuit includes at least one decoupling capacitor 324. In a particularly preferred embodiment, any decoupling capacitor in the output circuit of the intermediary uses PDC, and preferably, the decoupling capacitor is embedded in the intermediary. Preferably, at least one decoupling capacitor 324 and at least one DC link capacitor 325 are provided in the intermediary output circuit to decouple one part of the circuit from another part, as is known in the art. [0031] In FIG. 4, the WBG switch 340 has a buffer capacitor 342 electrically in parallel with the WBG switch. The snubber capacitor is preferably embedded in an interposer, which provides a significantly reduced current path length for the circuit, thereby reducing the volume of the circuit and therefore the inductance. The buffer capacitor is preferably a PDC capacitor. [0032] The advantages of the present invention will be described below with reference to FIGS. 1 and 2. Referring to Figures 5 and 6, Figure 5 schematically shows a conventional commercially available gate drive printed circuit board (PCB) with electronic components arranged on a circuit board. FIG. 6 schematically shows the layout of the electronic components of the ceramic interposer as the gate driver in the embodiment of the present invention. For the sake of clarity, its wiring is not shown. In FIG. 5, the driver 400 is a ceramic interposer surface-mounted to the circuit board 401 by a common technique in the art. The resistor 404, the diode 406, the wide band gap device 408, and the snubber capacitor 410 are usually surface-mounted on the same side as the male side to minimize the current path length. The decoupling capacitor and the filter capacitor are collectively denoted by reference numeral 412, and are installed on the surface opposite to the driver 400, and are electrically connected through the through hole 414. [0033] In FIG. 6, the driver 400, the resistor 404, the diode 406, and the wide band gap device 408 are preferably mounted on the common surface of the ceramic interposer 420 on the circuit board 403, and the decoupling capacitor, Filter capacitors and buffer capacitors are embedded in the ceramic interposer as active layers, so these components are not visible in the layout. [0034] Compared with commercially available gate drivers, the interposer of the present invention has the advantage of reducing parasitic inductance, which is introduced by components with undesirable circuit board layout and longer package leads in the prior art of. The reduction of the current path length allows better optimization of the capacitors, preferably including the use of PDC capacitors, which can reduce the electronic ringing of the gate-source drive voltage of the power transistor during high dI/dt and dv/dt switching. . By reducing electronic ringing, ringing conditions that exceed the threshold voltage can be reduced, and the risk of accidental connection or even breakdown can be reduced. In the prior art device, the ringing is usually reduced by applying a negative bias on the gate driver. However, the intermediary of the present invention is unnecessary. This eliminates the negative or reverse bias power supply, thereby helping For further miniaturization. [0035] A special advantage of the ceramic intermediary of the present invention is that the thermal buffer 316 for lateral heat dissipation is integrated. Although it is suitable for existing technology equipment, due to space constraints, it is generally undesirable to use thermal buffer technology. With the interposer of the present invention, the area vacated due to the smaller package size can be reused as a space for heat dissipation or other components without increasing the overall size or exceeding the size occupied by the prior art device. [0036] In a particularly preferred embodiment, an improved power module package including an embedded capacitor is provided, wherein the embedded capacitor preferably includes a paradielectric referred to herein as a paradielectric capacitor (PDC). The use of PDC can further miniaturize the power module, and can operate at a higher voltage and higher frequency. Embedding the PDC in the substrate allows the volume of the substrate to provide embedded capacitors without sacrificing circuit area and without the need to install components. In addition, the circuit conduction paths that make up the power module are significantly minimized, which improves the ESR and ESL, thereby improving the electrical functions of the module. To facilitate miniaturization, capacitors must be able to work at higher voltages and frequencies. Although the interface temperature of capacitors may be as high as 250°C, they can still be packaged close to wide band gap (WBG) semiconductors. [0037] The embodiment of the present invention will be described below with reference to FIG. 7. Figure 7 shows a part of the module in an isolated view. The paradielectric capacitor (PDC) is indicated by the reference number 10. The PDC includes parallel planar internal electrodes 14 with opposite polarities between adjacent electrodes. Between adjacent electrodes is a paradielectric 12. The internal electrodes form a capacitive coupling, and the parallel plane internal electrodes and the paradielectric together form the active layer. The capacitively coupled external terminals 16 are in electrical contact with the alternating internal electrodes 14, thereby providing a capacitively coupled electrical connection to the PDC interface pad 18 or equivalent electrical connection, so that it can be electrically connected to the module described further below. At least one component 24. The manner of connecting to the interface pad is not particularly limited, and preferably can be connected by solder balls, solder posts or wire bonding. [0038] Hereinafter, an embodiment of the present invention will be described with reference to FIG. 8. The module 20 is shown in a partial schematic diagram in FIG. 8. The module includes at least one capacitive coupling, and preferably embeds the PDC 10 into the structural substrate 22 of the ceramic interposer. Optionally and preferably, at least one internal electrode of the PDC 10 is encapsulated in the paradielectric 12. The several components 24 mounted on the structural substrate, the structural substrate or in the structural substrate are electrically connected to each other and/or connected to the PDC to provide electrical functions required by the module, which is also referred to as an intermediary herein. A power supply 28 can provide power to the module, and the controller 26 can adjust the power supplied to a power receiving device 30. The circuit wiring between the PDC and the multiple components is not shown in FIG. 8 because the connection between the components is known in the art for how to form a module, and is not limited to this. [0039] The PDC 10, the structural substrate 22, and the component 24 can be combined together to form a microprocessor, which is optionally located in the module 20. The PDC embedded in the microprocessor is particularly suitable for use at lower voltages, for example, less than 200 volts. [0040] The PDC will be described below with reference to FIGS. 9-12, which schematically shows a multilayer ceramic capacitor including a paradielectric. In FIG. 9, for the convenience of discussion, a pair of internal electrodes 100 are labeled A and B. In fact, the internal electrodes are preferably the same. Each internal electrode has a capacitor area 102 and a number of wiring lugs 104. The internal electrodes and the paradielectrics between adjacent electrodes are stacked together, and the internal electrodes A and B are alternately arranged to align the capacitor regions and alternately connect the lugs. For example, each internal electrode A is aligned to form a stacked internal electrode. The stack is shown in the schematic top view of FIG. 10, where adjacent wiring lugs have alternating polarities. The entire assembly is preferably encapsulated in ceramic, preferably in a paraelectric medium. In the embodiment shown in FIG. 11, the external terminals 106 are in electrical contact with the common polarity alignment terminal lugs. When in use, the external terminal is used as a capacitive coupling terminal and then electrically contacts the PDC interface pad. The external terminal preferably includes at least one material selected from copper, nickel, tungsten, silver, palladium, platinum, gold, or a combination thereof. [0041] In the embodiment shown in FIG. 12, after the alignment wiring lugs having a common polarity are stacked, a through hole 108 passing through the stack is formed. The through holes are used as capacitive coupling terminals, which are then preferably in electrical contact with the PDC interface pads via external terminals, preferably on the surface of the PDC. The through hole provides a low thermal resistance path to remove excess heat in the module. In the preferred case of using a calcium zirconate-based dielectric with nickel internal electrodes, it is better to fill the through holes with copper. The exposed copper surface on the wiring lugs and through holes can be plated with nickel, silver, tin, gold, palladium or a combination thereof. The through holes can be formed by the pores of the dielectric tape used in the structure, or formed by machining in a green body or a sintered body. Those skilled in the art will also understand that they can be used for purely mechanical attachments when the internal electrodes are not in contact. In addition, the wiring on the surface of the component can be formed by screen printing copper with optional overplating to provide bonding pads and electrical contact areas to package other components in the module and contact the semiconductor. [0042] Hereinafter, an embodiment of the present invention will be described with reference to FIG. 13. For ease of discussion and clear description, a three-phase power module is shown in the schematic diagram. In FIG. 13, the first component is represented by an AC power source 200. The second component is represented by the electromagnetic interference or radio frequency interference filter EMI/RFI 202, which can be surface-mounted and integrated into the AC power supply or the EMI/RFI can be embedded in the structure substrate 22 of the ceramic intermediary, as shown in the figure, capacitive coupling The terminals 16 ¹ -16 ³ terminate at the PDC interface pads 18 ¹ -18 ³ . A representative EMI/RFI filter is schematically indicated as A in FIG. 14. In an embodiment, at least the capacitor of the EMI/RFI filter is an embedded PDC as described herein. AC component to the third harmonic filter 204 is preferably indicated by the received ^2011-2013 EMI internal electrodes / RFI energy filtered. A representative AC harmonic filter is schematically indicated by the symbol B in FIG. 14. In one embodiment, the capacitors and inductors of the AC harmonic filter are embedded PDCs as described herein. The fourth component, labeled AC/DC converter 206, can be used to convert an AC signal to a DC signal. The AC/DC converter can be ^{electrically connected to the AC harmonic filter through capacitive coupling terminals 16 4} -16 ⁶ which are coupled to the PDC interface pads 18 ⁴ -18 ⁶ to minimize the conductive path length. Between the AC/DC converter and the fifth component designated as DC/AC inverter 214, there are embedded components of buffers 208, 212 and a DC link capacitor 210. A representative buffer labeled C is schematically shown in FIG. 14, and a representative DC link capacitor labeled D in FIG. 14 is shown schematically. The capacitor of the buffer is preferably an embedded PDC electrically connected to the PDC interface pads 18 ⁷ -18 ^{10 through the capacitive coupling terminals 16 7} -16 ^10. DC link capacitor are preferably embedded PDC, and preferably electrically connected to each of the buffers via the internal electrodes ^2013-2016. The use of internal electrodes improves Faraday shielding, thereby minimizing EMI noise emitted by the module. [0043] In certain circuit designs, it is advantageous to have the lowest equivalent series inductance (ESL) and/or the lowest equivalent series resistance (ESR) to obtain the best performance. The structure contains multiple capacitors of opposite polarity to minimize ESL. As will be understood from FIG. 15, as described above for FIGS. 9 to 10, layers A and B are alternately stacked so that the two capacitive couplings can be in a common structure, in which adjacent external terminals It has the opposite polarity so that ESL can be minimized. [0044] In order to prevent the circuit from ringing, it is sometimes desirable to increase the ESR of the capacitor. By increasing the path length in the internal electrodes of the PDC, the ESR in the PDC can be increased. It can be understood from FIG. 16 that a larger overlap area can be achieved by using rectangular internal electrodes as in a PDC with a dielectric between alternating layers A-1 and B-1. As shown from left to right in Figure 16, as the path length and the width decrease, the ESR can be increased. By combining the number of capacitors and electrode shapes, ESL and/or ESR can be optimized. [0045] Using these techniques, it is possible to optimize the performance of the module or intermediary containing the PDC. [0046] Low inductance is beneficial because in WBG semiconductor applications, a higher switching current edge rate dI/dt and a higher switching frequency will produce a larger voltage ringing to drive an inductive load. The snubber capacitor is located adjacent to the switch package to help reduce this ringing. Integrating the buffer in the substrate can further reduce the total loop inductance from the buffer to the switching device, thereby maximizing the advantages of the buffer. [0047] Embedded PDC together with other components can make modules or electronic packages suitable for many applications. Figure 17 schematically shows a flying capacitor circuit. Figure 18 schematically shows a zero voltage switching (ZVS) metal oxide semiconductor field effect transistor (MOSFET) circuit. Fig. 19 schematically shows the H-bridge circuit of the MOSFET. Fig. 20 schematically shows an integrated rectifier capacitor. [0048] In the example with 2 switching units shown in FIG. 17, the multi-stage flying capacitor inverter rectification loop inductance is a limiting factor. Adding an additional integrated rectifier capacitor near the switch can improve the rectification performance. In the soft switch as shown in Figure 18, when the load current changes direction and the zero voltage switch (ZVS) is activated, the buffer can be used to provide charging and discharging currents. [0049] In the four switching circuits shown in FIG. 19 and FIG. 20, adding capacitance near the switch can improve the performance of a high smoothing capacitor such as a DC link or a flying capacitor located slightly away from the switching device. [0050] Hereinafter, an embodiment of the present invention will be described with reference to FIG. 24. In FIG. 24, a module 218 may be a component of a ceramic interposer, and has at least one heat dissipation layer 20 on it that contacts at least one semiconductor 19. The heat dissipation layer helps to dissipate heat from the module laterally. At least one capacitor, preferably PDC10, is in electrical contact with the semiconductor, preferably with the heat dissipation layer between the semiconductor and the PDC. The PDC can be electrically connected to the semiconductor through an insulating through hole 222 through a heat dissipation layer, wherein the insulating through hole has a conductive core 226 and an insulator 224 that electrically isolates the conductive core from the heat dissipation layer in the through hole extending through the heat dissipation layer . [0051] Using PDCs with through holes (especially through holes) can provide an alternative to separate packaging. Using well-known techniques in the prior art, such as solder ball bonding, the obtained capacitors PDC are packaged into a microprocessor to form an integrated microprocessor-capacitor assembly. Consider packaging other types of components as part of the PDC. These components include ESD suppressors, inductors, and other components. [0052] A typical high-power substrate with various metallizations formed of oxides _{such as Al 2} O ₃ , BeO, AlN, Si ₃ N _{4 can be used as a heat dissipation layer.} For example, AlN and BeO are valued for their high thermal conductivity. For example, AlN has a thermal conductivity of 140-200 W/mK. However, BeO is poisonous, and the reliability of copper metallization of AlN is problematic. _{For these reasons, Si 3} N ₄ having a thermal conductivity of 35-60 W/mK and brazing Al is suitable as an exemplary example of the present invention. In order to improve the thermal conductivity of the PDC in the z direction, materials with higher thermal conductivity are preferred. The PDC may incorporate a cover layer on the last layer of the active internal electrode, which cover layer includes a higher thermal conductivity material than the PDC dielectric. Those skilled in the art will understand that this can be achieved by using an insulating bonding layer or more practically firing a cover layer containing a high thermal conductivity dielectric with the PDC during the manufacturing process. In the CaZrO ₃ based dielectric, due to its high affinity for oxygen, it can be used in combination with air-sensitive materials (such as AlN, Si ₃ N ₄ ). In the reducing atmosphere required for sintering metal-poor electrodes and non-oxide ceramics, oxygen will not be lost during the firing process. Other oxide ceramics will lose oxygen, so the resulting vacancies will subsequently migrate under the electric field, thus compromising reliability. This behavior of calcium zirconate makes the combination with non-oxide base materials feasible. When considering the coefficient of thermal expansion (CTE), the ability to effectively _{bond CaZrO 3} to these non-oxide base materials is also important. This is because it is important to minimize the mismatch between CTE and reliability improvement. The CTE of calcium zirconate is 8.4 PPM/℃, which is close to the 8-10 PPM/℃ of _{commercial Al 2} O _{3 and BeO-based substrates.} However, non-oxide base materials such as AlN and Si ₃ N ₄ have a low CTE of 3.3-5.6 PPM/°C. Therefore, _{effective combination of these materials with CaZrO 3} can solve this mismatch problem. [0053] A particularly preferred material for the heat dissipation layer is a dielectric having a lower dielectric constant than that of PDC. The heat dissipation layer including the dielectric constant lower than that of PDC ceramics has a special advantage in high-frequency performance. [0054] In another embodiment, the problems related to the internal self-heating of the PDC can be alleviated by adding at least one heat dissipation channel (preferably continuous) through the main body of the PDC, so that the core of the PDC The temperature is reduced by the heat transfer medium. Although in high-power applications, the internal electrodes of the PDC can more effectively dissipate heat to the terminals through the electrode surface, there is still a need for more effective heat dissipation. The heat-conducting medium can be static with limited flow, or it can flow in and pass through the heat dissipation channel to promote the heat energy to be transferred from the inside of the MLCC. [0055] Hereinafter, embodiments of the present invention will be described with reference to FIGS. 25 and 26, in which a PDC shown in the side cross-sectional view of FIG. 25 and the end cross-sectional view of FIG. 26 is marked with the reference number 110. In Figures 25 and 26, the PDC includes staggered parallel internal electrodes 112 and 114 and a dielectric 116 between the internal electrodes and external terminals 118, 120 of opposite polarity. The heat dissipation channel 122 parallel to the internal electrode preferably passes through at least one surface of the capacitor body, and more preferably provides a continuous channel through the capacitor body. The end of the heat dissipation channel or the heat dissipation port is preferably located on the surface of the capacitor body where there is no external terminal, so as to allow the heat dissipation port 124 of the channel to enter and exit the heat dissipation port 124 to allow the heat transfer medium to enter one heat dissipation port of the heat dissipation channel and preferably leave the other heat dissipation port Cooling channel. Optional pillars 126 that span the height of the heat dissipation channel may be provided to improve structural integrity or provide turbulence to reduce laminar flow, thereby increasing the rate of heat conduction between the capacitor body and the thermally conductive medium. The post preferably does not extend the entire width of the capacitor, for example, from the heat dissipation port to the heat dissipation port. In the embodiment of FIGS. 25 and 26, the heat dissipation channel is defined by ceramic on all sides, and there is no contact point between the heat dissipation channel and the internal electrodes 112 and 114. Ceramic is not an effective heat conductor, therefore, the heat dissipation channel is defined by ceramic on all sides. Ceramics lack thermal conductivity. However, ceramics are not electrically conductive, which allows a wider range of thermally conductive media, so this embodiment is advantageous in certain applications. [0056] In an alternative embodiment, the heat dissipation channel is defined by ceramics on three sides, and a part on at least one side is defined by internal electrodes. In another alternative embodiment, the heat dissipation channel is defined by ceramic on both sides and internal electrodes on at least a portion of both sides, as described in U.S. Patent No. 10,147,544, which is incorporated herein by reference. A particular advantage of the heat dissipation channel defined by the at least one internal electrode is the enhanced heat conduction provided by the internal electrode, which is generally more effective than ceramic in terms of heat conduction. If the heat-conducting medium is in contact with the internal electrode, it is preferable that the heat-conducting medium is non-conductive and non-corrosive. [0057] Hereinafter, an embodiment of the present invention will be described with reference to FIG. 27, in which the PDC of the present invention shown in a side sectional view is indicated by the reference number 110. In FIG. 27, the PDC includes a plurality of heat dissipation channels 122 with electrical insulation barriers 127, wherein the heat dissipation channels are arranged in a plurality of common heat dissipation channel planes, and each of the common heat dissipation channel planes is parallel to the internal electrode. Those skilled in the art will appreciate that the described thermal buffer can be applied to multiple independent capacitors in the intermediary. [0058] Hereinafter, an embodiment of the present invention will be described with reference to FIG. 28, which is a schematic cross-sectional view showing a PDC. In FIG. 28, the external terminals 118 and 120 and the dielectric 116 are as described above. The shielding electrodes 128 and 129 shown are defined as coplanar electrodes located on the outermost inner electrodes with opposite polarities in the PDC. The shield electrode prevents arcing from the external terminal to the internal electrode with the opposite polarity. For example, the electrodes 128 and 129' prevent arcing between the external terminals and the closest internal electrodes 130 and 131 of opposite polarity. The heat dissipation channel 122 is coplanar with the opposite coplanar internal electrodes 132 and 134 of opposite polarity. In the embodiment shown in FIG. 28, as described above, the heat dissipation channel is defined by ceramic on all sides. [0059] Hereinafter, an embodiment of the present invention will be described with reference to FIG. 29, which is a schematic cross-sectional view showing a PDC. The PDC of FIG. 29 includes coplanar active internal electrodes 136 and 138 with opposite polarities and a floating electrode 140 parallel to the coplanar active internal electrode, and preferably each floating electrode has a coplanar adjacent to each side Active internal electrodes. The active electrode is defined herein as an internal electrode that is in electrical contact with an external terminal. Floating electrodes are internal electrodes that are not in electrical contact with external terminals. At least one heat dissipation channel 122 is coplanar with the coplanar active electrode with opposite polarity. [0060] Hereinafter, an embodiment of the present invention will be described with reference to FIG. 30, which is a schematic cross-sectional view showing a PDC. The PDC of FIG. 30 includes coplanar active internal electrodes 136 and 138 with opposite polarities and a floating electrode 140 parallel to the coplanar active internal electrode, and preferably each floating electrode has a coplanar adjacent to each side Active internal electrodes. At least one heat dissipation channel 122 is coplanar with the coplanar active electrode with opposite polarity, and can optionally be in fluid contact with the internal electrode. [0061] Hereinafter, an embodiment of the present invention will be described with reference to FIG. 31, which is a schematic cross-sectional view showing a PDC. In FIG. 31, the inside of the heat dissipation channel 122 is coated with an optional coating 130, which is preferably a thermally conductive coating, thereby increasing the heat conduction between the ceramic and the thermally conductive medium 128. The coated material is not particularly limited to a preferred material that can be coated on the dielectric and can provide sufficient thermal conductivity from the dielectric to the thermally conductive medium. Hereinafter, an embodiment of the present invention will be described with reference to FIG. 32. In FIG. 32, a PDC 110 has a heat dissipation channel 122, which is not parallel to the electrodes 112, 114 and is preferably straight to the electrode. By passing through the heat dissipation channel of the electrode, a higher contact can be formed between the heat transfer medium and the internal electrode. In one embodiment, the thermally conductive medium is non-conductive. In another embodiment, a thermally conductive but electrically insulating coating may be applied to the inside of the heat dissipation channel. [0062] Hereinafter, an embodiment of the present invention will be described with reference to FIG. 33. In FIG. 33, a module 218 has a PDC 110 mounted on at least one semiconductor 19, wherein the PDC includes at least one through heat dissipation channel, wherein the heat dissipation channel is parallel to the electrodes, perpendicular to the electrodes, or at an intermediate angle between the electrodes. The cooling device 228 can dissipate the heat collected through the heat dissipation channel. The cooling device may be a passive device that dissipates heat by interacting with a medium such as a radiator, preferably air. Alternatively, the cooling device may be an active device that dissipates heat through electrical, mechanical, or chemical methods, such as through adiabatic expansion, flowing media, or through Peltier technology. [0063] Thermally conductive inorganic or organic materials including metals, thermally conductive ceramics, polymers, and combinations thereof are particularly suitable for use in the present invention. Silicone thermal grease is particularly preferred due to its high thermal conductivity, low heat resistance, cost, processability and reusability. As a non-limiting example of the present invention, for example, Dow Corning® TC-5026, Dow Corning® TC-5022, Dow Corning® TC-5600, Dow Corning® TC-5121, Dow Corning® SE4490CV, Dow Corning® SC 102 can be used. ; Dow Corning®340 radiator; Shin-Etsu MicroSI®X23-7853W1, Shin-Etsu MicroSI®X23-7783 D, Shin-Etsu MicroSI®G751 and Shin-Etsu MicroSI®X23-7762D are particularly suitable for use in heat dissipation channels coating. [0064] The heat transfer medium may be a static or flowing gas or liquid to improve heat transfer. Non-conductive materials are particularly preferred. Perfluorinated hydrocarbons, nanofluids, mineral oils and ethers are particularly suitable due to their high thermal conductivity and minimal electrical conductivity. As non-limiting examples, for example, Galden®HT55, Galden®HT70, Galden®HT80, Galden®HT110, Galden®HT135, Galden®HT170, Galden®HT200, Galden®HT230 and Galden®HT270 can be used particularly suitable as the present invention. Thermally conductive medium. Gases such as air, at least partially dried air or inert gases are particularly suitable as heat transfer media. [0065] During the PDC manufacturing process, a variety of technologies can be used to form the heat dissipation channel. The ceramic precursor layer may be printed with a sacrificial organic material or carbon in a predetermined pattern corresponding to the heat dissipation channel. During the baking and co-firing of the PDC, the sacrificial organic material or carbon is preferably removed by evaporation. The area of the ceramic tape can be removed before the lamination of the PDC, or the heat dissipation channel can be processed before or after baking and sintering. [0066] As known in the art, the PDC is prepared by stacking a ceramic precursor and a conductor precursor in an appropriate alignment sequence. After a sufficient number of layers have been established, the assembly is heated to form alternating layers of internal conductors and sintered ceramics, and heat dissipation channel precursors are formed in the ceramic layers. [0067] In each layer prepared to form a heat dissipation channel, a pattern of pre-channel material corresponding to the heat dissipation channel is printed. After sintering, the pre-channel material vaporizes, leaving gaps in the shape of the printed pre-channel material. A non-volatile material (preferably ceramic) can be added to the pre-channel material to form a support in the gap. [0068] The pre-channel material may be any material that is applied in a predetermined pattern and leaves the heat dissipation channel as a gap when the layer is sintered. A particularly preferred material is electrode ink that does not include metal. Such materials are preferred because they are readily available and inherently adaptable to the manufacturing environment. Another particularly suitable material is a binder used with ceramic precursors, excluding ceramic precursors. [0069] Large-area structural substrates generally do not have electrical functions. Redistributing these areas to form embedded capacitors can increase the overlap area for capacitive coupling without increasing the overall volume of the module. These advantages, coupled with the high dielectric constant of the dielectric, can provide a high capacitance value in the power module area, otherwise the area will not be able to achieve electrical functions. In addition, by incorporating high-voltage capacitors in the structure, surface arcs between components of opposite polarity are basically eliminated, which is a major advantage over surface-adhesive independent components. [0070] The ceramic materials used in the construction of the PDC are essential for reliable functions and higher voltages (for example, voltages above 200V). This is because the multilayer ceramic structure can be firmly coupled with the high voltage that causes mechanical displacement of the ceramic actuator. In ferroelectric materials and anti-ferroelectric materials, this electrical coupling is very high, which can cause malfunctions in high-voltage capacitors. Therefore, the preferred ceramic material is a paraelectric material with a low electrocoupling coefficient. Particularly preferred is a paraelectric medium having a relative dielectric constant of 10 or more and no more than 300, more preferably at least 25 and no more than 175. Particularly preferred paradielectrics include calcium zirconate, non-stoichiometric barium titanium oxide, such as Ba ₂ Ti ₉ O ₂₀ ; BaTi ₄ O ₉ ; barium rare earth oxide containing neodymium or magma, titanium dioxide doped with various additives, Calcium titanate, strontium titanate, strontium zirconate, zinc magnesium titanate, zirconium tin titanate, zinc bismuth niobate, zinc bismuth tantalate, and combinations thereof. In particular, the dielectrics of Type 1 EIA are particularly preferred, especially those containing at least 50% by weight of calcium zirconate. In addition, temperature-stable dielectrics that can comply with COG specifications are most preferred. C0G represents a dielectric with a temperature coefficient of + 30 ^{o C.} Use of calcium zirconate PDC can reach the rated voltage of 1V to 10,000V at least 260 ^o C operating temperature, more preferably to the rated voltage of 20,000V. Using calcium zirconate with a relative permittivity of 32 as a dielectric, a PDC with a rated voltage of 500V to 10,000V can be obtained. The capacitance per unit volume at 500V is 1.0µF/cc, and the electrical capacity per unit volume at 10,000V The capacity is at least 0.003µF/cc, and it is suitable for the rated operating temperature range of ^{-65 to 300 oC} and the highest rated temperature of ^{150 to 300 oC.} [0071] The structural substrate suitable for the present invention is not particularly limited herein, provided that it can withstand the voltage and temperature range expected in high-voltage, high-switching frequency applications. Those skilled in the art will understand that the structural substrate does not interfere with the function of the PDC, and if the structural substrate is conductive, the PDC is electrically isolated from the structural substrate. Non-conductive substrates are preferred. Particularly preferred structural substrates include ceramics such as alumina, such as 96% Al ₂ O ₃ or 99.6% Al ₂ O ₃ ; aluminum nitride silicon nitride or beryllium oxide; G10; FR (flame retardant) materials, For example FR 1-6, FR 4 (composite materials of epoxy resin and glass), FR2 using phenolic paper or phenolic cotton and paper; composite epoxy materials (CEM), such as CEM 1, 2, 3, 4, 5; insulation Metal substrates, such as aluminum substrates available from Bergquist Mfg, and flexible circuits including materials such as polyimide. Laminates, fiber reinforced resins, ceramic filled resins, special materials and flexible substrates are particularly suitable. Flame-retardant (FR) laminates are particularly suitable for use as interlayer materials, especially FR-1, FR-2, FR-3, FR-4, FR-5 or FR-6. FR-2 is phenolic paper, phenolic cotton paper or phenolic resin impregnated paper. Particularly preferred is FR-4, which is a glass fiber woven cloth impregnated with epoxy resin. Composite epoxy materials (CEM) are suitable, especially CEM-1, CEM-2, CEM-3, CEM-4 or CEM-5, each of which contains reinforcing materials, such as tissue paper, non-woven glass or rings. ??????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????? Oxygen woven glass. Glass substrates (G) are widely used, such as G-5, G-7, G-9, G-10, G-11, etc., among which G-10 and G-11 are the most preferred, each of which is Glass epoxy. Polytetrafluoroethylene (PTFE) can be ceramic-filled or glass fiber reinforced, such as RF-35, which is a particularly suitable substrate. Polyetheretherketone (PEEK) is also a suitable polymer, especially due to its high temperature resistance. Electronic grade ceramic materials, such as available alumina or yttria-stabilized zirconia, of which 96% Al ₂ O ₃ and 99.6% Al ₂ O _{3 are} easily commercially available. Bismaleimide-triazine (BT) epoxy resin is a particularly suitable substrate. The flexible substrate is usually a polyimide, such as the commercially available Kapton or UPILEX polyimide foil or the commercially available Pyralux polyimide-fluoropolymer composite. These substrates may contain leads made of ferrous alloys (such as Alloy 42, Insteel, Kovar) or non-ferrous materials (such as copper, phosphor bronze, or beryllium copper). [0072] The components can be selected from transistors, capacitors, diodes, resistors, varistors, inductors, fuses, integrated circuits, overvoltage discharge devices, sensors, switches, electrostatic discharge suppressors, Inverter, rectifier and filter. Particularly preferred transistors are wide band gap elements based on GaN and SiC. These components are preferably integrated into functional devices such as AC/DC converters, DC/AC inverters, EMI/RFI filters, buffers, harmonic filters, especially AC harmonic filters. [0073] The internal electrode preferably contains base metals such as nickel, copper, or precious metals/semi-precious metals such as silver, palladium, tungsten, platinum, or gold, or a combination thereof, with nickel or nickel alloys being preferred. The preferred nickel alloy includes at least one selected from the group consisting of manganese, chromium, cobalt and aluminum, and this nickel alloy preferably contains at least 95% by weight of nickel. It should be noted that nickel and nickel alloys may contain up to about 0.1% by weight of phosphorus and other trace components. Example [0074] A PDC including a paradielectric and nickel electrodes of the first group as shown in FIG. 16 was prepared. The electrodes are separated by calcium zirconate as a dielectric, and the size of the PDC is 3.1cm x 5cm x 0.3cm (cm). The thickness of the dielectric was selected based on the sample reliability of the BME C0G MLCC rated at 650 VDC. A typical MLCC manufacturing process is used to make a PDC containing 110 active layers. Figure 23 is a scanned image of CSAM, showing no signs of cracks, delamination, or structural-related defects. The final capacitance of the PDC is 2.7µF, and the resulting capacitance (µF)/volume (CC) is 0.58µF/cc. [0075] The data presented in FIGS. 21 and 22 indicate that the capacitance (µF)/volume (cc) can reach 1.0 to 0.003 when the K value of a dielectric of 500V to 10,000V is 32. When the same results are used for dielectrics with K values of 300 and 10, the capacitance (µF)/volume (cc) can be expected to be 9.8 to 0.020 and 0.33 to 0.001, respectively. [0076] The present invention has been described with reference to the preferred embodiments, but is not limited thereto. Those skilled in the art will be aware of other embodiments and modifications within the scope of the present invention that are not specifically described herein but are more specifically set forth in the scope of the appended application.

[0077] 10: Paradielectric capacitor 12: Paraelectric medium 14: Internal electrode 16: Capacitive coupling terminal 18: Interface pad 19: Semiconductor 20: Module 22: Structural substrate 24: components 26: Controller 28: Power 30: Powered equipment 100: Internal electrode 102: Capacitance area 104: Wiring lug 106: External terminal 110: Paradielectric capacitor 112, 114: Internal electrodes 116: Dielectric 118, 120: External terminals 122: cooling channel 124: radiator 127: Electrical Insulation Barrier 128, 129: shield electrode 130, 131: internal electrodes 132, 134: Internal electrodes 136, 138: internal electrodes 140: Floating electrode 200: AC power 201: Internal electrode 202: filter 204: AC harmonic filter 206: AC/DC converter 208: Buffer 210: DC link capacitor 212: Buffer 214: DC/AC inverter 218: Module 222: Through hole 224: Insulator 226: Conductive core 228: Cooling Device 300: Mediator 302: Gate Driver 304: Electrical isolation zone 306: snubber capacitor 308: Input filter resistor 310: Integrated function area 312: Integrated output area 314: Gate drive current control resistor 316: Thermal buffer 320: Intermediary input circuit 322: filter capacitor 324: Decoupling capacitor 325: DC link capacitor 336: timing capacitor 338: Mediator output circuit 340: WBG switch 342: snubber capacitor 400: drive 401: circuit board 403: circuit board 404: resistor 406: Diode 408: wide band gap device 410: snubber capacitor 412: Decoupling capacitor and filter capacitor 414: Through hole 420: ceramic intermediary

[0017] Figure 1 shows the graph of the relationship between capacitance and frequency at various power levels at 400V and 10% chain wave voltage. Figure 2 shows the graph of the relationship between capacitance and frequency at various power levels at 1200V and 10% chain wave voltage. Figure 3 is a block diagram of the present invention. Figure 4 is a circuit diagram of the present invention. Figure 5 is a schematic diagram of a prior art device. Figure 6 is a schematic diagram of the device of the present invention Fig. 7 is a schematic diagram of an embodiment of the present invention. Fig. 8 is a schematic diagram of an embodiment of the present invention. Figures 9-12 are schematic diagrams of an embodiment of a PDC in the present invention. Figure 13 is a schematic diagram of an embodiment of the present invention. Figure 14 is a schematic diagram of an embodiment of a representative component of the present invention. Figures 15-16 show schematic diagrams of internal electrode patterns suitable for the present invention. Figures 17-20 are schematic diagrams of embodiments of the present invention. Figures 21-22 are diagrams of embodiments of the present invention. Figure 23 is an image of an embodiment of the present invention. Fig. 24 is a schematic diagram of an embodiment of the present invention. Figure 25 is a schematic diagram of an embodiment of the present invention. Fig. 26 is a schematic diagram of an embodiment of the present invention. Fig. 27 is a schematic diagram of an embodiment of the present invention. Fig. 28 is a schematic diagram of an embodiment of the present invention. Figure 29 is a schematic diagram of an embodiment of the present invention. Fig. 30 is a schematic diagram of an embodiment of the present invention. Figure 31 is a schematic diagram of an embodiment of the present invention. Fig. 32 is a schematic diagram of an embodiment of the present invention. Figure 33 is a schematic diagram of an embodiment of the present invention.

300: Mediator

302: Gate Driver

304: Electrical isolation zone

306: snubber capacitor

308: Input filter resistor

310: Integrated function area

312: Integrated output area

314: Gate drive current control resistor

316: Thermal buffer

Claims (73)

A gate drive intermediary with integrated passive components for wide band gap semiconductor devices, including: A ceramic intermediary, including multiple layers; Wherein the active layer in the multilayer forms an embedded capacitor, the embedded capacitor including a plurality of parallel electrodes and a dielectric between adjacent electrodes, wherein the adjacent electrodes have opposite polarities; and A wide band gap device is located on the multilayer ceramic intermediary. The gate drive intermediary with integrated passive components for wide band gap semiconductor devices according to claim 1, wherein at least one of the embedded capacitors is selected from the group consisting of decoupling capacitors, buffer capacitors, and timing capacitors , One of filter capacitor and DC link capacitor. The gate drive intermediary with integrated passive components for wide band gap semiconductor devices according to claim 1 includes at least one gap region to electrically isolate the embedded capacitor. The gate drive intermediary with integrated passive components for wide band gap semiconductor devices according to claim 1, wherein the dielectric is a paraelectric ceramic dielectric having a relative permittivity higher than 10 and lower than 300. The gate drive intermediary with integrated passive components for wide band gap semiconductor devices according to claim 4, wherein the dielectric constant is at least 25 to not more than 175. The gate drive intermediary with integrated passive components for wide band gap semiconductor devices according to claim 4, wherein the paradielectric medium is a COG dielectric. The gate drive intermediary with integrated passive components for wide band gap semiconductor devices according to claim 4, wherein the paradielectric includes calcium zirconate. The gate drive intermediary with integrated passive components for wide band gap semiconductor devices according to claim 7, wherein the paradielectric includes at least 50% by weight of calcium zirconate. The gate drive intermediary with integrated passive components for wide band gap semiconductor devices according to claim 4, further comprising at least one PDC interface bonding pad. The gate drive intermediary with integrated passive components for a wide band gap semiconductor device according to claim 9, wherein the wide band gap device is in electrical contact with the PDC interface pad. The gate drive intermediary with integrated passive components for wide band gap semiconductor devices according to claim 10, wherein the PDC interface pads are made of solder balls, solder pillars, wire bonding, thick film paste or other Metallurgical bonding is connected to the semiconductor device. The gate drive intermediary with integrated passive components for wide band gap semiconductor devices according to claim 1, wherein the electrode includes copper, nickel, tungsten, silver, palladium, platinum, or gold. The gate drive intermediary with integrated passive components for wide band gap semiconductor devices according to claim 12, wherein the electrode includes nickel. The gate drive intermediary with integrated passive components for wide band gap semiconductor devices according to claim 1, further comprising external terminals. The gate drive intermediary with integrated passive components for wide band gap semiconductor devices according to claim 14, wherein the external terminal is in electrical contact with the electrode, and the external terminal includes copper, nickel, Tungsten, silver, palladium, platinum, or gold. The gate drive interposer with integrated passive components for a wide band gap semiconductor device according to claim 15, wherein the external terminal is in electrical contact with the electrode through a through hole in the ceramic interposer. The gate drive intermediary with integrated passive components for wide band gap semiconductor devices according to claim 1, wherein the ceramic intermediary further includes a gate driver. The gate drive intermediary with integrated passive components for wide band gap semiconductor devices according to claim 17, wherein the ceramic intermediary includes at least one selected from the group consisting of a transistor, a capacitor, a diode, and a resistor , Varistors, inductors, fuses, integrated circuits, overvoltage discharge devices, sensors, switches, electrostatic discharge suppressors, inverters, rectifiers, filters and components of one of the group of electrically isolated power supplies. The gate drive intermediary with integrated passive components for wide band gap semiconductor devices according to claim 18, wherein the electrically insulated power source is a reverse bias power source. The gate drive intermediary with integrated passive components for wide band gap semiconductor devices according to claim 1, wherein at least one of the embedded capacitors has a rated voltage of 1V to 20,000V. The gate drive intermediary with integrated passive components for wide band gap semiconductor devices according to claim 20, wherein the rated voltage of the embedded capacitor is 500V to 10,000V, and the unit volume of electricity at 500V The capacity is at least 1.0μF/cc, and the electric capacity per unit volume at 10,000V is at least 0.003μF/cc. The gate drive intermediary with integrated passive components for wide band gap semiconductor devices according to claim 1, wherein at least one of the embedded capacitors includes at least one heat dissipation channel. The gate drive intermediary with integrated passive components for wide band gap semiconductor devices according to claim 22, wherein at least one of the heat dissipation channels is selected from being parallel to and connected to the internal electrode vertical. The gate drive intermediary with integrated passive components for wide band gap semiconductor devices according to claim 22, wherein the embedded capacitor is located between the semiconductor and a cooling device. The gate drive intermediary with integrated passive components for wide band gap semiconductor devices according to claim 24, wherein the cooling device is selected from a passive device and an active device. The gate drive intermediary with integrated passive components for wide band gap semiconductor devices according to claim 1, further comprising at least one component in electrical contact with at least one of the capacitors. The gate drive intermediary with integrated passive components for wide band gap semiconductor devices according to claim 26, wherein the components are selected from the group consisting of transistors, capacitors, diodes, resistors, and varistors Resistors, inductors, fuses, integrated circuits, over-voltage discharge devices, sensors, switches, electrostatic discharge suppressors, inverters, rectifiers, filters, and electrically isolated power supplies are a group of components. The gate drive intermediary with integrated passive components for wide band gap semiconductor devices according to claim 26, wherein the electrically insulated power source is a reverse bias power source. The gate drive intermediary with integrated passive components for wide band gap semiconductor devices according to claim 1, wherein at least one of the capacitors includes a through hole. The gate drive intermediary with integrated passive components for wide band gap semiconductor devices according to claim 1, wherein at least one of the internal electrodes is in electrical contact with an external terminal through a through hole. The gate drive intermediary with integrated passive components for wide band gap semiconductor devices according to claim 1, further comprising a heat dissipation layer. 31. The gate drive intermediary with integrated passive components for wide band gap semiconductor devices according to claim 31, wherein the heat dissipation layer is located between the embedded capacitor and the semiconductor device. The gate drive interposer with integrated passive components for wide band gap semiconductor devices according to claim 32, further comprising at least one through hole passing through the heat dissipation layer. The gate drive intermediary with integrated passive components for wide band gap semiconductor devices according to claim 33, wherein the through hole is an insulating through hole. The gate drive intermediary with integrated passive components for wide band gap semiconductor devices according to claim 1, further comprising at least one switch. The gate drive intermediary with integrated passive components for wide band gap semiconductor devices according to claim 35 includes a buffer capacitor electrically connected in parallel with the at least one switch. The gate drive intermediary with integrated passive components for wide band gap semiconductor devices according to claim 35, wherein the buffer capacitor is a PDC. A gate drive intermediary with integrated passive components for wide band gap semiconductor devices, including: A ceramic intermediary, including multiple layers; The active layer in the multilayer forms an embedded capacitor, the embedded capacitor includes a plurality of parallel electrodes and a dielectric between adjacent electrodes, wherein the adjacent electrodes have opposite polarities, and wherein the dielectric has opposite polarities. Paraelectric ceramic dielectrics with a dielectric constant above 10 and below 300; and A wide band gap device is located on the multilayer ceramic intermediary. The gate drive intermediary with integrated passive components for wide band gap semiconductor devices according to claim 38, wherein at least one of the embedded capacitors is selected from the group consisting of decoupling capacitors, buffer capacitors, and timing capacitors , One of filter capacitor and DC link capacitor. The gate drive intermediary with integrated passive components for wide band gap semiconductor devices according to claim 38 includes at least one gap region to electrically isolate the embedded capacitor. The gate drive intermediary with integrated passive components for wide band gap semiconductor devices according to claim 38, wherein the dielectric constant is at least 25 and not more than 175. The gate drive intermediary with integrated passive components for wide band gap semiconductor devices according to claim 38, wherein the paradielectric medium is a COG dielectric. The gate drive intermediary with integrated passive components for wide band gap semiconductor devices according to claim 38, wherein the paradielectric includes calcium zirconate. The gate drive intermediary with integrated passive components for wide band gap semiconductor devices according to claim 43, wherein the paradielectric includes at least 50% by weight of calcium zirconate. The gate drive intermediary with integrated passive components for wide band gap semiconductor devices according to claim 38 further includes at least one PDC interface bonding pad. The gate drive intermediary with integrated passive components for a wide band gap semiconductor device according to claim 45, wherein the wide band gap device is in electrical contact with the PDC interface pad. The gate drive intermediary with integrated passive components for wide band gap semiconductor devices according to claim 46, wherein the PDC interface pads are made of solder balls, solder pillars, wire bonding, thick film paste or other Metallurgical bonding is connected to the semiconductor device. The gate drive intermediary with integrated passive components for wide band gap semiconductor devices according to claim 38, wherein the electrode includes copper, nickel, tungsten, silver, palladium, platinum, or gold. The gate drive intermediary with integrated passive components for wide band gap semiconductor devices according to claim 48, wherein the electrode includes nickel. The gate drive intermediary with integrated passive components for wide band gap semiconductor devices according to claim 38 further includes external terminals. The gate drive intermediary with integrated passive components for wide band gap semiconductor devices according to claim 50, wherein the external terminal is in electrical contact with the electrode, and the external terminal includes copper, nickel, Tungsten, silver, palladium, platinum, or gold. The gate drive interposer with integrated passive components for a wide band gap semiconductor device according to claim 51, wherein the external terminal is in electrical contact with the electrode through a through hole in the ceramic interposer. The gate drive intermediary with integrated passive components for wide band gap semiconductor devices according to claim 38, wherein the ceramic intermediary further includes a gate driver. The gate drive intermediary with integrated passive components for wide band gap semiconductor devices according to claim 53, wherein the ceramic intermediary includes at least one selected from the group consisting of a transistor, a capacitor, a diode, and a resistor , Varistors, inductors, fuses, integrated circuits, overvoltage discharge devices, sensors, switches, electrostatic discharge suppressors, inverters, rectifiers, filters and components of one of the group of electrically isolated power supplies. The gate drive intermediary with integrated passive components for wide band gap semiconductor devices according to claim 54, wherein the electrically insulated power source is a reverse bias power source. The gate drive intermediary with integrated passive components for wide band gap semiconductor devices according to claim 38, wherein at least one of the embedded capacitors has a rated voltage of 1V to 20,000V. The gate drive intermediary with integrated passive components for wide band gap semiconductor devices according to claim 56, wherein the rated voltage of the embedded capacitor is 500V to 10,000V, and the unit volume of electricity at 500V The capacity is at least 1.0μF/cc, and the electric capacity per unit volume at 10,000V is at least 0.003μF/cc. The gate drive intermediary with integrated passive components for wide band gap semiconductor devices according to claim 38, wherein at least one of the embedded capacitors includes at least one heat dissipation channel. The gate drive intermediary with integrated passive components for wide band gap semiconductor devices according to claim 58, wherein at least one of the heat dissipation channels is selected from being parallel to and connected to the internal electrode vertical. The gate drive intermediary with integrated passive components for wide band gap semiconductor devices according to claim 58, wherein the embedded capacitor is located between the semiconductor and a cooling device. The gate drive intermediary with integrated passive components for wide band gap semiconductor devices according to claim 60, wherein the cooling device is selected from a passive device and an active device. The gate drive intermediary with integrated passive components for wide band gap semiconductor devices according to claim 38 further includes at least one component electrically contacting at least one of the capacitors. The gate drive intermediary with integrated passive components for wide band gap semiconductor devices according to claim 62, wherein the components are selected from the group consisting of transistors, capacitors, diodes, resistors, and varistors. Resistors, inductors, fuses, integrated circuits, over-voltage discharge devices, sensors, switches, electrostatic discharge suppressors, inverters, rectifiers, filters, and electrically isolated power supplies are a group of components. The gate drive intermediary with integrated passive components for wide band gap semiconductor devices according to claim 62, wherein the electrically insulated power source is a reverse bias power source. The gate drive intermediary with integrated passive components for wide band gap semiconductor devices according to claim 38, wherein at least one of the capacitors includes a through hole. The gate drive intermediary with integrated passive components for wide band gap semiconductor devices according to claim 38, wherein at least one of the internal electrodes is in electrical contact with an external terminal through a through hole. The gate drive intermediary with integrated passive components for wide band gap semiconductor devices according to claim 38 further includes a heat dissipation layer. The gate drive intermediary with integrated passive components for wide band gap semiconductor devices according to claim 67, wherein the heat dissipation layer is located between the embedded capacitor and the semiconductor device. The gate drive interposer with integrated passive components for wide band gap semiconductor devices according to claim 68, further comprising at least one through hole passing through the heat dissipation layer. The gate drive interposer with integrated passive components for wide band gap semiconductor devices according to claim 69, wherein the through hole is an insulating through hole. The gate drive intermediary with integrated passive components for wide band gap semiconductor devices according to claim 38 further includes at least one switch. The gate drive intermediary with integrated passive components for wide band gap semiconductor devices according to claim 71 includes a buffer capacitor electrically connected in parallel with the at least one switch. The gate drive intermediary with integrated passive components for wide band gap semiconductor devices according to claim 71, wherein the buffer capacitor is a PDC.

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