TW202123016A - Storage controller, memory management method, and storage device - Google Patents

Abstract

A memory management method includes: grouping a plurality of physical pages of each of a plurality of physical blocks; updating, according to a performed write command, a first target segment valid data count corresponding to a first target physical segment among a plurality of target segment valid data counts of a plurality of target physical segments corresponding to the write command; updating, according to the updated first target segment valid data count, a target block valid data count corresponding to a target physical block among a plurality of block valid data counts of the physical blocks; and updating, according to the target segment valid data counts of the target physical block, a target valid segment count corresponding to the target physical block among a plurality of valid segment counts of the physical blocks.

Description

Storage controller, memory management method and storage device

The present invention relates to a memory management method, and more particularly to a storage device equipped with a rewritable non-volatile memory module, a storage controller of the storage device, and a used memory management method.

Generally speaking, when the free space of the rewritable non-volatile memory module of the storage device is insufficient, the controller of the storage device will treat multiple physical blocks of the rewritable non-volatile memory module ( Also known as reclaiming physical blocks) perform a garbage collection operation to release the available space of the multiple reclaimed physical blocks.

The garbage collection operation takes a lot of time to identify the physical addresses of the valid data stored in the multiple garbage collection blocks, which reduces the performance of the rewritable non-volatile memory module when performing garbage collection operations. .

Based on this, how to efficiently increase the speed of the garbage collection operation so as to increase the performance of the storage device is one of the subjects studied by those in the field.

An embodiment of the present invention provides a storage controller for controlling a storage device equipped with a rewritable non-volatile memory module. The storage controller includes a connection interface circuit, a memory interface control circuit, a block management circuit unit, and a processor. The connection interface circuit is used for coupling to the host system. The memory interface control circuit is used for coupling to the rewritable non-volatile memory module, wherein the rewritable non-volatile memory module has a plurality of physical blocks, and the plurality of Each physical block has multiple physical pages. The processor is coupled to the connection interface circuit, the memory interface control circuit, and the block management circuit unit. The block management circuit unit is used for grouping the plurality of physical pages of each of the plurality of physical blocks into a plurality of physical sections. The processor is used for executing a write command, wherein the write command is used for instructing to store a data in one or more logical pages, wherein the one or more logical pages have been mapped to a target physical block One or more target entity pages of the target entity page, and the one or more target entity pages belong to a first target entity section of the plurality of target entity sections of the target entity block. In addition, the block management circuit unit is further configured to update the first one corresponding to the first target physical section among the valid data counts of the plurality of target physical sections of the plurality of target physical sections according to the write instruction. The effective data count of the target section, wherein the block management circuit unit is further used to update the effective data counts of the plurality of physical blocks according to the updated effective data count of the first target section The target block effective data count corresponding to the target physical block, wherein the block management circuit unit is further used to update the multiple target block effective data counts of the target physical block A target effective section count corresponding to the target physical block among the plurality of effective section counts of a physical block, wherein each of the plurality of effective section counts is used to record one or more corresponding physical blocks The total number of valid physical segments, wherein the segment valid data count of each of the one or more valid physical segments is greater than zero.

An embodiment of the present invention provides a memory management method suitable for a storage controller for controlling a storage device equipped with a rewritable non-volatile memory module, wherein the rewritable non-volatile memory The module has a plurality of physical blocks, and each of the plurality of physical blocks has a plurality of physical pages. The method includes: grouping the plurality of physical pages of each of the plurality of physical blocks into a plurality of physical sections; executing a write command, wherein the write command is used to instruct storage A data into one or more logical pages, wherein the one or more logical pages have been mapped to one or more target physical pages of a target physical block, and the one or more target physical pages belong to all A first target entity section of the plurality of target entity sections of the target entity block; the corresponding one of the multiple target section valid data counts of the plurality of target entity sections is updated according to the write instruction The effective data count of the first target section of the first target physical section; and the effective data counts of the plurality of physical blocks are updated according to the updated effective data count of the first target section Corresponding to the effective data count of the target block of the target physical block; and updating the multiple effective section counts of the plurality of physical blocks according to the effective data count of the multiple target sections of the target physical block The target effective section count corresponding to the target physical block in the target physical block, wherein each of the plurality of effective section counts is used to record the total number of one or more effective physical sections of the corresponding physical block, wherein the The segment valid data count of each of one or more valid physical segments is greater than zero.

An embodiment of the present invention provides a storage device. The storage device includes a rewritable non-volatile memory module and a storage controller, wherein the rewritable non-volatile memory module has a plurality of physical blocks, and each of the plurality of physical blocks has Multiple physical pages. The storage controller is coupled to the rewritable non-volatile memory module. The storage controller is used for grouping the plurality of physical pages of each of the plurality of physical blocks into a plurality of physical sections, wherein the storage controller is further used for executing a write command, The write command is used to instruct to store a data in one or more logical pages, wherein the one or more logical pages have been mapped to one or more target physical pages of a target physical block, and The one or more target entity pages belong to a first target entity section of the plurality of target entity sections of the target entity block. The storage controller is further configured to update a first target segment corresponding to the first target physical segment in the valid data counts of a plurality of target segments of the plurality of target physical segments according to the write instruction. Data count, wherein the storage controller is further used to update the target entity in the plurality of block effective data counts of the plurality of physical blocks according to the updated first target section effective data count The effective data count of the target block of the block, wherein the storage controller is further used for updating the effective data of the plurality of physical blocks according to the effective data count of the plurality of target sections of the target physical block The section count corresponds to the target effective section count of the target physical block, wherein each of the plurality of effective section counts is used to record the total number of one or more effective physical sections of the corresponding physical block, The valid data count of each of the one or more valid physical segments is greater than zero.

Based on the above, the storage controller, the memory management method, and the storage device provided by the embodiments of the present invention can combine all the physical blocks of each of the multiple physical blocks of the rewritable non-volatile memory module. The multiple physical pages are grouped into multiple physical sections, and the corresponding section valid data count, the corresponding valid data count, and the corresponding valid section count are updated according to the write command, so as to use the block valid data count and The effective section count selects and sorts a plurality of reclaimed physical blocks, so as to sequentially perform a garbage collection operation on the plurality of garbage physical blocks according to the concentration of effective data, thereby efficiently releasing the rewritable type The space of the non-volatile memory module improves the overall access performance of the storage device

In this embodiment, the storage device includes a rewritable non-volatile memory module and a storage device controller (also referred to as a storage controller or a storage control circuit). In addition, the storage device is used together with the host system so that the host system can write data to the storage device or read data from the storage device.

FIG. 1 is a block diagram of a host system and a storage device according to an embodiment of the invention.

Please refer to FIG. 1, the host system 10 includes a processor 110, a host memory 120 and a data transfer interface circuit 130. In this embodiment, the data transmission interface circuit 130 is coupled (also referred to as electrically connected) to the processor 110 and the host memory 120. In another embodiment, the processor 110, the host memory 120, and the data transmission interface circuit 130 are coupled to each other by a system bus.

The storage device 20 includes a storage controller (Storage Controller) 210, a rewritable non-volatile memory module (Rewritable Non-Volatile Memory Module) 220 and a connection interface circuit (Connection Interface Circuit) 230. The storage controller 210 includes a processor 211, a data management circuit (Data Management Circuit) 212, and a memory interface control circuit (Memory Interface Control Circuit) 213.

In this embodiment, the host system 10 is coupled to the storage device 20 through the data transmission interface circuit 130 and the connection interface circuit 230 of the storage device 20 to perform data access operations. For example, the host system 10 can store data to the storage device 20 or read data from the storage device 20 via the data transmission interface circuit 130.

In this embodiment, the processor 110, the host memory 120, and the data transmission interface circuit 130 may be disposed on the main board of the host system 10. The number of the data transmission interface circuit 130 may be one or more. Through the data transmission interface circuit 130, the motherboard can be coupled to the storage device 20 in a wired or wireless manner. The storage device 20 may be, for example, a flash drive, a memory card, a solid state drive (SSD) or a wireless memory storage device. The wireless memory storage device may be, for example, a Near Field Communication (NFC) memory storage device, a wireless fax (WiFi) memory storage device, a Bluetooth (Bluetooth) memory storage device, or a Bluetooth low energy memory storage device Devices (for example, iBeacon) and other memory storage devices based on various wireless communication technologies. In addition, the motherboard can also be coupled to various I/O devices such as Global Positioning System (GPS) modules, network interface cards, wireless transmission devices, keyboards, screens, speakers, etc. through the system bus.

In this embodiment, the data transmission interface circuit 130 and the connection interface circuit 230 are interface circuits compatible with the Peripheral Component Interconnect Express (PCI Express) standard. In addition, the data transmission interface circuit 130 and the connection interface circuit 230 use a non-volatile memory interface standard (Non-Volatile Memory express, NVMe) communication protocol for data transmission.

However, it must be understood that the present invention is not limited to this. The data transmission interface circuit 130 and the connection interface circuit 230 may also conform to the Parallel Advanced Technology Attachment (PATA) standard, the Institute of Electrical and Electronics Engineers (Institute of Electrical and Electronic Engineers, IEEE) 1394 standard, Serial Advanced Technology Attachment (SATA) standard, Universal Serial Bus (USB) standard, SD interface standard, Ultra High Speed-I (UHS-I) I) Interface standard, Ultra High Speed-II (UHS-II) interface standard, Memory Stick (MS) interface standard, Multi-Chip Package interface standard, multimedia memory card ( Multi Media Card (MMC) interface standard, eMMC interface standard, Universal Flash Storage (UFS) interface standard, eMCP interface standard, CF interface standard, Integrated Device Electronics (IDE) standard or Other suitable standards. In addition, in another embodiment, the connection interface circuit 230 and the storage controller 210 may be packaged in a chip, or the connection interface circuit 230 may be arranged outside a chip including the storage controller 210.

In this embodiment, the host memory 120 is used to temporarily store instructions or data executed by the processor 110. For example, in this exemplary embodiment, the host memory 120 may be a dynamic random access memory (Dynamic Random Access Memory, DRAM), a static random access memory (Static Random Access Memory, SRAM), etc. However, it must be understood that the present invention is not limited to this, and the host memory 120 may also be other suitable memory.

The storage controller 210 is used to execute a plurality of logic gates or control commands implemented in a hardware type or a firmware type, and to write data in the rewritable non-volatile memory module 220 according to the commands of the host system 10 , Read and erase operations.

In more detail, the processor 211 in the storage controller 210 is a hardware capable of computing, which is used to control the overall operation of the storage controller 210. Specifically, the processor 211 has a plurality of control commands, and when the storage device 20 is operating, these control commands are executed to perform operations such as writing, reading, and erasing data.

It is worth mentioning that in this embodiment, the processor 110 and the processor 211 are, for example, a central processing unit (CPU), a microprocessor (micro-processor), or other programmable processing units. (Microprocessor), Digital Signal Processor (DSP), Programmable Controller, Application Specific Integrated Circuits (ASIC), Programmable Logic Device (PLD) or others Similar to circuit elements, the present invention is not limited to this.

In one embodiment, the storage controller 210 also has a read-only memory (not shown) and a random access memory (not shown). In particular, the read-only memory has a boot code, and when the storage controller 210 is enabled, the processor 211 will first execute the boot code to store it in the rewritable non-volatile memory module The control command in 220 is loaded into the random access memory of the storage controller 210. After that, the processor 211 runs these control commands to perform data writing, reading, and erasing operations. In another embodiment, the control commands of the processor 211 may also be stored in a specific area of the rewritable non-volatile memory module 220 in the form of program codes, for example, dedicated to the rewritable non-volatile memory module 220 In the physical storage unit storing system data.

In this embodiment, as described above, the storage controller 210 further includes a data management circuit 212 and a memory interface control circuit 213. It should be noted that the operations performed by the components of the storage controller 210 can also be regarded as operations performed by the storage controller 210.

The data management circuit 212 is coupled to the processor 211, the memory interface control circuit 213, and the connection interface circuit 230. The data management circuit 212 is used for receiving instructions from the processor 211 to transmit data. For example, read data from the host system 10 (eg, the host memory 120) through the connection interface circuit 230, and write the read data to the rewritable non-volatile memory module through the memory interface control circuit 213 220 (for example, a write operation is performed according to a write command from the host system 10). For another example, data can be read from one or more physical units of the rewritable non-volatile memory module 220 through the memory interface control circuit 213 (data can be read from one or more of the one or more physical units). Memory cells), and write the read data to the host system 10 (for example, the host memory 120) via the connection interface circuit 230 (for example, perform a read operation according to a read command from the host system 10) . In another embodiment, the data management circuit 212 can also be integrated into the processor 211.

The memory interface control circuit 213 is used to receive instructions from the processor 211 and cooperate with the data management circuit 212 to perform writing (also known as programming) operations and reading to the rewritable non-volatile memory module 220 Operate or erase operation.

For example, the processor 211 can execute a write command sequence to instruct the memory interface control circuit 213 to write data into the rewritable non-volatile memory module 220; the processor 211 can execute a read command sequence, To instruct the memory interface control circuit 213 to read data from one or more physical units (also known as target physical units) corresponding to the read instructions of the rewritable non-volatile memory module 220; the processor 211 can execute The erase command sequence instructs the memory interface control circuit 213 to perform an erase operation on the rewritable non-volatile memory module 220. The write command sequence, the read command sequence, and the erase command sequence may each include one or more program codes or command codes and are used to instruct to perform corresponding writing, writing, and writing to the rewritable non-volatile memory module 220. Operations such as reading and erasing. In one embodiment, the processor 211 may also issue other types of instruction sequences to the memory interface control circuit 213 to perform corresponding operations on the rewritable non-volatile memory module 220.

In addition, the data to be written into the rewritable non-volatile memory module 220 is converted into a format acceptable by the rewritable non-volatile memory module 220 through the memory interface control circuit 213. Specifically, if the processor 211 wants to access the rewritable non-volatile memory module 220, the processor 211 will send a corresponding command sequence to the memory interface control circuit 213 to instruct the memory interface control circuit 213 to execute the corresponding operating. For example, these command sequences may include a write command sequence instructing to write data, a read command sequence instructing to read data, an erase command sequence instructing to erase data, and various memory operations (e.g., changing presets). It is assumed that a plurality of preset read voltage values of the read voltage group are used to perform a read operation, or execute a garbage collection program, etc.) corresponding to the instruction sequence. These command sequences can include one or more signals, or data on the bus. These signals or data may include script codes or program codes. For example, in the read command sequence, the read identification code, memory address and other information will be included.

The rewritable non-volatile memory module 220 is coupled to the storage controller 210 (the memory interface control circuit 213) and is used to store data written by the host system 10. The rewritable non-volatile memory module 220 may be a single level cell (SLC) NAND flash memory module (that is, a flash memory that can store 1 bit in a memory cell). Module), Multi Level Cell (MLC) NAND-type flash memory module (that is, a flash memory module that can store 2 bits in a memory cell), and a third-level memory cell ( Triple Level Cell (TLC) NAND flash memory modules (that is, a flash memory module that can store 3 bits in a memory cell), Quadruple Level Cell (QLC) NAND flash memory modules Flash memory module (ie, a flash memory module that can store 4 bits in a memory cell), 3D NAND flash memory module (3D NAND flash memory module), or vertical NAND flash memory Other flash memory modules such as Vertical NAND flash memory module or other memory modules with the same characteristics. The memory cells in the rewritable non-volatile memory module 220 are arranged in an array.

In this embodiment, the rewritable non-volatile memory module 220 has a plurality of character lines, and each of the plurality of character lines is coupled to a plurality of memory cells. Multiple memory cells on the same character line form one or more physical programming units. In addition, multiple physical programming units can form a physical unit (physical block or physical erase unit).

In this embodiment, the memory cell is used as the smallest unit for writing (programming) data. The physical unit is the smallest unit of erasure, that is, each physical unit contains one of the smallest number of memory cells that are erased.

Each physical unit will have multiple physical sub-units. The physical subunit can be a physical page (page) or a physical sector (sector). In this embodiment, the physical subunit includes a data bit area and a redundancy bit area. The data bit area is used to store user data, and the redundant bit area is used to store system data. The system data is, for example, error correction code, error check code, or metadata (Meta Data). However, the present invention is not limited to this. For example, in another embodiment, the data transmission method described in this embodiment can also be modified and applied to a rewritable non-volatile memory module 220 that uses a physical unit as the smallest storage unit for writing data.

It should be noted that, in this embodiment, the system data used to record the information of a physical unit can be recorded by one or more physical subunits in the physical unit, or can be recorded in a system area for recording all One or more physical sub-units of a specific physical unit of the system data are recorded. In this embodiment, the system data corresponding to a physical unit includes the erase frequency value (Program erase cycle, PEC) of the physical unit, the block valid data count (Block Valid Data Count), and multiple section valid data. Count (Segment Valid Data Count) and valid segment count (Valid Segment Count) (also known as the total number of valid segments) and other information.

In the following embodiments, a physical block is used as an example of a physical unit. However, in another embodiment, a physical unit can also refer to any number of memory cells, depending on practical requirements. In addition, it must be understood that when the storage controller 211 groups the memory cells (or physical units) in the rewritable non-volatile memory module 220 to perform corresponding management operations, these memory cells (or physical units) Units) are logically grouped, and their actual locations have not changed.

The storage controller 210 allocates a plurality of logic units to the rewritable non-volatile memory module 220. The host system 10 accesses user data stored in multiple physical units through configured logical units. Here, each logical unit can be composed of one or more logical addresses. For example, the logical unit may be a logical block (Logical Block), a logical page (Logical Page) or a logical sector (Logical Sector). A logical unit can be mapped to one or more physical units, where the physical unit can be one or more physical addresses, one or more physical sectors, one or more physical programming units, or one or more physical erasures unit. In this embodiment, the logical unit is a logical block, and the logical sub-unit is a logical page. Each logic unit has multiple logic sub-units.

In addition, the storage controller 210 creates a logical to physical address mapping table (Logical To Physical address mapping table) and a physical to logical address mapping table (Physical To Logical address mapping table) to record the configuration to the rewritable non-volatile The address mapping relationship between logical units (eg, logical blocks, logical pages, or logical sectors) of the memory module 220 and physical units (eg, physical erase units, physical programming units, physical sectors). In other words, the storage controller 210 can use the logical-to-physical address mapping table to find the physical unit to which a logical unit is mapped, and the storage controller 210 can use the physical-to-logical address mapping table to find the physical unit to which a physical unit is mapped. Logical unit. However, the above-mentioned technical concepts related to the mapping between logical units and physical units are conventional technical means by those skilled in the art and are not technical solutions intended to be described in the present invention, and will not be repeated here. For example, the host system 10 may be configured with multiple logical pages, and the multiple logical pages may be mapped to multiple physical pages.

In this embodiment, the error checking and correcting circuit 214 is coupled to the processor 211 and used to perform error checking and correcting procedures to ensure the correctness of the data. Specifically, when the processor 211 receives a write command from the host system 10, the error checking and correction circuit 214 will generate a corresponding error correcting code (ECC) and/or for the data corresponding to the write command. Or error detecting code (EDC), and the processor 211 will write the data corresponding to this write command and the corresponding error correction code and/or error check code to the rewritable non-volatile memory module 220 in. After that, when the processor 211 reads data from the rewritable non-volatile memory module 220, it will read the error correction code and/or error check code corresponding to the data at the same time, and the error check and correction circuit 214 will follow This error correction code and/or error check code performs error checking and correction procedures on the read data.

In one embodiment, the storage controller 210 further includes a buffer memory 216 and a power management circuit 217. The buffer memory is coupled to the processor 211 and used to temporarily store data and instructions from the host system 10, data from the rewritable non-volatile memory module 220, or other systems for managing the storage device 20 Data, so that the processor 211 can quickly access the data, instructions, or system data from the buffer memory 216. The power management circuit 217 is coupled to the processor 211 and used to control the power of the storage device 20.

In this embodiment, the block management circuit unit 215 includes a valid data counting circuit 2151 and a valid section management circuit 2152. The block management circuit unit 215 is used to manage the information of multiple physical blocks in the rewritable non-volatile memory module 220. The operations of the components of the block management circuit unit 215 may also represent the operations of the block management circuit unit 215. The function of the block management circuit unit 215 and the corresponding memory management method provided in this embodiment are described below using FIG. 2.

FIG. 2 is a flowchart of a memory management method according to an embodiment of the invention. 2, in step S210, the block management circuit unit 215 groups the multiple physical pages of each of the multiple physical blocks of the rewritable non-volatile memory module 220 into multiple entities Section. Hereinafter, the description will be made using FIGS. 4A and 4B first.

4A is a schematic diagram of a codeword, a physical page, a physical block, and a rewritable non-volatile memory module according to an embodiment of the present invention. FIG. 4B is a schematic diagram illustrating that multiple physical pages of a grouped physical block are multiple physical sections according to an embodiment of the present invention.

Please refer to FIG. 4A. In this embodiment, the data received from the host system 10 is stored in a physical page in units of codewords, for example, codewords CW(1)~CW(M ), M is a positive integer. According to the specifications of each rewritable non-volatile memory module 220, the number of codewords stored in each physical page is different. Multiple physical pages P(1)~P(NP) will be divided into one physical block, N and P are positive integers (NP represents the product of N times P). A plurality of physical blocks B(1)~B(Q) belong to the rewritable non-volatile memory module 220, and Q is a positive integer.

It should be noted that the present invention is not limited to the specific values of M, N, P, and Q. The specific values of M, N, P, and Q are based on the specifications of the rewritable non-volatile memory module 220 or the requirements of the manufacturer. Is preset.

Referring to FIG. 4B, in this embodiment, the block management circuit unit 215 groups the multiple physical pages of each physical block. For example, the block management circuit unit 215 groups the multiple physical pages P(1)~P(NP) of the physical block B(1) into multiple physical sections S(1)~S(N). Each P physical pages will be grouped into a physical section. For example, physical section S(1) includes physical pages P(1)~P(P), and physical section S(2) includes physical pages P(P+ 1)~P(2P), the physical section S(N) includes physical pages P(NP-P+1)~P(NP), etc... After obtaining the grouped physical sections S(1) to S(N), the block management circuit unit 215 can correspondingly record/maintain/update related to the plurality of physical sections S(1) ~S(N) a variety of information (such as valid data count, segment valid data count, block valid data count, valid segment count, etc...).

Please return to FIG. 2. In step S220, the processor 211 executes a write instruction, where the write instruction is used to instruct to store a data in one or more logical pages of the logical block, where the logical The block has been mapped to a target physical block of the plurality of physical blocks, wherein the one or more logical pages have been mapped to one or more target physical pages of the target physical block, and The one or more target entity pages belong to a first target entity section of the plurality of target entity sections of the target entity block. Specifically, the write command may be a write command received from the host system 10, or a command used to update/move/copy data stored in the rewritable non-volatile memory module 220.

In this embodiment, if one or more physical pages (also known as target physical pages) mapped by one or more logical pages corresponding to the write instruction already have data stored in them, the processor 211 will select another entity The page is used to store the write data corresponding to the write command. The valid data stored in the one or more physical pages will become invalid data, which is then updated by the block management circuit unit 215 (or the valid data counting circuit 2151). Reduce the valid data count of the one or more physical pages (based on the total number of all codewords that become invalid data in the one or more physical pages).

On the other hand, if one or more physical pages (also known as target physical pages) mapped to one or more logical pages corresponding to the write instruction are blank (no data is yet stored), the processor 211 will Directly use the one or more target physical pages to store the write data corresponding to the write command, the write data stored in the one or more physical pages will become valid data, and the block management circuit unit 215 (or effective data counting circuit 2151) updates/increases the effective data count of the one or more physical pages (based on the total number of all codewords that are valid data in the one or more physical pages). On the other hand, if the one or more logical pages corresponding to the write instruction has not been mapped to one or more physical pages, the processor 211 will select one or more blank target physical surfaces to store the corresponding one or more physical pages. The write data of the input command, the write data stored in the one or more target physical pages will become valid data, and the one or more will be updated/incremented through the block management circuit unit 215 (or the valid data counting circuit 2151) A count of valid data of multiple target physical pages (based on the total number of all codewords that are valid data in the one or more physical pages). For example, suppose a blank target entity page can store up to 4 codewords. In response to the write data of the corresponding write command stored in the target physical page just filling the target physical page, the effective data count of the target physical page will change from 0 to 4.

In step S230, the block management circuit unit 215 (or the valid data counting circuit 2151) updates the valid data counts of the plurality of target physical segments corresponding to the first one of the valid data counts of the plurality of target physical segments according to the write instruction. The effective data count of the first target section of the target entity section.

Then, in step S240, the block management circuit unit 215 (or the effective data counting circuit 2151) updates the effective data of the plurality of physical blocks according to the updated effective data count of the first target section. The valid data count of the target block corresponding to the target physical block in the data count.

Then, in step S250, the block management circuit unit 215 (or the effective section management circuit 2152) updates the counts of the plurality of physical blocks according to the effective data counts of the plurality of target sections of the target physical block. A plurality of effective section counts corresponds to the target effective section count of the target physical block, wherein each of the plurality of effective section counts is used to record the number of one or more effective physical sections of the corresponding physical block The total number, wherein the segment valid data count of each of the one or more valid physical segments is greater than zero. The details of steps S220 to S250 are described below using FIGS. 5A to 5B.

5A to 5B are schematic diagrams of updating the valid data count according to a write command according to an embodiment of the present invention. Referring to FIG. 5A, suppose multiple physical pages 51(1), 51(2), 52(1), 52(2), 53(1), 53(2), 54(1), 54(2) has been mapped to logical pages L51(1), L51(2), L52(1), L52(2), L53(1), L53(2), L54(1), L54(2), and Multiple codewords (also known as invalid codewords) in physical pages 51(1) and 51(2) store invalid data; physical pages 52(1), 52(2), 53(1), 53(2) ), 54(1), 54(2) codewords (also known as valid codewords) store valid data. In addition, in this example, every two physical pages will be grouped into 1 physical section, for example, physical pages 51(1), 51(2) are grouped into physical section 51; physical pages 52(1), 52 (2) is grouped into a physical section 52; physical pages 53(1), 53(2) are grouped into a physical section 53; physical pages 54(1), 54(2) are grouped into a physical section 54.

Based on the total number of valid codewords in each physical page, the block management circuit unit 215 can recognize that the valid data count of the physical page 51(1) is "0"; the valid data count of the physical page 51(2) Is "0"; the valid data counts of physical pages 52(1) to 54(2) are all "4". In addition, the block management circuit unit 215 can calculate that the sum of the valid data counts of all the physical pages 51(1) to 51(2) in the physical section 51 is "0" (for example, 0+0=0); The sum of the valid data counts of all the physical pages 52(1)~52(2) in the physical section 52 is "8" (for example, 4+4=8); all the physical pages 53 in the physical section 53 (1)~53(2) The total of valid data counts is "8" (for example, 4+4=8); the valid data of all physical pages 54(1)~54(2) in the physical section 54 The sum of the counts is "8" (for example, 4+4=8).

Then, the block management circuit unit 215 (or the effective section management circuit 2152) can further recognize that the physical section 51 corresponding to the section with a valid data count of "0" is an invalid physical section and corresponding to a non-"0". The physical sections 52 to 54 of the section valid data count are valid physical sections, and the block management circuit unit 215 will calculate the total number of valid physical sections of the physical block 50 as the effective block count (e.g. , The effective block count corresponding to the three effective physical segments 52-54 is "3"). In addition, the block management circuit unit 215 can further calculate the sum of the valid data counts of all the segments 51-54 of the physical block 50 as the block valid data counts of the physical block 50 (eg, 0+ 8+8+8=24).

In this example, the processor 211 executes the write command WC, and as indicated by the arrow A51, the 4 code words (write data) corresponding to the write command WC are written to the logical page L52(1). The block management circuit unit 215 (or the processor 211) can identify the physical page 52(1) mapped to the logical page L52(1) as the target physical page.

Please refer to FIG. 5B, as indicated by arrow A52, reflecting that the logical page L52(1) has stored 4 codewords corresponding to the write command WC, the block management circuit unit 215 (or the processor 211) will recognize that the original The data of the 4 code words in the target physical page 52(1) becomes invalid data, the valid data count of the target physical page 52(1) is subtracted by 4 (the valid data count of the target physical page 52(1) will be reduced Is “0” (ie, 4-4=0)), and the section effective data count of the physical section 52 is updated from “8” to “4” (0+4=4). At this time, the block management circuit unit 215 (or the effective section management circuit 2152) will identify the effective entity of the physical block 50 based on the section effective data count of the latest identified physical section 51-54. The total number of segments is still 3 (the total number of valid physical segments with a segment valid data count greater than "0" is "3"), that is, the valid segment count is "3".

In an embodiment, the block management circuit unit 215 (or the processor 211) can record the valid data counts and the valid sector counts of the respective multiple sections corresponding to the multiple physical blocks. For example, the block management circuit unit 215 (or the processor 211) records the effective data counts of the plurality of sections corresponding to the respective physical blocks and the effective section counts in a valid data count table.

FIG. 6A is a schematic diagram illustrating the effective data count and the effective section count of the recording section according to an embodiment of the present invention. Please refer to Figure 6A, as shown in Table T60, for the convenience of description, suppose that the rewritable non-volatile memory module 220 has 4 physical blocks 50, 60, 70, 80, and each physical block has 4 physical blocks. Section, each physical section has 2 physical pages, and each physical page can store 4 codewords (the maximum valid data count of each physical page is "4", the largest section of each physical section The section valid data count is "8"), and each entry in the table T60 corresponds to a physical section.

The block management circuit unit 215 (or the processor 211) can record the effective data count of each of the identified/updated physical sections 51 to 84 in a field (also known as the effective data count table) of table T60 ( Also known as the first column), as recorded in Table T60, the valid data counts of the corresponding physical segments 51, 52 to 83, 84 are "0", "4" to "2", and "8". In addition, the block management circuit unit 215 (or the processor 211) may further record the effective section count of each of the identified/updated physical blocks 50-80 in another column of the table T60 (also known as the second column Bit), as recorded in table T60, the effective sector counts "3", "3", "1", and "3" of the corresponding physical blocks 50, 60, 70, and 80.

In addition, in one embodiment, the block management circuit unit 215 (or the processor 211) can also calculate the effective data of the respective physical blocks 50 to 80 in real time based on the recorded effective data count of the section. count. In another embodiment, the block management circuit unit 215 (or the processor 211) may also record the calculated effective data count of each of the physical blocks 50-80 in another field (also known as , The third column).

In this embodiment, through the memory management method provided in FIG. 2, the block management circuit unit 215 can instantly obtain/update the section effective data count of each physical block and the block of each physical block. Valid data count and valid section count. The processor 211 can further be used to perform a garbage collection operation according to the valid data counts of the plurality of blocks and the valid section counts. That is to say, the garbage collection operation provided by the implementation of the present invention can improve the efficiency of execution through the effective data counts of the multiple blocks and the multiple effective segment counts (effectively identify the physical blocks in the recycling Valid information).

Fig. 3 is a flowchart of a garbage collection operation according to an embodiment of the present invention. 3, in step S310, the block management circuit unit 215 (or the processor 211) may select the multiple physical areas according to the reclaimed block effective data count threshold and the multiple block effective data counts Multiple recycled physical blocks in the block. Each of the plurality of block effective data counts is used to record the sum of the respective section effective data counts of all the effective physical sections of the physical block to which they belong, and the section effective data count is used to record and store in The total number of all valid codewords in all the physical pages of the physical section to which it belongs. Wherein, the effective data count of each of the plurality of recycled physical blocks is less than the effective data count threshold value of the recycled block.

Then, in step S320, the block management circuit unit 215 (or the processor 211) may sort the multiple reclaimed blocks according to the effective section count of each of the multiple reclaimed physical blocks, from small to large. Physical block.

Then, in step S330, the processor 211 may perform the garbage collection operation according to the sorted plurality of reclaimed physical blocks, wherein the sorted plurality of reclaimed physical blocks are sorted at the forefront The first reclaimed physical block of is the first to be executed by the processor 211 for the garbage collection operation.

Specifically, the processor 211 only checks whether valid data is stored in one or more first valid physical sections of the first recovered physical block, and identifies the physical address of the valid data to move The valid information. In an embodiment, the processor 211 does not check whether the storage is stored in one or more second valid physical sections other than the one or more first valid physical sections in the first reclaimed physical block. The valid information. As a result, it is only through the logical to physical address mapping table and the physical to logical address mapping table to check the mapping relationship between the physical page and the logical page of the one or more first effective physical sections to confirm the one or more second The physical address of the valid data in a valid physical section can save a lot of time (because there is no need to check the invalid physical section in the first reclaimed physical block, and avoid the cost of checking the first reclaimed physical block. A lot of time for all the physical sections in).

The details of steps S310 to S330 are described below using FIG. 6B.

FIG. 6B is a schematic diagram of selecting and sorting a plurality of reclaimed physical blocks according to the effective data count of the block and the effective section count according to an embodiment of the present invention. Please refer to Figure 6B, assuming that the valid data count threshold of the recovered block is "14". Continuing the example of FIG. 6A, as shown by arrow A61, the block management circuit unit 215 (or the processor 211) can count the threshold value "14" according to the effective data of the recovered block and the corresponding physical block 50, 60, 70, 80. Multiple block valid data counts "21", "7", "7", "13" to select block valid data counts "7", "7", "7", "7", "7", The physical blocks 60, 70, and 80 corresponding to "13" are used as multiple reclaimed physical blocks (step S310). Then, as shown by arrow A62, the block management circuit unit 215 (or the processor 211) can count "3", "1", and "3" according to the multiple valid block counts corresponding to the physical blocks 60, 70, and 80. The reclaimed physical blocks 60, 70, and 80 are sorted from small to large (step S320) into a plurality of reclaimed physical blocks 70, 60, 80 that have been sorted. Sorted multiple recycling physical blocks 70, 60, 80 can be identified/added as garbage collection queue. According to the recycling order/arrangement order, the recycled physical blocks in the garbage collection queue are physical block 70 and physical area Block 60, physical block 80.

The processor 211 may sequentially perform garbage collection operations according to the sorted multiple recycling physical blocks 70, 60, and 80 (step S330). For example, as indicated by the arrow A63, among the sorted multiple reclaimed physical blocks 70, 60, 80, the reclaimed physical block 70 will first be subjected to a garbage collection operation. In addition, referring to Table T60, the processor 211 may only check whether the physical section 74 (valid physical section) in the reclaimed physical block 70 is stored by identifying the valid physical section and the invalid physical section in the reclaimed physical block 70 Valid data (do not check invalid entity section 71-73).

It is worth mentioning that in this embodiment, the effective section count of each physical block can also be used to indicate the concentration of the effective data of the corresponding physical block. To put it simply, a physical block with a smaller effective section count has a higher concentration of effective data; a physical block with a larger effective section count has a lower concentration of effective data. Using this concept, the memory management method provided by this embodiment can sort all reclaimed physical blocks according to the effective sector count, so as to effectively determine the recovery of all reclaimed physical blocks based on the concentration of all reclaimed physical blocks. The sequence of garbage collection operations performed by the physical block. In this way, even if the effective data counts of the two reclaimed physical blocks (for example, reclaimed physical blocks 60 and 70) are equal, the processor 211 can also rely on the concentration of the effective data of the two reclaimed physical blocks (effective Section count) to first select the reclaimed physical block with higher concentration (smaller effective section count) (for example, recycle physical block 70) to perform the garbage collection operation, so that only fewer effective physical areas are checked Segment, and quickly identify the physical address of the valid data in it, so as to achieve the effect of quickly recovering the reclaimed physical block.

In summary, the storage controller, memory management method, and storage device provided by the embodiments of the present invention can store each of the multiple physical blocks of the rewritable non-volatile memory module The multiple physical pages are grouped into multiple physical sections, and the corresponding section valid data count, the corresponding valid data count, and the corresponding valid section count are updated according to the write command, so as to utilize the block valid data Count and the effective section count to select and sort a plurality of reclaimed physical blocks, so as to sequentially perform garbage collection operations on the plurality of garbage physical blocks according to the concentration of valid data, and then release the recyclable blocks efficiently. The space of the copy-type non-volatile memory module improves the overall access performance of the storage device.

10: Host system 20: storage device 110, 211: processor 120: host memory 130: data transmission interface circuit 210: storage controller 212: Data Management Circuit 213: Memory Interface Control Circuit 214: Error checking and correction circuit 215: block management circuit unit 2151: Effective data counting circuit 2152: Effective section management circuit 216: buffer memory 217: Power Management Circuit 220: rewritable non-volatile memory module 230: connection interface circuit S210, S220, S230, S240, S250: Process steps of the memory management method S310, S320, S330: process steps of garbage collection operations CW(1)~CW(M): codeword WC: write command P(1)~P(NP), 51(1)~54(2): physical page B(1)~B(Q), 50, 60, 70, 80: physical block S(1), S(2)～S(N), 51, 52, 53, 54: physical section L51(1)~L54(2): Logic page A51, A52, A61, A62, A63: Arrow T60: table

FIG. 1 is a block diagram of a host system and a storage device according to an embodiment of the invention. FIG. 2 is a flowchart of a memory management method according to an embodiment of the invention. Fig. 3 is a flowchart of a garbage collection operation according to an embodiment of the present invention. 4A is a schematic diagram of a codeword, a physical page, a physical block, and a rewritable non-volatile memory module according to an embodiment of the present invention. FIG. 4B is a schematic diagram illustrating that multiple physical pages of a grouped physical block are multiple physical sections according to an embodiment of the present invention. 5A to 5B are schematic diagrams of updating the valid data count according to a write command according to an embodiment of the present invention. FIG. 6A is a schematic diagram illustrating the effective data count and the effective section count of the recording section according to an embodiment of the present invention. FIG. 6B is a schematic diagram of selecting and sorting a plurality of reclaimed physical blocks according to the effective data count of the block and the effective section count according to an embodiment of the present invention.

S210, S220, S230, S240, S250: Process steps of the memory management method

Claims (15)

A storage controller for controlling a storage device equipped with a rewritable non-volatile memory module, the storage controller comprising: A connection interface circuit for coupling to a host system; A memory interface control circuit for coupling to the rewritable non-volatile memory module, wherein the rewritable non-volatile memory module has a plurality of physical blocks, and the plurality of Each physical block has multiple physical pages; A block management circuit unit, and A processor coupled to the connection interface circuit, the memory interface control circuit and the block management circuit unit, The block management circuit unit is used for grouping the plurality of physical pages of each of the plurality of physical blocks into a plurality of physical sections, The processor is used to execute a write instruction, wherein the write instruction is used to instruct to store a data in one or more logical pages, wherein the one or more logical pages have been mapped to a target physical area One or more target physical pages of a block, and the one or more target physical pages belong to a first target physical section of a plurality of target physical sections of the target physical block, The block management circuit unit is further configured to update the first target corresponding to the first target physical section among the valid data counts of the plurality of target physical sections of the plurality of target physical sections according to the write instruction Count of valid data in the segment, The block management circuit unit is further configured to update the corresponding target physical area in the plurality of block effective data counts of the plurality of physical blocks according to the updated effective data count of the first target section The effective data count of the target block of the block, The block management circuit unit is further configured to update the valid data counts of the plurality of physical blocks corresponding to the target according to the valid data counts of the plurality of target segments of the target physical block The target effective section count of the physical block, wherein each of the plurality of effective section counts is used to record the total number of one or more effective physical sections of the corresponding physical block, wherein the one or more effective sections are The valid data count of the respective physical segments is greater than zero. According to the storage controller described in claim 1, wherein the processor is further configured to perform a garbage collection operation according to the valid data counts of the plurality of blocks and the valid section counts. The storage controller according to claim 2, wherein in the operation of executing the garbage collection operation according to the valid data counts of the plurality of blocks and the valid section counts, The block management circuit unit selects a plurality of recycled physical blocks of the plurality of physical blocks according to the effective data count threshold value of the recycled blocks and the plurality of effective data counts of the plurality of blocks, wherein the plurality of regions The block valid data counts are used to record the sum of the respective section valid data counts of all the valid physical sections of the physical block to which they belong, and the section valid data counts are used to record and store in the physical section to which they belong The total number of all valid codewords in all physical pages of The effective data count of each of the plurality of recycled physical blocks is less than the effective data count threshold value of the recycled block. The storage controller according to item 3 of the scope of patent application, wherein in the operation of executing the garbage collection operation based on the valid data counts of the plurality of blocks and the valid section counts, The block management circuit unit sorts the multiple reclaimed physical blocks from small to large according to the effective section count of each of the multiple reclaimed physical blocks, The processor executes the garbage collection operation according to the sorted multiple reclaimed physical blocks, and among the sorted multiple reclaimed physical blocks, the first reclaimed physical area that is sorted at the forefront The block will be the first to be executed by the processor for the garbage collection operation. The storage controller according to item 4 of the scope of patent application, wherein in the garbage collection operation performed on the first reclaimed physical block among the sorted reclaimed physical blocks, The processor only checks whether valid data is stored in one or more first valid physical sections of the first recovered physical block, and recognizes the physical address of the valid data to move the valid data. The storage controller according to item 5 of the scope of patent application, wherein in the garbage collection operation performed on the first reclaimed physical block of the sorted reclaimed physical blocks, The processor does not check whether the valid data is stored in one or more first invalid physical sections other than the one or more first valid physical sections in the first recovered physical block, wherein The section valid data count of each of the one or more first invalid physical sections is zero. The storage controller as described in item 1 of the scope of patent application, wherein The block management circuit unit records the effective data counts of the plurality of sections corresponding to each of the plurality of physical blocks and the effective section counts into a valid data count table, The valid data count table includes a plurality of entries corresponding to the plurality of physical sections of the plurality of physical units, wherein each of the plurality of entries includes a first field and a second field, The first field is used to record the effective data count of the corresponding physical section, and the second field is used to record the effective area of the corresponding physical section Segment count. A memory management method is suitable for a storage controller used to control a storage device equipped with a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module has multiple physical areas Block, and each of the plurality of physical blocks has a plurality of physical pages, the method includes: Grouping the plurality of physical pages of each of the plurality of physical blocks into a plurality of physical sections; Execute a write command, wherein the write command is used to instruct to store a data in one or more logical pages, wherein the one or more logical pages have been mapped to one or more of a target physical block A target entity page, and the one or more target entity pages belong to a first target entity section of a plurality of target entity sections of the target entity block; Updating the valid data count of the first target segment corresponding to the first target physical segment among the valid data counts of the plural target segment of the plural target physical segments according to the write instruction; Updating the effective data count of the target block corresponding to the target physical block among the plurality of block effective data counts of the plurality of physical blocks according to the updated effective data count of the first target section; and According to the valid data counts of the multiple target segments of the target physical block, the target valid segment counts of the multiple valid segment counts of the multiple physical blocks corresponding to the target physical block are updated, wherein Each of the plurality of valid segment counts is used to record the total number of one or more valid physical segments of the corresponding physical block, wherein the segment valid data of each of the one or more valid physical segments The count is greater than zero. The memory management method described in item 8 of the scope of patent application includes: The garbage collection operation is performed according to the valid data counts of the plurality of blocks and the valid section counts. The memory management method according to claim 9 of the scope of patent application, wherein the step of performing a garbage collection operation according to the valid data counts of the plurality of blocks and the valid section counts includes: According to the reclamation block effective data count threshold value and the plurality of block effective data counts, a plurality of reclamation physical blocks of the plurality of physical blocks are selected, wherein each of the plurality of block effective data counts is used The record is the sum of the effective data counts of the respective sections of all the effective physical sections of the physical block to which it belongs, and the effective data counts of the sections are used to record the data stored in all the physical pages of the physical section to which they belong The total number of all valid codewords, The effective data count of each of the plurality of recycled physical blocks is less than the effective data count threshold value of the recycled block. The memory management method according to claim 10, wherein the step of performing a garbage collection operation according to the valid data counts of the plurality of blocks and the valid section counts further includes: Sort the multiple reclaimed physical blocks according to the effective section count of each of the multiple reclaimed physical blocks, from small to large; Execute the garbage collection operation according to the sorted multiple reclaimed physical blocks, The first reclaimed physical block sorted at the forefront among the sorted reclaimed physical blocks is the first to be executed by the processor for the garbage collection operation. The memory management method as described in item 11 of the scope of patent application, wherein the garbage collection operation performed on the first reclaimed physical block includes: Only check whether valid data is stored in one or more first valid physical sections of the first recovered physical block, and identify the physical address of the valid data to move the valid data. The memory management method as described in item 12 of the scope of patent application, wherein the garbage collection operation performed on the first reclaimed physical block further includes: It is not checked whether the valid data is stored in one or more first invalid physical sections other than the one or more first valid physical sections in the first recycled physical block, wherein the one or more The valid data count of each of the first invalid physical segments is zero. The memory management method described in item 8 of the scope of patent application further includes: Recording the valid data counts of the plurality of sections corresponding to the respective physical blocks and the valid section counts into a valid data count table, The valid data count table includes a plurality of entries corresponding to the plurality of physical sections of the plurality of physical units, wherein each of the plurality of entries includes a first field and a second field, The first field is used to record the effective data count of the corresponding physical section, and the second field is used to record the effective area of the corresponding physical section Segment count. A storage device, the storage device comprising: A rewritable non-volatile memory module, wherein the rewritable non-volatile memory module has a plurality of physical blocks, and each of the plurality of physical blocks has a plurality of physical pages; and A storage controller coupled to the rewritable non-volatile memory module, Wherein the storage controller is used for grouping the plurality of physical pages of each of the plurality of physical blocks into a plurality of physical sections, The storage controller is further used to execute a write command, wherein the write command is used to instruct to store a data in one or more logical pages, wherein the one or more logical pages have been mapped to a One or more target physical pages of the target physical block, and the one or more target physical pages belong to a first target physical section of the plurality of target physical sections of the target physical block, The storage controller is further configured to update the first target section corresponding to the first target physical section in the valid data counts of the plurality of target section of the plurality of target physical sections according to the write instruction Valid data count, The storage controller is further configured to update the effective data count of the plurality of physical blocks corresponding to the target physical block according to the updated effective data count of the first target section The effective data count of the target block, The storage controller is further configured to update the valid data counts of the plurality of physical blocks corresponding to the target physical area according to the valid data counts of the plurality of target segments of the target physical block The target effective section count of the block, wherein each of the plurality of effective section counts is used to record the total number of one or more effective physical sections of the corresponding physical block, wherein the one or more effective physical sections The segment valid data count of each segment is greater than zero.

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