TW202122210A - Wafer single side polishing method, wafer manufacturing method and wafer single side polishing device - Google Patents
Wafer single side polishing method, wafer manufacturing method and wafer single side polishing device Download PDFInfo
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本發明係有關於晶圓的單面研磨方法、晶圓的製造方法及晶圓的單面研磨裝置。The present invention relates to a single-side polishing method of a wafer, a manufacturing method of a wafer, and a single-side polishing device of a wafer.
晶圓的製造中,實行各種步驟,其中之一,有晶圓的研磨步驟。晶圓的研磨步驟中,根據目的,研磨晶圓兩面的兩面研磨,或只研磨晶圓單面的單面研磨。In the manufacture of wafers, various steps are carried out, one of which is the polishing step of the wafer. In the wafer polishing step, depending on the purpose, both sides of the wafer are polished, or only one side of the wafer is polished.
晶圓的單面研磨中,要求晶圓表面的高平坦度。 例如,專利文獻1中,揭示對被研磨物表面的平坦性優異的研磨墊及其製造方法。In single-sided polishing of wafers, high flatness of the wafer surface is required. For example, Patent Document 1 discloses a polishing pad having excellent flatness on the surface of an object to be polished and a method of manufacturing the same.
又,專利文獻2中,揭示有效防止晶圓外周下垂的晶圓研磨方法及適於其晶圓的研磨方法使用之晶圓研磨用研磨墊。 [先行技術文獻] [專利文獻]In addition, Patent Document 2 discloses a wafer polishing method that effectively prevents the outer periphery of the wafer from sagging, and a polishing pad for wafer polishing suitable for use in the polishing method of the wafer. [Advanced Technical Literature] [Patent Literature]
[專利文獻1]國際公開第2015/178289號 [專利文獻2]專利公開第2003-142437號公報[Patent Document 1] International Publication No. 2015/178289 [Patent Document 2] Patent Publication No. 2003-142437
[發明所欲解決的課題][The problem to be solved by the invention]
近年來,根據元件的細微化及晶圓的元件形成區域擴大的觀點,晶圓最外周附近也要求高平坦度,不只是晶圓最外周附近的平坦度及表面變位量,其外周的周方向,也要求平坦化。 但是,上述專利文獻1中記載的研磨墊中,要利用多層構造的研磨墊降低微小的缺陷,作為平坦度指標,只測量ESFQR的變化,不注目於晶圓周方向的不均。 又,上述專利文獻2中記載的研磨墊中,根據研磨墊表面粗糙度與壓縮率的關係,要改善晶圓外周下垂,但不注目於晶圓周方向的不均。In recent years, from the viewpoint of the miniaturization of components and the expansion of the device formation area of the wafer, high flatness is also required near the outermost periphery of the wafer. Not only the flatness and the amount of surface displacement near the outermost periphery of the wafer, but also the outer periphery The direction also requires flattening. However, in the polishing pad described in Patent Document 1, a multi-layered polishing pad is used to reduce minute defects. As a flatness index, only changes in ESFQR are measured, and unevenness in the circumferential direction of the wafer is not noticed. In addition, in the polishing pad described in Patent Document 2, it is necessary to improve the sagging of the outer periphery of the wafer based on the relationship between the surface roughness of the polishing pad and the compressibility, but the unevenness in the circumferential direction of the wafer is not noticed.
又,本說明書中的「ESFQR(Edge Site flatness Front reference least sQuares Range(邊緣部位平坦度正面基準最小平方範圍))」,意味SEMIM67規定的ESFQR的最大值與最小值之差異。 具體地,ESFQR的測量中,使用平坦度測量裝置(KLA-Tencor公司製:Wafer sight 2)。ESFQR,係表示在晶圓外周部(邊緣)的部位平坦度之指標。ESFQR,係分割晶圓外周部為多數(例如72個)扇形區域(部位),以利用最小平方法算出部位內的資料之部位內平面作為基準,根據此部位內平面的變位量,各部位中具有1個資料。 又,本說明書中的「ESFQR Range」係以扇形的各部位算出的ESFQR的最大量與最小量的差異,表示其晶圓周方向的不均量。 本說明書中的ESFQR Range的部位(site),例如,直徑300mm的晶圓中,以離最外周往直徑方向2mm(毫米)的區域為除外區域,其更內側的外周基準端往徑方向中心側延伸的扇形長是300mm的2條直線與相當於晶圓外周方向5度(±2.5度)的圓弧所圍繞的72個略矩形之分割部位。於是,ESFQR Range是這些72個ESFQR值中,以最大值與最小值算出的值。In addition, "ESFQR (Edge Site flatness Front reference least sQuares Range)" in this specification means the difference between the maximum value and the minimum value of ESFQR specified by SEMIM67. Specifically, for the measurement of ESFQR, a flatness measuring device (manufactured by KLA-Tencor: Wafer sight 2) was used. ESFQR is an index indicating the flatness of the part on the outer periphery (edge) of the wafer. ESFQR means that the outer periphery of the divided wafer is divided into many (for example, 72) fan-shaped regions (parts). The inner plane of the part using the least square method to calculate the data in the part is used as the reference. According to the displacement amount of the inner plane of this part, each part There is 1 data in. In addition, "ESFQR Range" in this specification is the difference between the maximum and minimum ESFQR calculated for each part of the fan shape, and represents the amount of unevenness in the circumferential direction of the wafer. The ESFQR Range site in this specification, for example, on a wafer with a diameter of 300mm, the area 2mm (millimeters) from the outermost circumference in the diameter direction is the exclusion area, and the outer reference end of the inner circumference is toward the center side in the radial direction. The extended sector has 72 roughly rectangular divisions surrounded by two straight lines of 300 mm in length and a circular arc corresponding to 5 degrees (±2.5 degrees) in the peripheral direction of the wafer. Therefore, the ESFQR Range is a value calculated from the maximum value and the minimum value among these 72 ESFQR values.
本發明的目的在於提供可以降低晶圓外周部的周方向平坦度不均量之晶圓的單面研磨方法、晶圓的製造方法及晶圓的單面研磨裝置。An object of the present invention is to provide a single-side polishing method for a wafer, a method for manufacturing a wafer, and a single-side polishing apparatus for a wafer that can reduce the unevenness in the circumferential flatness of the outer periphery of the wafer.
本發明者們,關於可以降低晶圓外周部的周方向平坦度不均量之研磨方法,專心研討的結果,藉由提高卡盤保持的晶圓自轉率,發現可以降低晶圓外周部的周方向平坦度不均量。認為原因是根據研磨裝置的卡盤等的凹凸等往晶圓背面轉印的面壓不均平均化。The inventors of the present invention have intensively studied a polishing method that can reduce the unevenness in the circumferential flatness of the wafer outer periphery. As a result, by increasing the wafer rotation rate held by the chuck, they have found that the circumference of the wafer outer periphery can be reduced. The amount of unevenness in direction flatness. It is considered that the cause is uneven surface pressure transferred to the back surface of the wafer due to unevenness of the chuck of the polishing apparatus and the like.
根據本發明者們作成特性不同的各種研磨墊研討的結果,作為提高晶圓自轉率的要素,有(1)研磨墊的壓縮率、(2)研磨墊對純水的接觸角、(3)研磨墊的構成、(4)晶圓外周與護圈內周的間隙、(5)研磨頭及平台在研磨時的旋轉數、以及(6)研磨加壓力等。藉由管理這些要素,可以管理晶圓的自轉率,可以降低平坦度不均量。又,提高晶圓自轉率的要素,單獨應用也可以,複數應用這些要素也可以。換言之,提高晶圓自轉率的各要素要求的範圍,不必全部要素同時滿足這些範圍,只要至少單獨滿足其範圍即可。According to the results of the inventors’ research on creating various polishing pads with different characteristics, the factors to improve the wafer rotation rate include (1) the compression rate of the polishing pad, (2) the contact angle of the polishing pad to pure water, and (3) The composition of the polishing pad, (4) the gap between the outer periphery of the wafer and the inner periphery of the retainer, (5) the number of rotations of the polishing head and the table during polishing, and (6) the polishing pressure. By managing these elements, the rotation rate of the wafer can be managed, and the unevenness of the flatness can be reduced. In addition, the factors that increase the wafer rotation rate may be applied alone, or they may be applied in plural. In other words, it is not necessary for all the elements to satisfy these ranges at the same time as the ranges required for each element to increase the wafer rotation rate, as long as the ranges are satisfied at least individually.
根據圖4〜圖8,簡單說明提高本發明者們研討的晶圓自轉率之各要素與晶圓自轉率的關係。 這些圖4〜圖8,作成特性不同的各種研磨墊,根據取得的資料作成。 圖4,係顯示晶圓自轉率(度/min)與ESFQR Range(nm)的關係圖。 根據圖4,明白自轉率越大ESFQR Range(nm)越小(改善)。 因此,透過取得晶圓自轉率變大的對策,可以達成降低晶圓外周部的周方向平坦部不均量之本發明的目標。Based on FIGS. 4 to 8, the relationship between the factors that improve the wafer rotation rate discussed by the inventors and the wafer rotation rate will be briefly described. These Figures 4 to 8 are used to create various polishing pads with different characteristics, based on the acquired data. Figure 4 shows the relationship between wafer rotation rate (degrees/min) and ESFQR Range (nm). According to Figure 4, it is clear that the larger the rotation rate, the smaller the ESFQR Range (nm) (improvement). Therefore, it is possible to achieve the objective of the present invention to reduce the unevenness of the circumferential flat portion of the outer peripheral portion of the wafer by taking a countermeasure against the increase in the rotation rate of the wafer.
圖5,係顯示研磨墊具有的起毛(nap)層的壓縮率(Nap壓縮率)(%)與晶圓自轉率(a.u.)的關係圖。 根據圖5,明白Nap壓縮率(%)越大,晶圓自轉率(a.u.)越大。 因此,透過某程度增大Nap壓縮率(%),晶圓自轉率(a.u.)變大,可以降低晶圓外周部的周方向平坦部不均量。 在此,作為圖5到後述之圖8的晶圓自轉率(a.u.)具體單位,例如,是(度/min)。Figure 5 is a graph showing the relationship between the compression rate (Nap compression rate) (%) of the nap layer of the polishing pad and the wafer rotation rate (a.u.). According to Figure 5, it is understood that the greater the Nap compression rate (%), the greater the wafer rotation rate (a.u.). Therefore, by increasing the Nap compression rate (%) to a certain extent, the wafer rotation rate (a.u.) becomes larger, and the unevenness of the circumferential flat portion of the outer periphery of the wafer can be reduced. Here, as a specific unit of the wafer rotation rate (a.u.) in FIG. 5 to FIG. 8 described later, for example, (degree/min).
圖6,係顯示研磨墊之研磨晶圓的面(晶圓研磨面)表面上對於純水的接觸角(度)與晶圓自轉率(a.u.)的關係圖。 根據圖6,明白研磨墊之晶圓研磨面表面上對於純水的接觸角(度)越大,晶圓自轉率(a.u.)越大。 因此,透過某程度增大研磨墊之晶圓研磨面表面上對於純水的接觸角(度),晶圓自轉率(a.u.)變大,可以降低晶圓外周部的周方向平坦部不均量。FIG. 6 is a diagram showing the relationship between the contact angle (degrees) of the pure water on the surface of the polishing pad (wafer polishing surface) and the wafer rotation rate (a.u.). According to Figure 6, it is understood that the greater the contact angle (degree) of the polishing pad's wafer polishing surface to pure water, the greater the wafer rotation rate (a.u.). Therefore, by increasing the contact angle (degrees) of the wafer polishing surface of the polishing pad to pure water to a certain extent, the wafer rotation rate (au) increases, and the unevenness of the peripheral flat portion of the wafer outer periphery can be reduced. .
圖7,係顯示護圈內徑(mm)與晶圓自轉率(a.u.)的關係圖。圖7中使用的晶圓直徑是300mm。 根據圖7,明白護圈內徑越大,晶圓自轉率(a.u.)越大。 因此,透過某程度增大護圈內徑(mm),晶圓自轉率(a.u.)變大,可以降低晶圓外周部的周方向平坦部不均量。 所謂護圈內徑(mm)大,係考慮與晶圓外周之間的間隙變大,晶圓自轉率(a.u.)變大。Figure 7 shows the relationship between the inner diameter of the retainer ring (mm) and the wafer rotation rate (a.u.). The diameter of the wafer used in Figure 7 is 300mm. According to Figure 7, it is understood that the larger the inner diameter of the retainer, the larger the wafer rotation rate (a.u.). Therefore, by increasing the inner diameter (mm) of the retainer ring to some extent, the wafer rotation rate (a.u.) increases, and the unevenness of the circumferential flat portion of the outer periphery of the wafer can be reduced. The so-called retainer inner diameter (mm) is large, because the gap with the outer periphery of the wafer becomes larger, and the wafer rotation rate (a.u.) becomes larger.
圖8係顯示晶圓研磨時的研磨加壓(g/cm2 )與晶圓自轉率(a.u.)的關係圖。 根據圖8,明白雖不是直線關係,但研磨加壓(g/cm2 )越大,晶圓自轉率(a.u.)變大。 因此,透過某程度增大研磨加壓(g/cm2 ),晶圓自轉率(a.u.)變大,可以降低晶圓外周部的周方向平坦部不均量。 [用以解決課題的手段]FIG. 8 is a graph showing the relationship between polishing pressure (g/cm 2 ) and wafer rotation rate (au) during wafer polishing. According to Fig. 8, it is understood that although the relationship is not linear, the greater the polishing pressure (g/cm 2 ), the greater the wafer rotation rate (au). Therefore, by increasing the polishing pressure (g/cm 2 ) to a certain extent, the wafer rotation rate (au) becomes larger, and the unevenness in the circumferential flat portion of the outer periphery of the wafer can be reduced. [Means to solve the problem]
本發明的研磨方法,係晶圓的單面研磨方法,其特徵在於包括研磨步驟,按壓研磨頭保持的晶圓至平台表面上固定的研磨墊,透過旋轉上述研磨頭及上述平台,對上述晶圓的被研磨面施行研磨加工,上述研磨步驟中,上述晶圓的自轉率在25度/min以上60度/min以下,研磨上述晶圓。The polishing method of the present invention is a single-sided polishing method for wafers, characterized in that it includes a polishing step, pressing the wafer held by the polishing head to a polishing pad fixed on the surface of the platform, and rotating the polishing head and the platform to perform the polishing on the crystal The round surface to be polished is polished. In the polishing step, the rotation rate of the wafer is 25 degrees/min or more and 60 degrees/min or less, and the wafer is polished.
根據此發明,可以降低晶圓外周部的周方向平坦部不均量。According to this invention, it is possible to reduce the unevenness in the circumferential flat portion of the outer peripheral portion of the wafer.
上述晶圓的單面研磨方法中,作為上述研磨墊,最好使用具有壓縮率58.5%以上70%以下的起毛層之研磨墊。In the single-sided polishing method of the wafer, it is preferable to use a polishing pad having a raised layer with a compression ratio of 58.5% or more and 70% or less as the polishing pad.
上述晶圓的單面研磨方法中,作為上述研磨墊,在研磨上述晶圓的面的表面上對於純水之接觸角,最好採用上述純水滴下1800秒後58度以上70度以下的研磨墊。In the single-sided polishing method of the wafer, as the polishing pad, the contact angle of the pure water on the surface of the wafer to be polished is preferably 58 degrees or more and 70 degrees after the pure water is dropped for 1800 seconds. pad.
上述晶圓的單面研磨方法中,作為上述研磨墊,最好採用不使用不織布的起毛層單體的研磨墊。In the single-sided polishing method of the wafer described above, it is preferable to use a polishing pad that does not use a single raised layer of a non-woven fabric as the polishing pad.
上述晶圓的單面研磨方法中,保持上述晶圓的護圈內徑,最好採用上述護圈內徑與上述晶圓直徑的比例以下式 護圈內徑/晶圓直徑=1.0015以上1.0067以下 表示的護圈。In the single-sided polishing method of the wafer, the inner diameter of the retainer of the wafer is maintained, and the ratio of the inner diameter of the retainer to the diameter of the wafer is preferably the following formula Retainer inner diameter/wafer diameter=1.0015 or more and 1.0067 or less Represents the guard ring.
上述晶圓的單面研磨方法中,上述平台在研磨時的旋轉數最好設定在15rpm以上80rpm以下。In the single-sided polishing method of the wafer, the number of rotations of the table during polishing is preferably set at 15 rpm or more and 80 rpm or less.
上述晶圓的單面研磨方法中,研磨加壓最好設定在100g/cm2 以上300g/cm2 以下。In the single-sided polishing method of the wafer, the polishing pressure is preferably set to 100 g/cm 2 or more and 300 g/cm 2 or less.
上述晶圓的單面研磨方法中,預先求出研磨條件與晶圓自轉率的關係,最好根據上述關係決定研磨條件。In the single-sided polishing method of the wafer, the relationship between the polishing conditions and the rotation rate of the wafer is determined in advance, and it is preferable to determine the polishing conditions based on the relationship.
上述晶圓的單面研磨方法中,上述研磨條件,最好是研磨墊的壓縮率、接觸角、護圈內徑與上述晶圓直徑的比例、研磨平台旋轉數、研磨加壓量其中任一項或其組合。In the single-sided polishing method of the wafer, the polishing conditions are preferably any of the compressibility of the polishing pad, the contact angle, the ratio of the inner diameter of the guard ring to the diameter of the wafer, the number of rotations of the polishing table, and the amount of polishing pressure. Items or combinations thereof.
又,本發明的製造方法,是晶圓的製造方法,其特徵在於包括完成加工上述晶圓的至少一面之單面完工步驟,上述單面完工步驟中,利用上述晶圓的單面研磨方法,對上述晶圓的被研磨面施行研磨加工。In addition, the manufacturing method of the present invention is a method of manufacturing a wafer, which is characterized by including a single-sided finishing step for processing at least one side of the wafer. In the single-sided finishing step, the single-sided polishing method of the wafer is used, Polishing is performed on the polished surface of the above-mentioned wafer.
又,本發明的研磨裝置,係晶圓的單面研磨裝置,其特徵在於包括:頭部旋轉軸構件,設置保持上述晶圓的研磨頭;平台,固定研磨墊至表面;頭部驅動手段,驅動上述頭部旋轉軸構件;平台驅動手段,驅動上述平台;晶圓加壓力調整手段,調整按壓上述晶圓至上述研磨墊的壓力;以及研磨條件決定部,決定研磨條件;上述研磨條件決定部,決定研磨條件使晶圓的自轉率在25度/min以上60度/min以下。 [發明效果]In addition, the polishing device of the present invention is a single-side polishing device for wafers, which is characterized by comprising: a head rotating shaft member provided with a polishing head for holding the wafer; a platform for fixing the polishing pad to the surface; and head driving means, Driving the head rotating shaft member; a stage driving means to drive the stage; a wafer pressure adjusting means to adjust the pressure of pressing the wafer to the polishing pad; and a polishing condition determination unit to determine polishing conditions; the polishing condition determination unit , Determine the polishing conditions so that the rotation rate of the wafer is 25 degrees/min or more and 60 degrees/min or less. [Effects of the invention]
根據本發明,提供可以降低晶圓外周部的周方向平坦度不均量之晶圓的單面研磨方法、晶圓的製造方法及晶圓的單面研磨裝置。According to the present invention, there are provided a single-side polishing method for a wafer, a method for manufacturing a wafer, and a single-side polishing apparatus for a wafer that can reduce the unevenness in the circumferential flatness of the outer periphery of the wafer.
以下,詳細說明關於本發明的一實施形態。
[研磨裝置的構成]
首先,一邊參照附加圖面,一邊說明關於本發明一實施形態的單面研磨裝置1。
如圖1及圖2所示,單面研磨裝置1,包括複數頭部旋轉軸構件11、設置在各頭部旋轉軸構件11的研磨頭12、設置在各研磨頭12的背墊13、設置在各背墊13的護圈14、平台15、設置在平台15的研磨墊16、驅動各頭部旋轉軸構件11的頭部驅動手段20、平台驅動手段30、研磨液供給手段40、調整按壓各研磨頭12保持的晶圓W至研磨墊16之際的壓力之晶圓加壓力調整手段50、研磨控制手段60以及研磨條件決定部70。Hereinafter, an embodiment of the present invention will be described in detail.
[Configuration of Grinding Device]
First, referring to the attached drawings, a single-side polishing apparatus 1 according to an embodiment of the present invention will be described.
As shown in Figures 1 and 2, the single-sided polishing device 1 includes a plurality of head rotating
頭部旋轉軸構件11,以軸狀構件構成。頭部旋轉軸構件11,可繞軸旋轉,連接至具備馬達等旋轉驅動源的頭部驅動手段20的旋轉軸,旋轉研磨頭12。The head
研磨頭12,連接至頭部旋轉軸構件11的下端部。研磨頭12,由以頭部旋轉軸構件11的旋轉中心為中心之圓形厚板狀構成。研磨頭12,利用水的表面張力等,保持與晶圓W的被研磨面(表面)相反側的面(背面)。The grinding
背墊13,係設置在研磨頭12下面,與研磨頭12同徑的圓形板狀體。背墊13,例如,以多孔質樹脂材構成,可以包含水等液體。The
護圈14,設置在背墊13下面的外周部,由環狀構件形成。護圈14,接觸晶圓W的外周端部,保持晶圓W不偏離背墊13與之後敘述的研磨墊16的間隙。
當研磨晶圓W時,研磨中有使護圈14接觸研磨墊16的情況或不接觸的情況。接觸的情況下,護圈14的厚度不均影響晶圓W外周部周方向的平坦度不均,但根據本發明的方法,不會增加成本,可以降低周方向的不均。The
平台15,對向複數研磨頭12設置,形成圓形狀。平台15,被支撐自由旋轉,往與研磨頭12的旋轉方向同方向或反方向旋轉。在平台15上面,黏貼用以研磨晶圓W的被研磨面的研磨墊16。The
研磨墊16,以作為基材的不織布與上述不織布的一面上積層的起毛(Nap)層構成。透過以既定的力按壓晶圓W表面(對向研磨墊16的面)至研磨墊16的起毛(Nap)層,實行晶圓W的研磨。在此,所謂起毛(Nap)層係指具有以發泡形成多數孔的層。The
頭部驅動手段20,旋轉研磨頭12的頭部旋轉軸構件11。The head driving means 20 rotates the head rotating
平台驅動手段30,以馬達等構成,旋轉連接至平台15下面的平台旋轉軸構件31。The platform driving means 30 is composed of a motor or the like, and is rotatably connected to the platform
研磨液供給手段40,設置在平台15上方,構成為利用噴嘴41對研磨墊16與晶圓W的接觸面供給泥漿(slurry)狀的研磨液。The polishing liquid supply means 40 is provided above the
晶圓加壓力調整手段50,係固定加壓方式,調整對研磨墊16按壓晶圓W的壓力。固定加壓方式,利用圓柱加壓按下研磨頭12全體,透過經由背墊13按壓研磨頭12至晶圓W上面,按壓晶圓W的被研磨面至平台15上的研磨墊16。The wafer pressure adjusting means 50 adopts a fixed pressure method to adjust the pressure of the wafer W against the
研磨控制手段60,根據研磨條件決定部70決定的既定研磨條件,控制頭部驅動手段20、平台驅動手段30、研磨液供給手段40及晶圓加壓力調整手段50中的至少一個,控制單面研磨裝置1的動作。The polishing control means 60 controls at least one of the head driving means 20, the stage driving means 30, the polishing liquid supply means 40, and the wafer pressure adjusting means 50 based on the predetermined polishing conditions determined by the polishing
研磨條件決定部70,記憶預先求出的研磨條件與晶圓自轉率的關係,根據記憶的關係決定研磨條件。在那之際,使用計算機等自動決定研磨條件也可以。The polishing
[研磨方法]
其次,說明關於使用單面研磨裝置1之晶圓的單面研磨方法的一例。
單面研磨裝置1的研磨條件決定部70,在晶圓W的研磨前,預先求出並記憶研磨條件與晶圓自轉率的關係。
單面研磨裝置1,設定輸入開始研磨晶圓W之內容的指令時,在研磨條件決定部70中,根據記憶的研磨條件與晶圓自轉率的關係,決定研磨條件。
於是,以決定的研磨條件,利用研磨控制手段60,控制頭部驅動手段20、平台驅動手段30、研磨液供給手段40及晶圓加壓力調整手段50,實施晶圓W的研磨步驟。
具體地,首先,選定適合之決定好的研磨條件之研磨墊16,配置平台15。接著,平台15的研磨墊16上,由研磨液供給手段40供給既定量研磨液。於是,保持晶圓W的研磨頭12,透過頭部驅動手段20的驅動,一邊旋轉一邊下降,使晶圓W往透過平台驅動手段30的驅動旋轉的平台15的研磨墊16上接觸。之後,晶圓加壓力調整手段50調整按壓晶圓W至研磨墊16的壓力,實行研磨晶圓W的被研磨面之研磨步驟。[Grinding method]
Next, an example of a single-side polishing method for a wafer using the single-side polishing device 1 will be described.
The polishing
本實施形態中,研磨步驟中,控制晶圓W的自轉率在25度/min以上60度/min,對晶圓W的被研磨面施行研磨加工。 藉由控制晶圓W的自轉率在25度/min以上,可以降低晶圓外周部的周方向平坦度不均量。又,藉由設定晶圓W的自轉率在60度/min以下,可以防止晶圓W的擦傷以及晶圓跳出等。 另一方面,晶圓W的自轉率超過60度/min時,有可能背墊變得不能保持晶圓。 晶圓W的自轉率更理想是在25度/min以上40度/min以下,又更理想是在26度/min以上30度/min以下。又,關於晶圓W的自轉率,在25度/min以上60度/min以下的範圍內,最好是越接近26度/min以上30度/min以下的範圍,越可以發揮本發明的效果。因此,在25度/min以上60度/min以下的範圍內任何數值中即使畫分其範圍也可以發揮其對應的效果。In this embodiment, in the polishing step, the rotation rate of the wafer W is controlled to be 25 degrees/min or more and 60 degrees/min, and the polished surface of the wafer W is polished. By controlling the rotation rate of the wafer W to be 25 degrees/min or more, the unevenness in the circumferential flatness of the outer periphery of the wafer can be reduced. In addition, by setting the rotation rate of the wafer W to 60 degrees/min or less, it is possible to prevent the wafer W from scratching and wafer jumping out. On the other hand, when the rotation rate of the wafer W exceeds 60 degrees/min, the back pad may become unable to hold the wafer. The rotation rate of the wafer W is more preferably 25 degrees/min or more and 40 degrees/min or less, and more preferably 26 degrees/min or more and 30 degrees/min or less. In addition, regarding the rotation rate of the wafer W, within the range of 25 degrees/min or more and 60 degrees/min or less, it is preferable that the closer to the range of 26 degrees/min or more and 30 degrees/min or less, the more the effects of the present invention can be exerted. . Therefore, any numerical value in the range of 25 degrees/min or more and 60 degrees/min or less can exhibit its corresponding effect even if the range is divided.
晶圓W的自轉率,只要在研磨條件的選擇時確認即可。或者,藉由模擬,求出自轉率也可以。又,觀察研磨前後晶圓W的凹槽,或利用感應器等即時檢測等,直接觀察實際研磨時的晶圓自轉率也可以。 觀察凹槽位置求出晶圓W的自轉率之際,具體地,觀察研磨前後晶圓W的凹槽位置,透過以研磨時間(分)分割凹槽位置移動的角度,計算每1分鐘的自轉率(度/min)。The rotation rate of the wafer W can be confirmed when the polishing conditions are selected. Alternatively, the rotation rate may be obtained by simulation. In addition, it is also possible to observe the grooves of the wafer W before and after polishing, or to directly observe the rotation rate of the wafer during actual polishing by using a sensor or other real-time detection. When observing the position of the groove to obtain the rotation rate of the wafer W, specifically, observing the position of the groove of the wafer W before and after polishing, and calculating the rotation per minute by dividing the angle of the groove position movement by the polishing time (minutes) Rate (degrees/min).
本實施形態中,利用自轉率的控制,最好控制ESFQR Range在6.5nm以下。In this embodiment, it is better to control the ESFQR Range to 6.5 nm or less by controlling the rotation rate.
本實施形態中,例如,作為研磨墊16,藉由使用具有壓縮率在58.5%以上的起毛層之研磨墊,可以控制研磨步驟中的晶圓W自轉率在25度/min以上。
起毛層的壓縮率,例如使用購物者型厚度測量器,利用以下的方法可以測量。
(1) 以既定的初負重加壓一定時間,測量其厚度(t0
)。
(2) 其上裝載既定的追加負重,一定時間後測量厚度(t1
)。
(3) 以次式計算壓縮率。
壓縮率(%)={(t0
-t1
)/ t0
}×100
因為研磨的起毛層磨耗很少就可應付,起毛層的壓縮率理想在70%以下。起毛層的壓縮率更理想在58.5%以上63%以下。又,關於起毛層的壓縮率,在58.5%以上70%以下的範圍中,更理想是越接近58.5%以上63%以下的範圍,越可以發揮本發明的效果。因此,在58.5%以上70%以下的範圍內任何數值中即使畫分其範圍也可以發揮其對應的效果。In this embodiment, for example, as the
又,例如,本實施形態中,作為研磨墊16,藉由採用在研磨晶圓W的面之表面上對於純水之接觸角在58度以上70度以下的研磨墊,可以控制研磨步驟中晶圓W的自轉率在25度/min以上60度/min以下。
研磨墊16在研磨晶圓W的面之表面上對於純水之接觸角超過70度的研磨墊,在生產上作成很困難。
又,本說明書中的接觸角,係在研磨墊16表面上滴下純水1μm,從上述純水滴下1800秒後,以根據側面的圖像解析測量的水滴與研磨墊表面的接觸角。Also, for example, in the present embodiment, as the
上述起毛層的壓縮率及研磨墊的接觸角,例如,根據構成研磨墊16的樹脂及添加劑等的選定以及成膜製程條件及拋光(buffing)的加工餘量控制,可以調整所希望值。例如,壓縮率根據樹脂種類調整,接觸角根據添加劑種類調整等,壓縮率及接觸角可以分別獨自調整。
作為構成研磨墊的樹脂,例如,舉出聚氨酯(polyurethane)樹脂以及聚亞醯氨(polyimide)樹脂等。
作為添加劑,例如,舉出顏料、成膜安定劑以及發泡形成劑等。又,作為顏料,例如,舉出碳黑等。作為成膜安定劑,舉出非離子型界面活性劑等。作為發泡形成劑,舉出陰離子型界面活性劑等。The compressibility of the raised layer and the contact angle of the polishing pad can be adjusted to desired values, for example, according to the selection of the resin and additives constituting the
本實施形態中,根據更提高自轉率的觀點,最好採用內徑對晶圓W直徑的比例(護圈14的內徑/晶圓W的直徑)在1.0015以上1.0067以下的護圈。例如,晶圓W的直徑是300mm時,護圈14的內徑,最好是300.5mm以上302mm以下。In this embodiment, from the viewpoint of further increasing the rotation rate, it is preferable to adopt a retainer whose inner diameter to the diameter of the wafer W (the inner diameter of the
本實施形態,根據更提高自轉率的觀點,最好採用平台15在研磨時的旋轉數,最好在15rmp以上。另一方面,根據防止外周下垂的觀點,平台15在研磨時的旋轉數,最好在80rmp以下。 平台15在研磨時的旋轉數,更理想是在20rmp以上40rmp以下。上述旋轉數在40rmp以下的話,也沒有平坦度絕對值惡化的危險。又,關於上述旋轉數,在15rmp以上80rmp以下的範圍內,更理想是越接近20rmp以上40rmp以下的範圍,越可以發揮本發明的效果。因此,在15rmp以上80rmp以下的範圍內任何數值中即使畫分其範圍也可以發揮其對應的效果。In this embodiment, from the viewpoint of further increasing the rotation rate, it is preferable to use the number of rotations of the table 15 during polishing, and it is more preferable to be 15 rpm or more. On the other hand, from the viewpoint of preventing the outer circumference from sagging, the number of rotations of the table 15 during polishing is preferably 80 rpm or less. The number of rotations of the table 15 during polishing is more preferably 20 rpm or more and 40 rpm or less. If the above-mentioned number of rotations is less than 40 rpm, there is no danger that the absolute value of the flatness will deteriorate. In addition, the number of rotations described above is within the range of 15 rpm or more and 80 rpm or less, and it is more desirable that the closer to the range of 20 rpm or more and 40 rpm or less, the more the effects of the present invention can be exerted. Therefore, any numerical value in the range of 15 rpm or more and 80 rpm can exhibit the corresponding effect even if the range is divided.
本實施形態中,根據更提高晶圓W自轉率的觀點,研磨加壓(研磨時按壓晶圓W至研磨墊16的壓力),最好設定為100g/cm2
以上。另一方面,根據防止晶圓裂開的觀點,研磨加壓最好在300g/cm2
以下。
研磨加壓,更理想是在125g/cm2
以上200g/cm2
以下。研磨加壓在200g/cm2
以下的話,不阻礙研磨墊16與晶圓W之間流入研磨劑,也沒有使晶圓W發生缺陷的危險。又,關於研磨加壓,在100g/cm2
以上300g/cm2
以下的範圍內,更理想是越接近125g/cm2
以上200g/cm2
以下的範圍,越可以發揮本發明的效果。因此,在100g/cm2
以上300g/cm2
以下的範圍內任何數值中即使畫分其範圍也可以發揮其對應的效果。In this embodiment, from the viewpoint of further increasing the rotation rate of the wafer W, the polishing pressure (pressure for pressing the wafer W to the
本實施形態中,不特別限定研磨對象的晶圓W。作為晶圓W,例如,舉出矽晶圓以及SiC晶圓等。 又,本實施形態中,研磨對象的晶圓W直徑,不特別限定。例如,舉出直徑150mm的晶圓、直徑200mm的晶圓以及直徑300mm的晶圓等。 研磨這些不同直徑的晶圓時,也與上述相同,保持晶圓的護圈內徑與晶圓直徑的比例,最好採用次式表示的護圈。 護圈內徑/晶圓直徑=1.0015以上1.0067以下In this embodiment, the wafer W to be polished is not particularly limited. As the wafer W, for example, a silicon wafer, a SiC wafer, and the like are mentioned. In this embodiment, the diameter of the wafer W to be polished is not particularly limited. For example, a wafer with a diameter of 150 mm, a wafer with a diameter of 200 mm, and a wafer with a diameter of 300 mm are mentioned. When polishing these wafers of different diameters, the same is true as described above. To maintain the ratio of the inner diameter of the wafer retainer to the wafer diameter, it is best to use the retainer represented by the formula. Retainer inner diameter/wafer diameter=1.0015 or more and 1.0067 or less
利用本實施形態的研磨方法的研磨液,不特別限制。晶圓的研磨中使用的一般研磨液,也可以在本實施形態中使用。The polishing liquid used in the polishing method of this embodiment is not particularly limited. The general polishing liquid used for polishing wafers can also be used in this embodiment.
[晶圓的製造方法] 其次,說明關於包含本實施形態的單面研磨方法之矽晶圓的製造方法。 矽晶圓的製造方法概略,係利用Czochralski法(單晶成長法)製造矽晶圓,以上述單面研磨方法實行晶圓W研磨的方法。[Wafer manufacturing method] Next, a description will be given of a method of manufacturing a silicon wafer including the single-side polishing method of this embodiment. The outline of the manufacturing method of the silicon wafer is a method in which the silicon wafer is manufactured by the Czochralski method (single crystal growth method), and the wafer W is polished by the above-mentioned single-sided polishing method.
如圖3所示,矽晶圓的製造方法,具有提拉步驟S1、區塊加工步驟S2、切割步驟S3、前處理步驟S4、兩面同時研磨步驟S5、單面研磨裝置設定步驟S6、研磨條件決定步驟S7、研磨步驟S8、晶圓取出步驟S9。As shown in Figure 3, the manufacturing method of a silicon wafer has a pulling step S1, a block processing step S2, a cutting step S3, a pre-processing step S4, a two-side simultaneous polishing step S5, a single-side polishing device setting step S6, and polishing conditions The decision step S7, the polishing step S8, and the wafer take-out step S9 are determined.
在此,以單面研磨裝置設定步驟S6、研磨條件決定步驟S7、研磨步驟S8及晶圓取出步驟S9,構成單面完工步驟S20。Here, the single-side polishing device setting step S6, the polishing condition determination step S7, the polishing step S8, and the wafer take-out step S9 constitute a single-side finishing step S20.
提拉步驟S1,係利用Czochralski法(單晶成長法)從矽融液提拉單結晶的步驟。藉此,得到圓柱狀的單晶錠。 區塊加工步驟S2,係加工單晶錠為區塊的步驟。區塊加工步驟S2中,實行單晶錠的外周研削,根據結晶方位實行凹槽加工後,利用例如條帶鋸,切斷單晶錠為複數區塊。The pulling step S1 is a step of pulling a single crystal from the silicon melt by the Czochralski method (single crystal growth method). In this way, a columnar single crystal ingot is obtained. The block processing step S2 is a step of processing a single crystal ingot into a block. In the block processing step S2, the outer periphery of the single crystal ingot is ground, and after the groove processing is performed according to the crystal orientation, the single crystal ingot is cut into plural blocks using, for example, a band saw.
切割步驟S3中,利用內周刀切斷機或鋼線鋸,切割區塊為例如厚1mm左右的複數矽晶圓。 前處理步驟S4中,實行去角加工的同時,為了使晶圓兩面平行,以例如氧化鋁研磨材等實行粗研磨(lapping),根據需要施行蝕刻等後,實行去掉晶圓表面凹凸的平坦化加工。In the dicing step S3, using an inner peripheral knife cutter or a steel wire saw, the dicing block is, for example, a plurality of silicon wafers with a thickness of about 1 mm. In the pre-processing step S4, in order to make the two sides of the wafer parallel, rough lapping is carried out with an alumina abrasive, etc., and etching is carried out as necessary, and then the unevenness of the wafer surface is flattened. Processing.
兩面同時研磨步驟S5中,對實行前處理的晶圓實行平坦度高的鏡面完工。例如使用膠質氧化矽(colloidal silica)液等實行兩面研磨(polishing),更致力於平坦度,形成既定平坦度的晶圓。In the simultaneous double-sided polishing step S5, a highly flat mirror finish is performed on the wafer subjected to the pre-processing. For example, the use of colloidal silica (colloidal silica) liquid etc. to carry out double-sided polishing (polishing), and more efforts to flatness, to form a predetermined flatness of the wafer.
既定平坦度的晶圓在單面研磨裝置設定步驟S6由單面研磨裝置設定。 研磨條件決定步驟S7中,決定研磨控制手段中研磨條件決定部的研磨條件,平台中配置適合決定的研磨條件之研磨墊的同時,單面研磨裝置的各部,具體地,指示頭部驅動手段、平台驅動手段、研磨液供給手段、晶圓加壓力調整手段決定的研磨條件。 研磨步驟S8中,根據決定的研磨條件,進行研磨,在晶圓取出步驟S9中取出晶圓。 根據單面研磨裝置設定步驟S6、研磨條件決定步驟S7、研磨步驟S8以及晶圓取出步驟S9所得到的單面完工步驟S20中,藉由施行研磨加工,除去上述平坦度加工後的矽晶圓表面的缺陷及損傷的同時,可以整理矽晶圓的表面粗糙度。The wafer with a predetermined flatness is set by the single-side polishing device in the single-side polishing device setting step S6. In the polishing condition determination step S7, the polishing condition of the polishing condition determining part of the polishing control means is determined, the polishing pad suitable for the determined polishing condition is arranged in the platform, and each part of the single-side polishing device, specifically, instructs the head driving means, The polishing conditions are determined by the platform driving means, the polishing liquid supply means, and the wafer pressure adjustment means. In the polishing step S8, polishing is performed according to the determined polishing conditions, and the wafer is taken out in the wafer taking-out step S9. According to the single-sided polishing device setting step S6, the polishing condition determination step S7, the polishing step S8, and the wafer take-out step S9 in the single-sided finishing step S20, the silicon wafer after the flatness processing is removed by performing the polishing process At the same time as surface defects and damages, the surface roughness of silicon wafers can be adjusted.
晶圓取出步驟S9中取出的各個矽晶圓,在洗淨步驟S10中,進行例如利用鹼性溶液等的洗淨。Each silicon wafer taken out in the wafer take-out step S9 is cleaned, for example, with an alkaline solution in the cleaning step S10.
晶圓最終檢查步驟S11,使用晶圓表面檢查裝置等,檢查存在矽晶圓表面上的微粒或缺陷等的步驟。 進行晶圓在品質上必需的檢查後,將合格品包裝、出貨。The wafer final inspection step S11 is a step of inspecting particles or defects on the surface of the silicon wafer using a wafer surface inspection device or the like. After checking the quality of the wafers, the qualified products are packaged and shipped.
[實施形態的作用效果] 如上述,根據本發明者們的見解,因為單面研磨是夾住晶圓背面,研磨表面側的機構,受到保持側的卡盤形狀不均、背墊的保持材厚度不均以及護圈厚度等副資材產生的影響,往晶圓背面轉印的面壓中發生不均,明白矽晶圓外周部在周方向的加工餘量不均。 根據上述實施形態,藉由提高晶圓的自轉率,可以平均化上述副資材引起的往背面轉印的面壓不均。因此,可以降低晶圓在周方向的平坦度不均量。[Effects of the implementation form] As mentioned above, according to the findings of the present inventors, because single-sided polishing is a mechanism that clamps the backside of the wafer and polishes the surface side, the uneven shape of the chuck on the holding side, the uneven thickness of the holding material of the backing pad, and the thickness of the guard ring The surface pressure transferred to the back surface of the wafer has unevenness due to the influence of the auxiliary materials, and it is understood that the processing allowance of the outer periphery of the silicon wafer is uneven in the circumferential direction. According to the above-mentioned embodiment, by increasing the rotation rate of the wafer, it is possible to average out the uneven surface pressure caused by the sub-materials transferred to the back surface. Therefore, the unevenness of wafer flatness in the circumferential direction can be reduced.
上述實施形態中,作為提高晶圓自轉率的要素,著眼於研磨墊的壓縮率、接觸角、護圈內徑與上述晶圓直徑的比例,研磨平台旋轉數、研磨加壓量,單獨或組合各要素的任一個,得到所希望的晶圓的自轉率後,研磨條件選定的自由度高,具有可以實行根據晶圓狀況的研磨之效果。In the above embodiment, as the factors to increase the wafer rotation rate, focus on the compression ratio of the polishing pad, the contact angle, the ratio of the inner diameter of the guard ring to the diameter of the wafer, the number of rotations of the polishing table, and the amount of polishing pressure, alone or in combination For any of the elements, after obtaining the desired rotation rate of the wafer, the degree of freedom in selecting the polishing conditions is high, and there is an effect that polishing according to the condition of the wafer can be performed.
[變形例] 又,本發明不限於上述實施形態。在不脫離本發明主旨的範圍內,可以作各種改良及設計的變更等。[Modifications] In addition, the present invention is not limited to the above-mentioned embodiment. Various improvements and design changes can be made without departing from the scope of the present invention.
例如,上述實施形態中,作為單面研磨裝置1中的背墊13及護圈14,說明採用背墊13下面的外周部設置護圈14成為一體的模板例,但研磨裝置本體具有護圈也可以。For example, in the above embodiment, as the
又,例如,上述實施形態中,作為單面研磨裝置1中的研磨墊16,說明採用具有作為基材的不織布與起毛層之研磨墊的例,但研磨墊,採用不使用不織布的起毛層單體的研磨墊也可以。由於採用不使用不織布的起毛層單體的研磨墊,不受不織布等其它的基底層厚度起伏及密度粗密影響,可以抑制ESFQR Range的惡化。或者,採用以樹脂膜等作為基材的研磨墊也可以。
[實施例]Also, for example, in the above-mentioned embodiment, as the
聚氨酯(polyurethane)樹脂的選定,藉由調整CB(碳黑)、成膜安定劑及溶劑(DMF)等添加劑、成膜製程條件以及拋光(buffing)的加工餘量,製作壓縮率與接觸角不同的研磨墊(墊A〜C)。又,墊A〜C中,控制壓縮率與接觸角以外的物性不變化。在表1中顯示墊A〜C的各物性。The selection of polyurethane resin, by adjusting CB (carbon black), film forming stabilizer and solvent (DMF) and other additives, film forming process conditions and polishing (buffing) processing allowance, the production compression rate and contact angle are different Of polishing pads (pads A~C). In addition, in the pads A to C, physical properties other than the control compression rate and contact angle did not change. Table 1 shows the physical properties of pads A to C.
[表1]
研磨中,作為研磨墊,使用上述記載的墊A〜C。又,作為背墊及護圈,使用這些成為一體的模板型。又,作為上述模板,使用護圈內徑301mm、背墊直徑290mm位置的周方向Thickness range(36點測量)是10μm的Fujibou製模板(POLYPAS_Template)。In polishing, the pads A to C described above were used as polishing pads. In addition, as a back pad and a guard ring, a template type in which these are integrated is used. In addition, as the above-mentioned template, a Fujibou-made template (POLYPAS_Template) of 10 μm in the circumferential thickness range (36-point measurement) at the position of the retainer inner diameter of 301 mm and the back pad diameter of 290 mm was used.
研磨對象的晶圓,係準備直徑300mm的單晶矽晶圓,單面研磨(SMP)前的ESFQD平均值在0nm以上5nm以下之晶圓各60枚。研磨加壓為150 g/cm2 ,研磨墊及平台旋轉數分別為30rmp。研磨液中,使用包含粒徑35nm的膠質氧化矽(colloidal silica)0.3wt%之物,研磨晶圓4分鐘,使加工餘量在500nm以上1000nm以下。The wafers to be polished are single crystal silicon wafers with a diameter of 300mm. The average ESFQD before single-sided polishing (SMP) is 60 wafers each with an average value of 0nm to 5nm. The grinding pressure is 150 g/cm 2 , and the rotation number of the grinding pad and the platform is 30 rpm. In the polishing liquid, 0.3wt% of colloidal silica with a particle size of 35nm was used to polish the wafer for 4 minutes so that the machining allowance was above 500nm and below 1000nm.
[自轉率的測量] 藉由觀察研磨前後的凹槽位置,測量晶圓W的自轉率。顯示結果在表2。[Measurement of Rotation Rate] By observing the position of the groove before and after polishing, the rotation rate of the wafer W is measured. The results are shown in Table 2.
[ESFQR Range的算出] 關於研磨後的晶圓,根據以下的方法,算出ESFQR Range,實行外周部在周方向的平坦度不均量評估。顯示結果在表2。 以離晶圓最外周往直徑方向2mm的區域為除外區域,其更內側的外周基準端往徑方向中心側延伸的扇形長是300mm的2條直線與相當於晶圓外周方向5度(±2.5度)的圓弧所圍繞的72個略矩形之分割部位作為ESFQR Range的部位。於是,使用平坦度測量裝置(KLA-Tencor公司製:Wafer sight 2)測量這些72個部位中的ESFQR。ESFQR Range,在測量的72個ESFQR值中,根據最大值與最小值的差異算出。[Calculation of ESFQR Range] Regarding the polished wafer, the ESFQR Range is calculated according to the following method, and the amount of unevenness in flatness of the outer periphery in the circumferential direction is evaluated. The results are shown in Table 2. Taking the area 2mm in the diameter direction from the outermost circumference of the wafer as the exclusion area, the fan-shaped length of the outer reference end on the inner side extending toward the center side in the radial direction is 300mm and 2 straight lines equivalent to 5 degrees in the outer circumference of the wafer (±2.5 The 72 roughly rectangular divisions surrounded by the arc of (degrees) are regarded as the ESFQR Range. Then, a flatness measuring device (made by KLA-Tencor: Wafer sight 2) was used to measure ESFQR in these 72 locations. ESFQR Range is calculated based on the difference between the maximum value and the minimum value among the 72 measured ESFQR values.
[表2]
如表2所示,藉由控制晶圓的自轉率在25度/min以上60度/min以下研磨晶圓,可以降低晶圓外周部在周方向的平坦度不均量。As shown in Table 2, by controlling the rotation rate of the wafer to be 25 degrees/min or more and 60 degrees/min or less to polish the wafer, the unevenness in the circumferential flatness of the outer periphery of the wafer can be reduced.
1:單面研磨裝置 11:頭部旋轉軸構件 12:研磨頭 13:背墊 14:護圈 15:平台 16:研磨墊 20:頭部驅動手段 30:平台驅動手段 31:平台旋轉軸構件 40:研磨液供給手段 41:噴嘴 50:晶圓加壓力調整手段 60:研磨控制手段 70:研磨條件決定部 W:晶圓 S20:單面完工步驟1: Single-sided grinding device 11: Head rotating shaft component 12: Grinding head 13: back pad 14: Guard ring 15: platform 16: polishing pad 20: Head drive means 30: Platform-driven means 31: Platform rotation axis component 40: Grinding liquid supply means 41: Nozzle 50: Wafer pressure adjustment method 60: Grinding control means 70: Grinding condition determination department W: Wafer S20: Single-sided completion steps
[圖1]係顯示本發明的單面研磨方法中使用的本發明一實施形態的研磨裝置概略構成之模式圖; [圖2]係顯示本發明的單面研磨方法中使用的本發明一實施形態的研磨裝置概略構成之方塊圖; [圖3]係說明關於使用本發明一實施形態的單面研磨方法之本發明一實施形態的矽晶圓製造方法之流程圖; [圖4]係顯示晶圓自轉率與ESFQR Range的關係圖; [圖5]係顯示研磨墊具有的起毛層之壓縮率(Nap壓縮率)與晶圓自轉率的關係圖; [圖6]係顯示研磨墊之研磨晶圓面的表面上對於純水之接觸角與晶圓自轉率的關係圖; [圖7]係顯示護圈內徑與晶圓自轉率的關係圖;以及 [圖8]係顯示晶圓研磨時研磨加壓與晶圓自轉率的關係圖。[Fig. 1] is a schematic diagram showing the schematic configuration of a polishing apparatus according to an embodiment of the present invention used in the single-side polishing method of the present invention; [FIG. 2] A block diagram showing the schematic configuration of a polishing apparatus according to an embodiment of the present invention used in the single-side polishing method of the present invention; [FIG. 3] is a flowchart illustrating a method of manufacturing a silicon wafer according to an embodiment of the present invention using a single-side polishing method according to an embodiment of the present invention; [Figure 4] A diagram showing the relationship between wafer rotation rate and ESFQR Range; [Figure 5] A diagram showing the relationship between the compression rate (Nap compression rate) of the fluffing layer of the polishing pad and the wafer rotation rate; [Figure 6] A diagram showing the relationship between the contact angle of the polishing pad's polishing wafer surface to pure water and the wafer rotation rate; [Figure 7] A diagram showing the relationship between the inner diameter of the retainer ring and the wafer rotation rate; and [Fig. 8] A graph showing the relationship between polishing pressure and wafer rotation rate during wafer polishing.
11:頭部旋轉軸構件 11: Head rotating shaft component
12:研磨頭 12: Grinding head
13:背墊 13: back pad
14:護圈 14: Guard ring
15:平台 15: platform
16:研磨墊 16: polishing pad
20:頭部驅動手段 20: Head drive means
30:平台驅動手段 30: Platform-driven means
31:平台旋轉軸構件 31: Platform rotation axis component
40:研磨液供給手段 40: Grinding liquid supply means
41:噴嘴 41: Nozzle
50:晶圓加壓力調整手段 50: Wafer pressure adjustment method
60:研磨控制手段 60: Grinding control means
70:研磨條件決定部 70: Grinding condition determination department
W:晶圓 W: Wafer
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