TW202121410A - Bitline write driver - Google Patents

Abstract

The present invention proposes a bit line write driver with a novel architecture, which is composed of a first PMOS transistor (P71), a first NMOS transistor (M71), a second NMOS transistor (M72), and a third NMOS transistor (M73), a fourth NMOS transistor (Mcap), a first inverter (INV71), a second inverter (INV72), an input data (Din), a column decoder output signal (Y), a first delay circuit (Delay 1), a second delay circuit (Delay 2), and a first high power supply voltage (VDDH1), wherein the source and the drain of the fourth NMOS transistor (Mcap) are connected together to form a capacitor. When the bit line write driver is in an non-enabling state, the fourth NMOS transistor (Mcap) is in an on state, thereby increasing the capacitance value of the capacitor. In the first stage of write logic 0, the bit line write driver is designed with a voltage level lower than the ground voltage to speed up the writing speed of logic 0, and in the second stage of write logic 0, the bit line write driver is designed with a voltage level equaling to the ground voltage to slow down the writing disturbance of the half-selected cell. In addition, the bit line write driver is designed to be higher than the power supply voltage of the memory cell in the write logic 1 to improve the writing initial instant voltage of the storage node of the memory cell, thus increasing the speed of write logic 1.

Description

Bit line write driver

The present invention relates to a bitline write driver, especially a static random access memory (SRAM) that can be used for single port or dual port Or a dynamic random access memory (Dynamic Random Access Memory, referred to as DRAM) and a bit line write driver with both high-speed write logic 1, high-speed write logic 0, and low write interference.

Single-port or dual-port static random access memory (SRAM) or dynamic random access memory (DRAM) is composed of multiple rows of memory cell and multiple rows of memory cell, each row of memory cell and each A row of memory cell includes a plurality of memory cells, each memory cell has a storage node for storing data, each row of memory cell is controlled by a corresponding character line, and each row of memory cells The cell is connected to the corresponding bit line. The conventional single-port static random access memory (SRAM) unit cell is shown in Figure 1. Among them, PMOS transistors (P1) and (P2) are called load transistors, and NMOS transistors (M1) And (M2) are called driving transistors, NMOS transistors (M3) and (M4) are called access transistors, WL is a word line, and BL and BLB are respectively It is a bit line and a complementary bit line. Because the single-port SRAM cell requires 6 transistors, and when reading logic 0, in order to avoid the initial instant of the read operation ) Another driving transistor is turned on, and the read initial instantaneous voltage (V _AR ) of storage node A must satisfy equation (1):

V _AR =V _DD ×(R _M1 )/(R _M1 +R _M3 )<V _TM2 (1)

In order to prevent half-selected cell disturbance _{during reading, V AR} represents the initial instantaneous voltage of storage node A, and R _M1 and R _M3 represent the NMOS transistor (M1) and the The on-resistance of the NMOS transistor (M3), and V _DD and V _TM2 respectively represent the power supply voltage and the threshold voltage of the NMOS transistor (M2), which results in the current drive capability ratio between the drive transistor and the access transistor (That is, the cell ratio) is usually set between 2.2 and 3.5.

Next, we discuss the single-port and dual-port architecture of static random access memory (SRAM). The 6T static random access memory (SRAM) cell in Figure 1 is a single-port static random access memory (SRAM) cell. An example of a cell, which uses two bit lines BL and BLB for reading and writing, that is, reading and writing are achieved through the same pair of bit lines, so only reading can be performed at the same time Or write operation. Therefore, when you want to design a dual-port static random access memory cell with simultaneous read and write capabilities, you need to add two more access transistors and another pair of bit lines ( Please refer to the circuit shown in Figure 2, where WBL and WBLB are bit line pairs for writing, RBL and RBLB are bit line pairs for reading, WWL is a word line for writing, and RWL is a character for reading. line).

In the static random access memory, in order to efficiently drive the bit line (BL) and the complementary bit line (BLB), a bit line write driver must be provided. So far, many high-performance bit line write driver technologies have been proposed, such as the "Low active power write driver with reduced-power boost circuit" proposed in Patent Document 1 (US10199090B2, awarded to Apple on February 5, 108). Incorporation), its designated representative picture such as Figure 3 (same as US10199090B2, Figure 3) is shown, and the corresponding operation sequence diagram is shown in Figure 4 (same as US10199090B2, Figure 5); and as shown in Patent Document 2 "Capacitive lines and multi-voltage negative bitline write assist driver" (US10332570B1, granted to ADVANCED MICRO DEVICES Incorporation on June 25, 108), its designated representative diagram is shown in Figure 5 (same as US10332570B1 Figure 2), and the corresponding operation sequence diagram is Figure 6 ( Same as US10332570B1 Fig. 3); from Fig. 4 (same as US10199090B2, Fig. 5) and Fig. 6 (same as US10332570B1, Fig. 3), it can be seen that in order to increase the speed of writing logic 0, these patent documents During the writing logic 0 period (refers to the period during which the corresponding word line is in the enabled state), the bit line voltage level of the subsequent section is designed to be lower than the ground voltage, but the speed of writing logic is mainly determined in the previous section of the writing period And these patent documents lack a mechanism to increase the speed of writing logic 1, so there is still room for improvement.

In view of this, the main purpose of the present invention is to provide a bit line write driver with a novel architecture, which is designed to be a voltage level lower than the ground voltage in the first stage of writing logic 0 to speed up writing logic 0 In the second stage of writing logic 0, it is pulled back to the voltage level of the ground voltage to slow down the write disturbance of the half-selected cell.

The secondary objective of the present invention is to propose a bit line write driver with a novel architecture, which is designed to be higher than the power supply voltage of the SRAM cell when writing logic 1 to improve the writing of the storage node of the SRAM cell The initial instantaneous voltage, thereby increasing the speed of writing logic 1.

Another object of the present invention is to provide a bit line write driver with a novel architecture. When the bit line write driver is in a non-enabled state, the bit line is written into the NMOS circuit used to form a capacitor in the driver. The crystal is designed to be in an ON state, thereby increasing the capacitance value of the capacitor, thereby enhancing the capacitive coupling effect.

The present invention proposes a bit line write driver with a novel architecture, which is composed of a first PMOS transistor (P71), a first NMOS transistor (M71), a second NMOS transistor (M72), and a third NMOS transistor (M73), a fourth NMOS transistor (Mcap), a first inverter (INV71), a second inverter (INV72), an input data (Din), a row of decoder output signals ( Y), a first delay circuit (Delay 1), a second delay circuit (Delay 1), and a first high power supply voltage (VDDH1), wherein the source of the fourth NMOS transistor (Mcap) It is connected with the drain to form a capacitor, and when the bit line write driver is in an inactive state, the fourth NMOS transistor (Mcap) is in an ON state, thereby increasing the capacitor The capacitance value. The bit line write driver is designed to be lower than the ground voltage in the first stage of writing logic 0 to accelerate the speed of writing logic 0, and it is pulled back in the second stage of writing logic 0 The voltage level to the ground voltage to reduce the write interference of the half-selected cell; in addition, the bit line write driver is designed to be higher than the power supply voltage of the memory cell when writing logic 1 Increase the initial instantaneous voltage of the storage node of the memory cell to increase the speed of writing logic 1.

P71‧‧‧The first PMOS transistor

M71‧‧‧First NMOS transistor

M72‧‧‧Second NMOS Transistor

M73‧‧‧The third NMOS transistor

Mcap‧‧‧Fourth NMOS Transistor

INV71‧‧‧First inverter

INV72‧‧‧Second inverter

Din‧‧‧Enter data

Delay 1‧‧‧The first delay circuit

Delay 2‧‧‧The second delay circuit

Y‧‧‧Line decoder output signal

VDDH1‧‧‧The first highest power supply voltage

GND‧‧‧Ground voltage

C _BL ‧‧‧parasitic capacitance

BL‧‧‧Bit Line

BLB‧‧‧Complementary bit line

M1…M4‧‧‧NMOS transistor

P1…P2‧‧‧PMOS Transistor

WBL, WBLB‧‧‧Bit line pair for writing

RBL, RBLB‧‧‧Bit line pair for reading

WWL‧‧‧Character line for writing

RWL‧‧‧Character line for reading

VDD‧‧‧Power supply voltage

Figure 1 is a schematic diagram showing the circuit of a conventional 6T single-port static random access memory cell;

Figure 2 is a schematic diagram showing the circuit of a conventional 8T dual-port static random access memory cell;

Figure 3 is a schematic diagram showing the circuit in Figure 3 of US10199090B2;

Figure 4 shows the operation sequence diagram of Figure 5 of US10199090B2;

Figure 5 is a schematic diagram showing the circuit in Figure 2 of US10332570B1;

Figure 6 shows the operation sequence diagram of Figure 3 of US10332570B1;

Figure 7 shows the bit line write driver of the preferred embodiment of the present invention;

Figure 8 is a schematic diagram showing the circuit of the bit line write driver of the present invention in the first stage of writing logic 0;

Figure 9 is a schematic diagram showing the circuit of the bit line write driver of the present invention in the second stage of writing logic 0;

Fig. 10 is a schematic diagram showing the circuit of the bit line write driver of the present invention in writing logic 1.

According to the above objective, the present invention proposes a bit line write driver with a novel architecture. As shown in Figure 7, it is composed of a first PMOS transistor (P71), a first NMOS transistor (M71), and a A second NMOS transistor (M72), a third NMOS transistor (M73), a fourth NMOS transistor (Mcap), a first inverter (INV71), a second inverter (INV72), a Input data (Din), one line decoder output signal (Y), a first delay circuit (Delay 1), a second delay circuit (Delay 2), and a first high power supply voltage (VDDH1), among which, The source and drain of the fourth NMOS transistor (Mcap) are connected together to form a capacitor, and when the bit line write driver is in the inactive state, the fourth NMOS transistor (Mcap) is The ON state is used to increase the capacitance of the capacitor, thereby enhancing the capacitive coupling effect.

The source, gate, and drain of the first PMOS transistor (P71) are respectively connected to the first high power supply voltage (VDDH1), the output of the first inverter (INV71), and the first NMOS transistor. The drain of the crystal (M71), the source, gate and drain of the first NMOS transistor (M71) are respectively connected to the drain of the third NMOS transistor (M73), the first The output of the inverter (INV71) and the drain of the first PMOS transistor (P71), the source, gate and drain of the second NMOS transistor (M72) are connected to the ground voltage and the first The output of the delay circuit (Delay 1) and the drain of the first PMOS transistor (P71), the source, gate and drain of the third NMOS transistor (M73) are connected to the ground voltage and the first The output of the two inverters (INV72) and the source of the first NMOS transistor (M71), the input of the first inverter (INV71) is for receiving the input data (Din), and the output is connected to the The gate of the first PMOS transistor (P71), the gate of the first NMOS transistor (M71) and the input of the first delay circuit (Delay 1), and the input of the second inverter (INV72) Receive the row decoder output signal (Y), and the output is connected to the input of the second delay circuit (Delay 2) and the gate of the third NMOS transistor (M73), the fourth NMOS transistor (Mcap) The source and drain are connected together to form a capacitor (Cap), and when the bit line write driver is in an inactive state, the fourth NMOS transistor (Mcap) is in an ON state, In order to increase the capacitance of the capacitor, one end of the capacitor (Cap) (that is, the gate of the fourth NMOS transistor (Mcap)) is connected to the output of the second delay circuit (Delay 2), and the capacitor The other end of the (Cap) (that is, the source and drain of the fourth NMOS transistor (Mcap) connected together) is connected to the source of the first NMOS transistor (M71) and the third NMOS transistor ( The drain of M73), wherein the drain of the first PMOS transistor (P71), the drain of the first NMOS transistor (M71), and the drain of the second NMOS transistor (M72) are commonly connected to Corresponding bit line (BL), the corresponding bit line (BL) is designed to be lower than the voltage level of the ground voltage in the first stage of writing logic 0 to accelerate the speed of writing logic 0, When writing logic 1, it is designed to be higher than the voltage level of the first high power supply voltage (VDDH1) of the power supply voltage (VDD) of the memory cell to accelerate the speed of writing logic 1.

Whether the bit line write driver is enabled or not is determined by the logic level of the row decoder output signal (Y). When the row decoder output signal (Y) is at a logic low level, the bit line write driver It is in the disabled state, and when the row decoder output signal (Y) is at a logic high level, the bit line write driver is in the enabled state. When the output signal (Y) of the row decoder is at the low logic level of the inactive state, the output of the second inverter (INV72) is at the high logic level. On the one hand, the third NMOS transistor (M73) is turned on, and the other On the one hand, after the delay time provided by the second delay circuit (Delay 2), one end of the capacitor (Cap) (that is, the gate of the fourth NMOS transistor (Mcap)) is charged, because the turned-on third NMOS The transistor (M73) makes the other end of the capacitor (Cap) (that is, the source and drain of the fourth NMOS transistor (Mcap) connected together) the ground voltage, and one end of the capacitor (Cap) ( That is, the gate of the fourth NMOS transistor (Mcap) will maintain the voltage level of the power supply voltage (VDD) due to the charging of the capacitor (Cap).

The bit line write driver adopts a two-stage operation when the bit line write driver is in the enable state of writing logic 0. In the first stage of the bit line write driver enable state, the row decoder output signal (Y ), so that the output of the second inverter (INV72) is at a logic low level. On the one hand, the third NMOS transistor (M73) is turned off (OFF), and on the other hand, it passes through the second delay circuit (Delay 2 After the delay time provided by ), one end of the capacitor (Cap) is quickly discharged to the ground voltage. Because the input data (Din) is at a logic low level at this time, the output of the first delay circuit (Delay 1) is Logic high level, the first NMOS transistor (M71) is turned on, and the first PMOS transistor (P71) is turned off (OFF), so the voltage level of the corresponding bit line (BL) is at the The first stage of writing logic 0 by the bit line write driver satisfies equation (2):

V _BL1 = -VDD×Cap/(Cap+C _BL ) (2) where V _BL1 represents the voltage level of the corresponding bit line (BL) in the first stage of writing logic 0, the absolute value of _{V BL1} Designed to be less than the threshold voltage of the access transistor of the memory cell, for example, it can be designed to be -100mV, -150mV or -200mV, VDD is the voltage level of the power supply voltage (VDD) of the memory cell, and Cap and C _BL respectively represent the capacitance value of the capacitor (Cap) and the parasitic capacitance value of the corresponding bit line (BL).

It is worth noting that in the first stage of enabling the bit line write driver, the second NMOS transistor (M71) is in the OFF state. Figure 8 shows the bit line write driver The schematic diagram of the first stage of enabling; wherein, the delay time provided by the first delay circuit (Delay 1) is designed to be greater than the delay time provided by the second delay circuit (Delay 2), and the second delay circuit (Delay 2) The delay circuit (Delay 2) is used to ensure that the voltage level (V _BL1 ) of the corresponding bit line (BL) in the first stage of writing logic 0 can be effectively provided to the corresponding bit line (BL), Moreover, the second delay circuit (Delay 2) can also be omitted according to requirements.

When the input data (Din) at the logic low level has passed the delay time provided by the first inverter (INV71) and the first delay circuit (Delay 1), the bit line write driver enters the enabling In the second stage, since the second NMOS transistor (M72) is turned on, the voltage level of the corresponding bit line (BL) is at the same level as the bit line write driver writes logic 0. The second stage When the equation (3) is satisfied:

V _BL2 =0 (3) Where, V _BL2 represents the voltage level of the corresponding bit line (BL) in the second phase of writing logic 0; Figure 9 shows the bit line write driver during writing Schematic diagram of the second stage of logic 0. The sum of the time of the first phase and the second phase of writing logic 0 is the time when the corresponding character line is in the enabled state. It is worth noting here that the second NMOS transistor (M72) is used to ensure that the corresponding bit line (BL) can be effectively charged to _{the voltage level (V BL2) in the second stage of writing logic 0} The ground voltage.

The bit line write driver is designed to be higher than the power supply voltage (VDD) of the memory cell when writing logic 1 to increase the initial instantaneous voltage of the storage node of the memory cell, thereby increasing the write Enter the speed of logic 1. When the bit line write driver is writing logic 1, the input data (Din) at a logic high level makes the output of the first inverter (INV71) a logic low level, so the first PMOS is turned on on the one hand Transistor (P71) and on the other hand make the first NMOS transistor (M71) in the OFF state, so the voltage level of the corresponding bit line (BL) is written by the bit line write driver Logic 1 satisfies equation (4):

V _BL =VDDH1 (4) Where, V _BL represents the voltage level of the corresponding bit line (BL) in writing logic 1, VDDH1 is the voltage level of the first high power supply voltage (VDDH1), where, The voltage level of the first high power supply voltage (VDDH1) is designed to be higher than the voltage level of the power supply voltage (VDD) of the memory cell, for example, it can be designed to be higher than the power supply of the memory cell The voltage (VDD) is 100mV, 150mV or 200mV; Figure 10 shows the circuit diagram of the bit line write driver in writing logic 1. The time for writing logic 1 is the time when the corresponding word line is in the enabled state. It is worth noting here that the first PMOS transistor (P71) is used to ensure that the corresponding bit line (BL) can provide a higher voltage level than the memory during the _{writing of the logic 1 voltage level (V BL)} The first high power supply voltage (VDDH1) of the voltage level of the power supply voltage (VDD) of the bulk cell to the corresponding bit line (BL).

【Efficacy of Invention】

The bit line write driver proposed in the present invention has the following effects:

(1) Increasing the speed of writing logic 0: The bit line write driver is designed to be lower than the ground voltage in the first stage of writing logic 0 to accelerate the speed of writing logic 0. In the second stage of writing logic 0, it is pulled back to the voltage level of the ground voltage to alleviate the write interference of the half-selected cell;

(2) Increase the speed of writing logic 1: The bit line writing driver is designed to be higher than the power supply voltage of the memory cell when writing logic 1, so as to improve the writing of the storage node of the memory cell The initial instantaneous voltage, thereby increasing the speed of writing logic 1.

P71‧‧‧The first PMOS transistor

M71‧‧‧First NMOS transistor

M72‧‧‧Second NMOS Transistor

M73‧‧‧The third NMOS transistor

Mcap‧‧‧Fourth NMOS Transistor

INV71‧‧‧First inverter

INV72‧‧‧Second inverter

Din‧‧‧Enter data

Delay 1‧‧‧The first delay circuit

Delay 2‧‧‧The second delay circuit

Y‧‧‧Line decoder output signal

VDDH1‧‧‧The first highest power supply voltage

GND‧‧‧Ground voltage

BL‧‧‧Bit Line

C _BL ‧‧‧parasitic capacitance

Claims (10)

A bit line write driver for random access memory. The random access memory system is composed of a plurality of rows of memory cell and a plurality of rows of memory cell, each row of memory cell and each row of memory The volume unit cell includes a plurality of memory unit cells, each memory unit cell has a storage node for storing data, and each row of the memory unit cell is provided with a bit line write driver, and the bit line write driver system It consists of a first PMOS transistor (P71), a first NMOS transistor (M71), a second NMOS transistor (M72), a third NMOS transistor (M73), and a fourth NMOS transistor (Mcap) , A first inverter (INV71), a second inverter (INV72), an input data (Din), a row of decoder output signals (Y), a first delay circuit (Delay 1), a second It is composed of a delay circuit (Delay 1) and a first high power supply voltage (VDDH1); Wherein, the source, gate and drain of the first PMOS transistor (P71) are respectively connected to the first high power supply voltage (VDDH1), the output of the first inverter (INV71) and the first The drain of NMOS transistor (M71); The source, gate and drain of the first NMOS transistor (M71) are respectively connected to the drain of the third NMOS transistor (M73), the output of the first inverter (INV71) and the first Drain of PMOS transistor (P71); The source, gate and drain of the second NMOS transistor (M72) are respectively connected to the ground voltage, the output of the first delay circuit (Delay 1) and the drain of the first PMOS transistor (P71); The source, gate and drain of the third NMOS transistor (M73) are respectively connected to the ground voltage, the output of the second inverter (INV72) and the source of the first NMOS transistor (M71) ； The input of the first inverter (INV71) is for receiving the input data (Din), and the output is connected Connected to the gate of the first PMOS transistor (P71), the gate of the first NMOS transistor (M71) and the input of the first delay circuit (Delay 1); The input of the second inverter (INV72) is for receiving the row decoder output signal (Y), and the output is connected to the input of the second delay circuit (Delay 2) and the third NMOS transistor (M73) Gate The source and drain of the fourth NMOS transistor (Mcap) are connected together to form a capacitor (Cap), and when the bit line write driver is in a non-enabled state, the fourth NMOS transistor ( The Mcap is in an ON state, which can effectively increase the capacitance of the capacitor by the capacitive coupling effect. One end of the capacitor (Cap) (that is, the gate of the fourth NMOS transistor (Mcap)) is Connected to the output of the second delay circuit (Delay 2), and the other end of the capacitor (Cap) (that is, the source and drain of the fourth NMOS transistor (Mcap) connected together) is connected to the first The source of the NMOS transistor (M71) and the drain of the third NMOS transistor (M73); Wherein, the drain of the first PMOS transistor (P71), the drain of the first NMOS transistor (M71), and the drain of the second NMOS transistor (M72) are connected to the corresponding bit line ( BL), the corresponding bit line (BL) in the first stage of writing logic 0 is designed to be lower than the voltage level of the ground voltage to accelerate the speed of writing logic 0, while writing logic 1 When it is designed to be higher than the voltage level of the first high power supply voltage (VDDH1) of the power supply voltage (VDD) of the random access memory, to accelerate the speed of writing logic 1; Wherein, the corresponding bit line (BL) is pulled back to the ground voltage in the second stage of writing logic 0 to alleviate the write interference of the half-selected memory cell; Wherein, the sum of the time of the first stage and the second stage of writing logic 0 is equal to the time when the corresponding character line is in the enabled state, and the time of writing logic 1 is also equal to the corresponding character line. can State time Wherein, the second NMOS transistor (M72) is used to ensure that the voltage level of the corresponding bit line (BL) in the second stage of writing logic 0 can be effectively charged to the ground voltage; Wherein, the first PMOS transistor (P71) is used to ensure that the corresponding bit line (BL) can provide a higher voltage than the power supply voltage of the random access memory during the writing of the logic 1 voltage level The first high power supply voltage (VDDH1) at the voltage level of (VDD) to the corresponding bit line (BL). The bit line write driver described in item 1 of the scope of patent application, wherein the bit line write driver satisfies the following equation in the first stage of writing logic 0: V _BL1 =-VDD×Cap/(Cap+C _BL ) Wherein, V _BL1 represents the voltage level of the corresponding bit line (BL) in the first stage of writing logic 0, and the _{absolute value of V BL1} is designed to be smaller than the threshold voltage of the access transistor of the memory cell. VDD is the voltage level of the power supply voltage (VDD) of the random access memory, and Cap and C _BL respectively represent the capacitance value of the capacitor (Cap) and the parasitic capacitance value of the corresponding bit line (BL) ; And Wherein, the second delay circuit (Delay 2) is used to ensure that the voltage level (V _BL1 ) of the corresponding bit line (BL) in the first stage of writing logic 0 can be effectively provided to the corresponding bit Line (BL). In the bit line write driver described in item 2 of the scope of patent application, the voltage level of the corresponding bit line (BL) in the first stage of writing logic 0 is designed to be -100 mV. The bit line write driver described in item 2 of the scope of patent application, wherein the voltage level of the corresponding bit line (BL) in the first stage of writing logic 0 is designed to be -150 mV. The bit line write driver described in item 2 of the scope of patent application, wherein the corresponding bit line (BL) The voltage level of the first stage of writing logic 0 is designed to be -200mV. The bit line write driver described in claim 1, wherein the delay time provided by the first delay circuit (Delay 1) is designed to be greater than the delay provided by the second delay circuit (Delay 2) time. For the bit line write driver described in item 1 of the scope of patent application, the second delay circuit (Delay 2) can be omitted as required. The bit line write driver described in the first item of the scope of patent application, wherein the first high power supply voltage (VDDH1) is designed to be 100mV higher than the power supply voltage (VDD) of the random access memory Voltage level. The bit line write driver described in the first item of the scope of patent application, wherein the first high power supply voltage (VDDH1) is designed to be higher than the power supply voltage (VDD) of the random access memory by 150mV Voltage level. The bit line write driver described in the first item of the scope of patent application, wherein the first high power supply voltage (VDDH1) is designed to be 200mV higher than the power supply voltage (VDD) of the random access memory Voltage level.

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