TW202118363A - Lithographically defined electrical interconnects from conductive pastes - Google Patents

Abstract

The present invention relates to electrical interconnect structures formed from a lithographically defined polymer coating in conjunction with a conductive paste, and methods for forming same.

Description

Electronic interconnections defined by conductive adhesive lithography

The present invention relates to the electronic interconnection of devices in an electronic module. More specifically, the present invention relates to the electronic interconnection between discrete electronic devices, which are single or as part of a module, encapsulated or unencapsulated before being attached to a printed circuit board. Even more specifically, the present invention relates to a mold for fine-feature electronic interconnection and lithographic definition formed from conductive glue.

The mobile electronics industry is developing rapidly. The market drivers of new product generations are constantly moving towards faster performance and higher functionality of cheaper, lighter products with longer battery life. All aspects of the electronics industry are changing to meet these needs. This includes discrete electronic devices and packaging solutions as well as the architecture for interconnecting these discrete electronic devices.

Traditionally, active semiconductor devices have been individually packaged and then assembled on the surface of the circuit board along with all the devices necessary for the product to function. Most of the size reduction in the earlier generations of mobile electronic devices is attributable to the increase in the performance of active semiconductor die and functionality per unit area. The reduction of individual die packages as small as approximately the die size is a significant contribution to the reduction of the second wave of miniaturization products. The current wave of mobile electronic product evolution focuses on the integration of multiple devices-both active and passive-into a single package, and a combination of packages that enhance speed and functionality before being assembled on the circuit board.

This new wave of packaging integration has spurred the exploration of a variety of new packaging strategies and architectures. A major aspect of the packaging integration trend is the shift from two-dimensional architecture to three-dimensional architecture. There are numerous electronic performance, mechanical performance, and reliability considerations that need to be considered to support the three-dimensional integrated package architecture. With the continuous increase of signal interconnection points per unit area, this is particularly urgent in the packaging of high-performance semiconductor devices. For these devices, the three-dimensional architecture has evolved simultaneously with the increased density of electronic interconnects in the two-dimensional array.

The electronic interconnection in the vertical axis between packages is a particularly effective development area. The industry term used to stack two or more semiconductor packages for electronic interconnection is "package on package" or "POP". The electronic interconnection between packages in the POP architecture is called z-axis interconnection.

Electronic performance, mechanical performance, and reliability are all significant challenges in the production of z-axis interconnects in the POP architecture. Z-axis interconnections usually must be small in cross-sectional area and are often placed closely together, but the z-axis distance to be spanned can vary significantly. It is generally preferable to make the z-axis height of the interconnection higher than the width of the electronic conductor. In addition, although the z-axis conductor is usually small in cross-sectional area, it must also provide a robust mechanical and electrical connection from one packaged electronic terminal to another. The z-axis interconnect must also be able to withstand the mechanical strain imposed by the thermal expansion difference of the bonded package as well as the mechanical strain imposed by the surrounding material mechanically coupling the interconnect and the package together. The z-axis interconnect must also be able to withstand multiple solder reflow cycles to ensure assembly to the circuit board, and be able to accommodate any possible reprocessing. Finally, in the design of any z-axis interconnect strategy, cost is also a factor that appears in the manufacturing, yield, and reliability of POPs.

Several strategies have been proposed to form the z-axis interconnection in the POP architecture. The solder balls on the periphery, the overmolded solder balls, the electroplated bumps (also known as copper pillars) wrapped by the molding compound, and the solder balls filled into the holes prepared in the molding compound have all been moved across from the bottom The z-axis distance from the interconnection pads of the volt package substrate to their interconnection pads on the overlying package. Various interposer structures have also been proposed and studied. All these solutions are restrictive and the areas of development are very active.

The existing proposed solutions suffer from a variety of deficiencies. Enlarging the footprint of the lower package substrate to accommodate the peripheral solder balls outside the perimeter of the molding compound deposited on the active device is undesirable, because it negatively affects the miniaturization possibilities of the overall product and causes problems. Uniform warpage effect. The solder balls within the perimeter of the package molding compound achieve a certain package reduction and reduce the effect of warpage, but the height and proximity of the solder ball interconnects are limited by the shape of the balls. The growth of electroplated bumps on the interconnect pads on the lower substrate before overmolding allows the cross-section to be small, possibly quite tall and can be placed in close proximity to each other interconnect features, but the bumps are It is time consuming and expensive to electroplating, and the upper interconnection surface has the possibility of being too small to affect the mechanically robust interconnection. Holes are formed in the mold compound to accept multiple solder balls to produce most of the desired geometry, but the connection to the upper package is supported by the neck of the solder ball, which is not well supported by the mold compound and Solder balls are susceptible to remelting during subsequent solder assembly cycles. The interposer is usually the outer mold perimeter solution, and is sometimes made of materials that the industry is not good at handling (for example, glass) and can be expensive.

In its simplest terms, the structure of the present invention is a polymer mold defined by lithography on a substrate, in which the features defined in the mold are filled with a conductive composition that forms an electronic connection with the substrate and is heat-treated It is in a thermoset form so that it does not melt or change form during subsequent heating cycles.

The lithographically defined polymer is applied to the substrate as a coating, exposed to radiation to create the pattern of the mold, and chemically developed to define the mold. It adheres to the substrate, does not chemically react with the conductive composition, and can be subjected to heat treatment to affect the thermosetting state in the conductive composition without degradation, advancement or deformation; and can be subjected to heat treatment to affect the conductive composition in the conductive composition. The thermoset state is then chemically removed.

The conductive composition is provided in the form of glue, and can be installed in the recessed portion of the mold defined by the lithography so that the mold is substantially filled with glue. During the heat treatment, the conductive glue forms electrical interconnections to the conductive features on the substrate and becomes electronic interconnection elements through the bulk of the glue, which will not melt or change form during subsequent heating cycles. Once heat-treated, the glue acquires a fixed shape and can be electroplated or welded to affect the electronic interconnection to the overlying electronic interconnects (such as pads on the overlying POP substrate).

Once the conductive z-axis interconnect features have been lithographically defined into the polymer mold, filled with conductive glue, and heat-treated to affect the electrical interconnections to the underlying substrate and through the rest of the thermosetting composition, the lithographic definition The polymer can be kept as part of the final product, or can be chemically removed to make the thermosetting conductive adhesive deposit as a separate feature.

Although the present invention is particularly suitable for the application of z-axis interconnects in the POP architecture, it considers various implementations in which fine geometric shapes and interconnect patterns are established in a polymer mold defined by lithography. Some of these alternative embodiments include, but are not limited to, redistribution circuits in the xy plane, contact pads at the terminals of electroplated bumps, contact fingers for semiconductor wafer test cards, individual semiconductor dies Or packaged area array interconnects, interposers, height extensions for solder interconnects, interconnects directly between semiconductor dies, heat transfer arrays, and the like.

The present invention is an electronic interconnection structure, which includes: • A substrate, which carries conductive elements on at least one surface; • The polymer coating, which is located on the substrate, where the polymer coating has been lithographically defined in the pattern of the following characteristics: ○ Transverse the polymer coating in an axis perpendicular to the surface, ○ Expose the conductive elements on the surface, ○ The pattern of the feature is open at the surface of the coating that is not in contact with the substrate; and • Conductive glue, which is installed in these features so that: ○ The conductive glue basically fills these features, ○ The conductive adhesive is in physical and electronic contact with the conductive components, and ○ The conductive adhesive has been heat-treated to affect thermosetting electronic interconnects.

The electronic interconnect structure of the present invention may or may not be subsequently processed to selectively remove the polymer coating.

The structure of the present invention can be advantageously deployed in various electronic interconnection applications, including but not limited to the electronic interconnection between discrete electronic devices, which are single or as part of a module and are attached to the printed circuit board. The circuit board was previously packaged or unpackaged. In particular, the structure of the present invention can be advantageously deployed in various electronic interconnection applications, including but not limited to the z-axis interconnection in the POP architecture, the redistribution circuit in the xy plane, and the contact pads at the terminals of the electroplated bumps. , Contact fingers for semiconductor chip test cards, area array interconnects for individual semiconductor dies or packages, interposers, height extensions for solder interconnections, interconnections directly between semiconductor dies, heat transfer Arrays and the like. The current preferred implementation is the z-axis interconnection in the POP architecture.

Depending on the specific implementation, the substrate may be any of various structures commonly found in electronic modules. Structures considered as substrates include but are not limited to semiconductor dies, passive electronic components, lead frames, packaged semiconductor components, printed circuit boards, electronic substrates, stacked dies, flexible circuits, solar panels, electronic modules, and electronics Subsystem. The current preferred is the substrate used in the packaging of semiconductor dies. Typically, these substrates carry semiconductor dies that are mechanically attached to one surface and are electronically interconnected to circuits located on two opposing major surfaces and across the thickness of the substrate. Typical substrate materials are polymers, polymer laminates, ceramics, polymer coated metal sheets, glass, and the like.

The conductive elements on the surface of the substrate in the structure of the present invention can also be made of various materials depending on the specific implementation. The conductive elements under consideration for use in the practice of the present invention include copper pads, copper pads carrying metal surface finishes (eg, gold-nickel, silver, gold-palladium-nickel), copper pads with organic surface treatment, aluminum Pads, conductive paste deposits, gold bumps, solder deposits, solder balls, copper pillars, copper bumps, sintered metals, thick film conductors and the like. Most typically, the conductive element of the structure of the present invention may or may not carry a metal-coated copper pad.

The polymer coating of the structure of the present invention can be patterned by photolithography to form features of the desired geometric shape, expose the underlying conductive elements, and substantially maintain the defined feature geometry throughout the installation and heat treatment of the conductive adhesive Either.

The polymer coating of the structure of the present invention can be applied to the substrate by any method generally known to those skilled in the art. The applicable coating techniques include, but are not limited to, spin coating, extrusion, slit coating, curtain coating, doctor blading, spray coating, screen printing and the like.

The polymer coating considered in the structure of the present invention contains a photoresist material. Both positive ( for example , bonds in the polymer backbone are broken during irradiation) and negative ( for example , crosslinks between polymer molecules are formed during irradiation) resists are both considered for use in the present invention . Consider chemically enhanced resists to facilitate the formation of fine feature geometries through thick coatings (eg , 50 microns to 500 microns). In embodiments where it is desired to subsequently selectively remove the polymer coating from the electronic interconnect structure of the present invention, the ability to chemically peel the polymer coating from the substrate after the heat treatment necessary to affect the formation of the thermoset electronic interconnect It is also an important selection factor. The thermal stability of the polymer coating through the heat treatment of the conductive adhesive is a decisive factor. For example, polymer coating materials that melt, carbonize, or have significant dimensional changes during the heat exposure necessary for processing conductive adhesives will not be suitable for the present invention. In addition, the ability to accurately image through thick coatings to form well-defined, thermally stable, high aspect ratio molds is an advantageous feature in the application of the present invention. In certain embodiments, it may be desirable to have polymer coating chemistries suitable for retention in the final construction. Therefore, polymer coatings that will easily degrade, cause warpage, hinder adhesion to other package components, and the like may not be suitable for these embodiments. Finally, the use of a polymer coating applied as a liquid may be advantageous for certain embodiments of the present invention to smooth out uneven topography or provide flexibility in coating thickness. Particularly suitable polymer coatings are chemically enhanced negative thick film resists, such as the AZ 200nXT series provided by EMD Performance Materials Corp.

The pattern of features defined in the polymer coating can be formed by any lithography process known to those skilled in the art. The nature of the mask used to influence the pattern will depend on the nature of the selected polymer coating. Likewise, the specific coating application, baking, exposure, and development procedures will be specific to the specific polymer coating selected for use.

Any conductive adhesive can be used in the structure of the present invention, as long as it is of suitable consistency for filling features, forms electrical connections to conductive elements, and can be heat-treated to form thermosets and will not experience significant shape changes in subsequent thermal deviations Changed electronic interconnects. In this description of the invention, the term thermoset is meant to direct that a certain part of the bakelite must undergo an irreversible reaction during the heat treatment, so that the resulting electronic interconnect feature maintains its form during subsequent thermal exposure, even if the surrounding polymer coating that defines the feature Has been removed. Metal-filled thermosetting polymer glues, glues with sintered nano-particles, organometallic glues in which organic matter decomposes to produce molten metal, and transient liquid phase sintered glues are all considered. At present, transient liquid phase sintered adhesives (such as Ormet series products provided by Ormet Circuits, Inc.) are better. Suitable conductive adhesives are described in (for example) Patent Publication Nos. WO2014/082100, WO2016/174584, WO2018/231612 and WO2019/113208, the full text of each of these publications Incorporated into this article by reference.

Transient liquid phase sintering (TLPS) conductive adhesives provide thermoset metal systems instead of thermoset polymer systems. In the TLPS conductive adhesive, relatively low melting point alloys and relatively high melting point metals are mixed in the form of particles. When the temperature rises to the melting point of the alloy, the alloy particles become molten. The reactive elements in the relatively low melting point alloy then react with the receptive high melting point metal to form a new alloy composition and/or intermetallic. The TLPS composition therefore undergoes a thermosetting reaction both in the bulk of the glue and at any interface with the weldable material to form a mixture of intermetallic and alloy products, all of which have a melting temperature substantially higher than that of the initial welding alloy powder. The melting temperature. For this reason, the TLPS composition provides good conductivity, with almost no chance of conductivity degradation due to oxidation, corrosion, or thermal expansion and contraction. The TLPS reaction is irreversible and the resulting electroplatable and solderable interconnect features will not undergo significant melting or change in shape during any subsequent high temperature exposure.

The conductive adhesive can be installed in the structure of the present invention by any means known to those skilled in the art. The use of doctor blades, applicators, pressure-assisted applicators, pressure heads, dispensing tools, and vacuum chambers are all explicitly considered as potentially useful tools for installing conductive glue into features across the polymer coating. Conductive glue can be installed to substantially fill the pattern of features. The term "substantially filled" is intended to refer to features that are more than 50% filled, more than 75% filled, more than 85% filled, more than 90% filled, or more than 95% filled. In particular, the pattern of features should be filled so that the conductive glue is in physical, electronic and/or thermal contact with the conductive elements.

The heat treatment of the conductive adhesive can be achieved by any means known to those skilled in the art. The specific processing type will depend on the specific material selected and the nature of the electronic interconnect structure to be formed.

If desired, the polymer coating can be selectively removed. The removal of the polymer coating can be achieved by any means known to those skilled in the art. The specific processing type will depend on the specific material selected and the nature of the electronic interconnect structure to be formed. Generally, the removal of the polymer coating will be performed after the heat treatment of the conductive adhesive.

Those who are familiar with the technology will understand that various configurations and arrangements within the practical scope of the present invention can be used to practice the invention of this application.

The invention can be better understood by the following non-limiting examples. Instance

Reference will now be made to more specific embodiments of the present invention and experimental results that provide support for such embodiments. However, applicants note that the following disclosure is for illustrative purposes only and is not intended to limit the scope of the claimed subject matter in any way.

The feasibility demonstration of the structure of the present invention is prepared in the following manner.

AZ 200nXT thick film resist was used to coat silicon wafers carrying 3500 angstroms of copper. The coating was applied in two spin coating applications to achieve a total coating thickness of 180 microns. The coating was subjected to a soft baking for 960 seconds at 140 degrees Celsius and then irradiated at a dose of ^{1800 mJ/cm 2 through the mask.} The exposure unit used is a Suss MA200 CC mask aligner with a proximity gap of 40 microns.

Use the chemical development solution AZ 300 MIF to develop the pattern in the coating on the silicon wafer to selectively remove the polymer coating from the pattern, so that the formation traverses the thickness of the polymer coating and ends at the bare surface of the copper layer The desired geometric shape of the opening.

Using a Mass VHF 300 V hole filling machine, use Ormet 710 conductive glue to fill the openings across the polymer coating. The filling operation is carried out in a vacuum chamber with the aid of a pressure-assisted applicator head.

Once filled, the Ormet 710 in the opening in the polymer coating was dried at 100 degrees Celsius to evaporate the solvent and then the glue was sintered in a lamination press at 200 psi and 200 degrees Celsius for 10 minutes. During the sintering process, the metals in the Ormet 710 conductive adhesive react to form a thermosetting metal matrix.

After the sintering reaction is completed, the silicon wafer is cross-sectioned and photographed under high magnification.

As can be seen in Figure 3, Ormet 710 completely fills the opening across the thickness of the polymer coating and is in contact with the copper surface. Ormet 710 has changed from the brown of the raw rubber to silver in color, which indicates that the sintering operation is successful in the formation and conductive features, and the chemical properties of the polymer coating do not interfere with the sintering process. The desired characteristic shape has been maintained through filling and sintering operations. When the polymer coating is stripped from the wafer, a portion of the sintered conductive adhesive remains attached to the surface of the copper and appears to have been metallurgically bonded to the surface.

This experiment proves that the structure of the present invention can be successfully produced.

1: Lower package 2: Solder ball 3: Package structure on package A: Lower package B: Top package

Figure 1 shows a common prior art implementation of POP architecture 3. Note that the substrate of the lower package 1 extends beyond the perimeter of the molding compound enclosing the semiconductor die, so that the perimeter array of solder balls 2 can be added for the interaction between the upper package and the lower package (B and A, respectively) even. In one embodiment, the structure of the present invention replaces this peripheral ring of the solder ball. In another embodiment, the structure of the present invention allows the peripheral array to move within the area within the perimeter of the molding compound, thus enabling the formation of a POP structure with a smaller footprint. The structure of the present invention can be advantageously used in combination with a variety of specific semiconductor package types and a variety of POP architectures.

Figure 2 is a cross-section of a semiconductor wafer carrying a polymer coating that has been lithographically defined to form a mold in a pattern of rectangular-shaped hole arrays. Note the well-defined shape of the holes, and they traverse the entire thickness of the polymer coating to expose the underlying wafer. This feature is the key to the structure of the present invention to facilitate the mounting of conductive adhesive to form a uniformly shaped interconnect that can be physically contacted and electronically interconnected to the exposed bottom of the hole. Also pay attention to the particularity of the shape of the hole, and in particular, the z-axis height of the rectangle is significantly longer than the width and the slightly trapezoidal configuration. In the practice of the present invention, both the lithography-sensitive polymer used in the formation of the mold and the lithography process can be manipulated to form mold features with a variety of geometric specificities as the best suitable implementation. For example, the z-axis height dimension can be made quite large to accommodate a relatively thick lower package in the POP module, while maintaining high-density vertical interconnections in a small area footprint. In another example, the inverted trapezoidal shape can be enlarged to form a larger terminal pad at the top of the z-axis interconnect to facilitate robust mechanical and electronic interconnection to the overlying package. One of the key factors of the structure of the present invention is that the selected lithography-sensitive polymer can maintain the shape of the features defined by the lithography during the entire process of mounting and heat treatment of the conductive adhesive used to form the conductive interconnects.

FIG. 3 is a cross-section of the structure of the invention, in which the polymer mold defined by the lithography has been filled with conductive glue and heat-treated to affect the characteristics of the thermosetting electronic interconnection. Note that the mold is well filled, there is no obvious degradation of the regularity of the shape of the features defined by the mold, and the conductive adhesive interconnects are highly regular in shape and traverse the z-axis thickness of the mold to directly contact the underlying substrate. contact. Also note that there is a significant difference along the boundary between the polymer mold and the conductive adhesive interconnect, which implies that there is no chemical interference between the two materials that may deleteriously affect the electrical characteristics of the conductive adhesive interconnect. Note further the fine dimensions of electronic interconnects having a z-axis height measured to be about 180 microns and a width of the z-axis interconnection of about 80 microns.

Figure 4 is an optical image of the structure of the present invention, in which the polymer mold defined by the lithography has been removed by a selective process to make the conductive adhesive interconnection feature as a separate element.

Claims (4)

An electronic interconnection structure, which includes: a. A substrate, which carries a conductive element on at least one surface thereof; b. The polymer coating, which is located on the substrate, wherein the polymer coating has been lithographically defined in the pattern of the following features: i) traverse the polymer coating in an axis perpendicular to the surface, ii) Expose the conductive elements on the surface, and iii) wherein the pattern of features is open at the surface of the polymer coating that is not in contact with the substrate; and c. Conductive glue, which is installed in the pattern of the feature such that: i) The conductive glue basically fills these features, ii) The conductive adhesive is in physical and electronic contact with the conductive elements, and iii) The conductive adhesive has been heat-treated to affect thermoset electronic interconnects. A procedure for forming an electronic interconnection structure, which includes the following steps: a. Coating a substrate with a polymer to form a polymer coating on the substrate, wherein the substrate carries a conductive element on at least one surface thereof; b. Lithography processes the polymer coating to define the pattern of the following characteristics: i) traverse the polymer coating in an axis perpendicular to the surface, ii) Expose the conductive elements on the surface, and iii) wherein the pattern of features is open at the surface of the polymer coating that is not in contact with the substrate; and c. Install the conductive adhesive in the pattern of the feature so that: i) The conductive glue basically fills these features, and ii) The conductive adhesive is in physical and electronic contact with the conductive elements. Such as the procedure of claim 2, which further includes the step of heat-treating the conductive adhesive to affect the thermosetting electronic interconnection. The procedure of claim 3, which further includes a step of selectively removing the polymer coating after the step of heat-treating the conductive adhesive.

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