TW202114145A - Substrate for semiconductor device, method of manufacturing substrate for semiconductor device, and method of manufacturing wireless communication device - Google Patents

Substrate for semiconductor device, method of manufacturing substrate for semiconductor device, and method of manufacturing wireless communication device Download PDF

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TW202114145A
TW202114145A TW109131740A TW109131740A TW202114145A TW 202114145 A TW202114145 A TW 202114145A TW 109131740 A TW109131740 A TW 109131740A TW 109131740 A TW109131740 A TW 109131740A TW 202114145 A TW202114145 A TW 202114145A
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substrate
semiconductor device
semiconductor
base material
semiconductor devices
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河井翔太
田中龍一
村瀬清一郎
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日商東麗股份有限公司
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    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H—ELECTRICITY
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits

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Abstract

A substrate for a semiconductor device according to an aspect of the present invention has a resin base material, a plurality of semiconductor devices provided on the resin base material, and a reinforcement wire provided to surround the plurality of semiconductor devices. The reinforcement wire is made of the same material as a material constituting at least one of electrode layers included in the plurality of semiconductor devices. A plurality of regions in which one or more of the plurality of semiconductor devices are surrounded by the reinforcement wire are present on the resin base material. A plurality of semiconductor devices such as a wireless communication device can be obtained from said substrate for a semiconductor device.

Description

半導體裝置用基板、半導體裝置用基板的製造方法及無線通訊裝置的製造方法Substrate for semiconductor device, method for manufacturing substrate for semiconductor device, and method for manufacturing wireless communication device

本發明是有關於一種半導體裝置用基板、半導體裝置用基板的製造方法及無線通訊裝置的製造方法。The present invention relates to a substrate for a semiconductor device, a method for manufacturing a substrate for a semiconductor device, and a method for manufacturing a wireless communication device.

近年來，使用無線射頻辨識（Radio Frequency IDentification，RFID）技術的無線通訊系統受到關注。RFID標籤（tag）包括具有由場效型電晶體（以下，稱為FET（Field Effect Transistor））構成的電路的積體電路（integrated circuit，IC）晶片、以及用以進行與讀寫器（reader/writer）的無線通訊的天線。設置於RFID標籤內的天線接收由讀寫器發送的載波，而使IC晶片內的驅動電路運作。In recent years, wireless communication systems using radio frequency identification (Radio Frequency IDentification, RFID) technology have attracted attention. The RFID tag includes an integrated circuit (IC) chip with a circuit composed of a field-effect transistor (hereinafter referred to as FET (Field Effect Transistor)), and a chip used to perform and read/write (reader). /writer) wireless communication antenna. The antenna installed in the RFID tag receives the carrier wave sent by the reader, so that the driving circuit in the IC chip operates.

RFID標籤被期待用於物流管理、商品管理、防止扒竊等多種用途中，開始於交通卡等IC卡、商品標籤等一部分用途中導入。今後，為了於所有的商品中使用RFID標籤，需要減少RFID標籤的製造成本。因此，於RFID技術領域中，提出了使用塗佈、印刷技術於可撓性基板上製造RFID標籤的電路或天線的方法（例如，參照專利文獻1）。RFID tags are expected to be used in a variety of applications such as logistics management, product management, and pickpocket prevention, and have begun to be introduced in some applications such as IC cards such as transportation cards and product tags. In the future, in order to use RFID tags in all products, it is necessary to reduce the manufacturing cost of RFID tags. Therefore, in the field of RFID technology, a method of manufacturing a circuit or antenna of an RFID tag on a flexible substrate using coating and printing techniques has been proposed (for example, refer to Patent Document 1).

於構成RFID標籤內的電路的FET中，在產生特性偏差（例如，驅動電流值的偏差）時，難以實現按照設計規格的穩定的電路動作。尤其是於使用廉價的塑膠膜作為基板的情況下，溫度或濕度所引起的基板的伸縮大，因此由於所述伸縮，會產生構成FET的構件的圖案偏移。因此，無法穩定地製造FET，FET的特性偏差變大。In the FET constituting the circuit in the RFID tag, it is difficult to realize stable circuit operation in accordance with the design specification when a characteristic deviation (for example, a deviation in a drive current value) occurs. In particular, when an inexpensive plastic film is used as the substrate, the expansion and contraction of the substrate due to temperature or humidity is large, and therefore, due to the expansion and contraction, the pattern of the members constituting the FET may be shifted. Therefore, the FET cannot be manufactured stably, and the characteristic variation of the FET becomes large.

作為用於抑制所述圖案偏移的技術，研究了如下方法：於基板設置對準標記（alignment mark）並檢測所述對準標記，基於檢測出的對準標記的位置偏移量的大小進行基板的溫度控制或基板的濕度控制，藉此控制基板的伸縮（例如，參照專利文獻2）。另外，正在研究如下方法：將形成於基板上的閘極電極用作用於源極電極及汲極電極的圖案化的光罩，自基板的背面進行曝光，藉此抑制各電極間的位置偏移（例如，參照專利文獻3）。 [現有技術文獻] [專利文獻]As a technique for suppressing the pattern shift, the following method is studied: an alignment mark is provided on a substrate, the alignment mark is detected, and the measurement is performed based on the magnitude of the position shift amount of the detected alignment mark. The temperature control of the substrate or the humidity control of the substrate controls the expansion and contraction of the substrate (for example, refer to Patent Document 2). In addition, the following method is being studied: the gate electrode formed on the substrate is used as a mask for patterning the source electrode and the drain electrode, and exposure is carried out from the back of the substrate, thereby suppressing the positional deviation between the electrodes (For example, refer to Patent Document 3). [Prior Art Literature] [Patent Literature]

專利文獻1：國際公開第2017/030070號 專利文獻2：國際公開第2015/133391號 專利文獻3：國際公開第2018/051860號Patent Document 1: International Publication No. 2017/030070 Patent Document 2: International Publication No. 2015/133391 Patent Document 3: International Publication No. 2018/051860

[發明所欲解決之課題] 然而，於專利文獻2中記載的方法中，存在如下課題：即使可修正各FET的位置偏移，亦無法抑制基板內的FET的特性偏差，另外，於基板的應變不均勻（即由於變形方向或變形量無規則性而難以預測的應變）的情況下，亦變得難以控制FET的位置偏移。另外，於專利文獻3中記載的方法中，即使可抑制各FET中的電極形成位置的偏差，亦無法抑制由基板的伸縮引起的FET相互間的偏差。[The problem to be solved by the invention] However, in the method described in Patent Document 2, there is a problem that even if the positional deviation of each FET can be corrected, the characteristic deviation of the FET in the substrate cannot be suppressed, and the strain on the substrate is not uniform (that is, due to the deformation direction). Or in the case of irregular deformation and unpredictable strain), it also becomes difficult to control the positional deviation of the FET. In addition, in the method described in Patent Document 3, even if the deviation of the electrode formation position in each FET can be suppressed, the deviation between the FETs caused by the expansion and contraction of the substrate cannot be suppressed.

另外，於專利文獻2及專利文獻3的任一種方法中，均考慮到了藉由修正FET的位置偏移等製造步驟來抑制特性偏差，但並未考慮到控制由於FET形成後的溫度或濕度的變化所引起的基板的伸縮偏差、由於在連續的基板上連續形成FET並捲繞成卷狀的基板的卷未對準的影響所引起的FET相互間的特性偏差。In addition, in either of the methods of Patent Document 2 and Patent Document 3, it is considered to suppress the characteristic deviation by correcting the positional deviation of the FET and other manufacturing steps, but it does not consider the control of the temperature or humidity after the formation of the FET. Variations in the expansion and contraction of the substrates caused by changes, and variations in the characteristics of the FETs due to the effects of misalignment of the rolls of the substrates that are continuously formed on a continuous substrate and wound into a roll.

本發明是著眼於所述課題而成者，且目的在於提供一種即使於在基板上形成FET等多個半導體裝置後亦可抑制半導體裝置的特性偏差的半導體裝置用基板、半導體裝置用基板的製造方法及無線通訊裝置的製造方法。 [解決課題之手段]The present invention has been made focusing on the above-mentioned problems, and its object is to provide a substrate for semiconductor devices and the manufacture of substrates for semiconductor devices that can suppress variations in characteristics of the semiconductor devices even after forming multiple semiconductor devices such as FETs on the substrate Method and manufacturing method of wireless communication device. [Means to solve the problem]

為了解決所述課題並達成目的，本發明的半導體裝置用基板的特徵在於，具有樹脂基材、以及所述樹脂基材上所包括的多個半導體裝置，且於所述樹脂基材上具有以包圍所述多個半導體裝置的方式設置的加強線，所述加強線由與構成所述多個半導體裝置中所含的電極層中的至少一者的材料相同的材料構成，於所述樹脂基材上存在多個所述多個半導體裝置中的一個以上被所述加強線包圍的區域。In order to solve the problem and achieve the object, the substrate for a semiconductor device of the present invention is characterized by having a resin base material and a plurality of semiconductor devices included on the resin base material, and having the resin base material A reinforcing wire provided to surround the plurality of semiconductor devices, the reinforcing wire being made of the same material as the material constituting at least one of the electrode layers included in the plurality of semiconductor devices, and being formed on the resin base There is a region surrounded by the reinforcing line in one or more of the plurality of semiconductor devices on the material.

另外，本發明的半導體裝置用基板的特徵在於，於所述發明中，所述加強線以分別包圍所述多個半導體裝置的方式設置。In addition, the semiconductor device substrate of the present invention is characterized in that, in the invention, the reinforcing wires are provided so as to surround the plurality of semiconductor devices, respectively.

另外，本發明的半導體裝置用基板的特徵在於，於所述發明中，所述加強線的厚度與所述多個半導體裝置各自的厚度相同，或者比所述多個半導體裝置各自的厚度薄。In addition, the semiconductor device substrate of the present invention is characterized in that, in the invention, the thickness of the reinforcing wire is the same as the thickness of each of the plurality of semiconductor devices, or is thinner than the thickness of each of the plurality of semiconductor devices.

另外，本發明的半導體裝置用基板的特徵在於，於所述發明中，所述樹脂基材具有長邊方向與短邊方向，所述多個半導體裝置以於所述樹脂基材上的長邊方向上形成列的方式形成，所述加強線的一部分於所述樹脂基材的長邊方向上大致連續地設置。In addition, the semiconductor device substrate of the present invention is characterized in that, in the invention, the resin base material has a long side direction and a short side direction, and the plurality of semiconductor devices are arranged on the long side of the resin base material. It is formed in such a way that rows are formed in the direction, and a part of the reinforcing wire is provided substantially continuously in the longitudinal direction of the resin base material.

另外，本發明的半導體裝置用基板的特徵在於，於所述發明中，所述樹脂基材具有長邊方向與短邊方向，所述多個半導體裝置以於所述樹脂基材上的長邊方向上形成列的方式形成，所述加強線的一部分於所述多個半導體裝置的列的兩個外緣部中，於所述樹脂基材的長邊方向上大致連續地設置。In addition, the semiconductor device substrate of the present invention is characterized in that, in the invention, the resin base material has a long side direction and a short side direction, and the plurality of semiconductor devices are arranged on the long side of the resin base material. It is formed in such a manner that a row is formed in the direction, and a part of the reinforcing wire is provided substantially continuously in the longitudinal direction of the resin base material in the two outer edge portions of the row of the plurality of semiconductor devices.

另外，本發明的半導體裝置用基板的特徵在於，於所述發明中，所述多個半導體裝置各自包括場效型電晶體，所述場效型電晶體具有：源極電極、汲極電極及閘極電極；與所述源極電極及所述汲極電極分別接觸的半導體層；以及使所述源極電極、所述汲極電極及所述半導體層與所述閘極電極絕緣的閘極絕緣層。In addition, the semiconductor device substrate of the present invention is characterized in that, in the invention, each of the plurality of semiconductor devices includes a field-effect transistor, and the field-effect transistor has a source electrode, a drain electrode, and A gate electrode; a semiconductor layer that is in contact with the source electrode and the drain electrode, respectively; and a gate that insulates the source electrode, the drain electrode, and the semiconductor layer from the gate electrode Insulation.

另外，本發明的半導體裝置用基板的特徵在於，於所述發明中，所述半導體層含有碳奈米管。In addition, the semiconductor device substrate of the present invention is characterized in that, in the invention, the semiconductor layer contains a carbon nanotube.

另外，本發明的半導體裝置用基板的特徵在於，於所述發明中，所述多個半導體裝置各自包括場效型電晶體，所述加強線由與所述場效型電晶體中所含的源極電極、汲極電極及閘極電極中位於靠近所述樹脂基材的一側的基材側的電極相同的材料，設置於與所述基材側的電極相同的層。In addition, the semiconductor device substrate of the present invention is characterized in that, in the invention, each of the plurality of semiconductor devices includes a field-effect transistor, and the reinforcement line is composed of a semiconductor device contained in the field-effect transistor. Among the source electrode, the drain electrode, and the gate electrode, the same material as the electrode on the substrate side on the side closer to the resin substrate is provided on the same layer as the electrode on the substrate side.

另外，本發明的半導體裝置用基板的特徵在於，於所述發明中，所述多個半導體裝置各自包括具有底部閘極結構的場效型電晶體，所述加強線由與構成所述場效型電晶體中所含的閘極電極的材料相同的材料，設置於與所述閘極電極相同的層。In addition, the semiconductor device substrate of the present invention is characterized in that, in the invention, each of the plurality of semiconductor devices includes a field-effect transistor having a bottom gate structure, and the reinforcement line is composed of and constitutes the field-effect transistor. The same material as the gate electrode contained in the type transistor is provided on the same layer as the gate electrode.

另外，本發明的半導體裝置用基板的特徵在於，於所述發明中，多個所述場效型電晶體的至少一部分具有於相對於所述場效型電晶體的半導體層而與閘極絕緣層相反的一側和所述半導體層接觸的第二絕緣層，於所述樹脂基材上具有由與構成所述第二絕緣層的材料相同的材料構成的第二加強線。In addition, the semiconductor device substrate of the present invention is characterized in that, in the invention, at least a part of the plurality of field-effect transistors is insulated from the gate electrode with respect to the semiconductor layer of the field-effect transistor. The second insulating layer on the opposite side of the layer that is in contact with the semiconductor layer has a second reinforcing wire made of the same material as the material constituting the second insulating layer on the resin base material.

另外，本發明的半導體裝置用基板的特徵在於，於所述發明中，所述場效型電晶體的閘極電極及所述加強線彼此為相同的厚度，所述厚度為30 nm以上且500 nm以下。In addition, the semiconductor device substrate of the present invention is characterized in that, in the invention, the gate electrode of the field-effect transistor and the reinforcement line have the same thickness as each other, and the thickness is 30 nm or more and 500 nm. Below nm.

另外，本發明的半導體裝置用基板的特徵在於，於所述發明中，所述場效型電晶體是具有頂部接觸結構的場效型電晶體。In addition, the semiconductor device substrate of the present invention is characterized in that, in the invention, the field effect transistor is a field effect transistor having a top contact structure.

另外，本發明的半導體裝置用基板的特徵在於，於所述發明中，所述多個半導體裝置各自為無線通訊裝置。In addition, the semiconductor device substrate of the present invention is characterized in that, in the invention, each of the plurality of semiconductor devices is a wireless communication device.

另外，本發明的半導體裝置用基板的製造方法是製造所述發明中的任一者中記載的半導體裝置用基板的方法，且其特徵在於，於同一步驟中進行所述樹脂基材上的所述多個半導體裝置的構成構件中的任一者的形成與所述加強線的形成。In addition, the method for manufacturing a substrate for a semiconductor device of the present invention is a method for manufacturing the substrate for a semiconductor device described in any one of the inventions, and is characterized in that all the substrates on the resin substrate are performed in the same step. The formation of any one of the constituent members of the plurality of semiconductor devices and the formation of the reinforcing wire.

另外，本發明的半導體裝置用基板的製造方法的特徵在於，於所述發明中，所述多個半導體裝置及所述加強線的形成是於以輥對輥方式搬運所述樹脂基材的同時加以實施。In addition, the method for manufacturing a substrate for a semiconductor device of the present invention is characterized in that, in the invention, the plurality of semiconductor devices and the reinforcing wire are formed at the same time that the resin base material is transported in a roll-to-roll manner. Implement it.

另外，本發明的半導體裝置用基板的製造方法的特徵在於，於所述發明中，於同一步驟中進行所述多個半導體裝置各自中所含的電極層中的至少一者的形成與所述加強線的形成。In addition, the method for manufacturing a substrate for a semiconductor device of the present invention is characterized in that, in the invention, the formation of at least one of the electrode layers contained in each of the plurality of semiconductor devices and the Reinforce the formation of lines.

另外，本發明的半導體裝置用基板的製造方法的特徵在於，於所述發明中，所述多個半導體裝置各自以包括場效型電晶體的方式形成，於同一步驟中進行所述場效型電晶體中所含的源極電極、汲極電極及閘極電極中位於靠近所述樹脂基材的一側的基材側的電極的形成與所述加強線的形成。In addition, the method of manufacturing a substrate for a semiconductor device of the present invention is characterized in that, in the invention, each of the plurality of semiconductor devices is formed to include a field-effect transistor, and the field-effect transistor is performed in the same step. The formation of the source electrode, the drain electrode, and the gate electrode contained in the transistor and the electrode on the side of the substrate on the side close to the resin substrate and the formation of the reinforcement line.

另外，本發明的半導體裝置用基板的製造方法的特徵在於，於所述發明中，所述多個半導體裝置各自以包括具有底部閘極結構的場效型電晶體的方式形成，於同一步驟中進行所述場效型電晶體中所含的閘極電極的形成與所述加強線的形成。In addition, the method for manufacturing a substrate for a semiconductor device of the present invention is characterized in that, in the invention, each of the plurality of semiconductor devices is formed to include a field-effect transistor having a bottom gate structure in the same step The formation of the gate electrode contained in the field-effect transistor and the formation of the reinforcement line are performed.

另外，本發明的半導體裝置用基板的製造方法的特徵在於，於所述發明中，多個所述場效型電晶體的至少一部分以具有於相對於所述場效型電晶體的半導體層而與閘極絕緣層相反的一側和所述半導體層接觸的第二絕緣層的方式形成，於同一步驟中進行所述樹脂基材上的由與構成所述第二絕緣層的材料相同的材料構成的第二加強線的形成與所述第二絕緣層的形成。In addition, the method of manufacturing a substrate for a semiconductor device of the present invention is characterized in that, in the invention, at least a part of the plurality of field-effect transistors has an opposite side to the semiconductor layer of the field-effect transistor. The second insulating layer that is in contact with the semiconductor layer on the side opposite to the gate insulating layer is formed, and the resin substrate is made of the same material as the material constituting the second insulating layer in the same step. The formation of the second reinforcing wire and the formation of the second insulating layer.

另外，本發明的半導體裝置用基板的製造方法的特徵在於，於所述發明中，於同一步驟中進行所述閘極電極的形成與所述加強線的形成的加強線形成步驟包括圖案化步驟，所述圖案化步驟是加工藉由濺鍍或真空蒸鍍法於所述樹脂基材上成膜的金屬膜，並加工成與所述閘極電極及所述加強線對應的圖案。In addition, the method for manufacturing a substrate for a semiconductor device of the present invention is characterized in that, in the invention, the step of forming the gate electrode and forming the reinforcing line in the same step includes a step of patterning. The patterning step is to process a metal film formed on the resin substrate by sputtering or vacuum evaporation, and process it into a pattern corresponding to the gate electrode and the reinforcing line.

另外，本發明的半導體裝置用基板的製造方法的特徵在於，於所述發明中，於同一步驟中進行所述閘極電極的形成與所述加強線的形成的加強線形成步驟包括：成膜步驟，於所述樹脂基材上使用含有導電體粒子與感光性有機成分的感光性糊而形成塗佈膜；以及圖案化步驟，藉由光微影法將所述塗佈膜加工成與所述閘極電極及所述加強線對應的圖案。In addition, the method for manufacturing a substrate for a semiconductor device of the present invention is characterized in that, in the invention, the step of forming the gate electrode and forming the reinforcing line in the same step includes: forming a film Step, using a photosensitive paste containing conductive particles and photosensitive organic components on the resin substrate to form a coating film; and a patterning step, processing the coating film by photolithography into the same The gate electrode and the pattern corresponding to the reinforcing line.

另外，本發明的半導體裝置用基板的製造方法的特徵在於，於所述發明中，以分別包圍所述多個半導體裝置的方式設置所述加強線。In addition, the method of manufacturing a substrate for a semiconductor device of the present invention is characterized in that, in the invention, the reinforcing wires are provided so as to surround the plurality of semiconductor devices, respectively.

另外，本發明的半導體裝置用基板的製造方法的特徵在於，於所述發明中，所述樹脂基材具有長邊方向與短邊方向，以於所述樹脂基材上的長邊方向上形成列的方式形成所述多個半導體裝置，於所述樹脂基材的長邊方向上大致連續地設置所述加強線的一部分。In addition, the method for manufacturing a substrate for a semiconductor device of the present invention is characterized in that, in the invention, the resin substrate has a longitudinal direction and a short side direction so as to be formed on the resin substrate in the longitudinal direction. The plurality of semiconductor devices are formed in a row, and a part of the reinforcing wire is provided substantially continuously in the longitudinal direction of the resin base material.

另外，本發明的半導體裝置用基板的製造方法的特徵在於，於所述發明中，所述樹脂基材具有長邊方向與短邊方向，以於所述樹脂基材上的長邊方向上形成列的方式形成所述多個半導體裝置，於所述多個半導體裝置的列的兩個外緣部中，於所述樹脂基材的長邊方向上大致連續地設置所述加強線的一部分。In addition, the method for manufacturing a substrate for a semiconductor device of the present invention is characterized in that, in the invention, the resin substrate has a longitudinal direction and a short side direction so as to be formed on the resin substrate in the longitudinal direction. The plurality of semiconductor devices are formed in a row, and a part of the reinforcing wire is provided substantially continuously in the longitudinal direction of the resin base in the two outer edge portions of the row of the plurality of semiconductor devices.

另外，本發明的半導體裝置用基板的製造方法的特徵在於，於所述發明中，所述多個半導體裝置各自為無線通訊裝置或無線通訊裝置的電路。In addition, the method of manufacturing a substrate for a semiconductor device of the present invention is characterized in that, in the invention, each of the plurality of semiconductor devices is a wireless communication device or a circuit of a wireless communication device.

另外，本發明的無線通訊裝置的製造方法的特徵在於包括將藉由所述發明中記載的半導體裝置用基板的製造方法而獲得的半導體裝置用基板按照每個所述無線通訊裝置切分的步驟。In addition, the method of manufacturing a wireless communication device of the present invention is characterized by including a step of dividing the substrate for a semiconductor device obtained by the method of manufacturing a substrate for a semiconductor device described in the invention into each of the wireless communication devices. .

另外，本發明的無線通訊裝置的製造方法的特徵在於包括：將藉由所述發明中記載的半導體裝置用基板的製造方法而獲得的半導體裝置用基板按照每個所述無線通訊裝置的電路切分的步驟；以及將切分的所述無線通訊裝置的電路貼合至天線的步驟。In addition, the method of manufacturing a wireless communication device of the present invention is characterized by including: cutting the substrate for a semiconductor device obtained by the method of manufacturing a substrate for a semiconductor device described in the invention for each circuit of the wireless communication device. The step of dividing; and the step of attaching the divided circuit of the wireless communication device to the antenna.

另外，本發明的無線通訊裝置的製造方法的特徵在於包括：將藉由所述發明中記載的半導體裝置用基板的製造方法而獲得的半導體裝置用基板的所述無線通訊裝置的電路與天線貼合的步驟；以及將貼合所述無線通訊裝置的電路與所述天線後的所述半導體裝置用基板按照每個包括所述無線通訊裝置的電路與所述天線的無線通訊裝置切分的步驟。 [發明的效果]In addition, the method of manufacturing a wireless communication device of the present invention is characterized by including: pasting the circuit and antenna of the wireless communication device of the semiconductor device substrate obtained by the method of manufacturing a semiconductor device substrate described in the invention And the step of dividing the semiconductor device substrate after bonding the circuit of the wireless communication device and the antenna into each wireless communication device including the circuit of the wireless communication device and the antenna . [Effects of the invention]

根據本發明，可提供一種即使於在基板上形成多個半導體裝置後亦可抑制半導體裝置的特性偏差的半導體裝置用基板、半導體裝置用基板的製造方法及無線通訊裝置的製造方法。According to the present invention, it is possible to provide a substrate for a semiconductor device, a method for manufacturing a substrate for a semiconductor device, and a method for manufacturing a wireless communication device that can suppress variations in characteristics of the semiconductor device even after forming a plurality of semiconductor devices on the substrate.

以下，適宜參照圖式來對本發明的半導體裝置用基板、半導體裝置用基板的製造方法及無線通訊裝置的製造方法的較佳的實施形態進行詳細說明。再者，本發明並不受該些實施形態限定，當然可於可達成發明目的且不脫離發明主旨的範圍內進行各種變更。Hereinafter, preferred embodiments of the substrate for a semiconductor device, a method for manufacturing a substrate for a semiconductor device, and a method for manufacturing a wireless communication device of the present invention will be described in detail with reference to the drawings. In addition, the present invention is not limited to these embodiments, and it is of course possible to make various changes within the scope that the object of the invention can be achieved without departing from the gist of the invention.

＜半導體裝置用基板＞ 本發明的實施形態的半導體裝置用基板為如下半導體裝置用基板：具有樹脂基材、以及樹脂基材上所包括的多個半導體裝置，且於樹脂基材上具有以包圍半導體裝置的方式設置的加強線，加強線由與構成半導體裝置中所含的電極層中的至少一者的材料相同的材料構成，加強線以按照每個包含一個以上的半導體裝置的區域分別包圍的方式設置。換言之，本發明的實施形態的半導體裝置用基板為如下半導體裝置用基板：具有樹脂基材、以及所述樹脂基材上所包括的多個半導體裝置，且於所述樹脂基材上具有以包圍所述多個半導體裝置的方式設置的加強線，所述加強線由與構成所述多個半導體裝置中所含的電極層中的至少一者的材料相同的材料構成，於所述樹脂基材上存在多個所述多個半導體裝置中的一個以上被所述加強線包圍的區域。＜Substrates for semiconductor devices＞ The substrate for a semiconductor device according to an embodiment of the present invention is a substrate for a semiconductor device having a resin base material and a plurality of semiconductor devices included on the resin base material, and having a resin base material provided on the resin base material so as to surround the semiconductor device The reinforcing wire is made of the same material as the material constituting at least one of the electrode layers included in the semiconductor device, and the reinforcing wire is provided so as to surround each area including one or more semiconductor devices. In other words, the semiconductor device substrate of the embodiment of the present invention is a semiconductor device substrate having a resin base material, and a plurality of semiconductor devices included on the resin base material, and having a surrounding area on the resin base material The reinforcing wire is provided in the manner of the plurality of semiconductor devices, the reinforcing wire is made of the same material as the material constituting at least one of the electrode layers included in the plurality of semiconductor devices, and the resin substrate There is a region surrounded by the reinforcement line at more than one of the plurality of semiconductor devices.

（實施形態1） 圖1是表示本發明的實施形態1的半導體裝置用基板的一結構例的示意圖。如圖1所示，本發明的實施形態1的半導體裝置用基板50具有樹脂基材1，於所述樹脂基材1上具有多個半導體裝置、例如9個半導體裝置10。另外，半導體裝置用基板50於樹脂基材1上具有在樹脂基材1的橫向延伸存在的多個（例如4條）加強線11a～加強線11d、以及在樹脂基材1的縱向延伸存在的多個（例如4條）加強線12a～加強線12d。加強線11a～加強線11d及加強線12a～加強線12d以分別正交的方式配置，分別包圍該些多個半導體裝置10。此時，於樹脂基材1上存在多個（實施形態1中如圖1例示般為9個）由加強線11a～加強線11d及加強線12a～加強線12d包圍各半導體裝置10的區域。另外，於樹脂基材1具有與其橫向平行的端部的情況下，加強線11a～加強線11d較佳為相對於樹脂基材1的所述平行的端部平行地配置。(Embodiment 1) FIG. 1 is a schematic diagram showing a configuration example of a substrate for a semiconductor device according to Embodiment 1 of the present invention. As shown in FIG. 1, a substrate 50 for a semiconductor device according to the first embodiment of the present invention has a resin substrate 1 on which a plurality of semiconductor devices, for example, nine semiconductor devices 10 are provided. In addition, the semiconductor device substrate 50 has, on the resin base material 1, a plurality of (for example, four) reinforcing wires 11a to 11d extending in the lateral direction of the resin base material 1, and a plurality of reinforcing wires 11a to 11d extending in the longitudinal direction of the resin base material 1. A plurality of (for example, four) reinforcing wires 12a to 12d. The reinforcing wires 11 a to 11 d and the reinforcing wires 12 a to 12 d are arranged so as to be orthogonal to each other, and surround the plurality of semiconductor devices 10 respectively. At this time, there are a plurality of regions on the resin substrate 1 (9 in the first embodiment as illustrated in FIG. 1) where each semiconductor device 10 is surrounded by the reinforcing wires 11 a to 11 d and the reinforcing wires 12 a to 12 d. In addition, when the resin base material 1 has an end portion parallel to the lateral direction, it is preferable that the reinforcing wires 11 a to 11 d are arranged in parallel with respect to the parallel end portion of the resin base material 1.

樹脂基材1的橫向及縱向是彼此垂直的方向且是相對於樹脂基材1的厚度方向垂直的方向。樹脂基材1的厚度方向是與圖的紙面（實施形態1中為圖1的紙面）垂直的方向。樹脂基材1的厚度方向、橫向及縱向的定義於本發明中的所有實施形態中共用。The lateral direction and the longitudinal direction of the resin base material 1 are directions perpendicular to each other and are directions perpendicular to the thickness direction of the resin base material 1. The thickness direction of the resin base material 1 is a direction perpendicular to the paper surface of the drawing (the paper surface of FIG. 1 in Embodiment 1). The definitions of the thickness direction, the lateral direction, and the longitudinal direction of the resin substrate 1 are common to all embodiments in the present invention.

另外，於本實施形態1中，樹脂基材1是具有長邊方向與短邊方向的基材。例如，於圖1所示的樹脂基材1中，樹脂基材1的長邊方向是所述樹脂基材1的橫向，樹脂基材1的短邊方向是所述樹脂基材1的縱向。9個半導體裝置10以於樹脂基材1上的長邊方向上形成列的方式形成。於圖1所示的例子中，半導體裝置10的列是一列包含3個半導體裝置10且於短邊方向（縱向）上排列的列。所述半導體裝置10的列數為3。而且，加強線11a～加強線11d的一部分、例如該些加強線11a～加強線11d中位於樹脂基材1的短邊方向的兩端側的加強線11a及加強線11d於所述半導體裝置10的列（圖1中合計3列）的外緣部中，於樹脂基材1的長邊方向上連續地設置。即，加強線11a及加強線11d是於半導體裝置10的列的兩個外緣部中連續地設置的加強線。再者，半導體裝置10的列的兩個外緣部亦可以說為於樹脂基材1的長邊方向上延伸存在的兩個外緣部，該方面於以下所示的所有實施形態中共用。In addition, in the first embodiment, the resin base material 1 is a base material having a long-side direction and a short-side direction. For example, in the resin substrate 1 shown in FIG. 1, the long side direction of the resin substrate 1 is the horizontal direction of the resin substrate 1, and the short side direction of the resin substrate 1 is the longitudinal direction of the resin substrate 1. Nine semiconductor devices 10 are formed in such a way that rows are formed in the longitudinal direction of the resin base material 1. In the example shown in FIG. 1, the row of semiconductor devices 10 is a row including three semiconductor devices 10 and arranged in the short-side direction (vertical direction). The number of columns of the semiconductor device 10 is three. Furthermore, a part of the reinforcing wire 11a to the reinforcing wire 11d, for example, the reinforcing wire 11a and the reinforcing wire 11d located on the both ends of the resin base material 1 in the short-side direction of the reinforcing wire 11a to the reinforcing wire 11d are in the semiconductor device 10 In the outer edges of the rows of (3 rows in total in FIG. 1), they are continuously provided in the longitudinal direction of the resin base material 1. That is, the reinforcing wires 11 a and the reinforcing wires 11 d are reinforcing wires continuously provided in the two outer edge portions of the row of the semiconductor device 10. In addition, the two outer edge portions of the row of the semiconductor device 10 can also be said to be two outer edge portions extending in the longitudinal direction of the resin base material 1, and this aspect is common to all the embodiments shown below.

藉由半導體裝置用基板50具有加強線11a～加強線11d及加強線12a～加強線12d，半導體裝置用基板50於暴露於濕度或溫度等環境的變化時，可抑制樹脂基材1的面內的伸縮。因此，可抑制由半導體裝置用基板50的伸縮偏差所引起的9個半導體裝置10間的特性偏差。Since the semiconductor device substrate 50 has the reinforcing wires 11a to 11d and the reinforcing wires 12a to 12d, when the semiconductor device substrate 50 is exposed to changes in the environment such as humidity or temperature, the in-plane of the resin substrate 1 can be suppressed的flexibility. Therefore, it is possible to suppress variations in characteristics among the nine semiconductor devices 10 caused by variations in expansion and contraction of the substrate 50 for semiconductor devices.

樹脂基材1中使用的材料並無特別限制，只要至少配置有半導體裝置10的基材面為絕緣性的材料即可。作為此種樹脂基材1的材料，例如可較佳地使用聚醯亞胺（Polyimide，PI）樹脂、聚酯樹脂、聚醯胺樹脂、環氧樹脂、聚碳酸酯樹脂、纖維素系樹脂、聚醯胺醯亞胺樹脂、聚醚醯亞胺樹脂、聚醚酮樹脂、聚碸樹脂、聚苯硫醚（Polyphenylene Sulfide，PPS）樹脂、環烯烴樹脂等樹脂、或者包含聚丙烯（Polypropylene，PP）的片材。但是，樹脂基材1中使用的材料並不限定於該些。The material used for the resin substrate 1 is not particularly limited, as long as at least the surface of the substrate on which the semiconductor device 10 is arranged is an insulating material. As the material of the resin substrate 1, for example, polyimide (PI) resin, polyester resin, polyimide resin, epoxy resin, polycarbonate resin, cellulose resin, Polyamide imide resin, polyether imide resin, polyether ketone resin, polysulfide resin, polyphenylene sulfide (PPS) resin, cycloolefin resin and other resins, or resins containing polypropylene (Polypropylene, PP) )Sheet. However, the material used in the resin base material 1 is not limited to these.

該些中，較佳為包含選自聚對苯二甲酸乙二酯（Polyethylene Terephthalate，PET）、聚萘二甲酸乙二酯、PPS、聚苯碸、環烯烴聚合物、聚醯胺或PI中的至少一種樹脂作為樹脂基材1的材料。就價格低的觀點而言，PET膜較佳為作為樹脂基材1的材料。Among these, it is preferable to include those selected from polyethylene terephthalate (PET), polyethylene naphthalate, PPS, polystyrene, cycloolefin polymer, polyamide or PI. At least one kind of resin is used as the material of the resin substrate 1. From the viewpoint of low price, a PET film is preferable as the material of the resin base material 1.

另外，就樹脂基材1與電極或配線的密接性的觀點而言，聚碸樹脂、PPS樹脂亦較佳為作為樹脂基材1的材料。推測其原因在於：電極或配線中的金屬原子會與該些樹脂中所含的硫原子強烈地進行相互作用。In addition, from the viewpoint of the adhesiveness of the resin base material 1 and the electrodes or wiring, a polycarbonate resin and a PPS resin are also preferable as the material of the resin base material 1. It is presumed that the reason is that the metal atoms in the electrodes or wiring strongly interact with the sulfur atoms contained in these resins.

樹脂基材1的厚度較佳為25 μm以上且100 μm以下。藉由使樹脂基材1的厚度為所述範圍內，半導體裝置用基板50可具有高耐久性與適度的柔軟性。The thickness of the resin substrate 1 is preferably 25 μm or more and 100 μm or less. By setting the thickness of the resin base material 1 within the above-mentioned range, the substrate 50 for a semiconductor device can have high durability and moderate flexibility.

加強線11a～加強線11d及加強線12a～加強線12d較佳為全部由相同的材料形成，且使其厚度相等。另外，加強線11a～加強線11d及加強線12a～加強線12d的厚度較佳為與多個半導體裝置10的各自的厚度相同，或者比所述半導體裝置10的厚度薄。於使所述加強線的厚度比半導體裝置10的厚度厚的情況下，在將半導體裝置用基板50重疊或者捲繞成卷狀時，樹脂基材1與所述加強線摩擦，藉此所述加強線容易帶電，其結果，半導體裝置10容易產生損傷。The reinforcing wires 11a to 11d and the reinforcing wires 12a to 12d are preferably all formed of the same material and have the same thickness. In addition, the thicknesses of the reinforcing wires 11 a to 11 d and the reinforcing wires 12 a to 12 d are preferably the same as the respective thicknesses of the plurality of semiconductor devices 10 or thinner than the thickness of the semiconductor devices 10. When the thickness of the reinforcing wire is thicker than the thickness of the semiconductor device 10, when the semiconductor device substrate 50 is stacked or wound into a roll, the resin base material 1 rubs against the reinforcing wire, thereby The reinforcing wire is likely to be charged, and as a result, the semiconductor device 10 is likely to be damaged.

於本發明中，所謂「半導體裝置的厚度」是指於形成於樹脂基材上的半導體裝置的剖面中，自樹脂基材與半導體裝置的界面至樹脂基材的垂直方向（厚度方向）上的半導體裝置的最高部位的厚度。In the present invention, the "thickness of the semiconductor device" refers to the cross section of the semiconductor device formed on the resin substrate from the interface between the resin substrate and the semiconductor device to the vertical direction (thickness direction) of the resin substrate The thickness of the highest part of the semiconductor device.

另外，加強線11a～加強線11d及加強線12a～加強線12d分別由與構成多個半導體裝置10中所含的電極層中的至少一者的材料相同的材料構成。即，用於加強線11a～加強線11d及加強線12a～加強線12d的材料是與構成半導體裝置10的層之一即電極層的至少一者相同的材料。藉此，可減少半導體裝置用基板50的製造成本。In addition, the reinforcing wires 11 a to 11 d and the reinforcing wires 12 a to 12 d are each made of the same material as the material constituting at least one of the electrode layers included in the plurality of semiconductor devices 10. That is, the materials used for the reinforcing wires 11 a to 11 d and the reinforcing wires 12 a to 12 d are the same materials as at least one of the electrode layers, which are one of the layers constituting the semiconductor device 10. Thereby, the manufacturing cost of the substrate 50 for a semiconductor device can be reduced.

於本發明中，「加強線與構成半導體裝置的電極層的至少一個由相同的材料構成」是指於「加強線」與「構成半導體裝置的電極層的至少一個」中所含的元素中含有莫耳比率最高的元素相同。「加強線」與「構成半導體裝置的電極層的至少一個」的元素的種類及含有比率可藉由X射線光電子分光（X射線光電子能譜（X-Ray Photoelectron Spectroscopy，XPS））或二次離子質量分析法（二次離子質譜法（Secondary Ion Mass Spectrometry，SIMS））等的元素分析進行鑑定。In the present invention, "the reinforcing wire and at least one of the electrode layer constituting the semiconductor device are composed of the same material" means that the elements contained in the "reinforcing wire" and "at least one of the electrode layers constituting the semiconductor device" are contained The element with the highest molar ratio is the same. The types and content ratios of the elements of "strengthening line" and "at least one of the electrode layers of the semiconductor device" can be determined by X-ray photoelectron spectroscopy (X-Ray Photoelectron Spectroscopy, XPS) or secondary ions. Element analysis such as mass analysis (Secondary Ion Mass Spectrometry (SIMS)) is used for identification.

另外，多個（實施形態1中為9個）半導體裝置10可為該些的全部彼此相同的半導體裝置，亦可為該些中的一部分或全部彼此不同的半導體裝置，較佳為構成半導體裝置10的材料及層結構或各層的厚度相同。關於半導體裝置10的詳情將於後文進行說明。In addition, the plurality of (9 in the first embodiment) semiconductor devices 10 may be all of the semiconductor devices that are the same as each other, or some or all of these semiconductor devices may be different from each other, and preferably constitute a semiconductor device The material and layer structure of 10 or the thickness of each layer are the same. The details of the semiconductor device 10 will be described later.

（實施形態1的變形例） 圖2是表示本發明的實施形態1的變形例的半導體裝置用基板的一結構例的示意圖。於所述實施形態1中，多個半導體裝置10全部被加強線11a～加強線11d及加強線12a～加強線12d分別單獨包圍，但並不限於此，多個半導體裝置10的集合亦可由加強線包圍。例如，如圖2所示，所述變形例的半導體裝置用基板50A於樹脂基材1上具有加強線11a、加強線11b、加強線11d及加強線12a、加強線12b、加強線12d。於半導體裝置用基板50A中，形成有由該些加強線11a、加強線11b、加強線11d及加強線12a、加強線12b、加強線12d包圍多個半導體裝置10中的一個以上的四個區域。如圖2所示，作為所述變形例中的所述區域，可列舉包含一個半導體裝置10的區域、包含兩個半導體裝置10的集合的區域、以及包含四個半導體裝置10的集合的區域。(Modification of Embodiment 1) 2 is a schematic diagram showing a configuration example of a substrate for a semiconductor device according to a modification of the first embodiment of the present invention. In the first embodiment, the plurality of semiconductor devices 10 are all individually surrounded by the reinforcing wires 11a to 11d and the reinforcing wires 12a to 12d, respectively, but it is not limited to this, and a collection of the plurality of semiconductor devices 10 may also be reinforced by Surrounded by lines. For example, as shown in FIG. 2, the semiconductor device substrate 50A of the modified example has a reinforcing wire 11 a, a reinforcing wire 11 b, a reinforcing wire 11 d, and a reinforcing wire 12 a, a reinforcing wire 12 b, and a reinforcing wire 12 d on the resin base material 1. In the semiconductor device substrate 50A, four regions surrounded by one or more of the plurality of semiconductor devices 10 are formed by the reinforcing wires 11a, the reinforcing wires 11b, the reinforcing wires 11d, the reinforcing wires 12a, the reinforcing wires 12b, and the reinforcing wires 12d. . As shown in FIG. 2, as the region in the modification example, a region including one semiconductor device 10, a region including a collection of two semiconductor devices 10, and a region including a collection of four semiconductor devices 10 can be cited.

於所述變形例中，由加強線11a、加強線11b、加強線11d及加強線12a、加強線12b、加強線12d包圍的區域的形狀、由該些加強線包圍的半導體裝置10的集合的數量及所述集合中所含的半導體裝置10的數量並不限定於圖2所示者。例如，樹脂基材1上的加強線的結構亦可為如下結構等：將在樹脂基材1的縱向上排列的3個半導體裝置10設為一個集合且可形成三個所述集合。其中，關於所述加強線的結構，以分別包圍所述多個半導體裝置10的方式設置的結構比以包圍半導體裝置10的集合的方式設置的結構更佳。原因在於：與包圍半導體裝置10的集合的情況相比，由所述加強線分別包圍半導體裝置10更容易減少樹脂基材1的面內的伸縮偏差。In the above-mentioned modification, the shape of the area surrounded by the reinforcing wire 11a, the reinforcing wire 11b, the reinforcing wire 11d, the reinforcing wire 12a, the reinforcing wire 12b, and the reinforcing wire 12d, and the assembly of the semiconductor device 10 surrounded by the reinforcing wire The number and the number of semiconductor devices 10 included in the set are not limited to those shown in FIG. 2. For example, the structure of the reinforcing line on the resin base material 1 may also be a structure in which three semiconductor devices 10 arranged in the longitudinal direction of the resin base material 1 are set as one set and three such sets can be formed. Among them, with regard to the structure of the reinforcing wire, a structure provided to surround the plurality of semiconductor devices 10 is better than a structure provided to surround a collection of semiconductor devices 10. The reason is that it is easier to reduce the in-plane expansion and contraction deviation of the resin base material 1 by surrounding the semiconductor devices 10 by the reinforcing wires, compared to the case of surrounding the assembly of the semiconductor devices 10.

於所述實施形態1中，例示了加強線11a～加強線11d及加強線12a～加強線12d與半導體裝置10形成於樹脂基材1上的同一面的情況，但本發明並不限定於此。例如，加強線11a～加強線11d及加強線12a～加強線12d與半導體裝置10亦可分別形成於與樹脂基材1相反的面。In the first embodiment, the case where the reinforcing wires 11a to 11d and the reinforcing wires 12a to 12d are formed on the same surface as the semiconductor device 10 on the resin substrate 1 is illustrated, but the present invention is not limited to this . For example, the reinforcing wires 11 a to 11 d and the reinforcing wires 12 a to 12 d and the semiconductor device 10 may be formed on the opposite surface of the resin substrate 1, respectively.

另外，於所述實施形態1及其變形例中，例示了於樹脂基材1上設置有9個半導體裝置10的情況，但本發明並不限定於此。例如，半導體裝置10於樹脂基材1上的配置數量不限於所述9個，可為2個以上且未滿9個，亦可為9個以上。另外，於所述實施形態1及其變形例中，半導體裝置10於樹脂基材1上配置了3行3列，但本發明並不限定於此。例如，所述加強線及半導體裝置於可在樹脂基材1上形成加強線與半導體裝置的範圍內可以成為任意的行數及列數的方式配置於樹脂基材1上。In addition, in the first embodiment and its modification examples, the case where nine semiconductor devices 10 are provided on the resin substrate 1 is exemplified, but the present invention is not limited to this. For example, the number of semiconductor devices 10 arranged on the resin substrate 1 is not limited to the above-mentioned nine, and it may be two or more and less than nine, or it may be nine or more. In addition, in the first embodiment and its modification examples, the semiconductor device 10 is arranged in 3 rows and 3 columns on the resin substrate 1, but the present invention is not limited to this. For example, the reinforcing wire and the semiconductor device may be arranged on the resin base material 1 in an arbitrary number of rows and columns within a range in which the reinforcing wire and the semiconductor device can be formed on the resin base material 1.

關於以上說明的實施形態1及其變形例的變更於以下說明的各實施形態中亦可同樣地進行。Modifications of Embodiment 1 and its modified examples described above can also be carried out in the same manner in each embodiment described below.

（實施形態2） 圖3是表示本發明的實施形態2的半導體裝置用基板的一結構例的示意圖。如圖3所示，本發明的實施形態2的半導體裝置用基板50B具有樹脂基材1，於所述樹脂基材1上具有多個半導體裝置、例如12個半導體裝置10。另外，半導體裝置用基板50B於樹脂基材1上具有分別包圍該些半導體裝置10的多個（例如與半導體裝置10為相同數量的12條）加強線13。該些加強線13分別形成為大致圓狀的形狀，且以加強線13彼此接觸的方式配置。例如，於樹脂基材1上存在多個（圖3中為12個）由該些加強線13分別包圍多個半導體裝置10的大致圓狀的區域。半導體裝置用基板50B中的加強線13的作用與所述實施形態1中者相同。(Embodiment 2) 3 is a schematic diagram showing a configuration example of a semiconductor device substrate according to Embodiment 2 of the present invention. As shown in FIG. 3, the semiconductor device substrate 50B of the second embodiment of the present invention has a resin base material 1 on which a plurality of semiconductor devices, for example, 12 semiconductor devices 10 are provided. In addition, the semiconductor device substrate 50B has a plurality of (for example, the same number of 12 as the semiconductor device 10) reinforcing wires 13 surrounding the semiconductor devices 10 on the resin base material 1. These reinforcing wires 13 are respectively formed in a substantially circular shape, and are arranged such that the reinforcing wires 13 are in contact with each other. For example, there are a plurality of (12 in FIG. 3) on the resin substrate 1, a substantially circular region surrounded by the plurality of semiconductor devices 10 by the reinforcing wires 13 respectively. The function of the reinforcing wire 13 in the substrate 50B for a semiconductor device is the same as that in the first embodiment described above.

於所述實施形態2中，例示了以加強線13彼此接觸的方式配置的情況，但本發明並不限定於此，亦可以加強線13彼此分開的方式配置。其中，以加強線13彼此接觸的方式配置會更容易抑制樹脂基材1整體的變形，因此有利。In the second embodiment described above, the case where the reinforcing wires 13 are arranged in contact with each other is exemplified, but the present invention is not limited to this, and the reinforcing wires 13 may be arranged so as to be separated from each other. Among them, it is advantageous to arrange such that the reinforcing wires 13 are in contact with each other because it is easier to suppress the deformation of the entire resin base material 1.

（實施形態3） 圖4是表示本發明的實施形態3的半導體裝置用基板的一結構例的示意圖。如圖4所示，本發明的實施形態3的半導體裝置用基板50C具有樹脂基材1，於所述樹脂基材1上具有多個半導體裝置、例如18個半導體裝置10。另外，半導體裝置用基板50C於樹脂基材1上具有在相對於樹脂基材1的縱向及橫向傾斜的方向上延伸存在的多個加強線14、加強線15、以及在樹脂基材1的橫向上延伸存在的加強線16。加強線14以相對於橫向的加強線16在規定的方向（例如自圖4的紙面的左上側朝向右下側的方向）上傾斜的方式於樹脂基材1上形成有多個（圖4中為5條）。加強線15以相對於橫向的加強線16在與所述加強線不同的方向（例如自圖4的紙面的右上側朝向左下側的方向）上傾斜的方式於樹脂基材1上形成有多個（圖4中為4條）。加強線16相對於樹脂基材1的縱向兩端中的至少一個端部平行地配置。(Embodiment 3) 4 is a schematic diagram showing a configuration example of a semiconductor device substrate according to Embodiment 3 of the present invention. As shown in FIG. 4, the semiconductor device substrate 50C of the third embodiment of the present invention has a resin base material 1 on which a plurality of semiconductor devices, for example, 18 semiconductor devices 10 are provided. In addition, the semiconductor device substrate 50C has, on the resin base material 1, a plurality of reinforcing lines 14 extending in a direction inclined with respect to the longitudinal and lateral directions of the resin base material 1, the reinforcing lines 15, and the lateral direction of the resin base material 1. The existing reinforcement line 16 extends upward. The reinforcement line 14 is formed on the resin base material 1 in a manner inclined in a predetermined direction (for example, the direction from the upper left side to the lower right side of the paper in FIG. 4) with respect to the lateral reinforcement line 16 (in FIG. 4). For 5). The reinforcement line 15 is formed on the resin base material 1 in a manner that is inclined in a direction different from the reinforcement line (for example, the direction from the upper right side of the paper surface of FIG. 4 to the lower left side) with respect to the lateral reinforcement line 16 (4 in Figure 4). The reinforcing wire 16 is arranged in parallel to at least one of the longitudinal ends of the resin base material 1.

如圖4所示，所述加強線14～加強線16於樹脂基材1的面上彼此交差，形成分別包圍多個半導體裝置10的三角形狀的區域。於樹脂基材1上存在多個由該些加強線14～加強線16分別包圍多個半導體裝置10的三角形狀的區域。半導體裝置用基板50C中的加強線14～加強線16的作用與所述實施形態1中者相同。As shown in FIG. 4, the reinforcing wires 14 to 16 intersect each other on the surface of the resin base material 1 to form triangle-shaped regions each surrounding a plurality of semiconductor devices 10. There are a plurality of triangular-shaped regions surrounded by the plurality of semiconductor devices 10 by the reinforcing wires 14 to 16 respectively on the resin substrate 1. The functions of the reinforcing wire 14 to the reinforcing wire 16 in the substrate 50C for a semiconductor device are the same as those in the first embodiment described above.

（實施形態4） 圖5是表示本發明的實施形態4的半導體裝置用基板的一結構例的示意圖。如圖5所示，本發明的實施形態4的半導體裝置用基板50D具有樹脂基材1，於所述樹脂基材1上具有多個半導體裝置、例如13個半導體裝置10。另外，半導體裝置用基板50D於樹脂基材1上具有分別包圍該些多個半導體裝置10的加強線17。加強線17以形成彼此鄰接的多個六邊形的方式形成，以採取所謂的蜂窩結構的方式配置於樹脂基材1上。例如於樹脂基材1上存在多個由加強線17分別包圍多個半導體裝置10的六邊形狀的區域。半導體裝置用基板50D中的加強線17的作用與所述實施形態1中者相同。(Embodiment 4) 5 is a schematic diagram showing a configuration example of a semiconductor device substrate according to Embodiment 4 of the present invention. As shown in FIG. 5, a substrate 50D for a semiconductor device according to the fourth embodiment of the present invention has a resin substrate 1 on which a plurality of semiconductor devices, for example, 13 semiconductor devices 10 are provided. In addition, the substrate 50D for a semiconductor device has reinforcing wires 17 surrounding the plurality of semiconductor devices 10 on the resin base material 1. The reinforcing wires 17 are formed to form a plurality of hexagons adjacent to each other, and are arranged on the resin substrate 1 in a so-called honeycomb structure. For example, on the resin substrate 1, there are a plurality of hexagonal regions each surrounded by the plurality of semiconductor devices 10 by the reinforcing wires 17. The function of the reinforcing wire 17 in the substrate 50D for a semiconductor device is the same as that in the first embodiment described above.

（實施形態5） 圖6是表示本發明的實施形態5的半導體裝置用基板的一結構例的示意圖。如圖6所示，本發明的實施形態5的半導體裝置用基板50E具有長條膜狀的樹脂基材1，所述長條膜狀的樹脂基材1可成為自捲成卷狀的狀態起連續地送出並捲繞成卷狀的狀態。另外，半導體裝置用基板50E於自捲成卷狀的狀態起至再次捲繞成卷狀的狀態為止連續的樹脂基材1上，沿著樹脂基材1的長邊方向具有多個包括多個半導體裝置與加強線的設計。所述設計是藉由於樹脂基材1上組合至少多個半導體裝置與加強線而構成，是沿著樹脂基材1的長邊方向重複的結構部。例如，如圖6所示，半導體裝置用基板50E包括具有多個半導體裝置與加強線的設計D1、以及具有與所述設計D1相同的結構的設計D2。(Embodiment 5) 6 is a schematic diagram showing a configuration example of a semiconductor device substrate according to Embodiment 5 of the present invention. As shown in FIG. 6, the semiconductor device substrate 50E according to the fifth embodiment of the present invention has a long film-shaped resin base material 1 which can be rolled into a roll shape. It is continuously fed out and wound into a roll state. In addition, the substrate 50E for a semiconductor device is provided on the continuous resin base material 1 from the state wound into the roll shape to the state again wound into the roll shape, and has a plurality of including a plurality of portions along the longitudinal direction of the resin substrate 1. Design of semiconductor devices and reinforcement wires. The design is formed by combining at least a plurality of semiconductor devices and reinforcing wires on the resin base material 1, and is a structure repeated along the long side direction of the resin base material 1. For example, as shown in FIG. 6, the semiconductor device substrate 50E includes a design D1 having a plurality of semiconductor devices and reinforcing lines, and a design D2 having the same structure as the design D1.

如圖6所示，設計D1是具有所述實施形態1中記載的9個半導體裝置10、橫向的4條加強線11a～加強線11d、以及縱向的4條加強線12a～加強線12d的結構部。設計D2是重複與所述設計D1相同的結構者。即，設計D2中所含的9個半導體裝置是與所述設計D1相同的半導體裝置10。另外，設計D2中所含的橫向的4條加強線11e～加強線11h與所述設計D1的加強線11a～加強線11d相同，縱向的4條加強線12e～加強線12h與所述設計D1的加強線12a～加強線12d相同。於半導體裝置用基板50E的樹脂基材1上，該些設計D1、設計D2於樹脂基材1的長邊方向上大致連續地排列。As shown in FIG. 6, the design D1 is a structure having nine semiconductor devices 10 described in the first embodiment, four horizontal reinforcing lines 11a to 11d, and four vertical reinforcing lines 12a to 12d. unit. The design D2 repeats the same structure as the design D1. That is, the nine semiconductor devices included in the design D2 are the same semiconductor devices 10 as the design D1. In addition, the four horizontal reinforcing lines 11e to 11h included in the design D2 are the same as the reinforcing lines 11a to 11d of the design D1, and the four vertical reinforcing lines 12e to 12h are the same as those of the design D1. The reinforcing lines 12a to 12d are the same. On the resin base material 1 of the semiconductor device substrate 50E, the design D1 and the design D2 are arranged substantially continuously in the longitudinal direction of the resin base material 1.

於本實施形態5中，如圖6所示，樹脂基材1具有長邊方向與短邊方向，是可自捲成卷狀的狀態起至捲繞成卷狀的狀態為止連續地搬運的長條基材。即，所述樹脂基材1可藉由輥對輥方式於其長邊方向上連續地搬運。多個半導體裝置10以於樹脂基材1上的長邊方向上形成列的方式形成。於圖6所示的例子中，半導體裝置10的列於樹脂基材1的短邊方向（縱向）上排列有3個（3列）。即，所述半導體裝置10的列數為3。In the fifth embodiment, as shown in FIG. 6, the resin base material 1 has a long side direction and a short side direction, and is a length that can be continuously conveyed from a state wound into a roll shape to a state wound into a roll shape. Strip substrate. That is, the resin base material 1 can be continuously conveyed in the longitudinal direction thereof by a roll-to-roll method. The plurality of semiconductor devices 10 are formed so as to form rows in the longitudinal direction of the resin substrate 1. In the example shown in FIG. 6, three rows (three rows) of semiconductor devices 10 are arranged in the short-side direction (longitudinal direction) of the resin substrate 1. That is, the number of columns of the semiconductor device 10 is three.

多個加強線11a～加強線11h及加強線12a～加強線12h的一部分、例如加強線11a～加強線11h於樹脂基材1的長邊方向上大致連續地設置。而且，加強線11a、加強線11d及加強線11e、加強線11h於所述半導體裝置10的列的兩個外緣部中於樹脂基材1的長邊方向上大致連續地設置。即，設計D1中的加強線11a與設計D2中的加強線11e除了樹脂基材1上的設計間的間隙部以外，於樹脂基材1的長邊方向上連續地形成。與此同樣地，設計D1中的加強線11d與設計D2中的加強線11h除了樹脂基材1上的設計間的間隙部以外，於樹脂基材1的長邊方向上連續地形成。藉由於樹脂基材1的長邊方向上大致連續地形成加強線11a～加強線11h，與連續地形成加強線11a～加強線11h的情況相比，可定期地（週期性地）緩和樹脂基材1被捲繞時的彎折應力。其結果，可抑制加強線11a～加強線11h的斷線。The plurality of reinforcing wires 11 a to 11 h and a part of the reinforcing wires 12 a to 12 h, for example, the reinforcing wires 11 a to 11 h are provided substantially continuously in the longitudinal direction of the resin base material 1. Furthermore, the reinforcing wires 11a, the reinforcing wires 11d, the reinforcing wires 11e, and the reinforcing wires 11h are provided substantially continuously in the longitudinal direction of the resin substrate 1 in the two outer edge portions of the row of the semiconductor device 10. That is, the reinforcement line 11a in the design D1 and the reinforcement line 11e in the design D2 are continuously formed in the longitudinal direction of the resin base material 1 except for the gap between the designs on the resin base material 1. In the same manner, the reinforcement line 11d in the design D1 and the reinforcement line 11h in the design D2 are continuously formed in the longitudinal direction of the resin base material 1 except for the gap between the designs on the resin base material 1. Since the reinforcing wires 11a to 11h are formed substantially continuously in the longitudinal direction of the resin substrate 1, compared with the case where the reinforcing wires 11a to 11h are continuously formed, the resin base can be relaxed periodically (periodically). The bending stress when the material 1 is wound. As a result, it is possible to suppress disconnection of the reinforcing wires 11a to 11h.

於本發明中，「於長邊方向上大致連續地設置」是包括具有長邊方向與短邊方向的樹脂基材上的長邊方向上所形成的加強線於所述樹脂基材的長邊方向上為連續的狀態、以及以一定或不定間隔具有小間隙的狀態此兩者的概念。後者的例子是例如如設計D1中的加強線11a與設計D2中的加強線11e般，於樹脂基材上的長邊方向上隔開間隔地形成有加強線的狀態。於加強線具有多個間隔的情況下，較佳為由間隔分割的加強線各自的長度一定，多個間隔亦一定。藉此，於半導體裝置用基板的製造步驟中，可藉由光微影法或印刷法以樹脂基材的一定的搬運的進給量繼續形成加強線，因此可防止所述製造步驟的複雜化。In the present invention, "substantially continuously arranged in the longitudinal direction" means that the longitudinal direction of the resin substrate is formed on a resin substrate having a longitudinal direction and a short side direction. The longitudinal direction of the reinforcing line is formed on the long side of the resin substrate. It is a concept of both the state of being continuous in the direction and the state of having small gaps at certain or indefinite intervals. The latter example is, for example, a state in which reinforcement lines are formed at intervals in the longitudinal direction of the resin base material like the reinforcement lines 11a in the design D1 and the reinforcement lines 11e in the design D2. When the reinforcing wire has a plurality of intervals, it is preferable that the length of each reinforcing wire divided by the interval is constant, and the plurality of intervals are also constant. Thereby, in the manufacturing step of the substrate for semiconductor device, the reinforcement line can be continuously formed by the photolithography method or the printing method at a certain conveying feed rate of the resin base material, so that the complication of the manufacturing step can be prevented. .

藉由半導體裝置用基板50E具有加強線11a～加強線11h及加強線12a～加強線12h，半導體裝置用基板50E於暴露於濕度或溫度等環境的變化時，可控制樹脂基材1的每個設計的面內的伸縮。因此，可抑制由半導體裝置用基板50E的伸縮偏差所引起的設計內的9個半導體裝置10間的特性偏差、大致連續地形成的每個設計的半導體裝置10間的特性偏差。Since the semiconductor device substrate 50E has the reinforcing wires 11a to 11h and the reinforcing wires 12a to 12h, when the semiconductor device substrate 50E is exposed to changes in the environment such as humidity or temperature, each of the resin base materials 1 can be controlled. In-plane expansion and contraction of the design. Therefore, it is possible to suppress variations in characteristics among nine semiconductor devices 10 within a design due to variations in expansion and contraction of the semiconductor device substrate 50E, and variations in characteristics among semiconductor devices 10 of each design that are formed substantially continuously.

另外，樹脂基材1較佳為具有長邊方向與短邊方向，加強線11a～加強線11h平行地配置於在樹脂基材1的長度方向上延伸存在的樹脂基材端（即樹脂基材1的短邊方向兩端中的至少一者）。另外，多個半導體裝置10較佳為配置於與在樹脂基材1的長邊方向上延伸存在的樹脂基材端平行的列上。藉此，由於樹脂基材1的應變的控制在與樹脂基材1的長邊方向平行的方向上作用於樹脂基材1，因此樹脂基材1在半導體裝置用基板50E中的卷狀態穩定，容易減少外部衝擊或溫度、濕度變化所引起的樹脂基材1的卷未對準（進而半導體裝置用基板50E的卷未對準）。In addition, the resin base material 1 preferably has a long side direction and a short side direction, and the reinforcing lines 11a to 11h are arranged in parallel at the ends of the resin base material extending in the length direction of the resin base material 1 (ie, the resin base material At least one of both ends in the short-side direction of 1). In addition, the plurality of semiconductor devices 10 are preferably arranged in a row parallel to the end of the resin substrate extending in the longitudinal direction of the resin substrate 1. Thereby, since the control of the strain of the resin base material 1 acts on the resin base material 1 in a direction parallel to the longitudinal direction of the resin base material 1, the roll state of the resin base material 1 in the semiconductor device substrate 50E is stabilized. It is easy to reduce the roll misalignment of the resin base material 1 (and further the roll misalignment of the semiconductor device substrate 50E) caused by external impact or temperature and humidity changes.

另外，即使為可捲繞的長條基材，樹脂基材1的厚度亦較佳為25 μm以上且100 μm以下。藉由使樹脂基材1的厚度為所述範圍內，半導體裝置用基板50E可具有高耐久性與適度的柔軟性。In addition, even if it is a long substrate that can be wound, the thickness of the resin substrate 1 is preferably 25 μm or more and 100 μm or less. By making the thickness of the resin base material 1 within the said range, the board|substrate 50E for semiconductor devices can have high durability and moderate flexibility.

加強線11a～加強線11h及加強線12a～加強線12h較佳為全部由相同的材料形成，且使其厚度相等。另外，用於加強線11a～加強線11h及加強線12a～加強線12h的材料較佳為與構成半導體裝置10的層之一即電極層的至少一者相同的材料。藉此，可於減少半導體裝置用基板50E的製造成本的同時，提高連續的樹脂基材1被捲成卷狀時的摩擦等所引起的耐機械衝擊性。It is preferable that the reinforcing wires 11a to 11h and the reinforcing wires 12a to 12h are all formed of the same material and have the same thickness. In addition, the material used for the reinforcing wires 11 a to 11 h and the reinforcing wires 12 a to 12 h is preferably the same material as at least one of the electrode layers, which is one of the layers constituting the semiconductor device 10. Thereby, while reducing the manufacturing cost of the substrate 50E for a semiconductor device, it is possible to improve the mechanical shock resistance due to friction when the continuous resin base material 1 is wound into a roll shape.

於所述實施形態5中，例示了加強線11a～加強線11h及加強線12a～加強線12h與半導體裝置10形成於樹脂基材1上的同一面上的情況，但本發明並不限定於此。例如，加強線11a～加強線11h及加強線12a～加強線12h與半導體裝置10亦可分別形成於與樹脂基材1相反的面。其中，於樹脂基材1上的同一面上形成該些加強線及半導體裝置的情況可防止在將連續的樹脂基材1捲成卷狀時加強線與半導體裝置直接摩擦，因此有利。In the fifth embodiment, the case where the reinforcing wires 11a to 11h and the reinforcing wires 12a to 12h are formed on the same surface as the semiconductor device 10 on the resin substrate 1 is illustrated, but the present invention is not limited to this. For example, the reinforcing wires 11a to 11h and the reinforcing wires 12a to 12h and the semiconductor device 10 may be formed on the opposite surface of the resin base material 1, respectively. Among them, the formation of these reinforcing wires and the semiconductor device on the same surface of the resin substrate 1 can prevent the reinforcing wires from directly rubbing against the semiconductor device when the continuous resin substrate 1 is rolled into a roll shape, which is advantageous.

（實施形態5的變形例1） 圖7是表示本發明的實施形態5的變形例1的半導體裝置用基板的一結構例的示意圖。於所述實施形態5中，於自捲成卷狀的狀態起至捲繞成卷狀的狀態為止連續的樹脂基材1上，具有9個半導體裝置10、橫向的4條加強線11a～加強線11d及縱向的4條加強線12a～加強線12d的設計D1、和具有與其相同的結構的設計D2於樹脂基材1的長邊方向上大致連續地排列，但本發明的半導體裝置用基板的結構並不限定於此。例如，如圖7所示，實施形態5的變形例1的半導體裝置用基板50F於與實施形態5相同的樹脂基材1上包括設計D1a、設計D2a的重複結構來代替所述設計D1、設計D2的重複結構。(Modification 1 of Embodiment 5) FIG. 7 is a schematic diagram showing a configuration example of a semiconductor device substrate according to Modification 1 of Embodiment 5 of the present invention. In the fifth embodiment described above, the resin base material 1 that is continuous from the state wound into a roll shape to the state wound into a roll shape has 9 semiconductor devices 10 and 4 horizontal reinforcing lines 11a to reinforcing The design D1 of the line 11d and the four vertical reinforcement lines 12a to 12d to the reinforcement line 12d and the design D2 having the same structure are arranged substantially continuously in the longitudinal direction of the resin base material 1, but the semiconductor device substrate of the present invention The structure of is not limited to this. For example, as shown in FIG. 7, a semiconductor device substrate 50F of Modification 1 of Embodiment 5 includes a repeating structure of design D1a and design D2a on the same resin substrate 1 as that of Embodiment 5 instead of the design D1. The repeating structure of D2.

如圖7所示，設計D1a是具有所述9個半導體裝置10、橫向的3條加強線11a～加強線11c、以及縱向的4條加強線12a～加強線12d的結構部。設計D2a是重複與所述設計D1a相同的結構者。即，設計D2a中所含的9個半導體裝置是與所述設計D1a相同的半導體裝置10。另外，設計D2a中所含的橫向的3條加強線11e～加強線11g與所述設計D1a的加強線11a～加強線11c相同，縱向的4條加強線12e～加強線12h與所述設計D1a的加強線12a～加強線12d相同。於半導體裝置用基板50F的樹脂基材1上，該些設計D1a、設計D2a於樹脂基材1的長邊方向上大致連續地排列。As shown in FIG. 7, the design D1a is a structure having the nine semiconductor devices 10, three horizontal reinforcing lines 11a to 11c, and four vertical reinforcing lines 12a to 12d. The design D2a repeats the same structure as the design D1a. That is, the nine semiconductor devices included in the design D2a are the same semiconductor devices 10 as the design D1a. In addition, the three horizontal reinforcing lines 11e to 11g included in the design D2a are the same as the reinforcing lines 11a to 11c of the design D1a, and the four vertical reinforcing lines 12e to 12h are the same as those of the design D1a. The reinforcing lines 12a to 12d are the same. On the resin base material 1 of the semiconductor device substrate 50F, these designs D1a and D2a are arranged substantially continuously in the longitudinal direction of the resin base material 1.

於本實施形態5的變形例1中，如圖7所示，樹脂基材1與所述實施形態5同樣地具有長邊方向與短邊方向。多個半導體裝置10與所述實施形態5同樣地，以於樹脂基材1上的長邊方向上形成列的方式形成。而且，加強線11a～加強線11c及加強線11e～加強線11g以相對於該些多個半導體裝置10的列平行的方式形成，於樹脂基材1的長邊方向上大致連續地設置。即，設計D1a中的加強線11a～加強線11c與設計D2a中的加強線11e～加強線11g除了樹脂基材1上的設計間的間隙部以外，於樹脂基材1的長邊方向上連續地形成。於所述變形例1的半導體裝置用基板50F中，與實施形態5不同，未形成加強線11d及加強線11h。因此，於該些多個半導體裝置10的列的外緣部的其中一者中，加強線並非於樹脂基材1的長邊方向上大致連續地設置。In the modification 1 of the fifth embodiment, as shown in FIG. 7, the resin base material 1 has a longitudinal direction and a short side direction similarly to the above-mentioned fifth embodiment. Similar to the fifth embodiment described above, the plurality of semiconductor devices 10 are formed so as to form rows in the longitudinal direction of the resin substrate 1. In addition, the reinforcing wires 11a to 11c and the reinforcing wires 11e to 11g are formed in parallel to the rows of the plurality of semiconductor devices 10 and are provided substantially continuously in the longitudinal direction of the resin base material 1. That is, the reinforcement line 11a to reinforcement line 11c in design D1a and the reinforcement line 11e to reinforcement line 11g in design D2a are continuous in the longitudinal direction of the resin substrate 1 except for the gap between the designs on the resin substrate 1.地 formed. In the substrate 50F for a semiconductor device of the above-mentioned modification 1, unlike the fifth embodiment, the reinforcing wire 11d and the reinforcing wire 11h are not formed. Therefore, in one of the outer edge portions of the rows of the plurality of semiconductor devices 10, the reinforcing wire is not provided substantially continuously in the longitudinal direction of the resin base material 1.

（實施形態5的變形例2） 圖8是表示本發明的實施形態5的變形例2的半導體裝置用基板的一結構例的示意圖。如圖8所示，所述變形例2的半導體裝置用基板50G於自捲成卷狀的狀態起至捲繞成卷狀的狀態為止連續的樹脂基材1上，包括設計D1b、設計D2b的重複結構來代替所述設計D1、設計D2的重複結構。設計D1b是具有所述9個半導體裝置10、橫向的3條加強線11a、加強線11c、加強線11d、以及縱向的4條加強線12a～加強線12d的結構部。設計D2b是重複與所述設計D1b相同的結構者。即，設計D2b中所含的9個半導體裝置是與所述設計D1b相同的半導體裝置10。另外，設計D2b中所含的橫向的3條加強線11e、加強線11g、加強線11h與所述設計D1b的加強線11a、加強線11c、加強線11d相同，縱向的4條加強線12e～加強線12h與所述設計D1b的加強線12a～加強線12d相同。於半導體裝置用基板50G的樹脂基材1上，該些設計D1b、設計D2b於樹脂基材1的長邊方向上大致連續地排列。(Modification 2 of Embodiment 5) 8 is a schematic diagram showing a configuration example of a semiconductor device substrate according to Modification 2 of Embodiment 5 of the present invention. As shown in FIG. 8, the semiconductor device substrate 50G of the second modification is on a continuous resin base material 1 from a state wound into a roll shape to a state wound into a roll shape, and includes design D1b and design D2b. The repetitive structure replaces the repetitive structure of the design D1 and the design D2. Design D1b is a structure having the nine semiconductor devices 10, three horizontal reinforcing wires 11a, a reinforcing wire 11c, a reinforcing wire 11d, and four vertical reinforcing wires 12a to 12d. The design D2b repeats the same structure as the design D1b. That is, the nine semiconductor devices included in the design D2b are the same semiconductor devices 10 as the design D1b. In addition, the horizontal three reinforcement lines 11e, the reinforcement line 11g, and the reinforcement line 11h included in the design D2b are the same as the reinforcement line 11a, the reinforcement line 11c, and the reinforcement line 11d of the design D1b, and the longitudinal four reinforcement lines 12e~ The reinforcement line 12h is the same as the reinforcement line 12a-the reinforcement line 12d of the said design D1b. On the resin base material 1 of the semiconductor device substrate 50G, the design D1b and the design D2b are arranged substantially continuously in the longitudinal direction of the resin base material 1.

於本實施形態5的變形例2中，如圖8所示，樹脂基材1與所述實施形態5同樣地具有長邊方向與短邊方向。多個半導體裝置10與所述實施形態5同樣地，以於樹脂基材1上的長邊方向上形成列的方式形成。而且，加強線11a、加強線11c、加強線11d及加強線11e、加強線11g、加強線11h以相對於該些多個半導體裝置10的列平行的方式形成，於樹脂基材1的長邊方向上大致連續地設置。即，設計D1b中的加強線11a、加強線11c、加強線11d與設計D2b中的加強線11e、加強線11g、加強線11h除了樹脂基材1上的設計間的間隙部以外，於樹脂基材1的長邊方向上連續地形成。In the second modification of the fifth embodiment, as shown in FIG. 8, the resin base material 1 has a longitudinal direction and a short side direction as in the fifth embodiment. Similar to the fifth embodiment described above, the plurality of semiconductor devices 10 are formed so as to form rows in the longitudinal direction of the resin substrate 1. Furthermore, the reinforcing wires 11a, the reinforcing wires 11c, the reinforcing wires 11d and the reinforcing wires 11e, the reinforcing wires 11g, and the reinforcing wires 11h are formed in parallel with respect to the rows of the plurality of semiconductor devices 10, and are formed on the long sides of the resin substrate 1. It is arranged substantially continuously in the direction. That is, the reinforcement line 11a, the reinforcement line 11c, the reinforcement line 11d in the design D1b and the reinforcement line 11e, the reinforcement line 11g, and the reinforcement line 11h in the design D2b are in the resin base except for the gap between the designs on the resin substrate 1. The material 1 is formed continuously in the longitudinal direction.

於所述變形例2的半導體裝置用基板50G中，與實施形態5同樣地，加強線11a、加強線11d及加強線11e、加強線11h於該些多個半導體裝置10的列的兩個外緣部中，於樹脂基材1的長邊方向上大致連續地設置。即，設計D1b中的加強線11a及加強線11d與設計D2b中的加強線11e及加強線11h除了樹脂基材1上的設計間的間隙部以外，於樹脂基材1的長邊方向上連續地形成。另外，於半導體裝置用基板50G中，與實施形態5不同，未形成加強線11b及加強線11f。因此，於該些多個半導體裝置10的全部列中，加強線並非於樹脂基材1的長邊方向上大致連續地設置。In the semiconductor device substrate 50G of the second modification, similarly to the fifth embodiment, the reinforcing wire 11a, the reinforcing wire 11d, the reinforcing wire 11e, and the reinforcing wire 11h are located outside two of the rows of the plurality of semiconductor devices 10 In the edge part, it is provided substantially continuously in the longitudinal direction of the resin base material 1. That is, the reinforcement line 11a and reinforcement line 11d in design D1b and the reinforcement line 11e and reinforcement line 11h in design D2b are continuous in the longitudinal direction of the resin substrate 1 except for the gap between the designs on the resin substrate 1.地 formed. In addition, in the semiconductor device substrate 50G, unlike the fifth embodiment, the reinforcing wire 11b and the reinforcing wire 11f are not formed. Therefore, in all the rows of the plurality of semiconductor devices 10, the reinforcing wires are not provided substantially continuously in the longitudinal direction of the resin base material 1.

於樹脂基材1上大致連續地形成的加強線的配置並不限於所述配置，如實施形態5或其變形例2般，較佳為於樹脂基材1的長邊方向上延伸存在的所有加強線大致連續地形成，且於多個半導體裝置10的列的兩個外緣部中具有加強線。原因在於：於樹脂基材1被捲成卷狀時，容易減少外部衝擊或溫度、濕度變化所引起的樹脂基材1的卷未對準（進而半導體裝置用基板的卷未對準）。另外，所述效果於多個半導體裝置10的列的兩個外緣部及各列之間全部形成加強線的情況下進一步提高，因此尤佳為以所述方式形成加強線。The arrangement of the reinforcing lines formed substantially continuously on the resin substrate 1 is not limited to the above-mentioned arrangement. As in Embodiment 5 or its modification 2, it is preferable to extend all the lines extending in the longitudinal direction of the resin substrate 1. The reinforcement lines are formed substantially continuously, and there are reinforcement lines in the two outer edge portions of the rows of the plurality of semiconductor devices 10. The reason is that when the resin base material 1 is rolled into a roll shape, it is easy to reduce the roll misalignment of the resin base material 1 (and the roll misalignment of the substrate for semiconductor device) caused by external impact or temperature and humidity changes. In addition, the above-mentioned effect is further improved in the case where the two outer edge portions of the rows of the plurality of semiconductor devices 10 and the reinforcing lines are formed between all the rows, and therefore, it is particularly preferable to form the reinforcing lines in the manner described above.

＜半導體裝置＞ 其次，關於可較佳地用於所述本發明的各實施形態的半導體裝置，以將實施形態1的半導體裝置用基板50的一部分作為代表例的內容為中心進行詳細說明。如上所述，本發明的半導體裝置用基板中使用多個半導體裝置（例如圖1所示的半導體裝置10）。例如，該些多個半導體裝置各自為場效型電晶體（FET）、包括FET的各種電子設備的IC、顯示器用薄膜電晶體（Thin Film Transistor，TFT）陣列、TFT存儲器、感測器、RFID標簽等無線通訊裝置。於本發明中，所述半導體裝置並不限制於該些具體例。＜Semiconductor device＞ Next, regarding semiconductor devices that can be suitably used in each embodiment of the present invention described above, a part of the semiconductor device substrate 50 of the first embodiment will be described in detail as a representative example. As described above, a plurality of semiconductor devices (for example, the semiconductor device 10 shown in FIG. 1) is used in the substrate for a semiconductor device of the present invention. For example, each of the plurality of semiconductor devices is a field-effect transistor (FET), IC of various electronic devices including FET, thin film transistor (TFT) array for display, TFT memory, sensor, RFID Wireless communication devices such as tags. In the present invention, the semiconductor device is not limited to these specific examples.

圖9是摘選本發明的實施形態1的半導體裝置用基板的一部分而表示的立體圖。圖10是圖9所示的半導體裝置用基板於I-I'線上的示意剖面圖。於圖9、圖10中，例示實施形態1的半導體裝置用基板50的半導體裝置10（參照圖1）為FET 20的情況，對應用於本發明的半導體裝置用基板的多個半導體裝置進行說明。雖未特別圖示，但FET 20的結構於半導體裝置10為包括FET 20的裝置的情況下亦相同。Fig. 9 is a perspective view showing an excerpt of a part of the semiconductor device substrate according to the first embodiment of the present invention. Fig. 10 is a schematic cross-sectional view of the semiconductor device substrate shown in Fig. 9 on line II'. In FIGS. 9 and 10, a case where the semiconductor device 10 (see FIG. 1) of the semiconductor device substrate 50 of the first embodiment is an FET 20 will be described corresponding to a plurality of semiconductor devices used in the semiconductor device substrate of the present invention. . Although not shown in particular, the structure of the FET 20 is also the same when the semiconductor device 10 is a device including the FET 20.

如圖9、圖10所示，FET 20具有形成於樹脂基材1上的閘極電極2、覆蓋閘極電極2的閘極絕緣層3、設置於閘極絕緣層3上的源極電極5及汲極電極6、以及設置於該些電極之間的半導體層4。另外，如圖9、圖10所示，半導體裝置用基板50於樹脂基材1上具有多個加強線11、加強線12。加強線11是所述實施形態1中的橫向的加強線11a～加強線11d的總稱。加強線12是所述實施形態1中的縱向的加強線12a～加強線12d的總稱。As shown in FIGS. 9 and 10, the FET 20 has a gate electrode 2 formed on the resin substrate 1, a gate insulating layer 3 covering the gate electrode 2, and a source electrode 5 provided on the gate insulating layer 3. And the drain electrode 6, and the semiconductor layer 4 disposed between the electrodes. In addition, as shown in FIGS. 9 and 10, the substrate 50 for a semiconductor device has a plurality of reinforcing wires 11 and 12 on the resin base material 1. The reinforcement line 11 is a general term for the lateral reinforcement line 11a to the reinforcement line 11d in the first embodiment. The reinforcing wire 12 is a general term for the longitudinal reinforcing wire 12a to the reinforcing wire 12d in the first embodiment.

如圖10例示般，FET 20的結構為閘極電極2配置於半導體層4的下側的所謂的底部閘極結構。於FET 20的結構為底部閘極結構的情況下，可使樹脂基材1的材質所引起的FET 20的特性變化難以發生。As illustrated in FIG. 10, the structure of the FET 20 is a so-called bottom gate structure in which the gate electrode 2 is arranged on the lower side of the semiconductor layer 4. In the case where the structure of the FET 20 is a bottom gate structure, the change in the characteristics of the FET 20 caused by the material of the resin substrate 1 can be made difficult to occur.

另外，FET 20的結構並不限定於圖10所例示的形態的底部閘極結構。圖11是表示圖10所示的半導體裝置用基板的第一變形例的示意剖面圖。如圖11例示般，FET 20的結構亦可為形成有於多個FET 20中共用的閘極絕緣層3的底部閘極結構。於所述情況下，如圖11所示，加強線12可由閘極絕緣層3覆蓋。於圖11中雖未特別圖示，但與所述加強線12同樣地，加強線11亦可由閘極絕緣層3覆蓋。In addition, the structure of the FET 20 is not limited to the bottom gate structure of the form illustrated in FIG. 10. FIG. 11 is a schematic cross-sectional view showing a first modification of the semiconductor device substrate shown in FIG. 10. As illustrated in FIG. 11, the structure of the FET 20 may also be a bottom gate structure formed with a gate insulating layer 3 shared by a plurality of FETs 20. In this case, as shown in FIG. 11, the reinforcing wire 12 may be covered by the gate insulating layer 3. Although not particularly shown in FIG. 11, the reinforcing wire 11 may be covered by the gate insulating layer 3 like the reinforcing wire 12 described above.

加強線11、加強線12由與構成多個半導體裝置（例如FET 20）中所含的電極層中的至少一者的材料相同的材料構成。於圖9、圖10中，加強線11、加強線12與閘極電極2由相同的材料形成於同一層中。圖12是表示圖10所示的半導體裝置用基板的第二變形例的示意剖面圖。加強線11、加強線12亦可由與源極電極5及汲極電極6相同的材料形成於與該些的電極相同的層。於所述情況下，如圖12例示般，FET 20的結構亦可為形成有於多個FET 20中共用的閘極絕緣層3的底部閘極結構。於該些FET 20的底部閘極結構中，加強線11、加強線12與源極電極5及汲極電極6形成於閘極絕緣層3上。The reinforcing wire 11 and the reinforcing wire 12 are made of the same material as the material constituting at least one of the electrode layers included in the plurality of semiconductor devices (for example, the FET 20). In FIG. 9 and FIG. 10, the reinforcing wire 11, the reinforcing wire 12 and the gate electrode 2 are formed of the same material in the same layer. FIG. 12 is a schematic cross-sectional view showing a second modification of the semiconductor device substrate shown in FIG. 10. The reinforcing wire 11 and the reinforcing wire 12 may also be formed of the same material as the source electrode 5 and the drain electrode 6 in the same layer as these electrodes. In this case, as illustrated in FIG. 12, the structure of the FET 20 may also be a bottom gate structure formed with a gate insulating layer 3 shared by a plurality of FETs 20. In the bottom gate structure of the FET 20, the reinforcing wire 11, the reinforcing wire 12, the source electrode 5 and the drain electrode 6 are formed on the gate insulating layer 3.

加強線11、加強線12與閘極電極2形成於同一層、或者加強線11、加強線12與源極電極5及汲極電極6形成於同一層可藉由利用掃描式電子顯微鏡（Scanning Electron Microscope，SEM）或穿透式電子顯微鏡（Transmission Electron Microscope，TEM）等觀察半導體裝置用基板50的剖面來確認。The reinforcing wire 11, the reinforcing wire 12 and the gate electrode 2 are formed on the same layer, or the reinforcing wire 11, the reinforcing wire 12 and the source electrode 5 and the drain electrode 6 are formed on the same layer. Microscope, SEM), transmission electron microscope (Transmission Electron Microscope, TEM), etc., observe and confirm the cross section of the semiconductor device substrate 50.

另外，如圖10例示般，FET 20的結構是於半導體層4的上表面配置有源極電極5及汲極電極6的所謂的頂部接觸結構。但是，可應用於FET 20的結構並不限於此，亦可為底部接觸結構。In addition, as illustrated in FIG. 10, the structure of the FET 20 is a so-called top contact structure in which a source electrode 5 and a drain electrode 6 are arranged on the upper surface of the semiconductor layer 4. However, the structure applicable to the FET 20 is not limited to this, and may also be a bottom contact structure.

另外，圖10、圖11所例示的FET 20的結構是閘極電極2配置於半導體層4的下側（樹脂基材1側）的所謂的底部閘極結構，但並不限於此。例如，FET 20的結構亦可為閘極電極2配置於半導體層4的上側（與樹脂基材1為相反的一側）的所謂的頂部閘極結構。雖未特別圖示，但於FET 20的結構為頂部閘極結構的情況下，加強線11、加強線12較佳為由與位於半導體層4的下側的源極電極5及汲極電極6相同的材料，設置於與該些源極電極5及汲極電極6相同的層。In addition, the structure of the FET 20 illustrated in FIGS. 10 and 11 is a so-called bottom gate structure in which the gate electrode 2 is arranged on the lower side of the semiconductor layer 4 (the resin substrate 1 side), but it is not limited to this. For example, the structure of the FET 20 may also be a so-called top gate structure in which the gate electrode 2 is arranged on the upper side of the semiconductor layer 4 (the side opposite to the resin substrate 1 ). Although not shown in particular, when the structure of the FET 20 is a top gate structure, the reinforcing wire 11 and the reinforcing wire 12 are preferably connected to the source electrode 5 and the drain electrode 6 located on the lower side of the semiconductor layer 4. The same material is arranged on the same layer as the source electrode 5 and the drain electrode 6.

根據以上，無論FET 20的結構為底部閘極結構或者為頂部閘極結構，加強線11、加強線12由與FET 20中所含的源極電極5、汲極電極6及閘極電極2中位於靠近樹脂基材1的一側（例如半導體層4的下部側）的電極（即基材側的電極）相同的材料設置於與所述基材側的電極相同的層的情況容易抑制樹脂基材1的變形。於FET 20的結構為底部閘極結構的情況下，所述基材側的電極為閘極電極2（參照圖10、圖11）。於FET 20的結構為頂部閘極結構的情況下，所述基材側的電極為源極電極5及汲極電極6。According to the above, whether the structure of the FET 20 is a bottom gate structure or a top gate structure, the reinforcing wire 11 and the reinforcing wire 12 are composed of the source electrode 5, the drain electrode 6 and the gate electrode 2 contained in the FET 20. When the electrode (ie, the electrode on the substrate side) located on the side close to the resin substrate 1 (for example, the lower side of the semiconductor layer 4) is provided with the same material on the same layer as the electrode on the substrate side, it is easy to suppress the resin matrix. Deformation of material 1. When the structure of the FET 20 is a bottom gate structure, the electrode on the substrate side is the gate electrode 2 (refer to FIGS. 10 and 11 ). When the structure of the FET 20 is a top gate structure, the electrodes on the substrate side are the source electrode 5 and the drain electrode 6.

其中，FET 20的結構為底部閘極結構的情況與FET 20的結構為頂部閘極結構的情況相比，可使樹脂基材1的材質所引起的FET 20的特性變化難以發生。Among them, when the structure of the FET 20 is a bottom gate structure, compared with a case where the structure of the FET 20 is a top gate structure, the change in the characteristics of the FET 20 due to the material of the resin substrate 1 can be made less likely to occur.

（實施形態6） 圖13是表示本發明的實施形態6的半導體裝置用基板的一結構例的示意圖。圖13表示摘選本發明的實施形態6的半導體裝置用基板50H的一部分而表示的立體圖。圖14是圖13所示的半導體裝置用基板於II-II'線上的示意剖面圖。於本發明的實施形態6中，例示半導體裝置用基板50H包括多個FET 20及FET 30作為所述多個半導體裝置10的情況，對本發明的半導體裝置用基板及應用於其的多個半導體裝置的結構進行說明。(Embodiment 6) FIG. 13 is a schematic diagram showing a configuration example of a semiconductor device substrate according to Embodiment 6 of the present invention. FIG. 13 is a perspective view showing an excerpt of a part of the semiconductor device substrate 50H according to the sixth embodiment of the present invention. Fig. 14 is a schematic cross-sectional view of the semiconductor device substrate shown in Fig. 13 on line II-II'. In the sixth embodiment of the present invention, a case where the semiconductor device substrate 50H includes a plurality of FETs 20 and FETs 30 as the plurality of semiconductor devices 10 is illustrated. The semiconductor device substrate of the present invention and the plurality of semiconductor devices applied thereto The structure is explained.

如圖13所示，半導體裝置用基板50H具有樹脂基材1，於所述樹脂基材1上具有多個FET 20、FET 30、多個加強線11、加強線12、以及多個第二加強線41、第二加強線42。多個FET 20、FET 30中，FET 20及FET 30的一組構成所述半導體裝置10。加強線11、加強線12於樹脂基材1上形成多個按照每一組包圍該些多個FET 20、FET 30的區域。第二加強線41、第二加強線42分別沿著加強線11、加強線12設置於樹脂基材1上。例如，第二加強線41以重疊於橫向（樹脂基材1的長邊方向）的加強線11上的方式形成。第二加強線42以重疊於縱向（樹脂基材1的短邊方向）的加強線12上的方式形成。As shown in FIG. 13, the semiconductor device substrate 50H has a resin base material 1 on which there are a plurality of FETs 20, FETs 30, a plurality of reinforcing wires 11, a plurality of reinforcing wires 12, and a plurality of second reinforcing members. Line 41, the second reinforcement line 42. Among the plurality of FET 20 and FET 30, a set of FET 20 and FET 30 constitutes the semiconductor device 10. The reinforcing wire 11 and the reinforcing wire 12 are formed on the resin substrate 1 to form a plurality of regions surrounding the plurality of FETs 20 and 30 according to each group. The second reinforcement line 41 and the second reinforcement line 42 are respectively arranged on the resin substrate 1 along the reinforcement line 11 and the reinforcement line 12. For example, the second reinforcement line 41 is formed so as to overlap the reinforcement line 11 in the lateral direction (the longitudinal direction of the resin base material 1). The second reinforcement line 42 is formed so as to overlap the reinforcement line 12 in the longitudinal direction (the short-side direction of the resin base material 1 ).

另外，如圖13、圖14所示，FET 20及FET 30具有形成於樹脂基材1上的閘極電極2、覆蓋閘極電極2的閘極絕緣層3、設置於閘極絕緣層3上的源極電極5及汲極電極6、以及設置於該些電極之間的半導體層4。FET 30進而具有在與閘極絕緣層3相反的一側與半導體層4接觸的第二絕緣層7。藉由於半導體層4上形成此種第二絕緣層7，例如通常可將顯示出p型半導體特性的碳奈米管（Carbon nanotube，CNT）-FET轉換為顯示出n型半導體特性的半導體元件。所述「CNT-FET」是包括由碳奈米管（以下，稱為CNT）形成的半導體層的FET。例如，於本實施形態6中，FET 20及FET 30各自為CNT-FET，該些FET 20及FET 30的各半導體層4含有CNT。In addition, as shown in FIGS. 13 and 14, the FET 20 and the FET 30 have a gate electrode 2 formed on the resin substrate 1, a gate insulating layer 3 covering the gate electrode 2, and a gate insulating layer 3 provided on the The source electrode 5 and the drain electrode 6, and the semiconductor layer 4 disposed between these electrodes. The FET 30 further has a second insulating layer 7 in contact with the semiconductor layer 4 on the side opposite to the gate insulating layer 3. By forming such a second insulating layer 7 on the semiconductor layer 4, for example, a carbon nanotube (CNT)-FET exhibiting p-type semiconductor characteristics can be generally converted into a semiconductor device exhibiting n-type semiconductor characteristics. The “CNT-FET” is an FET including a semiconductor layer formed of carbon nanotubes (hereinafter referred to as CNT). For example, in the sixth embodiment, each of the FET 20 and the FET 30 is a CNT-FET, and each semiconductor layer 4 of the FET 20 and the FET 30 contains CNT.

如圖14例示般，FET 20、FET 30的結構為閘極電極2配置於半導體層4的下側的所謂的底部閘極結構。於FET 20、FET 30的結構為底部閘極結構的情況下，可使樹脂基材1的材質所引起的FET 20、FET 30的特性變化難以發生。As illustrated in FIG. 14, the structure of the FET 20 and the FET 30 is a so-called bottom gate structure in which the gate electrode 2 is arranged on the lower side of the semiconductor layer 4. When the structure of the FET 20 and the FET 30 is a bottom gate structure, the change in the characteristics of the FET 20 and the FET 30 due to the material of the resin substrate 1 can be made difficult to occur.

另外，FET 20、FET 30的結構並不限定於圖14所例示的形態的底部閘極結構。圖15是表示圖13所示的半導體裝置用基板的第一變形例的示意剖面圖。如圖15例示般，FET 20、FET 30的結構亦可為形成有多個FET 20、FET 30彼此連續的閘極絕緣層3的底部閘極結構。於所述情況下，如圖15所示，加強線12可由閘極絕緣層3覆蓋。於圖15中雖未特別圖示，但與所述加強線12同樣地，加強線11亦可由閘極絕緣層3覆蓋。In addition, the structure of the FET 20 and the FET 30 is not limited to the bottom gate structure of the form illustrated in FIG. 14. 15 is a schematic cross-sectional view showing a first modification example of the semiconductor device substrate shown in FIG. 13. As illustrated in FIG. 15, the structure of the FET 20 and the FET 30 may also be a bottom gate structure in which a plurality of FET 20 and the FET 30 are formed with a continuous gate insulating layer 3. In this case, as shown in FIG. 15, the reinforcing wire 12 may be covered by the gate insulating layer 3. Although not particularly shown in FIG. 15, the reinforcing wire 11 may be covered by the gate insulating layer 3 in the same way as the reinforcing wire 12.

加強線11、加強線12由與構成多個半導體裝置（例如FET 20、FET 30）中所含的電極層中的至少一者的材料相同的材料構成。於圖13、圖14中，加強線11、加強線12與閘極電極2由相同的材料形成於同一層中。圖16是表示圖13所示的半導體裝置用基板的第二變形例的示意剖面圖。加強線11、加強線12亦可由與源極電極5及汲極電極6相同的材料形成於與該些的電極相同的層。於所述情況下，如圖16例示般，FET 20及FET 30的結構亦可為形成有於多個FET 20及FET 30中共用的閘極絕緣層3的底部閘極結構。於該些FET 20及FET 30的底部閘極結構中，加強線11、加強線12與源極電極5及汲極電極6形成於閘極絕緣層3上。The reinforcing wire 11 and the reinforcing wire 12 are made of the same material as the material constituting at least one of the electrode layers included in the plurality of semiconductor devices (for example, the FET 20 and the FET 30). In FIG. 13 and FIG. 14, the reinforcing wire 11, the reinforcing wire 12 and the gate electrode 2 are formed of the same material in the same layer. FIG. 16 is a schematic cross-sectional view showing a second modification of the semiconductor device substrate shown in FIG. 13. The reinforcing wire 11 and the reinforcing wire 12 may also be formed of the same material as the source electrode 5 and the drain electrode 6 in the same layer as these electrodes. In this case, as illustrated in FIG. 16, the structure of the FET 20 and the FET 30 may also be a bottom gate structure formed with a gate insulating layer 3 shared by a plurality of FETs 20 and 30. In the bottom gate structure of the FET 20 and the FET 30, the reinforcing wire 11, the reinforcing wire 12, the source electrode 5 and the drain electrode 6 are formed on the gate insulating layer 3.

另外，第二加強線41、第二加強線42較佳為與所述FET 20、FET 30的底部閘極結構的種類無關而由與第二絕緣層7相同的材料構成。藉此，可抑制由於局部形成的第二絕緣層7而產生的樹脂基材1的刮削。In addition, the second reinforcing wire 41 and the second reinforcing wire 42 are preferably made of the same material as the second insulating layer 7 regardless of the type of the bottom gate structure of the FET 20 and the FET 30. Thereby, the scraping of the resin base material 1 due to the partially formed second insulating layer 7 can be suppressed.

於圖13、圖14所示的例子中，第二加強線41及第二加強線42分別以與加強線11及加強線12重疊的方式形成，可以僅與該些加強線11、加強線12的一部分重疊的方式形成，亦可以與該些加強線11、加強線12不重疊的方式形成。另外，於圖13所示的例子中，第二加強線41及第二加強線42以彼此連續的方式形成，亦可分別斷續地形成。In the example shown in FIGS. 13 and 14, the second reinforcement line 41 and the second reinforcement line 42 are formed in a manner overlapping with the reinforcement line 11 and the reinforcement line 12, respectively, and may only overlap with the reinforcement line 11 and the reinforcement line 12. It is formed in a way that a part of it overlaps, and it can also be formed in a way that it does not overlap with the reinforcing lines 11 and 12. In addition, in the example shown in FIG. 13, the second reinforcement line 41 and the second reinforcement line 42 are formed in a continuous manner with each other, or they may be formed intermittently.

另外，如圖15例示般，閘極絕緣層3亦可形成為於多個FET 20及多個FET 30中共用的結構。於所述情況下，加強線11、加強線12可被閘極絕緣層3覆蓋，亦可於閘極絕緣層3上形成第二加強線41、第二加強線42。In addition, as illustrated in FIG. 15, the gate insulating layer 3 may also be formed as a structure shared by a plurality of FETs 20 and a plurality of FETs 30. In this case, the reinforcing wire 11 and the reinforcing wire 12 may be covered by the gate insulating layer 3, and the second reinforcing wire 41 and the second reinforcing wire 42 may also be formed on the gate insulating layer 3.

加強線11、加強線12與閘極電極2形成於同一層、或者加強線11、加強線12與源極電極5及汲極電極6形成於同一層可藉由利用掃描式電子顯微鏡（SEM）或穿透式電子顯微鏡（TEM）等觀察半導體裝置用基板50H的剖面來確認。The reinforcement line 11, the reinforcement line 12 and the gate electrode 2 are formed on the same layer, or the reinforcement line 11, the reinforcement line 12 and the source electrode 5 and the drain electrode 6 are formed on the same layer. The scanning electron microscope (SEM) can be used Or it can be confirmed by observing the cross section of the semiconductor device substrate 50H with a transmission electron microscope (TEM) or the like.

另外，如圖14例示般，FET 20及FET 30的結構是於半導體層4的上表面配置有源極電極5及汲極電極6的所謂的頂部接觸結構。但是，可應用於FET 20及FET 30的結構並不限於此，亦可為底部接觸結構。In addition, as illustrated in FIG. 14, the structure of the FET 20 and the FET 30 is a so-called top contact structure in which the source electrode 5 and the drain electrode 6 are arranged on the upper surface of the semiconductor layer 4. However, the structure applicable to the FET 20 and the FET 30 is not limited to this, and may also be a bottom contact structure.

（閘極電極） 閘極電極2只要為包含可用作電極的導電性材料者，則可為任意者。作為閘極電極2的導電性材料，例如可列舉：氧化錫、氧化銦、氧化錫銦（Indium Tin Oxide，ITO）等導電性金屬氧化物。另外，作為閘極電極2的導電性材料，可列舉鉑、金、銀、銅、鐵、錫、鋅、鋁、銦、鉻、鋰、鈉、鉀、銫、鈣、鎂、鈀、鉬、非晶矽或多晶矽等金屬或自該些中選擇的多個金屬的合金、碘化銅、硫化銅等無機導電性物質。另外，作為閘極電極2的導電性材料，可列舉藉由聚噻吩、聚吡咯、聚苯胺、聚乙烯二氧噻吩與聚苯乙烯磺酸的錯合物、藉由碘等的摻雜而提高了導電率的導電性聚合物。進而，作為閘極電極2的導電性材料，可列舉碳材料、含有有機成分與導電體的材料等。(Gate electrode) The gate electrode 2 may be anything as long as it contains a conductive material that can be used as an electrode. Examples of the conductive material of the gate electrode 2 include conductive metal oxides such as tin oxide, indium oxide, and indium tin oxide (ITO). In addition, as the conductive material of the gate electrode 2, platinum, gold, silver, copper, iron, tin, zinc, aluminum, indium, chromium, lithium, sodium, potassium, cesium, calcium, magnesium, palladium, molybdenum, Metals such as amorphous silicon or polycrystalline silicon, alloys of a plurality of metals selected from these, and inorganic conductive materials such as copper iodide and copper sulfide. In addition, as the conductive material of the gate electrode 2, there can be mentioned polythiophene, polypyrrole, polyaniline, a complex of polyethylene dioxythiophene and polystyrene sulfonic acid, and the increase by doping with iodine or the like. The conductivity of the conductive polymer. Furthermore, examples of the conductive material of the gate electrode 2 include carbon materials, materials containing organic components and conductors, and the like.

於使用含有所述有機成分與導電體的材料作為閘極電極2的材料的情況下，閘極電極2的柔軟性增加，彎曲時閘極電極2的密接性亦良好，閘極電極2的電連接變得良好。作為此種材料中所含的有機成分，並無特別限制，可列舉單體、寡聚物或聚合物、光聚合起始劑、塑化劑、調平劑、界面活性劑、矽烷偶合劑、消泡劑、顏料等。該些中，就閘極電極2的耐彎折性提高的觀點而言，較佳為寡聚物或聚合物。但是，閘極電極2及配線的導電性材料並不限定於該些。該些導電性材料可單獨使用，亦可將多個材料積層或混合而使用。When a material containing the organic component and a conductor is used as the material of the gate electrode 2, the flexibility of the gate electrode 2 is increased, and the adhesion of the gate electrode 2 when bent is also good, and the electrical conductivity of the gate electrode 2 The connection becomes good. The organic components contained in such materials are not particularly limited, and examples include monomers, oligomers or polymers, photopolymerization initiators, plasticizers, leveling agents, surfactants, silane coupling agents, Defoamers, pigments, etc. Among these, from the viewpoint of improving the bending resistance of the gate electrode 2, an oligomer or a polymer is preferable. However, the conductive material of the gate electrode 2 and the wiring is not limited to these. These conductive materials may be used alone, or multiple materials may be laminated or mixed for use.

另外，閘極電極2的寬度、厚度及各閘極電極間的間隔為任意。具體而言，閘極電極2的寬度較佳為5 μm以上且1 mm以下。藉由將閘極電極2的寬度設為所述範圍內，容易進行基於閘極電極2與源極電極5及汲極電極6的交疊控制或通道長度控制的FET特性控制。於FET（例如所述FET 20、FET 30）為底部閘極結構的情況下，閘極電極2的厚度與加強線11、加強線12為相同厚度，較佳為30 nm以上且500 nm以下。加強線11、加強線12的厚度與閘極電極2的厚度相同可藉由利用掃描式電子顯微鏡（SEM）或穿透式電子顯微鏡（TEM）等觀察半導體裝置用基板的剖面來確認。In addition, the width and thickness of the gate electrode 2 and the interval between the gate electrodes are arbitrary. Specifically, the width of the gate electrode 2 is preferably 5 μm or more and 1 mm or less. By setting the width of the gate electrode 2 within the above range, it is easy to perform FET characteristic control based on the overlap control of the gate electrode 2 and the source electrode 5 and the drain electrode 6 or the channel length control. When the FET (for example, the FET 20 and the FET 30) has a bottom gate structure, the thickness of the gate electrode 2 is the same as the thickness of the reinforcing wire 11 and the reinforcing wire 12, preferably 30 nm or more and 500 nm or less. The thickness of the reinforcing wire 11 and the reinforcing wire 12 and the thickness of the gate electrode 2 can be confirmed by observing the cross section of the semiconductor device substrate with a scanning electron microscope (SEM) or a transmission electron microscope (TEM).

（閘極絕緣層） 作為閘極絕緣層3中使用的材料，並無特別限定，可列舉氧化矽、氧化鋁等無機材料；聚醯亞胺、聚乙烯醇、聚氯乙烯、聚對苯二甲酸乙二酯、聚偏二氟乙烯、聚矽氧烷、聚乙烯基苯酚等有機高分子材料；或無機材料粉末與有機材料的混合物。其中，閘極絕緣層3的材料較佳為包含具有矽原子與碳原子的鍵的有機化合物。另外，除此以外，閘極絕緣層3的材料進而佳為包含具有金屬原子與氧原子的鍵的金屬化合物。(Gate insulation layer) The material used in the gate insulating layer 3 is not particularly limited. Examples include inorganic materials such as silica and alumina; polyimide, polyvinyl alcohol, polyvinyl chloride, polyethylene terephthalate, and poly(ethylene terephthalate). Organic polymer materials such as vinylidene fluoride, polysiloxane, polyvinyl phenol; or a mixture of inorganic material powder and organic material. Among them, the material of the gate insulating layer 3 preferably includes an organic compound having a bond between silicon atoms and carbon atoms. In addition, the material of the gate insulating layer 3 further preferably contains a metal compound having a bond between a metal atom and an oxygen atom.

閘極絕緣層3可為單層亦可為多層。另外，閘極絕緣層3可為由多種絕緣性材料形成一層者，亦可為將多種絕緣性材料積層而形成多個絕緣層者。The gate insulating layer 3 can be a single layer or multiple layers. In addition, the gate insulating layer 3 may be a layer made of a plurality of insulating materials, or a plurality of insulating materials may be laminated to form a plurality of insulating layers.

（源極電極及汲極電極） 源極電極5及汲極電極6（以下，適宜簡稱為源極/汲極電極）只要為包含可用作電極的導電材料者，則可為任意者。作為源極/汲極電極的導電性材料，例如可列舉：氧化錫、氧化銦、氧化錫銦（ITO）等導電性金屬氧化物。另外，作為源極/汲極電極的導電性材料，可列舉鉑、金、銀、銅、鐵、錫、鋅、鋁、銦、鉻、鋰、鈉、鉀、銫、鈣、鎂、鈀、鉬、非晶矽或多晶矽等金屬或自該些中選擇的多個金屬的合金、碘化銅、硫化銅等無機導電性物質。另外，作為源極/汲極電極的導電性材料，可列舉藉由聚噻吩、聚吡咯、聚苯胺、聚乙烯二氧噻吩與聚苯乙烯磺酸的錯合物、藉由碘等的摻雜而提高了導電率的導電性聚合物。進而，作為源極/汲極電極的導電性材料，可列舉碳材料、含有有機成分與導電體的材料等。(Source electrode and drain electrode) The source electrode 5 and the drain electrode 6 (hereinafter, referred to as source/drain electrode as appropriate) may be any as long as they contain a conductive material that can be used as an electrode. Examples of the conductive material of the source/drain electrode include conductive metal oxides such as tin oxide, indium oxide, and indium tin oxide (ITO). In addition, as the conductive material of the source/drain electrode, platinum, gold, silver, copper, iron, tin, zinc, aluminum, indium, chromium, lithium, sodium, potassium, cesium, calcium, magnesium, palladium, Metals such as molybdenum, amorphous silicon, or polycrystalline silicon, or alloys of a plurality of metals selected from these, and inorganic conductive materials such as copper iodide and copper sulfide. In addition, as the conductive material of the source/drain electrode, for example, polythiophene, polypyrrole, polyaniline, a complex of polyethylene dioxythiophene and polystyrene sulfonic acid, doping with iodine, etc. The conductive polymer with improved conductivity. Furthermore, as the conductive material of the source/drain electrode, a carbon material, a material containing an organic component and a conductor, and the like can be cited.

於使用含有所述有機成分與導電體的材料作為源極/汲極電極的導電性材料的情況下，源極/汲極電極的柔軟性增加，彎曲時源極/汲極電極的密接性亦良好，源極/汲極電極的電連接變得良好。作為此種材料中所含的有機成分，並無特別限制，可列舉單體、寡聚物或聚合物、光聚合起始劑、塑化劑、調平劑、界面活性劑、矽烷偶合劑、消泡劑、顏料等。該些中，就源極/汲極電極的耐彎折性提高的觀點而言，較佳為寡聚物或聚合物。但是，源極/汲極電極及配線的導電性材料並不限定於該些。該些導電性材料可單獨使用，亦可將多個材料積層或混合而使用。In the case of using a material containing the organic component and a conductor as the conductive material of the source/drain electrode, the flexibility of the source/drain electrode increases, and the adhesion of the source/drain electrode when bent is also Good, the electrical connection of the source/drain electrodes becomes good. The organic components contained in such materials are not particularly limited, and examples include monomers, oligomers or polymers, photopolymerization initiators, plasticizers, leveling agents, surfactants, silane coupling agents, Defoamers, pigments, etc. Among these, from the viewpoint of improving the bending resistance of the source/drain electrode, an oligomer or a polymer is preferable. However, the conductive materials of the source/drain electrodes and wiring are not limited to these. These conductive materials may be used alone, or multiple materials may be laminated or mixed for use.

源極電極5與汲極電極6的間隔較佳為1 μm以上且500 μm以下。進而，與源極/汲極電極連接的配線的寬度及厚度亦為任意。具體而言，所述配線的厚度較佳為0.01 μm以上且100 μm以下。所述配線的寬度較佳為5 μm以上且500 μm以下。但是，該些尺寸並不限於所述尺寸。The distance between the source electrode 5 and the drain electrode 6 is preferably 1 μm or more and 500 μm or less. Furthermore, the width and thickness of the wiring connected to the source/drain electrodes are also arbitrary. Specifically, the thickness of the wiring is preferably 0.01 μm or more and 100 μm or less. The width of the wiring is preferably 5 μm or more and 500 μm or less. However, these dimensions are not limited to the above-mentioned dimensions.

（半導體層） 作為半導體層4中使用的材料，若為顯示出半導體性的材料，則並無特別限定，可較佳地使用載子遷移率高的材料。另外，作為半導體層4的材料，較佳為可應用低成本且簡便的塗佈製程的材料，可列舉有機半導體或碳材料作為較佳例。(Semiconductor layer) The material used in the semiconductor layer 4 is not particularly limited as long as it is a material exhibiting semiconductivity, and a material with high carrier mobility can be preferably used. In addition, the material of the semiconductor layer 4 is preferably a material that can be applied with a low-cost and simple coating process, and an organic semiconductor or a carbon material can be cited as a preferable example.

作為半導體層4中使用的有機半導體，可利用稠五苯、聚噻吩類、於主鏈中包含噻吩單元的化合物、聚吡咯類、聚(對苯乙炔)類、聚苯胺類、聚乙炔（polyacetylene）類、聚丁二炔（polydiacetylene）類、聚咔唑類、聚呋喃類、將含氮芳香環作為結構單元的聚雜芳基類、縮合多環芳香族化合物、雜芳香族化合物、芳香族胺衍生物、雙咔唑衍生物、吡唑啉衍生物、二苯乙烯系化合物、腙系化合物、銅酞菁等金屬酞菁類、銅卟啉等金屬卟啉類、二苯乙烯基苯衍生物、胺基苯乙烯基衍生物、芳香族乙炔衍生物、縮合環四羧酸二醯亞胺類、有機色素等公知者。所述有機半導體可含有該些的兩種以上。As the organic semiconductor used in the semiconductor layer 4, fused pentacene, polythiophenes, compounds containing thiophene units in the main chain, polypyrroles, poly(p-phenylene acetylene), polyanilines, polyacetylene (polyacetylene) can be used as organic semiconductors. ) Class, polydiacetylene class, polycarbazole class, polyfuran class, polyheteroaryl group with nitrogen-containing aromatic ring as the structural unit, condensed polycyclic aromatic compound, heteroaromatic compound, aromatic Amine derivatives, biscarbazole derivatives, pyrazoline derivatives, stilbene-based compounds, hydrazone-based compounds, metal phthalocyanines such as copper phthalocyanine, metal porphyrins such as copper porphyrin, and stilbene benzene derivative Known substances, amino styryl derivatives, aromatic acetylene derivatives, condensed cyclic tetracarboxylic diamides, organic dyes, and the like. The organic semiconductor may contain two or more of these.

作為半導體層4中使用的碳材料，可列舉碳奈米管（CNT）、石墨烯、富勒烯等。其中，於應用輥對輥方式作為樹脂基材1的搬運方式的情況下，就可形成200℃以下的低溫的方面、對塗佈製程的適應性高的方面而言，作為所述碳材料，較佳為CNT。進而，與有機半導體不同而不需要結晶化且藉由CNT彼此的網路結構可達成高遷移率，因此即使片基材因熱或張力等外部原因而伸縮亦容易維持高遷移率，就該方面而言，作為所述碳材料，亦較佳為CNT。Examples of the carbon material used in the semiconductor layer 4 include carbon nanotubes (CNT), graphene, fullerene, and the like. Among them, when the roll-to-roll method is applied as the conveying method of the resin substrate 1, in terms of being able to form a low temperature of 200°C or less and having high adaptability to the coating process, as the carbon material, Preferably it is CNT. Furthermore, unlike organic semiconductors, crystallization is not required, and high mobility can be achieved by the network structure of CNTs. Therefore, even if the sheet substrate expands and contracts due to external factors such as heat or tension, it is easy to maintain high mobility. In terms of the carbon material, CNT is also preferred.

作為CNT，可使用將一片碳膜（石墨烯片（graphene·sheet））捲成圓筒狀的單層CNT、將兩片石墨烯片捲成同心圓狀的兩層CNT、將多片石墨烯片捲成同心圓狀的多層CNT的任一種，亦可使用該些中的兩種以上。其中，就顯示出半導體的特性的觀點而言，較佳為使用單層CNT，尤其是所述單層CNT更佳為包含90重量%以上的半導體型單層CNT。進而佳為單層CNT包含95重量%以上的半導體型單層CNT。As the CNT, a single-layer CNT in which a sheet of carbon film (graphene sheet) is rolled into a cylindrical shape, a two-layer CNT in which two graphene sheets are rolled into concentric circles, and multiple sheets of graphene can be used. Any one of the multi-layered CNTs in which the sheet is rolled into a concentric shape, and two or more of these may be used. Among them, from the viewpoint of exhibiting the characteristics of a semiconductor, it is preferable to use a single-layer CNT, and in particular, the single-layer CNT preferably contains 90% by weight or more of a semiconductor-type single-layer CNT. More preferably, the single-layer CNT contains 95% by weight or more of the semiconductor-type single-layer CNT.

進而，於表面的至少一部分附著有共軛系聚合體的CNT（以下，稱為CNT複合體）於溶液中的分散穩定性優異，可獲得高遷移率，因此作為半導體層4的碳材料尤佳。此處，所謂共軛系聚合體，是指重複單元取共軛結構且聚合度為2以上的化合物。另外，藉由使用均勻地分散有CNT的溶液，可藉由噴墨法等塗佈法形成均勻地分散有CNT的膜（構成半導體層4的膜）。Furthermore, CNTs with conjugated polymers attached to at least a part of the surface (hereinafter referred to as CNT composites) have excellent dispersion stability in the solution and can obtain high mobility, so they are particularly suitable as a carbon material for the semiconductor layer 4 . Here, the term “conjugated polymer” refers to a compound in which the repeating unit has a conjugated structure and the degree of polymerization is 2 or more. In addition, by using a solution in which CNTs are uniformly dispersed, a film in which CNTs are uniformly dispersed (a film constituting the semiconductor layer 4) can be formed by a coating method such as an inkjet method.

所謂「共軛系聚合體附著於CNT表面的至少一部分的狀態」，是指共軛系聚合體包覆CNT表面的一部分、或者全部的狀態。推測共軛系聚合體可包覆CNT的原因在於：藉由源自各自的共軛系結構的π電子雲重疊而產生相互作用。CNT是否由共軛系聚合體所包覆可藉由下述情況來判別：作為對象的CNT的反射色由未經包覆的CNT的顏色變得接近共軛系聚合體的顏色。可以定量的方式，藉由X射線光電子分光法（XPS）等元素分析來鑑定附著物的存在與附著物相對於CNT的質量比。The "state where the conjugated polymer is attached to at least a part of the surface of the CNT" refers to a state where the conjugated polymer covers a part or all of the surface of the CNT. It is speculated that the reason why the conjugated polymer can coat the CNT is that interaction occurs due to the overlapping of π electron clouds derived from the respective conjugated system structures. Whether the CNT is covered by the conjugated polymer can be judged by the fact that the reflected color of the target CNT becomes close to the color of the conjugated polymer from the color of the uncovered CNT. It can be quantitatively identified by X-ray photoelectron spectroscopy (XPS) and other elemental analysis to identify the presence of attachments and the mass ratio of attachments to CNTs.

附著於CNT的共軛系聚合體可無關於分子量、分子量分佈或結構地來使用。就對CNT的附著容易度的觀點而言，該共軛系聚合體較佳為重量平均分子量為1000以上。The conjugated polymer attached to CNT can be used regardless of molecular weight, molecular weight distribution, or structure. From the viewpoint of ease of adhesion to CNTs, the conjugated polymer preferably has a weight average molecular weight of 1,000 or more.

作為使共軛系聚合體附著於CNT的方法，例如可列舉以下所示的第一方法～第四方法等。作為第一方法，可列舉於熔融的共軛系聚合體中添加CNT而進行混合的方法。作為第二方法，可列舉使共軛系聚合體溶解於溶媒中並於其中添加CNT而進行混合的方法。作為第三方法，可列舉於在溶媒中預先利用超音波等預分散CNT的地方添加共軛系聚合體而進行混合的方法。作為第四方法，可列舉將共軛系聚合體與CNT加入溶媒中並對所述混合體系照射超音波而進行混合的方法。本發明中，亦可將該些多種方法加以組合。As a method of attaching the conjugated polymer to the CNT, for example, the first to fourth methods shown below can be cited. As the first method, a method of adding and mixing CNTs to a molten conjugated polymer can be cited. As the second method, a method of dissolving a conjugated polymer in a solvent and adding CNTs to the mixture can be cited. As a third method, a method of adding and mixing a conjugated polymer in a solvent where CNTs are pre-dispersed by ultrasonic waves or the like is exemplified. As a fourth method, a method of adding a conjugated polymer and CNTs to a solvent and irradiating the mixed system with ultrasonic waves to mix them can be cited. In the present invention, these multiple methods can also be combined.

於本發明中，CNT的長度較佳為短於源極電極5與汲極電極6之間的距離（通道長度）。CNT的平均長度取決於通道長度，較佳為2 μm以下，更佳為0.5 μm以下。一般市售的CNT於長度上存在分佈，有時包含較通道長度更長的CNT。因此，較佳為於形成半導體層4的步驟中加入使CNT比通道長度短的步驟。作為使CNT比通道長度短的方法，例如有效的是藉由利用硝酸、硫酸等進行的酸處理、超音波處理或冷凍粉碎法等將CNT切割為短纖維狀的方法。另外，就提高CNT的純度的觀點而言，進而佳為併用利用過濾器進行的分離。另外，CNT的直徑並無特別限定，較佳為1 nm以上且100 nm以下，更佳為50 nm以下。In the present invention, the length of the CNT is preferably shorter than the distance (channel length) between the source electrode 5 and the drain electrode 6. The average length of the CNT depends on the channel length, and is preferably 2 μm or less, more preferably 0.5 μm or less. Generally, commercially available CNTs are distributed in length, and sometimes contain CNTs longer than the channel length. Therefore, it is preferable to add a step of making the CNT shorter than the channel length in the step of forming the semiconductor layer 4. As a method of making the CNT shorter than the channel length, for example, a method of cutting the CNT into short fibers by acid treatment with nitric acid, sulfuric acid, or the like, ultrasonic treatment, or freeze crushing method is effective. In addition, from the viewpoint of improving the purity of CNTs, it is more preferable to use the separation by a filter in combination. In addition, the diameter of the CNT is not particularly limited, but is preferably 1 nm or more and 100 nm or less, and more preferably 50 nm or less.

作為包覆所述CNT的共軛系聚合體，可列舉：聚噻吩系聚合體、聚吡咯系聚合體、聚苯胺系聚合體、聚乙炔系聚合體、聚對苯系聚合體、聚對苯乙炔系聚合體、於重複單元中具有噻吩單元與雜芳基單元的噻吩-伸雜芳基系聚合體等。所述共軛系聚合體可為使用該些的兩種以上者。作為所述共軛系聚合體，可使用單一的單體單元排列而成者、將不同的單體單元進行嵌段共聚而成者、進行無規共聚而成者、或者進行接枝聚合而成者等。Examples of the conjugated polymer covering the CNT include: polythiophene-based polymer, polypyrrole-based polymer, polyaniline-based polymer, polyacetylene-based polymer, poly-p-phenylene-based polymer, and poly-p-phenylene Acetylene-based polymer, thiophene-heteroaryl-based polymer having thiophene unit and heteroaryl unit in the repeating unit, etc. The conjugated polymer may use two or more of these. As the conjugated polymer, it is possible to use a structure formed by arranging a single monomer unit, a structure formed by block copolymerization of different monomer units, a structure formed by random copolymerization, or a structure formed by graft polymerization.者 etc.

另外，作為半導體層4，亦可使用將CNT複合體與有機半導體混合而成者。藉由使CNT複合體均勻地分散於有機半導體中，可在維持有機半導體自身的特性的同時實現高遷移率。In addition, as the semiconductor layer 4, a mixture of a CNT composite and an organic semiconductor may also be used. By uniformly dispersing the CNT composite in the organic semiconductor, high mobility can be achieved while maintaining the characteristics of the organic semiconductor itself.

另外，半導體層4亦可進而包含絕緣性材料。作為此處所使用的絕緣性材料，可列舉本發明的絕緣材料組成物、或聚(甲基丙烯酸甲酯)、聚碳酸酯、聚對苯二甲酸乙二酯等聚合物材料，但並不特別地限定於該些材料。In addition, the semiconductor layer 4 may further include an insulating material. Examples of the insulating material used here include the insulating material composition of the present invention, or polymer materials such as poly(methyl methacrylate), polycarbonate, and polyethylene terephthalate, but it is not particularly The ground is limited to these materials.

半導體層4可為單層亦可為多層。半導體層4的膜厚較佳為1 nm以上且200 nm以下，進而佳為100 nm以下。藉由將半導體層4設為所述範圍內的膜厚，容易形成均勻的薄膜，進而抑制無法藉由閘極電壓進行控制的源極/汲極電極間的電流，可進一步提高FET的開關比（on off ratio）。半導體層4的膜厚可藉由原子力顯微鏡或橢圓偏光法等來測定。The semiconductor layer 4 may be a single layer or multiple layers. The thickness of the semiconductor layer 4 is preferably 1 nm or more and 200 nm or less, and more preferably 100 nm or less. By setting the semiconductor layer 4 to a film thickness within the above range, it is easy to form a uniform thin film, thereby suppressing the current between the source/drain electrodes that cannot be controlled by the gate voltage, and further improving the switching ratio of the FET (On off ratio). The film thickness of the semiconductor layer 4 can be measured by an atomic force microscope, ellipsometry, or the like.

另外，亦可於閘極絕緣層3與半導體層4之間設置配向性層。作為所述配向性層的材料，可使用矽烷化合物、鈦化合物、有機酸、雜有機酸等公知的材料，尤佳為有機矽烷化合物。In addition, an alignment layer can also be provided between the gate insulating layer 3 and the semiconductor layer 4. As the material of the alignment layer, known materials such as silane compounds, titanium compounds, organic acids, and heteroorganic acids can be used, and organosilane compounds are particularly preferred.

於本發明中，亦可於多個FET的至少一部分的半導體層4的、與閘極絕緣層3為相反的一側形成與半導體層4接觸的第二絕緣層（例如圖14所示的第二絕緣層7）。藉此，可保護半導體層4不受氧或水分等外部環境影響。In the present invention, a second insulating layer in contact with the semiconductor layer 4 (for example, the first insulating layer shown in FIG. 14) may be formed on the side opposite to the gate insulating layer 3 of the semiconductor layer 4 of at least a part of the plurality of FETs. Two insulating layer 7). Thereby, the semiconductor layer 4 can be protected from the external environment such as oxygen or moisture.

作為所述第二絕緣層中使用的材料，並無特別限定，具體而言，可列舉氧化矽、氧化鋁等無機材料、聚醯亞胺或其衍生物、聚乙烯醇、聚氯乙烯、聚對苯二甲酸乙二酯、聚偏二氟乙烯、聚矽氧烷或其衍生物、聚乙烯基苯酚或其衍生物等聚合物材料、或者無機材料粉末與聚合物材料的混合物或有機低分子材料與聚合物材料的混合物。The material used in the second insulating layer is not particularly limited. Specifically, inorganic materials such as silica and alumina, polyimide or its derivatives, polyvinyl alcohol, polyvinyl chloride, polyvinyl chloride, and Polymer materials such as ethylene terephthalate, polyvinylidene fluoride, polysiloxane or its derivatives, polyvinylphenol or its derivatives, or a mixture of inorganic material powder and polymer material, or organic low molecular weight Mixture of materials and polymer materials.

所形成的FET（例如圖14等中所示的FET 20、FET 30）可藉由使閘極電壓變化而控制源極電極5與汲極電極6之間所流動的電流。作為FET的性能的指標的遷移率可使用下述（a）式而算出。 遷移率μ=（δId/δVg）L·D/（W·εr·ε·Vsd）  （a）The formed FET (for example, the FET 20 and the FET 30 shown in FIG. 14 and the like) can control the current flowing between the source electrode 5 and the drain electrode 6 by changing the gate voltage. The mobility, which is an index of the performance of the FET, can be calculated using the following equation (a). Mobility μ=(δId/δVg)L·D/(W·εr·ε·Vsd) (a)

其中，（a）式中，Id為源極/汲極電極間的電流，Vsd為源極/汲極電極間的電壓。Vg為閘極電壓。D為閘極絕緣層3的厚度。L為通道長度，W為通道寬度。εr為閘極絕緣層3的相對介電常數，ε為真空的介電常數（8.85×10-12 F/m）。Among them, in the formula (a), Id is the current between the source/drain electrodes, and Vsd is the voltage between the source/drain electrodes. Vg is the gate voltage. D is the thickness of the gate insulating layer 3. L is the channel length, W is the channel width. εr is the relative dielectric constant of the gate insulating layer 3, and ε is the dielectric constant of vacuum (8.85×10 -12 F/m).

所述FET為遷移率高、閘極電極2與源極電極5及汲極電極6的相對位置被高精度地控制的FET。The FET is a FET with high mobility and the relative positions of the gate electrode 2 and the source electrode 5 and the drain electrode 6 are controlled with high precision.

（第二絕緣層） 第二絕緣層7形成於半導體層4的與形成有閘極絕緣層3的一側為相反的一側。所謂「半導體層4的與形成有閘極絕緣層3的一側為相反的一側」，例如於在半導體層4的下側具有閘極絕緣層3的情況下，是指半導體層4的上側。藉由形成第二絕緣層，通常可將顯示出p型半導體特性的CNT-FET轉換為顯示出n型半導體特性的半導體元件。(Second insulating layer) The second insulating layer 7 is formed on the side of the semiconductor layer 4 opposite to the side on which the gate insulating layer 3 is formed. The term "the side of the semiconductor layer 4 on which the gate insulating layer 3 is formed is the opposite side", for example, when the gate insulating layer 3 is provided on the lower side of the semiconductor layer 4, it refers to the upper side of the semiconductor layer 4 . By forming the second insulating layer, the CNT-FET exhibiting p-type semiconductor characteristics can usually be converted into a semiconductor element exhibiting n-type semiconductor characteristics.

第二絕緣層7較佳為含有具有碳原子與氮原子的鍵的有機化合物。此種有機化合物可為任意的有機化合物，例如可列舉：醯胺系化合物、醯亞胺系化合物、脲系化合物、胺系化合物、亞胺系化合物、苯胺系化合物、腈系化合物等。進而，認為第二絕緣層7藉由含有聚合物，可穩定地保持具有碳原子與氮原子的鍵的有機化合物和CNT相互作用的情況，因此推測可獲得更穩定的n型半導體特性。作為第二絕緣層7中所含的聚合物，可列舉丙烯酸樹脂、甲基丙烯酸樹脂、烯烴聚合物、環烯烴聚合物、聚苯乙烯、聚矽氧烷、聚醯亞胺、聚碳酸酯、乙烯醇系樹脂、酚系樹脂等。The second insulating layer 7 preferably contains an organic compound having a bond between carbon atoms and nitrogen atoms. Such an organic compound may be any organic compound, and examples thereof include amide-based compounds, imine-based compounds, urea-based compounds, amine-based compounds, imine-based compounds, aniline-based compounds, and nitrile-based compounds. Furthermore, it is considered that by containing a polymer, the second insulating layer 7 can stably maintain the interaction between the organic compound having a carbon atom and a nitrogen atom and CNT, and therefore, it is presumed that more stable n-type semiconductor characteristics can be obtained. Examples of the polymer contained in the second insulating layer 7 include acrylic resin, methacrylic resin, olefin polymer, cycloolefin polymer, polystyrene, polysiloxane, polyimide, polycarbonate, Vinyl alcohol resin, phenol resin, etc.

第二絕緣層7除了有機化合物或聚合物以外，亦可含有其他化合物。作為所述其他化合物，例如可列舉藉由塗佈而形成第二絕緣層7時的、用於調節溶液的黏度或流變的增黏劑或觸變劑等。另外，第二絕緣層7可為單層亦可為多層。In addition to organic compounds or polymers, the second insulating layer 7 may also contain other compounds. As the other compound, for example, a thickener or thixotropic agent for adjusting the viscosity or rheology of the solution when the second insulating layer 7 is formed by coating. In addition, the second insulating layer 7 may be a single layer or multiple layers.

作為第二絕緣層7的形成方法，並無特別限定，亦可使用電阻加熱蒸鍍、電子束、濺鍍、化學氣相沈積（Chemical Vapor Deposition，CVD）等乾式方法，就製造成本或適合於大面積的觀點而言，較佳為使用塗佈法。作為所述塗佈法，具體而言，可較佳地使用旋塗法、刮塗法、縫模塗佈法、網版印刷法、棒塗機法、鑄模法、印刷轉印法、浸漬提拉法、噴墨法、滴鑄法等。可對應於塗膜厚度控制或配向控制等所欲獲得的塗膜特性來選擇第二絕緣層7的塗佈法。The method for forming the second insulating layer 7 is not particularly limited, and dry methods such as resistance heating vapor deposition, electron beam, sputtering, chemical vapor deposition (Chemical Vapor Deposition, CVD), etc. can also be used. From the viewpoint of a large area, it is preferable to use a coating method. As the coating method, specifically, a spin coating method, a blade coating method, a slot die coating method, a screen printing method, a bar coater method, a mold method, a printing transfer method, and a dip coating method can be preferably used. Pull method, inkjet method, drop casting method, etc. The coating method of the second insulating layer 7 can be selected in accordance with the coating film characteristics to be obtained such as coating film thickness control or alignment control.

＜半導體裝置用基板的製造方法＞ 其次，關於本發明的半導體裝置用基板的製造方法，以將所述實施形態5的半導體裝置用基板50E的製造方法作為代表例的內容為中心進行詳細說明。本發明的半導體裝置用基板的製造方法是製造所述各實施形態的半導體裝置用基板中的任一者的方法。製造所述各實施形態的半導體裝置用基板的任一者時的製造方法較佳為於同一步驟中進行樹脂基材1上的多個半導體裝置的構成構件中的任一者的形成與加強線的形成。藉此，可削減半導體裝置用基板的製造所需的材料的種類及步驟數。＜Method of manufacturing substrate for semiconductor device＞ Next, regarding the manufacturing method of the semiconductor device substrate of the present invention, the method of manufacturing the semiconductor device substrate 50E of the fifth embodiment described above will be described in detail, focusing on the content as a representative example. The method of manufacturing a substrate for a semiconductor device of the present invention is a method of manufacturing any one of the substrates for a semiconductor device of each embodiment described above. The method of manufacturing any one of the semiconductor device substrates of the aforementioned embodiments is preferably to perform the formation and reinforcement of any one of the plurality of semiconductor device constituent members on the resin substrate 1 in the same step Formation. Thereby, it is possible to reduce the types of materials and the number of steps required for the manufacture of the semiconductor device substrate.

圖17是用以說明本發明的實施形態5的半導體裝置用基板的製造方法的一例的立體圖。圖18A是表示本發明的實施形態5的半導體裝置用基板的製造方法的第一步驟例的部分放大示意圖。圖18B是表示本發明的實施形態5的半導體裝置用基板的製造方法的第二步驟例的部分放大示意圖。於圖18A、圖18B中摘選圖17所示的半導體裝置用基板50E的一部分（由虛線III包圍的部分）並示出所述半導體裝置用基板50E的製造方法的各步驟。於製造所述半導體裝置用基板50E時，在藉由輥對輥方式搬運長條的樹脂基材1的同時進行以下各步驟。於所述輥對輥方式的搬運中，樹脂基材1的搬運方向與所述樹脂基材1的長邊方向（參照圖17中的粗線箭頭）為相同方向。FIG. 17 is a perspective view for explaining an example of a method of manufacturing a substrate for a semiconductor device according to Embodiment 5 of the present invention. 18A is a partially enlarged schematic diagram showing a first step example of a method of manufacturing a substrate for a semiconductor device according to Embodiment 5 of the present invention. 18B is a partially enlarged schematic diagram showing a second step example of the method of manufacturing a substrate for a semiconductor device according to the fifth embodiment of the present invention. In FIGS. 18A and 18B, a part of the semiconductor device substrate 50E shown in FIG. 17 (the portion surrounded by the broken line III) is extracted, and each step of the method of manufacturing the semiconductor device substrate 50E is shown. When manufacturing the substrate 50E for a semiconductor device, the following steps are performed while conveying the long resin base material 1 by a roll-to-roll method. In the transfer of the roll-to-roll method, the transfer direction of the resin base material 1 and the longitudinal direction of the resin base material 1 (refer to the thick-line arrow in FIG. 17) are the same direction.

於半導體裝置用基板50E的製造方法中，首先，如圖18A的狀態S1所示，實施於樹脂基材1的面上進行閘極電極2的形成與加強線31～加強線38的形成的加強線形成步驟。於所述加強線形成步驟中，於同一步驟中於樹脂基材1上形成閘極電極2及加強線31～加強線38。再者，此處所述的同一步驟，不僅包括一併形成閘極電極2及加強線31～加強線38，亦包括先形成閘極電極2或加強線31～加強線38中的其中一者，接著於形成下一個閘極絕緣層的步驟之前形成另一者（閘極電極2或加強線31～加強線38中未形成者）。該些中，較佳為一併形成閘極電極2及加強線31～加強線38。In the manufacturing method of the semiconductor device substrate 50E, first, as shown in the state S1 of FIG. 18A, the formation of the gate electrode 2 and the formation of the reinforcing wires 31 to 38 are performed on the surface of the resin base material 1. Line formation step. In the step of forming the reinforcing wire, the gate electrode 2 and the reinforcing wire 31 to the reinforcing wire 38 are formed on the resin substrate 1 in the same step. Furthermore, the same step described here includes not only forming the gate electrode 2 and the reinforcing wire 31 to the reinforcing wire 38 together, but also including forming one of the gate electrode 2 or the reinforcing wire 31 to the reinforcing wire 38 first. Then, before the step of forming the next gate insulating layer, the other one (the gate electrode 2 or the reinforcing wire 31 to the reinforcing wire 38 is not formed) is formed. Among these, it is preferable to form the gate electrode 2 and the reinforcing wire 31 to the reinforcing wire 38 together.

作為所述加強線形成步驟中的閘極電極2及加強線31～加強線38的形成方法，可列舉使用真空蒸鍍、電子束、濺鍍、鍍敷、CVD、離子鍍塗佈、噴墨、印刷等公知技術的方法，或者利用刮塗法、縫模塗佈法、網版印刷法、棒塗機法、鑄模法、印刷轉印法、浸漬提拉法等公知的技術將包含有機成分及導電體粒子的糊塗佈於絕緣基板上，並使用烘箱、加熱板、紅外線等進行乾燥而形成的方法等。該些閘極電極2及加強線31～加強線38的形成方法只要可使閘極電極2與配線（未圖示）導通，則並無特別限制。另外，於所述加強線形成步驟中，加強線31～加強線38由與構成閘極電極2的材料相同的材料形成。As a method of forming the gate electrode 2 and the reinforcing wires 31 to 38 in the step of forming the reinforcing wire, the use of vacuum vapor deposition, electron beam, sputtering, plating, CVD, ion plating coating, and inkjet can be mentioned. , Printing and other known techniques, or the use of known techniques such as blade coating, slot die coating, screen printing, bar coater method, casting method, printing transfer method, dipping and pulling method, etc. will contain organic ingredients The paste of conductive particles is applied on an insulating substrate and dried using an oven, a hot plate, infrared rays, or the like. The method of forming the gate electrode 2 and the reinforcing wire 31 to the reinforcing wire 38 is not particularly limited as long as the gate electrode 2 and the wiring (not shown) can be electrically connected. In addition, in the step of forming the reinforcing wire, the reinforcing wire 31 to the reinforcing wire 38 are formed of the same material as the material constituting the gate electrode 2.

另外，於所述加強線形成步驟中，作為將閘極電極2及加強線31～加強線38形成為圖案狀的圖案形成方法，可為將藉由所述方法而製作的電極薄膜利用公知的光微影法等而圖案形成為所需形狀的方法，或者亦可為於電極及配線物質的真空蒸鍍或濺鍍時介隔所需形狀的遮罩來進行圖案形成的方法。另外，作為所述圖案形成方法，亦可為使用噴墨法或印刷法來直接形成圖案的方法。In addition, in the step of forming the reinforcement line, as a pattern forming method for forming the gate electrode 2 and the reinforcement line 31 to the reinforcement line 38 into a pattern, a well-known electrode thin film produced by the method can be used. A method of forming a pattern into a desired shape such as a photolithography method, or a method of forming a pattern through a mask of a desired shape at the time of vacuum vapor deposition or sputtering of electrodes and wiring materials. In addition, as the pattern forming method, a method of directly forming a pattern using an inkjet method or a printing method may also be used.

於該些方法中，所述加強線形成步驟亦較佳為包括圖案化步驟，所述圖案化步驟是加工藉由濺鍍或真空蒸鍍法而於樹脂基材1上成膜的金屬膜，並將所述金屬膜加工成與閘極電極2及加強線31～加強線38對應的圖案。另外，所述加強線形成步驟亦較佳為包括：成膜步驟，於樹脂基材1上使用含有導電體粒子與感光性有機成分的感光性糊而形成塗佈膜；以及圖案化步驟，藉由光微影法將所述塗佈膜加工成與閘極電極2及加強線31～加強線38對應的圖案。藉由將該些方法（步驟）用於所述加強線形成步驟，可形成平坦性高、厚度及圖案形狀均勻的閘極電極2及加強線31～加強線38。因此，可減少所製作的FET的洩漏率且減少所述FET的特性偏差。作為本發明中使用的感光性糊的較佳的實施形態，例如可列舉國際公開第2018/051860號或國際公開第2017/030070號中記載的感光性糊。In these methods, the step of forming the reinforcing line preferably includes a patterning step, and the patterning step is to process a metal film formed on the resin substrate 1 by sputtering or vacuum evaporation. The metal film is processed into a pattern corresponding to the gate electrode 2 and the reinforcing lines 31 to 38. In addition, the step of forming the reinforcing line preferably also includes: a film forming step of forming a coating film on the resin substrate 1 using a photosensitive paste containing conductive particles and a photosensitive organic component; and a patterning step, by The coating film is processed into a pattern corresponding to the gate electrode 2 and the reinforcing lines 31 to 38 by photolithography. By using these methods (steps) in the reinforcing wire forming step, the gate electrode 2 and the reinforcing wires 31 to 38 with high flatness, uniform thickness and pattern shape can be formed. Therefore, the leakage rate of the manufactured FET can be reduced and the characteristic deviation of the FET can be reduced. As a preferable embodiment of the photosensitive paste used in the present invention, for example, the photosensitive paste described in International Publication No. 2018/051860 or International Publication No. 2017/030070 can be cited.

於將藉由輥對輥方式連續地搬運的樹脂基材1捲繞成卷狀時，與加強線31～加強線34對應的樹脂基材1的部位因它們的重疊而輥厚度變厚，形成與加強線31～加強線34的列數相對應的尺狀(Gauge)的帶。於加強線31～加強線34的厚度均勻的情況下，藉由使各帶的厚度均勻，可減少樹脂基材1的卷未對準。另外，藉由使加強線31～加強線38的厚度與閘極電極2的厚度均勻，於捲成卷狀的樹脂基材1中，與閘極電極2重疊蓄積的厚度相比，加強線31～加強線34重疊蓄積的厚度更厚。因此，可減少因樹脂基材1的卷被捲緊並摩擦而發生的閘極電極2的斷線的發生。When the resin base material 1 continuously conveyed by the roll-to-roll method is wound into a roll, the parts of the resin base material 1 corresponding to the reinforcing lines 31 to 34 are overlapped and the roll thickness becomes thicker. Gauge-shaped bands corresponding to the number of rows of the reinforcing wires 31 to 34. In the case where the thickness of the reinforcing wire 31 to the reinforcing wire 34 is uniform, by making the thickness of each tape uniform, the misalignment of the roll of the resin base material 1 can be reduced. In addition, by making the thickness of the reinforcing wires 31 to 38 and the thickness of the gate electrode 2 uniform, the thickness of the reinforcing wire 31 in the resin substrate 1 rolled into a roll is compared with the thickness of the gate electrode 2 stacked and accumulated. -The thickness of the reinforcement wire 34 that is stacked and accumulated is thicker. Therefore, it is possible to reduce the occurrence of disconnection of the gate electrode 2 caused by the winding of the resin base material 1 being wound up and rubbed.

樹脂基材1的厚度較佳為25 μm以上且100 μm以下。藉由將樹脂基材1的厚度設為所述範圍內，樹脂基材1可具有高耐久性與適度的柔軟性，因此可抑制輥對輥方式中的樹脂基材1的搬運蜿蜒或卷未對準。其結果，半導體裝置於樹脂基材1上的形成效率提高。The thickness of the resin substrate 1 is preferably 25 μm or more and 100 μm or less. By setting the thickness of the resin base material 1 within the above range, the resin base material 1 can have high durability and moderate flexibility, and therefore, it is possible to suppress the meandering or winding of the resin base material 1 in the roll-to-roll method. Misaligned. As a result, the formation efficiency of the semiconductor device on the resin substrate 1 is improved.

再者，所謂厚度均勻，是指測定任意5處的厚度時相對於平均值的標準偏差控制在5%以內。另外，所謂閘極電極等電極的厚度與加強線的厚度相同，是指對形成於樹脂基材1的面內的電極及加強線分別測定任意的5處的厚度時的平均值之差相對於值更大的平均值而言控制在10%以內。In addition, the term “uniform thickness” means that the standard deviation from the average value when measuring the thickness at any five locations is controlled within 5%. In addition, the thickness of the electrode such as the gate electrode and the thickness of the reinforcing wire is the same as the difference between the average value when the thickness of the electrode and the reinforcing wire formed in the surface of the resin substrate 1 are measured at five arbitrary locations, respectively. For larger values, the average value is controlled within 10%.

其次，如圖18A的狀態S2所示，實施進行閘極絕緣層3的形成的第一絕緣層形成步驟。於所述第一絕緣層形成步驟中，於所述閘極電極2（參照圖18A的狀態S1）上形成閘極絕緣層3。作為閘極絕緣層3的形成方法，可列舉真空蒸鍍、電子束、濺鍍、鍍敷、CVD、離子鍍塗佈、噴墨、印刷、旋塗法、刮塗法、縫模塗佈法、棒塗機法、鑄模法、印刷轉印法、浸漬提拉法等公知的技術。但是，閘極絕緣層3的形成方法並不限定於該些。Next, as shown in the state S2 of FIG. 18A, the first insulating layer forming step for forming the gate insulating layer 3 is performed. In the step of forming the first insulating layer, a gate insulating layer 3 is formed on the gate electrode 2 (refer to the state S1 of FIG. 18A). Examples of methods for forming the gate insulating layer 3 include vacuum vapor deposition, electron beam, sputtering, plating, CVD, ion plating coating, inkjet, printing, spin coating, blade coating, and slot die coating. , Bar coater method, mold method, printing transfer method, dip pulling method and other well-known technologies. However, the method of forming the gate insulating layer 3 is not limited to these.

另外，圖18A中雖未圖示，但閘極絕緣層3亦可形成於加強線31～加強線38上，亦可形成於形成有閘極電極2及加強線31～加強線38的樹脂基材1的整個面。In addition, although not shown in FIG. 18A, the gate insulating layer 3 may also be formed on the reinforcing wire 31 to the reinforcing wire 38, or may be formed on the resin base on which the gate electrode 2 and the reinforcing wire 31 to the reinforcing wire 38 are formed. The entire surface of the material 1.

其次，如圖18B的狀態S3所示，實施進行半導體層4的形成的半導體層形成步驟。於所述半導體層形成步驟中，於所述閘極絕緣層3（參照圖18A的狀態S2）上塗佈含有CNT的溶液而形成半導體層4。作為半導體層4的形成方法，就製造成本或適合於大面積的觀點而言，較佳為使用塗佈法。作為所述塗佈法，可列舉旋塗法、刮塗法、縫模塗佈法、網版印刷法、棒塗法、鑄模法、印刷轉印法、浸漬提拉法、噴墨法等公知的塗佈方法。其中，所述塗佈法較佳為選自由噴墨法、分配器法及噴霧法所組成的群組中的任一種。進而，就原料的使用效率的觀點而言，更佳為噴墨法。作為所述塗佈法，可對應於塗膜厚度控制或配向控制等所欲獲得的塗膜特性而自該些塗佈方法中選擇適當的方法。另外，於所述半導體層形成步驟中，亦可於大氣下、減壓下或惰性氣體環境下（氮氣或氬氣環境下）對所形成的塗膜進行退火處理。Next, as shown in the state S3 of FIG. 18B, a semiconductor layer forming step for forming the semiconductor layer 4 is performed. In the semiconductor layer forming step, the gate insulating layer 3 (refer to the state S2 of FIG. 18A) is coated with a solution containing CNTs to form the semiconductor layer 4. As a method of forming the semiconductor layer 4, it is preferable to use a coating method from the viewpoint of manufacturing cost or suitability for a large area. As the coating method, well-known methods such as spin coating method, blade coating method, slot die coating method, screen printing method, bar coating method, casting method, printing transfer method, dipping and pulling method, and inkjet method can be cited.的coating method. Among them, the coating method is preferably any one selected from the group consisting of an inkjet method, a dispenser method, and a spray method. Furthermore, from the viewpoint of the efficiency of the use of raw materials, the inkjet method is more preferable. As the coating method, an appropriate method can be selected from these coating methods in accordance with the coating film characteristics to be obtained such as coating film thickness control or alignment control. In addition, in the semiconductor layer forming step, the formed coating film may also be annealed under the atmosphere, under reduced pressure, or in an inert gas environment (under nitrogen or argon atmosphere).

其次，如圖18B的狀態S4所示，實施進行源極/汲極電極的形成的電極形成步驟。於所述電極步驟中，於所述閘極絕緣層3及半導體層4（參照圖18B的狀態S3）上形成源極電極5及汲極電極6。作為源極電極5及汲極電極6的形成方法，可列舉使用真空蒸鍍、電子束、濺鍍、鍍敷、CVD、離子鍍塗佈、噴墨、印刷等公知技術的方法，或者利用旋塗法、刮塗法、縫模塗佈法、網版印刷法、棒塗機法、鑄模法、印刷轉印法、浸漬提拉法等公知的技術將包含有機成分及導電性粒子的糊塗佈於絕緣基板上，並使用烘箱、加熱板、紅外線等進行乾燥而形成的方法等。但是，該些電極的形成方法只要可使源極電極5及汲極電極6與配線（未圖示）導通，則並無特別限制。Next, as shown in the state S4 of FIG. 18B, an electrode forming step of forming source/drain electrodes is performed. In the electrode step, a source electrode 5 and a drain electrode 6 are formed on the gate insulating layer 3 and the semiconductor layer 4 (refer to the state S3 of FIG. 18B). As a method of forming the source electrode 5 and the drain electrode 6, a method using known techniques such as vacuum vapor deposition, electron beam, sputtering, plating, CVD, ion plating coating, inkjet, printing, etc., or the use of spin The coating method, the knife coating method, the slot die coating method, the screen printing method, the bar coater method, the casting method, the printing transfer method, the dipping and pulling method, and other well-known techniques apply the paste containing organic components and conductive particles It is formed on an insulating substrate and dried using an oven, a hot plate, infrared rays, and the like. However, the method of forming these electrodes is not particularly limited as long as the source electrode 5 and the drain electrode 6 can be connected to the wiring (not shown).

另外，於半導體裝置用基板50E的製造方法中，可進行於同一步驟中形成源極電極5及汲極電極6與加強線31～加強線38來代替如上所述於同一步驟中形成閘極電極2與加強線31～加強線38的加強線形成步驟。此時，加強線31～加強線38的材料是與構成源極電極5及汲極電極6的材料相同的材料。於所述加強線形成步驟中，作為將源極電極5及汲極電極6與加強線31～加強線38形成為圖案狀的圖案形成方法，可為將藉由所述方法而製作的電極薄膜利用公知的光微影法等圖案形成為所需形狀的方法，或者亦可為於電極及配線物質的蒸鍍或濺鍍時介隔所需形狀的遮罩來進行圖案形成的方法。另外，作為所述圖案形成方法，亦可為使用噴墨法或印刷法來直接形成圖案的方法。In addition, in the manufacturing method of the semiconductor device substrate 50E, the source electrode 5 and the drain electrode 6 and the reinforcement line 31 to the reinforcement line 38 may be formed in the same step instead of forming the gate electrode in the same step as described above. 2 Reinforcement line forming step with reinforcement line 31 to reinforcement line 38. At this time, the material of the reinforcing wire 31 to the reinforcing wire 38 is the same material as the material constituting the source electrode 5 and the drain electrode 6. In the step of forming the reinforcement line, as a pattern forming method of forming the source electrode 5 and the drain electrode 6 and the reinforcement line 31 to the reinforcement line 38 into a pattern, the electrode thin film produced by the method may be A method of forming a pattern into a desired shape using a known photolithography method or the like may also be a method of forming a pattern by interposing a mask of a desired shape during vapor deposition or sputtering of electrodes and wiring materials. In addition, as the pattern forming method, a method of directly forming a pattern using an inkjet method or a printing method may also be used.

其次，例示所述實施形態6的半導體裝置用基板50H（參照圖13），對本發明的半導體裝置用基板的製造方法的變形例進行說明。圖19A是表示本發明的實施形態6的半導體裝置用基板的製造方法的第一步驟例的部分放大示意圖。圖19B是表示本發明的實施形態6的半導體裝置用基板的製造方法的第二步驟例的部分放大示意圖。於圖19A、圖19B中摘選本實施形態6的半導體裝置用基板50H的一部分並示出所述半導體裝置用基板50H的製造方法的各步驟。圖19A、圖19B所示的半導體裝置用基板50H的一部分與圖17所示的半導體裝置用基板50E的由虛線III包圍的部分相同。於所述半導體裝置用基板50H的製造方法中，樹脂基材1與所述實施形態5的半導體裝置用基板50E的製造方法（參照圖17）同樣地為長條的樹脂基材。另外，於製造所述半導體裝置用基板50H時，在藉由輥對輥方式搬運長條的樹脂基材1的同時進行以下各步驟。此時，樹脂基材1的搬運方向與所述實施形態5中的搬運方向（參照圖17中的粗線箭頭）為相同方向。Next, the semiconductor device substrate 50H of the sixth embodiment (see FIG. 13) is illustrated, and a modification example of the method of manufacturing the semiconductor device substrate of the present invention will be described. 19A is a partially enlarged schematic diagram showing an example of the first step of the manufacturing method of the semiconductor device substrate according to the sixth embodiment of the present invention. 19B is a partially enlarged schematic diagram showing a second step example of the manufacturing method of the semiconductor device substrate according to the sixth embodiment of the present invention. A part of the semiconductor device substrate 50H of the sixth embodiment is extracted from FIGS. 19A and 19B and each step of the manufacturing method of the semiconductor device substrate 50H is shown. A part of the semiconductor device substrate 50H shown in FIGS. 19A and 19B is the same as the part surrounded by the broken line III of the semiconductor device substrate 50E shown in FIG. 17. In the method of manufacturing the semiconductor device substrate 50H, the resin base material 1 is a long resin substrate similar to the manufacturing method of the semiconductor device substrate 50E of the fifth embodiment (see FIG. 17 ). Moreover, when manufacturing the said board|substrate 50H for semiconductor devices, the following steps are performed while conveying the long resin base material 1 by a roll-to-roll method. At this time, the conveying direction of the resin base material 1 is the same direction as the conveying direction in the fifth embodiment (refer to the thick-line arrow in FIG. 17).

於半導體裝置用基板50H的製造方法中，首先，如圖19A所示，實施進行閘極電極2的形成與加強線31～加強線38的形成的加強線形成步驟（狀態S11）、進行閘極絕緣層3的形成的第一絕緣層形成步驟（狀態S12）、以及進行半導體層4的形成的半導體層形成步驟（狀態S13）。於本實施形態6的加強線形成步驟中，除了閘極電極2的形成數量以外，藉由與所述實施形態5相同的方法，於同一步驟中於樹脂基材1上形成閘極電極2及加強線31～加強線38。於本實施形態6的第一絕緣層形成步驟中，除了閘極絕緣層3覆蓋的閘極電極2的數量以外，藉由與所述實施形態5相同的方法，於所述閘極電極2上形成閘極絕緣層3。此時，閘極絕緣層3可如圖19A所示形成為覆蓋2個1組的閘極電極2，亦可形成於加強線31～加強線38上，亦可形成於形成有閘極電極2及加強線31～加強線38的樹脂基材1的整個面。於本實施形態6的半導體層形成步驟中，除了半導體層4的形成圖案以外，藉由與所述實施形態5相同的方法，於所述閘極絕緣層3上形成半導體層4。In the method of manufacturing the substrate 50H for a semiconductor device, first, as shown in FIG. 19A, a reinforcement line forming step (state S11) of forming the gate electrode 2 and forming the reinforcement line 31 to the reinforcement line 38 is performed, and the gate electrode is formed. The first insulating layer forming step of forming the insulating layer 3 (state S12), and the semiconductor layer forming step of forming the semiconductor layer 4 (state S13). In the reinforcing line forming step of the sixth embodiment, except for the number of gate electrodes 2 formed, the gate electrode 2 and the gate electrode 2 are formed on the resin substrate 1 in the same step by the same method as that of the fifth embodiment. Reinforced line 31～reinforced line 38. In the first insulating layer forming step of the sixth embodiment, except for the number of gate electrodes 2 covered by the gate insulating layer 3, the same method as that of the fifth embodiment is used to form the gate electrode 2 The gate insulating layer 3 is formed. At this time, the gate insulating layer 3 may be formed as shown in FIG. 19A to cover the two gate electrodes 2 in one group, or may be formed on the reinforcing wire 31 to the reinforcing wire 38, or may be formed on the gate electrode 2 formed thereon. And the entire surface of the resin base material 1 of the reinforcing wire 31 to the reinforcing wire 38. In the semiconductor layer forming step of the sixth embodiment, except for the formation pattern of the semiconductor layer 4, the semiconductor layer 4 is formed on the gate insulating layer 3 by the same method as that of the fifth embodiment.

其次，如圖19B的狀態S14所示，實施進行源極/汲極電極的形成的電極形成步驟。於本實施形態6的電極形成步驟中，除了源極/汲極電極的形成數量以外，藉由與所述實施形態5相同的方法，於所述閘極絕緣層3及半導體層4上形成源極電極5及汲極電極6。此時，於所述加強線形成步驟中，亦可於同一步驟中形成源極電極5及汲極電極6與加強線31～加強線38來代替於同一步驟中形成閘極電極2與加強線31～加強線38。於所述步驟中，加強線31～加強線38的材料是與構成源極電極5及汲極電極6的材料相同的材料。Next, as shown in the state S14 of FIG. 19B, an electrode forming step of forming source/drain electrodes is performed. In the electrode formation step of the sixth embodiment, except for the number of source/drain electrodes formed, the source is formed on the gate insulating layer 3 and the semiconductor layer 4 by the same method as that of the fifth embodiment. Pole electrode 5 and drain electrode 6. At this time, in the step of forming the reinforcement line, the source electrode 5, the drain electrode 6 and the reinforcement line 31 to the reinforcement line 38 can also be formed in the same step instead of forming the gate electrode 2 and the reinforcement line in the same step. 31～Strengthen line 38. In the above steps, the material of the reinforcing wire 31 to the reinforcing wire 38 is the same material as the material constituting the source electrode 5 and the drain electrode 6.

其次，如圖19B的狀態S15所示，實施進行第二絕緣層7的形成與第二加強線51～第二加強線58的形成的第二加強線形成步驟。於所述第二加強線形成步驟中，於同一步驟中進行於所述多個半導體層4中的一部分半導體層4上形成第二絕緣層7的步驟、以及於所述加強線31～加強線38上形成第二加強線51～第二加強線58的步驟。此時，第二加強線51～第二加強線58的材料是與構成第二絕緣層7的材料相同的材料。Next, as shown in the state S15 of FIG. 19B, a second reinforcement line forming step of forming the second insulating layer 7 and forming the second reinforcement line 51 to the second reinforcement line 58 is performed. In the second reinforcement line forming step, the step of forming the second insulating layer 7 on a part of the semiconductor layers 4 of the plurality of semiconductor layers 4 and the reinforcement line 31 to the reinforcement line are performed in the same step. 38 is a step of forming the second reinforcement line 51 to the second reinforcement line 58. At this time, the material of the second reinforcing wire 51 to the second reinforcing wire 58 is the same material as the material constituting the second insulating layer 7.

作為第二絕緣層7及第二加強線51～第二加強線58的形成方法，並無特別限定，亦可使用電阻加熱蒸鍍、電子束、濺鍍、CVD等乾式方法，就製造成本或適合於大面積的觀點而言，較佳為使用塗佈法。作為所述塗佈法，具體而言，可較佳地使用旋塗法、刮塗法、縫模塗佈法、網版印刷法、棒塗機法、鑄模法、印刷轉印法、浸漬提拉法、噴墨法、滴鑄法等。可對應於塗膜厚度控制或配向控制等所欲獲得的塗膜特性來選擇第二絕緣層7及第二加強線51～第二加強線58的塗佈法。另外，於所述第二加強線形成步驟中，亦可於大氣下、減壓下或惰性氣體環境下（氮氣或氬氣環境下）對所形成的塗膜進行退火處理。The method for forming the second insulating layer 7 and the second reinforcing wire 51 to the second reinforcing wire 58 is not particularly limited. Dry methods such as resistance heating vapor deposition, electron beam, sputtering, CVD, etc. can also be used. From the viewpoint of being suitable for a large area, it is preferable to use a coating method. As the coating method, specifically, a spin coating method, a blade coating method, a slot die coating method, a screen printing method, a bar coater method, a mold method, a printing transfer method, and a dip coating method can be preferably used. Pull method, inkjet method, drop casting method, etc. The coating method of the second insulating layer 7 and the second reinforcing wire 51 to the second reinforcing wire 58 can be selected in accordance with the desired coating film characteristics such as coating film thickness control or alignment control. In addition, in the step of forming the second reinforcement line, the formed coating film may also be annealed under the atmosphere, under reduced pressure, or in an inert gas environment (under nitrogen or argon atmosphere).

於將藉由輥對輥方式連續地搬運的樹脂基材1捲繞成卷狀時，與第二加強線51～第二加強線54（於樹脂基材1的長邊方向上延伸存在的第二加強線）對應的樹脂基材1的部位因它們的重疊而樹脂基材1的輥厚度變厚。藉此，可防止於被捲繞時於卷狀的樹脂基材1內產生的局部且不均勻的厚度不均。其結果，可抑制由捲成卷狀的樹脂基材1與第二絕緣層7摩擦所引起的第二絕緣層7的剝離。When the resin base material 1 continuously conveyed by the roll-to-roll method is wound into a roll, the second reinforcement line 51 to the second reinforcement line 54 (the first extending in the longitudinal direction of the resin base material 1 The second reinforcement line) corresponds to the position of the resin base material 1 due to their overlap, so that the roll thickness of the resin base material 1 becomes thick. Thereby, it is possible to prevent local and uneven thickness unevenness that occurs in the roll-shaped resin base material 1 when being wound. As a result, it is possible to suppress the peeling of the second insulating layer 7 caused by the friction between the resin substrate 1 and the second insulating layer 7 wound in a roll.

根據以上說明的實施形態5、實施形態6的半導體裝置用基板的製造方法，多個半導體裝置以各自包括具有底部閘極結構的場效型電晶體的方式形成於樹脂基材上，且於同一步驟中進行場效型電晶體中所含的閘極電極的形成與加強線的形成，因此可於形成閘極電極後立即藉由加強線控制樹脂基材內的伸縮。因此，於之後的絕緣層形成步驟或源極電極及汲極電極的形成步驟中，對位精度提高，可抑制樹脂基材面內的多個場效型電晶體的特性偏差。According to the method of manufacturing a semiconductor device substrate of Embodiment 5 and Embodiment 6 described above, a plurality of semiconductor devices are formed on a resin substrate so as to each include a field-effect transistor having a bottom gate structure, and are on the same substrate. The formation of the gate electrode contained in the field-effect transistor and the formation of the reinforcing wire are performed in the step. Therefore, the reinforcing wire can be used to control the expansion and contraction in the resin substrate immediately after the gate electrode is formed. Therefore, in the subsequent insulating layer formation step or the source electrode and drain electrode formation step, the alignment accuracy is improved, and it is possible to suppress the variation in the characteristics of the plurality of field-effect transistors in the surface of the resin base material.

另外，於具有長邊方向與短邊方向的樹脂基材上以於樹脂基材上的長邊方向上形成列的方式形成多個半導體裝置，於半導體裝置的列的兩個外緣部中，於樹脂基材的長邊方向上大致連續地設置加強線的一部分，因此於大致連續地形成的加強線重疊的同時樹脂基材被捲繞，其結果，樹脂基材的卷狀態變得牢固，且可抑制被捲繞成卷狀的樹脂基材的卷未對準。另外，於樹脂基材面形成多個由大致連續地形成的加強線包圍半導體裝置的區域，因此於半導體裝置用基板暴露於濕度或溫度等環境的變化時，可於每個由大致連續的加強線包圍的區域中控制樹脂基材面內的伸縮的偏差。因此，於大致連續地形成多個半導體裝置時，可提高大致連續的樹脂基材面的每個區域的對位精度，可抑制樹脂基材面上的多個半導體裝置的特性偏差。In addition, a plurality of semiconductor devices are formed on a resin substrate having a long-side direction and a short-side direction so as to form rows in the long-side direction on the resin substrate, and in the two outer edge portions of the row of semiconductor devices, A part of the reinforcing wire is provided substantially continuously in the longitudinal direction of the resin base material, so that the resin base material is wound while the substantially continuously formed reinforcing wires overlap, and as a result, the rolled state of the resin base material becomes firm. In addition, it is possible to suppress the misalignment of the roll of the resin base material wound into a roll shape. In addition, a plurality of areas of the semiconductor device are surrounded by reinforcement lines formed substantially continuously on the surface of the resin base material. Therefore, when the semiconductor device substrate is exposed to environmental changes such as humidity or temperature, each area can be substantially continuously reinforced. In the area enclosed by the line, the deviation of expansion and contraction in the surface of the resin base material is controlled. Therefore, when a plurality of semiconductor devices are formed substantially continuously, the alignment accuracy of each region of the substantially continuous resin substrate surface can be improved, and the characteristic variation of the plurality of semiconductor devices on the resin substrate surface can be suppressed.

再者，本發明的半導體裝置用基板的製造方法並不限定於所述實施形態5、實施形態6的製造方法，例如亦可為藉由輥對輥方式以外的方法連續或斷續地搬運樹脂基材且於所述樹脂基材上形成多個半導體裝置及加強線的方法。另外，較佳為於同一步驟中進行半導體裝置中所含的電極層中的至少一者的形成與加強線的形成。即，亦可於同一步驟中進行源極電極及汲極電極的形成與加強線的形成。In addition, the manufacturing method of the semiconductor device substrate of the present invention is not limited to the manufacturing methods of the fifth and sixth embodiments. For example, the resin may be continuously or intermittently conveyed by a method other than the roll-to-roll method. A method of forming a plurality of semiconductor devices and reinforcing wires on the resin substrate. In addition, it is preferable to perform the formation of at least one of the electrode layers included in the semiconductor device and the formation of the reinforcing wires in the same step. That is, the formation of the source electrode and the drain electrode and the formation of the reinforcement line can also be performed in the same step.

另外，圖18A、圖18B及圖19A、圖19B所例示的FET的結構是閘極電極2配置於半導體層4的下側（樹脂基材1側）的所謂的底部閘極結構，但並不限於此。例如，所述FET的結構亦可為閘極電極2配置於半導體層4的上側（與樹脂基材1為相反的一側）的所謂的頂部閘極結構。雖未特別圖示，但於所述FET的結構為頂部閘極結構的情況下，加強線31～加強線38較佳為由與位於半導體層4的下側的源極電極5及汲極電極6相同的材料，設置於與該些源極電極5及汲極電極6相同的層。In addition, the structure of the FET illustrated in FIGS. 18A, 18B, 19A, and 19B is a so-called bottom gate structure in which the gate electrode 2 is arranged on the lower side of the semiconductor layer 4 (the resin substrate 1 side), but it is not Limited to this. For example, the structure of the FET may also be a so-called top gate structure in which the gate electrode 2 is arranged on the upper side of the semiconductor layer 4 (the side opposite to the resin substrate 1). Although not shown in particular, when the structure of the FET is a top gate structure, the reinforcing lines 31 to 38 are preferably connected to the source electrode 5 and the drain electrode located on the lower side of the semiconductor layer 4. 6 The same material is arranged on the same layer as the source electrode 5 and drain electrode 6.

根據以上，無論所述FET的結構為底部閘極結構或者為頂部閘極結構，加強線31～加強線38由與所述FET中所含的源極電極5、汲極電極6及閘極電極2中位於靠近樹脂基材1的一側（例如半導體層4的下部側）的基材側的電極相同的材料設置於與所述基材側的電極相同的層的情況容易抑制樹脂基材1的變形，因此較佳。其中，所述FET的結構較佳為底部閘極結構。原因在於：可自形成閘極電極2時開始抑制樹脂基材1的變形，因此可容易抑制之後的閘極電極2與源極電極5及汲極電極6的對位等構成元件結構的FET的構件的圖案偏移。According to the above, no matter the structure of the FET is a bottom gate structure or a top gate structure, the reinforcing line 31 to the reinforcing line 38 are connected to the source electrode 5, the drain electrode 6 and the gate electrode contained in the FET. In 2, the case where the electrode on the substrate side located on the side close to the resin substrate 1 (for example, the lower side of the semiconductor layer 4) of the same material is provided on the same layer as the electrode on the substrate side is likely to suppress the resin substrate 1 The deformation is therefore better. Wherein, the structure of the FET is preferably a bottom gate structure. The reason is that the deformation of the resin substrate 1 can be suppressed from the time the gate electrode 2 is formed, so the subsequent alignment of the gate electrode 2 with the source electrode 5 and the drain electrode 6 can be easily suppressed. The pattern of the component is offset.

＜無線通訊裝置＞ 其次，對本發明中使用的半導體裝置（例如圖1等中所示的半導體裝置10）為無線通訊裝置的情況進行說明。所述無線通訊裝置例如是如商品標籤、防竊標簽、各種票或智慧卡之類的使用無線電波進行資訊的通訊的裝置。所述無線通訊裝置例如是如RFID標籤般藉由接收自搭載於外部的讀寫器的天線發送的無線信號（載波）而進行電氣通訊的裝置。＜Wireless communication device＞ Next, a case where the semiconductor device used in the present invention (for example, the semiconductor device 10 shown in FIG. 1 and the like) is a wireless communication device will be described. The wireless communication device is, for example, a device that uses radio waves to communicate information, such as commodity tags, anti-theft tags, various tickets, or smart cards. The wireless communication device is, for example, a device that performs electrical communication by receiving a wireless signal (carrier wave) transmitted from an antenna of a reader/writer mounted on the outside, like an RFID tag.

作為無線通訊裝置的一例的RFID標籤的具體動作例如如下所述。RFID標籤的天線接收自搭載於讀寫器的天線發送的無線信號。RFID標簽內的FET基於所述接收到的無線信號取得命令，進行與所述命令相應的動作。之後，RFID標籤將與該指令相對應的結果的回答以無線信號的形式從自身天線朝向讀寫器天線發送。再者，與指令相對應的動作由包含FET的公知的解調電路、動作控制邏輯電路、調變電路等來進行。The specific operation of an RFID tag as an example of a wireless communication device is as follows, for example. The antenna of the RFID tag receives the wireless signal transmitted from the antenna mounted on the reader/writer. The FET in the RFID tag acquires a command based on the received wireless signal, and performs an operation corresponding to the command. After that, the RFID tag sends the answer to the result corresponding to the instruction in the form of a wireless signal from its own antenna to the reader/writer antenna. Furthermore, the operation corresponding to the command is performed by a well-known demodulation circuit, operation control logic circuit, modulation circuit, etc. including FETs.

本發明中使用的無線通訊裝置的較佳的實施形態至少具有所述FET與天線。圖20是表示應用於本發明的無線通訊裝置的第一結構例的示意圖。圖21是表示應用於本發明的無線通訊裝置的第二結構例的示意圖。作為本發明中的無線通訊裝置的更具體的結構，可列舉圖20或圖21所示的一例。即，如圖20或圖21所示，無線通訊裝置110、無線通訊裝置110A包括基板100，於所述基板100上包括：天線圖案101、包含FET的電路102、以及連接該些電路102與天線圖案101的連接配線103。於該些無線通訊裝置110、無線通訊裝置110A中，基板100是藉由將所述本發明的半導體裝置用基板的樹脂基材（例如圖1等中所示的樹脂基材1）按照每個半導體裝置切分而形成。A preferred embodiment of the wireless communication device used in the present invention has at least the FET and antenna. Fig. 20 is a schematic diagram showing a first configuration example of a wireless communication device applied to the present invention. Fig. 21 is a schematic diagram showing a second configuration example of the wireless communication device applied to the present invention. As a more specific structure of the wireless communication device in the present invention, an example shown in FIG. 20 or FIG. 21 can be cited. That is, as shown in FIG. 20 or FIG. 21, the wireless communication device 110 and the wireless communication device 110A include a substrate 100. The substrate 100 includes an antenna pattern 101, a circuit 102 including an FET, and connecting these circuits 102 and an antenna The connection wiring 103 of the pattern 101. In the wireless communication device 110 and the wireless communication device 110A, the substrate 100 is formed by using the resin substrate of the semiconductor device substrate of the present invention (for example, the resin substrate 1 shown in FIG. 1 and the like) according to each The semiconductor device is divided and formed.

於本發明的半導體裝置用基板的製造方法中，於多個半導體裝置各自為無線通訊裝置的情況下，可獲得於同一樹脂基材上形成有如上所述的多個無線通訊裝置的半導體裝置用基板。本發明的無線通訊裝置的製造方法包括將此種半導體裝置用基板按照每個無線通訊裝置切分的切斷步驟。具體而言，於所述無線通訊裝置的製造方法中，藉由利用所述切斷步驟將所述半導體裝置用基板按照每個無線通訊裝置切分，可分別獲得無線通訊裝置。In the method of manufacturing a substrate for a semiconductor device of the present invention, when the plurality of semiconductor devices are each a wireless communication device, it is possible to obtain a semiconductor device in which a plurality of wireless communication devices as described above are formed on the same resin base material. Substrate. The manufacturing method of the wireless communication device of the present invention includes a cutting step of dividing such a substrate for a semiconductor device for each wireless communication device. Specifically, in the method of manufacturing the wireless communication device, by using the cutting step to separate the semiconductor device substrate for each wireless communication device, wireless communication devices can be obtained separately.

另外，於本發明的半導體裝置用基板的製造方法中，於多個半導體裝置各自為無線通訊裝置中的電路（例如圖20、圖21中所示的電路102）的情況下，可獲得於樹脂基材上形成有該些多個電路102的半導體裝置用基板。本發明的無線通訊裝置的製造方法包括：切斷步驟，將此種半導體裝置用基板按照每個所述無線通訊裝置的電路切分；以及貼附步驟，將藉由所述切斷步驟切分的所述無線通訊裝置的電路貼合至天線。具體而言，於所述無線通訊裝置的製造方法中，於藉由所述切斷步驟而將所述半導體裝置用基板按照每個電路102分別切分後，藉由所述貼附步驟而將所獲得的多個電路102分別貼合至天線。藉此，該些電路102與天線（例如圖20、圖21中所示的天線圖案101）藉由所述連接配線103等配線而連接。其結果，可獲得無線通訊裝置。In addition, in the method of manufacturing a substrate for a semiconductor device of the present invention, when each of the plurality of semiconductor devices is a circuit in a wireless communication device (for example, the circuit 102 shown in FIG. 20 and FIG. 21), it can be obtained from resin A substrate for a semiconductor device in which the plurality of circuits 102 are formed on a base material. The manufacturing method of the wireless communication device of the present invention includes: a cutting step of dividing such a substrate for a semiconductor device according to the circuit of each wireless communication device; and an attaching step of dividing the substrate by the cutting step The circuit of the wireless communication device is attached to the antenna. Specifically, in the method of manufacturing the wireless communication device, after the semiconductor device substrate is divided for each circuit 102 in the cutting step, the bonding step is used to separate The obtained multiple circuits 102 are respectively attached to the antenna. Thereby, the circuits 102 and the antenna (for example, the antenna pattern 101 shown in FIG. 20 and FIG. 21) are connected by wiring such as the connection wiring 103. As a result, a wireless communication device can be obtained.

或者，本發明的無線通訊裝置的製造方法包括：貼附步驟，將形成於所述半導體裝置用基板的無線通訊裝置的電路102與天線貼合；以及切斷步驟，將藉由所述貼附步驟使電路102與天線貼合後的半導體裝置用基板按照每個無線通訊裝置（包括該些電路102與天線的裝置）切分。具體而言，於所述無線通訊裝置的製造方法中，於藉由所述貼附步驟而將形成有多個電路102的半導體裝置用基板的電路部分與天線貼合後，藉由所述切斷步驟而將包括電路102與所述天線的無線通訊裝置分別切分。於所述貼附步驟中，該些電路102與天線由配線連接。其結果，可獲得無線通訊裝置。Alternatively, the method of manufacturing a wireless communication device of the present invention includes: an attaching step of attaching the circuit 102 of the wireless communication device formed on the semiconductor device substrate to the antenna; In the step, the semiconductor device substrate after the circuit 102 and the antenna are bonded is divided for each wireless communication device (devices including the circuit 102 and the antenna). Specifically, in the method of manufacturing the wireless communication device, after the circuit portion of the semiconductor device substrate on which the plurality of circuits 102 are formed and the antenna are bonded by the bonding step, the cutting is performed The disconnection step separates the wireless communication device including the circuit 102 and the antenna respectively. In the attaching step, the circuits 102 and the antenna are connected by wiring. As a result, a wireless communication device can be obtained.

於所述無線通訊裝置的製造方法中，天線材料及連接配線材料只要為導電材料，則可為任意者。具體而言，作為所述導電材料，可列舉與閘極電極材料相同的材料。其中，就柔軟性增加、於彎曲時密接性亦良好且電性連接變得良好的方面而言，較佳為含有導電體與黏合劑的糊材料。就製造成本減少的觀點而言，天線材料及連接配線材料較佳為彼此為相同的材料。In the method of manufacturing the wireless communication device, the antenna material and the connection wiring material may be any one as long as they are conductive materials. Specifically, as the conductive material, the same material as the gate electrode material can be cited. Among them, in terms of increased flexibility, good adhesion during bending, and improved electrical connection, a paste material containing a conductor and a binder is preferred. From the viewpoint of reducing the manufacturing cost, the antenna material and the connection wiring material are preferably the same material as each other.

作為形成天線圖案及連接配線圖案的圖案形成方法，有如下方法等：使用沖刀對銅箔或鋁箔等金屬箔進行加工並轉印至樹脂基材的方法；將形成於金屬箔上的抗蝕劑層作為遮罩，對貼附於樹脂基材的金屬箔進行蝕刻的方法；藉由塗佈法於樹脂基材形成導電性糊的圖案，並藉由熱或光而使該圖案硬化的方法。其中，就製造成本減少的觀點而言，較佳為於樹脂基材塗佈導電糊而形成的方法。As a pattern formation method for forming the antenna pattern and the connection wiring pattern, there are the following methods: a method of processing metal foil such as copper or aluminum foil with a punching knife and transferring it to a resin substrate; The agent layer is used as a mask to etch the metal foil attached to the resin substrate; the method of forming a conductive paste pattern on the resin substrate by a coating method and hardening the pattern by heat or light . Among them, from the viewpoint of reducing the manufacturing cost, a method of coating a conductive paste on a resin substrate is preferred.

另外，於使用含有導電體與黏合劑的糊作為所述導電材料的情況下，亦可列舉使用旋塗法、刮塗法、縫模塗佈法、網版印刷法、棒塗機法、鑄模法、印刷轉印法、浸漬提拉法等公知的技術將所述糊塗佈於樹脂基材上並使用烘箱、加熱板、紅外線等來進行乾燥的方法等作為所述圖案形成方法的一例。另外，天線圖案及連接配線圖案可將藉由所述方法製作的導電膜利用公知的光微影法等而圖案形成為所需形狀，亦可於真空蒸鍍或濺鍍時介隔所需形狀的遮罩來進行圖案形成。In addition, in the case of using a paste containing a conductor and a binder as the conductive material, the use of spin coating method, doctor blade method, slot die coating method, screen printing method, bar coater method, and mold A method in which the paste is applied to a resin substrate and dried using an oven, a hot plate, infrared rays, etc., by well-known techniques such as a printing transfer method, a dipping and pulling method, etc., is an example of the pattern forming method. In addition, the antenna pattern and the connection wiring pattern can be patterned into a desired shape by using a known photolithography method or the like to pattern the conductive film produced by the above method, and the desired shape can also be interposed during vacuum evaporation or sputtering. The mask is used for pattern formation.

進而，天線圖案及連接配線圖案較佳為與FET的閘極電極及配線由相同的材料構成。原因在於：可減少無線通訊裝置的製造所需的材料的種類且藉由於同一步驟中製作所述天線圖案及連接配線圖案與FET的閘極電極及配線，可削減無線通訊裝置的製造步驟數，其結果，可減少無線通訊裝置的製造成本。Furthermore, it is preferable that the antenna pattern and the connection wiring pattern are made of the same material as the gate electrode and wiring of the FET. The reason is that the types of materials required for the manufacture of wireless communication devices can be reduced, and the number of manufacturing steps of wireless communication devices can be reduced by making the antenna pattern and connecting wiring pattern and the gate electrode and wiring of the FET in the same step. As a result, the manufacturing cost of the wireless communication device can be reduced.

所謂「天線圖案及連接配線圖案與FET的閘極電極及配線由相同的材料構成」，是指天線圖案及連接配線圖案與FET的閘極電極及配線中所含的元素中含有莫耳比率最高的元素相同。天線圖案及連接配線圖案與FET的閘極電極及配線中所含的元素的種類及含有比率可藉由X射線光電子分光（XPS）或二次離子質量分析法（SIMS）等的元素分析進行鑑定。The so-called "antenna pattern and connection wiring pattern are composed of the same material as the gate electrode and wiring of the FET" means that the elements contained in the antenna pattern and connection wiring pattern and the gate electrode and wiring of the FET have the highest molar ratio. The elements are the same. The type and content ratio of the elements contained in the antenna pattern and the connecting wiring pattern and the gate electrode and wiring of the FET can be identified by elemental analysis such as X-ray photoelectron spectroscopy (XPS) or secondary ion mass analysis (SIMS) .

若於同一步驟中製作天線圖案、連接配線圖案、FET的閘極電極及配線，則天線圖案與連接配線圖案的連接部、以及連接配線圖案與FET的閘極電極用配線的連接部分別以連續相形成。就天線圖案、連接配線圖案、FET的閘極電極及配線的密接性、製造成本減少的觀點而言，天線圖案、連接配線圖案、FET的閘極電極及配線較佳為以形成連續相的方式形成。所謂「天線圖案、連接配線圖案、FET的閘極電極及配線圖案為連續相」，是指該些圖案一體化且於該些的連接部不存在連接界面的情況。所述連接部為連續相的情況可藉由利用掃描式電子顯微鏡（SEM）或穿透式電子顯微鏡（TEM）等對連接部的剖面進行觀察來確認。If the antenna pattern, the connection wiring pattern, the gate electrode and wiring of the FET are produced in the same step, the connection part of the antenna pattern and the connection wiring pattern and the connection part of the connection wiring pattern and the gate electrode of the FET are respectively continuous Phase formation. From the viewpoint of the adhesion of the antenna pattern, the connection wiring pattern, the gate electrode of the FET and the wiring, and the reduction in manufacturing cost, the antenna pattern, the connection wiring pattern, the gate electrode of the FET, and the wiring are preferably formed in a continuous phase form. "The antenna pattern, the connection wiring pattern, the gate electrode of the FET, and the wiring pattern are continuous phases" refers to the case where these patterns are integrated and there is no connection interface at the connection portion. The fact that the connection part is a continuous phase can be confirmed by observing the cross section of the connection part with a scanning electron microscope (SEM), a transmission electron microscope (TEM), or the like.

於本發明中，天線圖案與連接配線圖案的連接部的寬度及厚度、以及連接配線圖案與FET的閘極電極用配線的連接部的寬度及厚度分別為任意。 [實施例]In the present invention, the width and thickness of the connection portion between the antenna pattern and the connection wiring pattern, and the width and thickness of the connection portion between the wiring pattern and the gate electrode wiring of the FET are arbitrary. [Example]

以下，基於實施例對本發明進一步進行具體的說明。再者，本發明並不限定於下述實施例。Hereinafter, the present invention will be further specifically described based on examples. In addition, the present invention is not limited to the following examples.

（感光性糊的製作） （合成例1） 於合成例1中，合成作為感光性有機成分的化合物P1。所述化合物P1的合成中的共聚比率為如下所述。 共聚比率（質量基準）：丙烯酸乙酯（Ethyl Acrylate）（以下為「EA」）/甲基丙烯酸2-乙基己酯（2-Ethylhexyl Methacrylate）（以下為「2-EHMA」）/苯乙烯（Styrene）（以下為「St」）/甲基丙烯酸縮水甘油酯（Glycidyl Methacrylate）（以下為「GMA」）/丙烯酸（Acrylic Acid）（以下為「AA」）=20/40/20/5/15(Production of photosensitive paste) (Synthesis example 1) In Synthesis Example 1, compound P1 as a photosensitive organic component was synthesized. The copolymerization ratio in the synthesis of the compound P1 is as follows. Copolymerization ratio (quality basis): Ethyl Acrylate (hereinafter referred to as "EA") / 2-Ethylhexyl Methacrylate (hereinafter referred to as "2-EHMA") / styrene ( Styrene (hereinafter referred to as "St") / Glycidyl Methacrylate (hereinafter referred to as "GMA") / Acrylic Acid (hereinafter referred to as "AA") = 20/40/20/5/15

具體而言，首先，於氮氣環境的反應容器中，放入150 g的二乙二醇單乙醚乙酸酯（Diethylene Glycol Monoethyl Ether Acetate）（以下為「DMEA」），使用油浴（oil bath）升溫至80℃為止。於其中，歷時1小時滴加包含20 g的EA、40 g的2-EHMA、20 g的St、15 g的AA、0.8 g的2,2'-偶氮雙異丁腈及10 g的DMEA的混合物。於滴加結束後，進而進行6小時聚合反應。之後，添加1 g的對苯二酚單甲醚而停止聚合反應。繼而，歷時0.5小時滴加包含5 g的GMA、1 g的三乙基苄基氯化銨及10 g的DMEA的混合物。於滴加結束後，進而進行2小時加成反應。利用甲醇對所獲得的反應溶液進行純化，藉此將未反應的雜質去除，進而藉由進行24小時真空乾燥而獲得化合物P1。Specifically, first, put 150 g of Diethylene Glycol Monoethyl Ether Acetate (hereinafter referred to as "DMEA") in a reaction vessel in a nitrogen atmosphere, and use an oil bath. The temperature is increased to 80°C. To it, dropwise add 20 g of EA, 40 g of 2-EHMA, 20 g of St, 15 g of AA, 0.8 g of 2,2'-azobisisobutyronitrile and 10 g of DMEA over 1 hour. mixture. After completion of the dropwise addition, the polymerization reaction was further carried out for 6 hours. After that, 1 g of hydroquinone monomethyl ether was added to stop the polymerization reaction. Then, a mixture containing 5 g of GMA, 1 g of triethylbenzylammonium chloride, and 10 g of DMEA was added dropwise over 0.5 hours. After the dropwise addition was completed, the addition reaction was further carried out for 2 hours. The obtained reaction solution was purified with methanol to remove unreacted impurities, and then the compound P1 was obtained by vacuum drying for 24 hours.

（合成例2） 於合成例2中，合成作為感光性有機成分的化合物P2。所述化合物P2的合成中的共聚比率為如下所述。 共聚比率（質量基準）：二官能環氧丙烯酸酯單體（環氧酯（epoxy ester）3002A；共榮社化學公司製造）/二官能環氧丙烯酸酯單體（環氧酯70PA；共榮社化學公司製造）/GMA/St/AA=20/40/5/20/15(Synthesis example 2) In Synthesis Example 2, compound P2 as a photosensitive organic component was synthesized. The copolymerization ratio in the synthesis of the compound P2 is as follows. Copolymerization ratio (quality basis): difunctional epoxy acrylate monomer (epoxy ester (epoxy ester) 3002A; manufactured by Kyoeisha Chemical Co., Ltd.)/difunctional epoxy acrylate monomer (epoxy ester 70PA; Kyoeisha) Made by chemical company)/GMA/St/AA=20/40/5/20/15

具體而言，首先，於氮氣環境的反應容器中，放入150 g的二乙二醇單乙醚乙酸酯（以下為「DMEA」），使用油浴升溫至80℃為止。於其中，歷時1小時滴加包含20 g的環氧酯3002A、40 g的環氧酯70PA、20 g的St、15 g的AA、0.8 g的2,2'-偶氮雙異丁腈及10 g的DMEA的混合物。於滴加結束後，進而進行6小時聚合反應。之後，添加1 g的對苯二酚單甲醚而停止聚合反應。繼而，歷時0.5小時滴加包含5 g的GMA、1 g的三乙基苄基氯化銨及10 g的DMEA的混合物。於滴加結束後，進而進行2小時加成反應。利用甲醇對所獲得的反應溶液進行純化，藉此將未反應的雜質去除，進而藉由進行24小時真空乾燥而獲得化合物P2。Specifically, first, 150 g of diethylene glycol monoethyl ether acetate (hereinafter referred to as "DMEA") is put in a reaction vessel in a nitrogen atmosphere, and the temperature is raised to 80°C using an oil bath. Among them, the epoxy ester 3002A containing 20 g, epoxy ester 70PA 40 g, St, 20 g, AA 15 g, 0.8 g 2,2'-azobisisobutyronitrile and 0.8 g of epoxy ester were added dropwise over 1 hour. A mixture of 10 g of DMEA. After completion of the dropwise addition, the polymerization reaction was further carried out for 6 hours. After that, 1 g of hydroquinone monomethyl ether was added to stop the polymerization reaction. Then, a mixture containing 5 g of GMA, 1 g of triethylbenzylammonium chloride, and 10 g of DMEA was added dropwise over 0.5 hours. After the dropwise addition was completed, the addition reaction was further carried out for 2 hours. The obtained reaction solution was purified with methanol to remove unreacted impurities, and then the compound P2 was obtained by vacuum drying for 24 hours.

（合成例3） 於合成例3中，合成作為感光性有機成分的化合物P3。化合物P3是所述合成例2的化合物P2的胺基甲酸酯改質化合物。(Synthesis example 3) In Synthesis Example 3, compound P3 as a photosensitive organic component was synthesized. Compound P3 is a urethane-modified compound of Compound P2 of Synthesis Example 2.

具體而言，首先，於氮氣環境的反應容器中，放入100 g的DMEA，使用油浴升溫至80℃為止。於其中，歷時1小時滴加包含10 g的化合物P2（合成例2的感光性成分）、3.5 g的正己基異氰酸酯及10 g的DMEA。於滴加結束後，進而進行3小時反應。利用甲醇對所獲得的反應溶液進行純化，藉此將未反應的雜質去除，進而藉由進行24小時真空乾燥而獲得具有胺基甲酸酯鍵的化合物P3。Specifically, first, 100 g of DMEA is put in a reaction vessel in a nitrogen atmosphere, and the temperature is raised to 80°C using an oil bath. To this, 10 g of compound P2 (the photosensitive component of Synthesis Example 2), 3.5 g of n-hexyl isocyanate, and 10 g of DMEA were added dropwise over 1 hour. After the dropwise addition was completed, the reaction was further carried out for 3 hours. The obtained reaction solution was purified with methanol to remove unreacted impurities, and then vacuum-dried for 24 hours to obtain compound P3 having a urethane bond.

（製備例1） 於製備例1中，製備感光性糊A。具體而言，首先，於100 mL的清潔瓶（clean bottle）中，加入藉由所述合成例1而獲得的化合物P1（16 g）、藉由所述合成例3而獲得的化合物P3（4 g）、共榮社化學公司製造的萊特丙烯酸酯（Light Acrylate）BP-4EA（2 g）、巴斯夫（BASF）日本公司製造的光聚合起始劑OXE-1（4 g）、三新化學工業公司製造的酸產生劑SI-110（0.6 g）、以及三菱氣體化學公司製造的γ-丁內酯（10 g），利用自轉-公轉真空混合機「去泡攪拌太郎」（註冊商標）（ARE-310；新基（THINKY）公司製造）進行混合。藉此，獲得製備例1的感光性樹脂溶液（固體成分78.5質量%）。此時，感光性樹脂溶液的質量為34.6 g。將該獲得的感光性樹脂溶液（8.0 g）與平均粒徑0.06 μm的Ag粒子（42.0 g）予以混合，使用三輥「艾卡特（EXAKT）M-50」（商品名，艾卡特（EXAKT）公司製造）來進行混練。藉此，獲得50 g的感光性糊A。(Preparation Example 1) In Preparation Example 1, photosensitive paste A was prepared. Specifically, first, the compound P1 (16 g) obtained by the synthesis example 1 and the compound P3 (4) obtained by the synthesis example 3 were added to a 100 mL clean bottle (clean bottle). g) Light Acrylate BP-4EA (2 g) manufactured by Kyoeisha Chemical Co., Photopolymerization initiator OXE-1 (4 g) manufactured by BASF Japan Co., Ltd., Sanshin Chemical Industry The acid generator SI-110 (0.6 g) manufactured by the company and the γ-butyrolactone (10 g) manufactured by Mitsubishi Gas Chemical Co., Ltd. are used in the rotation-revolution vacuum mixer "Defoaming Stirring Taro" (registered trademark) (ARE -310; made by THINKY company) for mixing. Thereby, the photosensitive resin solution (solid content 78.5% by mass) of Preparation Example 1 was obtained. At this time, the mass of the photosensitive resin solution was 34.6 g. The obtained photosensitive resin solution (8.0 g) and Ag particles (42.0 g) with an average particle diameter of 0.06 μm were mixed, and a three-roller "EXAKT M-50" (trade name, EXAKT) was used. Made by the company) for mixing. Thus, 50 g of photosensitive paste A was obtained.

（製備例2） 於製備例2中，製備感光性糊B。具體而言，首先，於清潔瓶中，加入25.0 g的鹼可溶性樹脂的溶液（40質量%）、作為光聚合起始劑的1.5 g的豔佳固（Irgacure）（註冊商標）OXE02（肟酯系化合物；巴斯夫（BASF）公司製造）、5.5 g的萊特丙烯酸酯（Light Acrylate）（註冊商標）PE-4A（共榮社化學公司製造）及作為分散劑的2.0 g的迪斯帕畢克（DISPERBYK）（註冊商標）140（日本畢克化學公司製造）（胺價：146 mgKOH/g），利用自轉公轉混合機「去泡攪拌太郎」（註冊商標）（ARE-310；新基（THINKY）公司製造）進行混合。藉此，獲得製備例2的感光性樹脂溶液。將所述製備例2中獲得的感光性樹脂溶液（8.0 g）與平均粒徑0.06 μm的Ag粒子（42.0 g）予以混合，進而以固體成分比率成為80質量%的方式加入DMEA後，使用三輥「艾卡特（EXAKT）M-50」（商品名，艾卡特（EXAKT）公司製造）來進行混練。藉此，獲得感光性糊B。(Preparation Example 2) In Preparation Example 2, photosensitive paste B was prepared. Specifically, first, 25.0 g of an alkali-soluble resin solution (40% by mass) and 1.5 g of Irgacure (registered trademark) OXE02 (oxime ester) as a photopolymerization initiator were added to a clean bottle. Compound; BASF (BASF) company), 5.5 g of Light Acrylate (registered trademark) PE-4A (manufactured by Kyoeisha Chemical Co., Ltd.) and 2.0 g of Disparbic as a dispersant DISPERBYK) (registered trademark) 140 (manufactured by BYK Chemical Co., Japan) (amine price: 146 mgKOH/g), using a rotation and revolution mixer "Defoaming Stirring Taro" (registered trademark) (ARE-310; THINKY) Company manufacturing) for mixing. In this way, the photosensitive resin solution of Preparation Example 2 was obtained. The photosensitive resin solution (8.0 g) obtained in Preparation Example 2 was mixed with Ag particles (42.0 g) with an average particle diameter of 0.06 μm, and DMEA was added so that the solid content ratio became 80% by mass, and then three Roll "EXAKT M-50" (trade name, manufactured by EXAKT Corporation) for kneading. In this way, photosensitive paste B was obtained.

（製備例3） 於製備例3中，製備感光性糊C。具體而言，除了使用平均粒徑0.15 μm的Ag粒子以外，利用與所述製備例2相同的方法進行製備，藉此獲得感光性糊C。(Preparation Example 3) In Preparation Example 3, photosensitive paste C was prepared. Specifically, except that Ag particles with an average particle diameter of 0.15 μm were used, the preparation was performed by the same method as the preparation example 2 described above, whereby the photosensitive paste C was obtained.

（半導體溶液的製作） 於半導體溶液的製作中，首先，於含有2.0 mg的P3HT（奧德里奇（Aldrich）公司製造，聚(3-己基噻吩)）的氯仿溶液（10 mL）中加入1.0 mg的CNT（CNI公司製造，單層CNT，純度95%），一邊進行冰浴冷卻一邊使用超音波均質機（東京理化器械公司製造，VCX-500）以輸出20%進行4小時超音波攪拌。藉此獲得CNT分散液A11（相對於溶媒的CNT複合體濃度為0.96 g/l者）。(Production of semiconductor solution) In the preparation of the semiconductor solution, first, 1.0 mg of CNT (manufactured by CNI) was added to a chloroform solution (10 mL) containing 2.0 mg of P3HT (manufactured by Aldrich, poly(3-hexylthiophene)). , Single-layer CNT, purity 95%), while cooling in an ice bath, use an ultrasonic homogenizer (manufactured by Tokyo Rikaki Co., Ltd., VCX-500) to perform ultrasonic stirring with an output of 20% for 4 hours. Thereby, CNT dispersion liquid A11 (the CNT composite concentration relative to the solvent is 0.96 g/l) was obtained.

其次，使用薄膜過濾器（孔徑10 μm、直徑25 mm、密理博（Millipore）公司製造的歐米泊薄膜（Omnipore Membrane））進行所述CNT分散液A11的過濾，將長度10 μm以上的CNT複合體去除。於藉此所獲得的濾液中加入5 mL的鄰二氯苯（ortho dichlorobenzene，o-DCB）（和光純藥工業公司製造）後，使用旋轉蒸發器將作為低沸點溶媒的氯仿蒸餾去除，藉此利用o-DCB對溶媒進行置換，從而獲得CNT分散液B11。於CNT分散液B11（1 mL）中加入3 mL的o-DCB，藉此獲得半導體溶液A10（相對於溶媒的CNT複合體濃度為0.03 g/l者）。Secondly, a membrane filter (10 μm in pore size, 25 mm in diameter, Omnipore Membrane manufactured by Millipore) was used to filter the CNT dispersion A11, and the CNT composite with a length of 10 μm or more was filtered. Remove. After adding 5 mL of ortho dichlorobenzene (o-DCB) (manufactured by Wako Pure Chemical Industries, Ltd.) to the obtained filtrate, chloroform, which is a low-boiling solvent, was distilled off using a rotary evaporator, thereby The solvent was replaced with o-DCB to obtain CNT dispersion liquid B11. 3 mL of o-DCB was added to the CNT dispersion B11 (1 mL), thereby obtaining a semiconductor solution A10 (with a CNT composite concentration of 0.03 g/l relative to the solvent).

（閘極絕緣層的製作例） 於閘極絕緣層的製作例中，製作閘極絕緣層溶液A20。具體而言，首先，將甲基三甲氧基矽烷（61.29 g（0.45莫耳））、2-(3,4-環氧環己基)乙基三甲氧基矽烷（12.31 g（0.05莫耳））及苯基三甲氧基矽烷（99.15 g（0.5莫耳））溶解於203.36 g的丙二醇單丁醚（沸點170℃）中。於其中，一邊攪拌一邊加入水（54.90 g）及磷酸（0.864 g）。將藉此所獲得的溶液於浴溫105℃下加熱2小時，使內溫上昇至90℃為止，使主要包含副產生的甲醇的成分餾出。繼而，於浴溫130℃下加熱2小時，使內溫上昇至118℃為止，使主要包含水與丙二醇單丁醚的成分餾出。之後，冷卻至室溫，從而獲得固體成分濃度為26.0重量%的聚矽氧烷溶液A3。所獲得的聚矽氧烷溶液A3中的聚矽氧烷的重量平均分子量為6000。(Production example of gate insulating layer) In the example of making the gate insulating layer, the gate insulating layer solution A20 was made. Specifically, first, methyl trimethoxysilane (61.29 g (0.45 mol)), 2-(3,4-epoxycyclohexyl) ethyl trimethoxysilane (12.31 g (0.05 mol)) And phenyl trimethoxysilane (99.15 g (0.5 mol)) was dissolved in 203.36 g of propylene glycol monobutyl ether (boiling point 170°C). To it, add water (54.90 g) and phosphoric acid (0.864 g) while stirring. The solution obtained in this way was heated at a bath temperature of 105°C for 2 hours, the internal temperature was raised to 90°C, and a component mainly containing by-produced methanol was distilled out. Then, heating was carried out at a bath temperature of 130°C for 2 hours, the internal temperature was raised to 118°C, and the components mainly containing water and propylene glycol monobutyl ether were distilled out. After that, it was cooled to room temperature to obtain a polysiloxane solution A3 having a solid content concentration of 26.0% by weight. The weight average molecular weight of the polysiloxane in the obtained polysiloxane solution A3 was 6000.

其次，將所獲得的聚矽氧烷溶液A3秤取10 g，於其中，混合54.4 g的丙二醇單乙醚乙酸酯（以下，稱為PGMEA），於室溫下攪拌2小時。如此，獲得閘極絕緣層溶液A20。Next, 10 g of the obtained polysiloxane solution A3 was weighed, and 54.4 g of propylene glycol monoethyl ether acetate (hereinafter referred to as PGMEA) was mixed therein, and stirred at room temperature for 2 hours. In this way, a gate insulating layer solution A20 was obtained.

（第二絕緣層的製作例） 於第二絕緣層的製作例中，製作第二絕緣層溶液A30。具體而言，首先，將2.5 g的聚甲基丙烯酸甲酯（富士膠片和光純藥公司製造）溶解於7.5 g的N,N-二甲基甲醯胺中，製備聚合物溶液A31。其次，將1 g的N,N,N',N'-四甲基-1,4-苯二胺（東京化成工業公司製造）溶解於9.0 g的N,N-二甲基甲醯胺中，製備化合物溶液A32。之後，於聚合物溶液A31（0.68 g）中添加化合物溶液A32（0.30 g），藉此獲得第二絕緣層溶液A30。(Production example of the second insulating layer) In the manufacturing example of the second insulating layer, the second insulating layer solution A30 was prepared. Specifically, first, 2.5 g of polymethyl methacrylate (manufactured by Fujifilm Wako Pure Chemical Industries, Ltd.) was dissolved in 7.5 g of N,N-dimethylformamide to prepare a polymer solution A31. Next, 1 g of N,N,N',N'-tetramethyl-1,4-phenylenediamine (manufactured by Tokyo Chemical Industry Co., Ltd.) was dissolved in 9.0 g of N,N-dimethylformamide , Compound solution A32 was prepared. After that, the compound solution A32 (0.30 g) was added to the polymer solution A31 (0.68 g), thereby obtaining a second insulating layer solution A30.

（實施例1） 於實施例1中，製作了作為本發明的實施形態1的半導體裝置用基板50（參照圖1）的一具體例的半導體裝置用基板。所述實施例1的半導體裝置用基板是具有底部閘極-頂部接觸結構的場效型電晶體作為半導體裝置的類型的半導體裝置用基板。圖22A是表示本發明的實施例1的半導體裝置用基板的製造方法的第一步驟例的示意圖。圖22B是表示本發明的實施例1的半導體裝置用基板的製造方法的第二步驟例的示意圖。(Example 1) In Example 1, a semiconductor device substrate as a specific example of the semiconductor device substrate 50 (see FIG. 1) of the first embodiment of the present invention was produced. The semiconductor device substrate of the first embodiment is a semiconductor device substrate of a type in which a field-effect transistor having a bottom gate-top contact structure is used as a semiconductor device. 22A is a schematic diagram showing a first step example of the method of manufacturing a substrate for a semiconductor device according to the first embodiment of the present invention. 22B is a schematic diagram showing a second step example of the manufacturing method of the semiconductor device substrate according to the first embodiment of the present invention.

具體而言，首先，於PET膜製的樹脂基材1（寬度300 mm、長度420 mm、膜厚50 μm）上，利用電阻加熱法，於100 nm整個面上真空蒸鍍銅。於其上利用狹縫塗佈整個面印刷光阻劑（商品名「LC100-10cP」，羅門哈斯（Rohm and Haas）公司製造），並於100℃下藉由熱風乾燥爐加熱乾燥4分鐘。介隔設計有閘極電極2的有效遮罩尺寸為280 mm×400 mm的光罩，對藉此製作的光阻劑膜進行曝光量為60 mJ/cm2 （以波長365 nm換算）的全線曝光。設計於所述光罩的閘極電極寬度為100 μm。於曝光後，利用2.38重量%的氫氧化四甲基銨水溶液進行30秒顯影，繼而利用水清洗1分鐘。之後，利用混合酸（商品名SEA-5，關東化學公司製造）進行30秒蝕刻處理後，利用水清洗30秒。繼而，於AZ去除劑（AZ REMOVER）100（商品名，安智電子材料（AZ Electronic Materials）公司製造）中浸漬2分鐘，將光阻劑膜剝離，利用水清洗30秒後，利用氣刀去除水滴，之後，於80℃下藉由熱風乾燥爐加熱乾燥60秒。藉此，如圖22A所示，於樹脂基材1的面上形成9處閘極電極2（狀態S21）。Specifically, first, on a resin substrate 1 (width 300 mm, length 420 mm, and film thickness 50 μm) made of a PET film, copper was vacuum vapor-deposited on the entire surface of 100 nm by the resistance heating method. A photoresist (trade name "LC100-10cP", manufactured by Rohm and Haas) was coated on the entire surface using a slit, and heated and dried in a hot air drying oven at 100°C for 4 minutes. A photomask with an effective mask size of 280 mm×400 mm is designed with gate electrode 2 in the intermediary, and the photoresist film produced therefrom is exposed to a full line of 60 mJ/cm 2 (converted to a wavelength of 365 nm) exposure. The width of the gate electrode designed on the photomask is 100 μm. After the exposure, development was performed with a 2.38% by weight tetramethylammonium hydroxide aqueous solution for 30 seconds, and then washed with water for 1 minute. Then, after performing an etching process for 30 seconds with a mixed acid (trade name SEA-5, manufactured by Kanto Chemical Co., Ltd.), it was washed with water for 30 seconds. Then, immerse in AZ REMOVER 100 (trade name, manufactured by AZ Electronic Materials) for 2 minutes, peel off the photoresist film, rinse with water for 30 seconds, and remove it with an air knife The water droplets are then heated and dried in a hot-air drying oven at 80°C for 60 seconds. Thereby, as shown in FIG. 22A, nine gate electrodes 2 are formed on the surface of the resin base material 1 (state S21).

之後，利用狹縫塗佈整個面連續印刷作為閘極絕緣層3的閘極絕緣層溶液A20，藉由熱風乾燥爐於大氣環境下、100℃下進行3分鐘熱處理，藉由紅外線（Infrared，IR）乾燥爐於氮氣環境下、150℃下進行20分鐘熱處理。藉此，如圖22A所示，於樹脂基材1上形成膜厚500 nm的閘極絕緣層3（狀態S22）。After that, the gate insulating layer solution A20, which is the gate insulating layer 3, is continuously printed on the entire surface by slit coating, and heat-treated in a hot air drying oven at 100°C for 3 minutes in an atmospheric environment. Infrared (Infrared, IR) ) The drying furnace is heat-treated at 150°C for 20 minutes in a nitrogen environment. Thereby, as shown in FIG. 22A, the gate insulating layer 3 with a film thickness of 500 nm is formed on the resin substrate 1 (state S22).

於如上所述形成有閘極絕緣層3的樹脂基材1上，在作為投影9處閘極電極2的位置的閘極絕緣層3上的各部分，分別利用噴墨法塗佈100 pL的半導體溶液A10，利用IR乾燥爐於氮氣流下、150℃下進行30分鐘熱處理。藉此，如圖22A所示，於閘極絕緣層3上的9處形成半導體層4（狀態S23）。On the resin substrate 1 on which the gate insulating layer 3 is formed as described above, 100 pL of each part on the gate insulating layer 3 as the position of the gate electrode 2 at the projection 9 is coated by inkjet method. The semiconductor solution A10 was heat-treated in an IR drying furnace at 150°C for 30 minutes under a nitrogen stream. Thereby, as shown in FIG. 22A, the semiconductor layer 4 is formed at 9 locations on the gate insulating layer 3 (state S23).

其次，藉由網版印刷於形成有所述閘極絕緣層3的PET膜製的樹脂基材1上塗佈感光性糊A。此時，感光性糊A以印刷尺寸280 mm×400 mm、以與形成閘極電極2及加強線31～加強線38時的曝光區域重疊的方式塗佈。繼而，藉由熱風乾燥爐於100℃下對所述塗佈的感光性糊A進行4分鐘預烘烤。之後，介隔設計有源極電極5及汲極電極6的有效遮罩尺寸280 mm×400 mm的光罩，以與塗佈了感光性糊A的區域重疊的方式進行曝光量80 mJ/cm2 （以波長365 nm換算）的全線曝光。於曝光後利用0.5%的Na2 CO3 溶液進行30秒顯影，於利用超純水清洗60秒後，利用IR乾燥爐於150℃下進行10分鐘固化。藉此，如圖22B所示，於閘極絕緣層3上形成9處源極電極5及汲極電極6（狀態S24）。將源極電極5及汲極電極6的寬度設為100 μm，將該些電極間的距離設為20 μm。Next, a photosensitive paste A is applied on the resin substrate 1 made of a PET film on which the gate insulating layer 3 is formed by screen printing. At this time, the photosensitive paste A is applied in a printing size of 280 mm×400 mm so as to overlap the exposure area when the gate electrode 2 and the reinforcing lines 31 to 38 are formed. Then, the applied photosensitive paste A was pre-baked at 100°C for 4 minutes in a hot-air drying oven. After that, the effective mask size of the source electrode 5 and the drain electrode 6 is designed to be 280 mm×400 mm, and the exposure amount is 80 mJ/cm so that it overlaps the area where the photosensitive paste A is applied. 2 Full-line exposure (converted with wavelength of 365 nm). After exposure, it was developed with a 0.5% Na 2 CO 3 solution for 30 seconds, washed with ultrapure water for 60 seconds, and then cured at 150° C. for 10 minutes in an IR drying oven. Thereby, as shown in FIG. 22B, 9 source electrodes 5 and drain electrodes 6 are formed on the gate insulating layer 3 (state S24). The width of the source electrode 5 and the drain electrode 6 was set to 100 μm, and the distance between these electrodes was set to 20 μm.

其次，將利用DMEA 2倍稀釋感光性糊B後的糊噴墨塗佈於形成有源極電極5及汲極電極6的PET膜製的樹脂基材1上而形成加強線31～加強線38的圖案，藉由熱風乾燥爐於大氣環境下、100℃下進行4分鐘熱處理。之後，以曝光量80 mJ/cm2 （以波長365 nm換算）進行全線曝光。於曝光後利用IR乾燥爐於150℃下進行10分鐘固化，藉此，如圖22B所示，形成加強線31～加強線38（狀態S25）。Next, the paste obtained by diluting the photosensitive paste B twice with DMEA is ink-jet coated on the resin substrate 1 made of PET film on which the source electrode 5 and the drain electrode 6 are formed to form the reinforcing lines 31 to 38 The pattern is heat-treated in a hot-air drying oven at 100°C for 4 minutes in an atmospheric environment. After that, the exposure amount is 80 mJ/cm 2 (converted to a wavelength of 365 nm) for full-line exposure. After the exposure, curing is performed at 150° C. for 10 minutes in an IR drying oven, whereby, as shown in FIG. 22B, the reinforcing lines 31 to 38 are formed (state S25).

以所述方式獲得了實施例1的半導體裝置用基板。對所獲得的半導體裝置用基板測定改變FET的閘極電壓（Vg）時的源極/汲極電極間的電流（Id）與源極/汲極電極間的電壓（Vsd）的電流-電壓特性。於所述測定中使用半導體特性評價系統4200-SCS型（吉時利儀器（Keithley Instruments）公司製造），於大氣下測定所述特性。於實施例1中，測量於Vg=+5 V～-5 V的範圍內變化時的Vsd=-5 V下的Vg=-5 V時的Id的值。之後，將樣品投入至85℃、85%RH的恆溫恆濕槽中24小時，取出樣品後再次測定於Vg=+5 V～-5 V的範圍內變化時的Vsd=-5 V下的Vg=-5 V時的Id的值。對9處FET全部進行所述測定，計算出該些9處FET的平均值及標準偏差，按照以下基準進行評價。將實施例1的結果示於後述表1中。 A（良好）：相對於平均值而言標準偏差為15%以內。 B（合格）：相對於平均值而言標準偏差大於15%且為30%以內。 C（不合格）：相對於平均值而言標準偏差大於30%。In the manner described above, the semiconductor device substrate of Example 1 was obtained. For the obtained semiconductor device substrate, the current-voltage characteristics of the current between the source/drain electrodes (Id) and the voltage between the source/drain electrodes (Vsd) when the gate voltage (Vg) of the FET was changed were measured . For the measurement, a semiconductor characteristic evaluation system 4200-SCS (manufactured by Keithley Instruments) was used, and the characteristics were measured under the atmosphere. In Example 1, the value of Id when Vsd=-5 V and Vg=-5 V when Vg=+5 V to -5 V is changed. After that, put the sample in a constant temperature and humidity chamber at 85°C and 85%RH for 24 hours, take out the sample and measure again when Vg=+5 V～-5 V Vsd=Vg at -5 V = The value of Id at -5 V. The measurement was performed on all 9 FETs, the average value and standard deviation of these 9 FETs were calculated, and the evaluation was performed according to the following criteria. The result of Example 1 is shown in Table 1 mentioned later. A (good): The standard deviation is within 15% relative to the average. B (Pass): The standard deviation is greater than 15% and within 30% relative to the average. C (Failure): The standard deviation is greater than 30% relative to the average.

（比較例1） 於比較例1中，除了不實施實施例1中的加強線31～加強線38的形成步驟以外，利用與實施例1相同的方法進行與實施例1相同的評價。將比較例1的評價結果示於表1中。(Comparative example 1) In Comparative Example 1, the same evaluation as in Example 1 was performed by the same method as in Example 1, except that the steps of forming the reinforcing wires 31 to 38 in Example 1 were not implemented. The evaluation results of Comparative Example 1 are shown in Table 1.

[表1] （表1）   恆溫恆濕環境試驗前 恆溫恆濕環境試驗後 平均值[μA] 標準偏差 平均值[μA] 標準偏差 實施例1 1.3 A 1.5 A 比較例1 1.2 A 1.5 C [Table 1] (Table 1) Before the constant temperature and humidity environment test After constant temperature and humidity environment test Average value [μA] standard deviation Average value [μA] standard deviation Example 1 1.3 A 1.5 A Comparative example 1 1.2 A 1.5 C

（實施例2） 於實施例2中，製作了作為本發明的實施形態5的半導體裝置用基板50E（參照圖6）的一具體例的半導體裝置用基板。所述實施例2的半導體裝置用基板是具有底部閘極-頂部接觸結構的場效型電晶體作為半導體裝置的類型的基板，於藉由輥對輥方式搬運樹脂基材1的同時連續地製作（參照圖17、圖18A、圖18B）。(Example 2) In Example 2, a semiconductor device substrate as a specific example of the semiconductor device substrate 50E (see FIG. 6) of the fifth embodiment of the present invention was produced. The semiconductor device substrate of the second embodiment is a type of substrate with a field-effect transistor having a bottom gate-top contact structure as a semiconductor device, and is continuously manufactured while transporting the resin substrate 1 by a roll-to-roll method (Refer to Figure 17, Figure 18A, Figure 18B).

具體而言，首先，於PET膜製的樹脂基材1（寬度300 mm、長度50 m、膜厚50 μm）上，利用電阻加熱法，於100 nm整個面上真空蒸鍍銅。於其上利用狹縫塗佈整個面連續印刷光阻劑（商品名「LC100-10cP」，羅門哈斯（Rohm and Haas）公司製造），並於100℃下藉由熱風乾燥爐加熱乾燥4分鐘。介隔設計有閘極電極2及加強線31～加強線38的有效遮罩尺寸為280 mm×400 mm的光罩，於曝光量為60 mJ/cm2 （以波長365 nm換算）且樹脂基材1的進給量為420 mm的條件下，對藉此製作的光阻劑膜進行100次全線曝光。將設計於所述光罩的閘極電極寬度設為100 μm，將加強線31～加強線38的寬度設為1 mm，將加強線31～加強線34的長度設為370 mm，將加強線35～加強線38的長度設為280 mm。於曝光後，利用2.38重量%的氫氧化四甲基銨水溶液進行30秒顯影，繼而利用水清洗1分鐘。之後，利用混合酸（商品名SEA-5，關東化學公司製造）進行30秒蝕刻處理後，利用水清洗30秒。繼而，於AZ去除劑（AZ REMOVER）100（商品名，安智電子材料（AZ Electronic Materials）公司製造）中浸漬2分鐘，將光阻劑膜剝離，利用水清洗30秒後，利用氣刀去除水滴，之後，於80℃下藉由熱風乾燥爐加熱乾燥60秒。藉此，如圖18A所示，於樹脂基材1的面上每一處曝光區域形成9處閘極電極2與加強線31～加強線38（狀態S1）。Specifically, first, on a resin substrate 1 (width 300 mm, length 50 m, and film thickness 50 μm) made of a PET film, copper was vacuum vapor-deposited on the entire surface of 100 nm by the resistance heating method. Coat the entire surface with a slit to print a photoresist (trade name "LC100-10cP", manufactured by Rohm and Haas), and heat and dry it in a hot air drying oven at 100°C for 4 minutes . The effective mask size is 280 mm×400 mm with gate electrode 2 and reinforcing lines 31～38 designed in the intervening space. The exposure amount is 60 mJ/cm 2 (converted to the wavelength of 365 nm) and resin-based Under the condition that the feed rate of the material 1 is 420 mm, the photoresist film thus produced is subjected to 100 full-line exposures. The width of the gate electrode designed on the mask is set to 100 μm, the width of the reinforcement line 31 to the reinforcement line 38 is set to 1 mm, the length of the reinforcement line 31 to the reinforcement line 34 is set to 370 mm, and the reinforcement line The length of the 35-reinforcement line 38 is set to 280 mm. After the exposure, development was performed with a 2.38% by weight tetramethylammonium hydroxide aqueous solution for 30 seconds, and then washed with water for 1 minute. Then, after performing an etching process for 30 seconds with a mixed acid (trade name SEA-5, manufactured by Kanto Chemical Co., Ltd.), it was washed with water for 30 seconds. Then, immerse in AZ REMOVER 100 (trade name, manufactured by AZ Electronic Materials) for 2 minutes, peel off the photoresist film, rinse with water for 30 seconds, and remove it with an air knife The water droplets are then heated and dried in a hot-air drying oven at 80°C for 60 seconds. As a result, as shown in FIG. 18A, 9 gate electrodes 2 and reinforcing lines 31 to 38 are formed in each exposed area on the surface of the resin substrate 1 (state S1).

之後，利用狹縫塗佈整個面連續印刷作為閘極絕緣層3的閘極絕緣層溶液A20，藉由熱風乾燥爐於大氣環境下、100℃下進行3分鐘熱處理，藉由IR乾燥爐於氮氣環境下、150℃下進行20分鐘熱處理。藉此，如圖18A所示，於樹脂基材1上形成膜厚500 nm的閘極絕緣層3（狀態S2）。After that, the gate insulating layer solution A20 as the gate insulating layer 3 was continuously printed using slit coating on the entire surface, and heat-treated in a hot air drying oven at 100°C for 3 minutes in an atmospheric environment, and an IR drying oven in nitrogen Heat treatment at 150°C for 20 minutes under ambient conditions. Thereby, as shown in FIG. 18A, the gate insulating layer 3 with a film thickness of 500 nm is formed on the resin substrate 1 (state S2).

於如上所述形成有閘極絕緣層3的樹脂基材1上，在作為投影9處閘極電極2的位置的閘極絕緣層3上的各部分，分別利用噴墨法塗佈100 pL的半導體溶液A10，利用IR乾燥爐於氮氣流下、150℃下進行30分鐘熱處理。藉此，如圖18B所示，於閘極絕緣層3上的9處形成半導體層4（狀態S3）。On the resin substrate 1 on which the gate insulating layer 3 is formed as described above, 100 pL of each part on the gate insulating layer 3 as the position of the gate electrode 2 at the projection 9 is coated by inkjet method. The semiconductor solution A10 was heat-treated in an IR drying furnace at 150°C for 30 minutes under a nitrogen stream. Thereby, as shown in FIG. 18B, the semiconductor layer 4 is formed at 9 locations on the gate insulating layer 3 (state S3).

其次，藉由網版印刷於形成有所述閘極絕緣層3的PET膜製的樹脂基材1上塗佈感光性糊A。此時，感光性糊A是以印刷尺寸280 mm×400 mm、以與形成閘極電極2及加強線31～加強線38時的曝光區域重疊的方式，將樹脂基材1的進給量設為420 mm並塗佈100次。繼而，藉由熱風乾燥爐於100℃下對所述塗佈的感光性糊A進行4分鐘預烘烤。之後，介隔設計有源極電極5及汲極電極6的有效遮罩尺寸280 mm×400 mm的光罩，以與塗佈了感光性糊A的區域重疊的方式以曝光量80 mJ/cm2 （以波長365 nm換算）、樹脂基材1的進給量為420 mm間距（pitch）進行全線曝光。於曝光後利用0.5%的Na2 CO3 溶液進行30秒顯影，於利用超純水清洗60秒後，利用IR乾燥爐於150℃下進行10分鐘固化。藉此，如圖18B所示，於閘極絕緣層3上形成9處源極電極5及汲極電極6（狀態S4）。將源極電極5及汲極電極6的寬度設為100 μm，將該些電極間的距離設為20 μm。Next, a photosensitive paste A is applied on the resin substrate 1 made of a PET film on which the gate insulating layer 3 is formed by screen printing. At this time, the photosensitive paste A has a printing size of 280 mm×400 mm, and sets the feed amount of the resin base material 1 so as to overlap with the exposure area when the gate electrode 2 and the reinforcing lines 31 to 38 are formed. It is 420 mm and applied 100 times. Then, the applied photosensitive paste A was pre-baked at 100°C for 4 minutes in a hot-air drying oven. After that, the effective mask size of the source electrode 5 and the drain electrode 6 was designed to be 280 mm×400 mm, and the exposure amount was 80 mJ/cm so as to overlap the area where the photosensitive paste A was applied. 2 (Converted with a wavelength of 365 nm), the feed rate of the resin substrate 1 is 420 mm pitch (pitch) for full-line exposure. After exposure, it was developed with a 0.5% Na 2 CO 3 solution for 30 seconds, washed with ultrapure water for 60 seconds, and then cured at 150° C. for 10 minutes in an IR drying oven. Thereby, as shown in FIG. 18B, 9 source electrodes 5 and drain electrodes 6 are formed on the gate insulating layer 3 (state S4). The width of the source electrode 5 and the drain electrode 6 was set to 100 μm, and the distance between these electrodes was set to 20 μm.

以所述方式獲得了實施例2的半導體裝置用基板。對所獲得的半導體裝置用基板進行以下的第一項目～第四項目中說明的各評價。將第一項目及第二項目的各評價的結果示於表2中，將第三項目的評價的結果示於表3中，將第四項目的評價的結果示於表4中。The semiconductor device substrate of Example 2 was obtained in the manner described above. Each evaluation described in the following items 1 to 4 was performed on the obtained substrate for a semiconductor device. The results of each evaluation of the first item and the second item are shown in Table 2, the results of the evaluation of the third item are shown in Table 3, and the results of the evaluation of the fourth item are shown in Table 4.

（第一項目：卷未對準試驗） 於第一項目中，對半導體裝置用基板的卷未對準試驗進行說明。於第一項目的卷未對準試驗中，以寬度為320 mm、直徑為3吋的ABS芯為中心，以±1 mm精度將寬度為300 mm、長度為50 m的半導體裝置用基板捲繞成卷狀。之後，利用數位遊標卡尺測定在與所述ABS芯的寬度方向垂直的方向上使所述卷狀的半導體裝置用基板自10 cm的高度落下時的輥捲繞寬度。基於所獲得的輥捲繞寬度的測定值，按照以下基準進行卷未對準的評價。 A（良好）：輥捲繞寬度為301 mm以內。 B（合格）：輥捲繞寬度大於301 mm且為305 mm以內。 C（不合格）：輥捲繞寬度大於305 mm。(The first item: roll misalignment test) In the first item, a roll misalignment test of a substrate for a semiconductor device will be described. In the roll misalignment test of the first project, a semiconductor device substrate with a width of 300 mm and a length of 50 m was wound with an accuracy of ±1 mm centered on an ABS core with a width of 320 mm and a diameter of 3 inches. In a roll. After that, the roll winding width when the roll-shaped semiconductor device substrate was dropped from a height of 10 cm in a direction perpendicular to the width direction of the ABS core was measured with a digital vernier caliper. Based on the obtained measured value of the roll winding width, the evaluation of roll misalignment was performed according to the following criteria. A (Good): The roll winding width is within 301 mm. B (Qualified): The roll winding width is greater than 301 mm and within 305 mm. C (Unqualified): The roll winding width is greater than 305 mm.

（第二項目：膜厚的測定） 於第二項目中，對半導體裝置用基板的膜厚的測定進行說明。於第二項目的膜厚的測定中，自長度為50 m的半導體裝置用基板，以所述曝光步驟實施的進給間距將第1次至第100次的各部分（基板樣品）切出單張紙狀。於該些切出的基板樣品中，對於第10次、第50次、第90次的各基板樣品，使用掃描式電子顯微鏡（SEM）觀察剖面，自閘極電極測量任意5處的厚度（膜厚）且自加強線測量任意5處的厚度（膜厚）。對該些測量的閘極電極膜厚及加強線膜厚分別計算出平均值及標準偏差。(The second item: measurement of film thickness) In the second item, the measurement of the film thickness of the substrate for a semiconductor device will be described. In the measurement of the film thickness of the second item, from a semiconductor device substrate with a length of 50 m, each part (substrate sample) from the first to the 100th time was cut out at the feed pitch performed in the exposure step. Sheet of paper. Among these cut-out substrate samples, for each substrate sample of the 10th, 50th, and 90th times, the cross-section was observed using a scanning electron microscope (SEM), and the thickness (film) was measured at any five places from the gate electrode. Thickness) and measure the thickness (film thickness) at any 5 places from the reinforcement line. The average value and standard deviation of these measured gate electrode film thickness and reinforcing wire film thickness are calculated respectively.

（第三項目：FET的Id偏差的評價） 於第三項目中，對半導體裝置用基板上所形成的FET的Id偏差的評價進行說明。圖23是表示由實施例2的半導體裝置用基板所獲得的基板樣品的一例的示意圖。圖23中圖示了將自以卷狀連續的半導體裝置用基板切出的基板樣品（測定中使用的樣品）於其厚度方向上重疊所觀察時的投影圖。於第三項目的評價中，與所述第二項目的評價同樣地，使用自半導體裝置用基板切出的多個基板樣品中的第10次、第50次、第90次的各基板樣品，對圖23所示的9個FET 21～FET 29分別測定改變閘極電壓（Vg）時的源極/汲極電極間的電流（Id）與源極/汲極電極間的電壓（Vsd）的電流-電壓特性。於所述測定中使用半導體特性評價系統4200-SCS型（吉時利儀器（Keithley Instruments）公司製造），於大氣下進行測定。關於在Vg=+5 V～-5 V的範圍內變化時的Vsd=-5 V下的Vg=-5 V時的Id，對所述各次的每個基板樣品計算出基於9個FET 21～FET 29的平均值及標準偏差。基於所獲得的Id的平均值及標準偏差，按照以下基準進行了FET的Id偏差的評價。 A（良好）：相對於Id的平均值而言標準偏差為15%以內。 B（合格）：相對於Id的平均值而言標準偏差大於15%且為30%以內。 C（不合格）：相對於Id的平均值而言標準偏差大於30%。(The third item: Evaluation of FET Id deviation) In the third item, the evaluation of the Id deviation of the FET formed on the semiconductor device substrate will be described. FIG. 23 is a schematic diagram showing an example of a substrate sample obtained from the semiconductor device substrate of Example 2. FIG. FIG. 23 illustrates a projection view when a substrate sample (a sample used for measurement) cut out from a continuous roll-shaped substrate for a semiconductor device is superimposed in the thickness direction thereof and observed. In the evaluation of the third item, similar to the evaluation of the second item, the 10th, 50th, and 90th substrate samples among the plurality of substrate samples cut out from the semiconductor device substrate were used, For the 9 FETs 21 to FET 29 shown in FIG. 23, the current (Id) between the source/drain electrodes and the voltage (Vsd) between the source/drain electrodes when the gate voltage (Vg) is changed are measured. Current-voltage characteristics. For the measurement, a semiconductor characteristic evaluation system 4200-SCS model (manufactured by Keithley Instruments) was used, and the measurement was performed under the atmosphere. Regarding the Id when Vg=+5 V～-5 V when Vsd=-5 V and Vg=-5 V, the calculation is based on 9 FET 21 for each substrate sample of each time. ～The average value and standard deviation of FET 29. Based on the obtained average value and standard deviation of the Id, the Id deviation of the FET was evaluated according to the following criteria. A (good): The standard deviation is within 15% relative to the average value of Id. B (Pass): The standard deviation is greater than 15% and within 30% relative to the average value of Id. C (Fail): The standard deviation is greater than 30% relative to the average value of Id.

（第四項目：閘極電極圖案的座標測量） 於第四項目中，對半導體裝置用基板的閘極電極圖案的座標測量進行說明。於第四項目的測量中，與所述第二項目的評價同樣地，對於自半導體裝置用基板切出的多個基板樣品中的第10次、第50次、第90次的各基板樣品，使用座標測定機SMIC-800（新東超精密（Sinto S-Precision）公司製造），測量9個FET 21～FET 29（參照圖23）中的各閘極電極的座標，分別計算出半導體裝置用基板的長邊方向及短邊方向的標準偏差作為每次間的每個閘極電極的座標偏差。將所獲得的長邊方向的標準偏差及短邊方向的標準偏差中較大的值作為評價對象，按照以下基準進行閘極電極圖案的座標偏差的評價。於後述的表4中，「21」～「29」的數值是確定評價對象的各FET的數值（符號）。 A（良好）：標準偏差為20 μm以下。 B（合格）：標準偏差大於20 μm且為40 μm以下。 C（不合格）：標準偏差大於40 μm。(The fourth item: the coordinate measurement of the gate electrode pattern) In the fourth item, the coordinate measurement of the gate electrode pattern of the substrate for the semiconductor device will be described. In the measurement of the fourth item, similar to the evaluation of the second item, for each of the 10th, 50th, and 90th substrate samples among a plurality of substrate samples cut out from the substrate for a semiconductor device, Use the coordinate measuring machine SMIC-800 (manufactured by Sinto S-Precision) to measure the coordinates of each gate electrode in 9 FET 21 to FET 29 (refer to Figure 23), and calculate the coordinates for each of the semiconductor devices. The standard deviation of the long-side direction and the short-side direction of the substrate is used as the coordinate deviation of each gate electrode between each time. The larger value of the obtained standard deviation in the long-side direction and the standard deviation in the short-side direction was used as an evaluation target, and the coordinate deviation of the gate electrode pattern was evaluated according to the following criteria. In Table 4 to be described later, the numerical values of "21" to "29" are numerical values (symbols) that determine each FET to be evaluated. A (good): The standard deviation is 20 μm or less. B (Pass): The standard deviation is greater than 20 μm and less than 40 μm. C (Unqualified): The standard deviation is greater than 40 μm.

（實施例3） 於實施例3中，除了於形成閘極電極2及加強線31～加強線38時的電阻加熱法中，於60 nm的整個面真空蒸鍍鋁來代替銅以外，利用與實施例2相同的方法進行與實施例2的第一項目～第三項目的各評價相同的評價。將實施例3的評價結果示於表2及表3中。(Example 3) In Example 3, the same method as in Example 2 was used except that in the resistance heating method when forming the gate electrode 2 and the reinforcing wires 31 to 38, aluminum was vacuum deposited on the entire surface of 60 nm instead of copper. Method The same evaluations as those of the first item to the third item of Example 2 were performed. The evaluation results of Example 3 are shown in Tables 2 and 3.

（實施例4） 於實施例4中，製作了作為本發明的實施形態1的半導體裝置用基板50（參照圖1）的一具體例的半導體裝置用基板。所述實施例4的半導體裝置用基板是具有場效型電晶體作為半導體裝置的類型的半導體裝置用基板，與所述實施形態5同樣地，於藉由輥對輥方式搬運樹脂基材1的同時連續地製作。(Example 4) In Example 4, a semiconductor device substrate as a specific example of the semiconductor device substrate 50 (see FIG. 1) of the first embodiment of the present invention was produced. The semiconductor device substrate of the fourth embodiment is a semiconductor device substrate of a type having a field-effect transistor as a semiconductor device. As in the fifth embodiment, the resin substrate 1 is transported by a roll-to-roll method. Produce continuously at the same time.

具體而言，首先，於PET膜製的樹脂基材1（寬度300 mm、長度50 m、膜厚50 μm）上利用狹縫塗佈整個面連續印刷感光性糊B，藉由熱風乾燥爐於大氣環境下、100℃下進行4分鐘熱處理。介隔設計有閘極電極2及加強線31～加強線38的有效遮罩尺寸為280 mm×400 mm的光罩，於曝光量為80 mJ/cm2 （以波長365 nm換算）且樹脂基材1的進給量為420 mm間距的條件下，對藉此製作的塗佈膜進行全線曝光。於曝光後以2.38%的TMAH溶液進行30秒顯影，於利用超純水清洗60秒後，利用IR乾燥爐於150℃下進行10分鐘固化。藉此，於樹脂基材1的面上每一處曝光區域形成9處閘極電極2與加強線31～加強線38。利用與實施例2相同的方法進行閘極絕緣層3以後的步驟，並進行與實施例2相同的評價。將實施例4的評價結果示於表2～表4中。Specifically, first, the entire surface of the resin substrate 1 (width 300 mm, length 50 m, film thickness 50 μm) made of PET film was coated with a slit to continuously print the photosensitive paste B, and the photosensitive paste B was continuously printed in a hot-air drying oven. Heat treatment at 100°C for 4 minutes in an atmospheric environment. The effective mask size is 280 mm×400 mm with gate electrode 2 and reinforcing lines 31～38 designed in the intervening space. The exposure amount is 80 mJ/cm 2 (converted at the wavelength of 365 nm) and resin-based Under the condition that the feed amount of the material 1 is 420 mm pitch, the coating film produced thereby is exposed to the entire line. After exposure, it was developed with a 2.38% TMAH solution for 30 seconds, washed with ultrapure water for 60 seconds, and cured at 150°C for 10 minutes in an IR drying oven. In this way, 9 gate electrodes 2 and reinforcing lines 31 to 38 are formed in each exposed area on the surface of the resin substrate 1. The gate insulating layer 3 and subsequent steps were performed by the same method as in Example 2, and the same evaluation as in Example 2 was performed. The evaluation results of Example 4 are shown in Tables 2 to 4.

（實施例5） 於實施例5中，除了於形成閘極電極2及加強線31～加強線38時使用感光性糊C代替感光性糊B來進行狹縫塗佈以外，利用與實施例4相同的方法製作半導體裝置用基板，進行與實施例2的第一項目～第三項目的各評價相同的評價。將實施例5的評價結果示於表2及表3中。(Example 5) In Example 5, the semiconductor was produced by the same method as Example 4, except that the photosensitive paste C was used instead of the photosensitive paste B for slit coating when forming the gate electrode 2 and the reinforcing lines 31 to 38 when forming the gate electrode 2 and the reinforcing lines 31 to 38. For the device substrate, the same evaluations as those of the first item to the third item of Example 2 were performed. The evaluation results of Example 5 are shown in Tables 2 and 3.

（實施例6） 於實施例6中，製作了作為本發明的實施形態1的變形例的半導體裝置用基板（參照圖2）的一具體例的半導體裝置用基板。實施例6的半導體裝置用基板是具有底部閘極-頂部接觸結構的場效型電晶體作為半導體裝置的類型的半導體裝置用基板，於藉由輥對輥方式搬運（參照圖6）樹脂基材1的同時連續地製作。具體而言，除了使用自實施例1中使用的光罩的設計中去除了加強線33及加強線37的設計的光罩以外，利用與實施例1相同的方法進行實施例6的半導體裝置用基板的製作。另外，於實施例6中，進行了與實施例2的第一項目～第三項目的各評價相同的評價。將實施例6的評價結果示於表2及表3中。(Example 6) In Example 6, a semiconductor device substrate as a specific example of a semiconductor device substrate (see FIG. 2) of a modification of the first embodiment of the present invention was produced. The semiconductor device substrate of Example 6 is a type of semiconductor device substrate with a field-effect transistor with a bottom gate-top contact structure as a semiconductor device, and is transported by a roll-to-roll method (refer to Figure 6). The resin base material 1 is produced continuously at the same time. Specifically, the semiconductor device of Example 6 was used in the same manner as in Example 1, except that the design of the photomask used in Example 1 except for the design of the reinforcement line 33 and the reinforcement line 37 was used. Substrate production. In addition, in Example 6, the same evaluations as those of the first item to the third item of Example 2 were performed. The evaluation results of Example 6 are shown in Table 2 and Table 3.

（實施例7） 於實施例7中，製作了作為本發明的實施形態4的半導體裝置用基板50D（參照圖5）的一具體例的半導體裝置用基板。實施例7的半導體裝置用基板是具有底部閘極-頂部接觸結構的場效型電晶體作為半導體裝置的類型的半導體裝置用基板，於藉由輥對輥方式搬運（參照圖6）樹脂基材1的同時連續地製作。具體而言，對於實施例2中的形成閘極電極2及加強線31～加強線38的步驟與形成源極電極5及汲極電極6的步驟中使用的光罩而言，使用以加強線31～加強線38及半導體裝置10（實施例7中為FET）的配置設計成為圖5所示的本發明的實施形態4中的配置設計的方式設計的光罩，除此以外，利用與實施例2相同的方法製作實施例7的半導體裝置用基板。另外，於實施例7中，進行了與實施例2的第一項目～第三項目的各評價相同的評價。於實施例7中的第三項目的評價中，測定各基板樣品的13處FET中的任意9處FET，進行與實施例2相同的評價。將實施例7的評價結果示於表2及表3中。(Example 7) In Example 7, a semiconductor device substrate as a specific example of the semiconductor device substrate 50D (see FIG. 5) of the fourth embodiment of the present invention was produced. The semiconductor device substrate of Example 7 is a type of semiconductor device substrate with a field-effect transistor with a bottom gate-top contact structure as a semiconductor device, and is transported by a roll-to-roll method (refer to FIG. 6). The resin base material 1 is produced continuously at the same time. Specifically, for the photomask used in the step of forming the gate electrode 2 and the reinforcing wire 31 to the reinforcing wire 38 and the step of forming the source electrode 5 and the drain electrode 6 in the second embodiment, the reinforcing wire is used The layout design of the 31-stiffened wire 38 and the semiconductor device 10 (FET in the seventh embodiment) becomes the mask designed in the layout design of the fourth embodiment of the present invention shown in FIG. 5. In addition, the use and implementation The semiconductor device substrate of Example 7 was produced in the same manner as in Example 2. In addition, in Example 7, the same evaluations as those of the first item to the third item of Example 2 were performed. In the evaluation of the third item in Example 7, any 9 FETs out of 13 FETs of each substrate sample were measured, and the same evaluation as in Example 2 was performed. The evaluation results of Example 7 are shown in Tables 2 and 3.

（實施例8） 於實施例8中，製作了作為本發明的實施形態5的變形例1的半導體裝置用基板（參照圖6及圖7）的一具體例的半導體裝置用基板。實施例8的半導體裝置用基板是具有底部閘極-頂部接觸結構的場效型電晶體作為半導體裝置的類型的半導體裝置用基板，於藉由輥對輥方式搬運樹脂基材1的同時連續地製作。具體而言，對於實施例2中的形成閘極電極2及加強線31～加強線38的步驟中使用的光罩而言，使用以加強線31～加強線38及半導體裝置10（實施例8中為FET）的配置設計成為圖7所示的本發明的實施形態5的變形例1中的配置設計的方式設計的光罩，除此以外，利用與實施例2相同的方法製作實施例8的半導體裝置用基板。另外，於實施例8中，進行了與實施例2的第一項目～第三項目的各評價相同的評價。於實施例7中的第三項目的評價中，測定各基板樣品的13處FET中的任意9處FET，進行與實施例2相同的評價。將實施例8的評價結果示於表2及表3中。(Example 8) In Example 8, a semiconductor device substrate as a specific example of the semiconductor device substrate (see FIGS. 6 and 7) of Modification 1 of the fifth embodiment of the present invention was produced. The semiconductor device substrate of Example 8 is a semiconductor device substrate of a type in which a field-effect transistor having a bottom gate-top contact structure is used as a semiconductor device, and the resin substrate 1 is continuously conveyed by a roll-to-roll method. Make. Specifically, for the photomask used in the step of forming the gate electrode 2 and the reinforcing wire 31 to the reinforcing wire 38 in the second embodiment, the reinforcing wire 31 to the reinforcing wire 38 and the semiconductor device 10 are used (Example 8 The layout design of FET) is the mask designed in the layout design of Modification 1 of Embodiment 5 of the present invention shown in FIG. 7. Except for this, the same method as Example 2 was used to produce Example 8 Substrates for semiconductor devices. In addition, in Example 8, the same evaluations as those of the first item to the third item of Example 2 were performed. In the evaluation of the third item in Example 7, any 9 FETs out of 13 FETs of each substrate sample were measured, and the same evaluation as in Example 2 was performed. The evaluation results of Example 8 are shown in Tables 2 and 3.

（比較例2） 於比較例2中，除了使用未設計加強線31～加強線38的光罩作為實施例2中的形成閘極電極2及加強線31～加強線38的步驟中使用的光罩以外，利用與實施例2相同的方法進行與實施例2相同的評價。將比較例2的評價結果示於表2～表4中。(Comparative example 2) In Comparative Example 2, in addition to using a photomask without the reinforcement wires 31 to 38 as the photomask used in the step of forming the gate electrode 2 and the reinforcement wires 31 to the reinforcement wires 38 in Example 2, the use of and In the same manner as in Example 2, the same evaluation as in Example 2 was performed. The evaluation results of Comparative Example 2 are shown in Tables 2 to 4.

（比較例3） 於比較例3中，除了使用未設計加強線31～加強線38的光罩作為實施例4中的形成閘極電極2及加強線31～加強線38的步驟中使用的光罩以外，利用與實施例4相同的方法進行與實施例2相同的評價。將比較例3的評價結果示於表2～表4中。(Comparative example 3) In Comparative Example 3, in addition to the use of a photomask without the reinforcement wires 31 to 38 as the photomask used in the step of forming the gate electrode 2 and the reinforcement wires 31 to the reinforcement wires 38 in Example 4, and In the same manner as in Example 4, the same evaluation as in Example 2 was performed. The evaluation results of Comparative Example 3 are shown in Tables 2 to 4.

[表2] （表2）   卷未對準試驗 閘極電極膜厚 平均值±標準偏差[nm] 加強線膜厚 平均值±標準偏差[nm] 實施例2 A 100±0.1 100±0.1 實施例3 A 60±0.1 60±0.1 實施例4 A 215±3.2 226±5.4 實施例5 A 483±8.3 475±9.2 實施例6 B 100±0.1 100±0.1 實施例7 A 100±0.1 100±0.1 實施例8 A 100±0.1 100±0.1 比較例2 C 100±0.1   比較例3 C 221±2.8   [Table 2] (Table 2) Roll misalignment test Gate electrode film thickness average ± standard deviation [nm] Reinforced line film thickness average ± standard deviation [nm] Example 2 A 100±0.1 100±0.1 Example 3 A 60±0.1 60±0.1 Example 4 A 215±3.2 226±5.4 Example 5 A 483±8.3 475±9.2 Example 6 B 100±0.1 100±0.1 Example 7 A 100±0.1 100±0.1 Example 8 A 100±0.1 100±0.1 Comparative example 2 C 100±0.1 Comparative example 3 C 221±2.8

[表3] （表3）   第10次 第50次 第90次 平均值[μA] 標準偏差 平均值[μA] 標準偏差 平均值[μA] 標準偏差 實施例2 1.3 A 1.3 A 1.3 A 實施例3 1.4 A 1.4 A 1.4 A 實施例4 1.2 A 1.3 A 1.2 A 實施例5 1.2 A 1.2 A 1.2 A 實施例6 1.3 B 1.3 B 1.3 B 實施例7 0.6 A 0.6 A 0.7 A 實施例8 0.9 B 0.9 B 0.9 B 比較例2 1.2 C 1.3 C 1.3 C 比較例3 1.2 C 1.1 C 1.2 C [Table 3] (Table 3) 10th time 50th 90th Average value [μA] standard deviation Average value [μA] standard deviation Average value [μA] standard deviation Example 2 1.3 A 1.3 A 1.3 A Example 3 1.4 A 1.4 A 1.4 A Example 4 1.2 A 1.3 A 1.2 A Example 5 1.2 A 1.2 A 1.2 A Example 6 1.3 B 1.3 B 1.3 B Example 7 0.6 A 0.6 A 0.7 A Example 8 0.9 B 0.9 B 0.9 B Comparative example 2 1.2 C 1.3 C 1.3 C Comparative example 3 1.2 C 1.1 C 1.2 C

[表4] （表4）   座標偏差 FET 21 22 23 24 25 26 27 28 29 實施例2 A A A A A A A A A 實施例4 A A A A A A A A A 比較例2 B C C B B C C C C 比較例3 C C C C C B B B B [Table 4] (Table 4) Coordinate deviation FET twenty one twenty two twenty three twenty four 25 26 27 28 29 Example 2 A A A A A A A A A Example 4 A A A A A A A A A Comparative example 2 B C C B B C C C C Comparative example 3 C C C C C B B B B

（實施例9） 於實施例9中，製作了作為本發明的實施形態5的變形例1的半導體裝置用基板50F的一具體例的半導體裝置用基板。所述實施例9的半導體裝置用基板是具有底部閘極-頂部接觸結構的場效型電晶體作為半導體裝置的類型的基板，於藉由輥對輥方式搬運樹脂基材1的同時連續地製作。(Example 9) In Example 9, a semiconductor device substrate as a specific example of the semiconductor device substrate 50F of Modification 1 of the fifth embodiment of the present invention was produced. The semiconductor device substrate of Example 9 is a type of substrate with a field-effect transistor having a bottom gate-top contact structure as a semiconductor device, and is continuously manufactured while transporting the resin substrate 1 by a roll-to-roll method .

具體而言，首先，於PET膜製的樹脂基材1（寬度300 mm、長度50 m、膜厚50 μm）上，利用電阻加熱法，於100 nm整個面上真空蒸鍍銅。於其上利用狹縫塗佈整個面連續印刷光阻劑（商品名「LC100-10cP」，羅門哈斯（Rohm and Haas）公司製造），並於100℃下藉由熱風乾燥爐加熱乾燥4分鐘。介隔設計有閘極電極2及加強線31～加強線38的有效遮罩尺寸為280 mm×400 mm的光罩，於曝光量為60 mJ/cm2 （以波長365 nm換算）且樹脂基材1的進給量為420 mm的條件下，對藉此製作的光阻劑膜進行100次全線曝光。將設計於所述光罩的閘極電極寬度設為100 μm，將加強線31～加強線38的寬度設為1 mm，將加強線31～加強線34的長度設為370 mm，將加強線35～加強線38的長度設為280 mm。於曝光後，利用2.38重量%的氫氧化四甲基銨水溶液進行30秒顯影，繼而利用水清洗1分鐘。之後，利用混合酸（商品名SEA-5，關東化學公司製造）進行30秒蝕刻處理後，利用水清洗30秒。繼而，於AZ去除劑（AZ REMOVER）100（商品名，安智電子材料（AZ Electronic Materials）公司製造）中浸漬2分鐘，將光阻劑膜剝離，利用水清洗30秒後，利用氣刀去除水滴，之後，於80℃下藉由熱風乾燥爐加熱乾燥60秒。藉此，於樹脂基材1的面上每一處曝光區域形成18處閘極電極2與加強線31～加強線38（參照圖19A的狀態S11）。Specifically, first, on a resin substrate 1 (width 300 mm, length 50 m, and film thickness 50 μm) made of a PET film, copper was vacuum vapor-deposited on the entire surface of 100 nm by the resistance heating method. Coat the entire surface with a slit to print a photoresist (trade name "LC100-10cP", manufactured by Rohm and Haas), and heat and dry it in a hot air drying oven at 100°C for 4 minutes . The effective mask size is 280 mm×400 mm with gate electrode 2 and reinforcing lines 31～38 designed in the intervening space. The exposure amount is 60 mJ/cm 2 (converted to the wavelength of 365 nm) and resin-based Under the condition that the feed rate of the material 1 is 420 mm, the photoresist film thus produced is subjected to 100 full-line exposures. The width of the gate electrode designed on the mask is set to 100 μm, the width of the reinforcement line 31 to the reinforcement line 38 is set to 1 mm, the length of the reinforcement line 31 to the reinforcement line 34 is set to 370 mm, and the reinforcement line The length of the 35-reinforcement line 38 is set to 280 mm. After the exposure, development was performed with a 2.38% by weight tetramethylammonium hydroxide aqueous solution for 30 seconds, and then washed with water for 1 minute. Then, after performing an etching process for 30 seconds with a mixed acid (trade name SEA-5, manufactured by Kanto Chemical Co., Ltd.), it was washed with water for 30 seconds. Then, immerse in AZ REMOVER 100 (trade name, manufactured by AZ Electronic Materials) for 2 minutes, peel off the photoresist film, rinse with water for 30 seconds, and remove it with an air knife The water droplets are then heated and dried in a hot-air drying oven at 80°C for 60 seconds. As a result, 18 gate electrodes 2 and reinforcing lines 31 to 38 are formed in each exposed area on the surface of the resin substrate 1 (refer to the state S11 of FIG. 19A ).

之後，利用狹縫塗佈整個面連續印刷作為閘極絕緣層3的閘極絕緣層溶液A20，藉由熱風乾燥爐於大氣環境下、100℃下進行3分鐘熱處理，藉由IR乾燥爐於氮氣環境下、150℃下進行20分鐘熱處理。藉此，於樹脂基材1上形成膜厚500 nm的閘極絕緣層3（參照圖19A的狀態S12）。After that, the gate insulating layer solution A20 as the gate insulating layer 3 was continuously printed using slit coating on the entire surface, and heat-treated in a hot air drying oven at 100°C for 3 minutes in an atmospheric environment, and an IR drying oven in nitrogen Heat treatment at 150°C for 20 minutes under ambient conditions. Thereby, the gate insulating layer 3 with a film thickness of 500 nm was formed on the resin substrate 1 (refer to the state S12 of FIG. 19A).

於如上所述形成有閘極絕緣層3的樹脂基材1上，在作為投影18處閘極電極2的位置的閘極絕緣層3上的各部分，分別利用噴墨法塗佈100 pL的半導體溶液A10，利用IR乾燥爐於氮氣流下、150℃下進行30分鐘熱處理。藉此，於閘極絕緣層3上的18處形成半導體層4（參照圖19A的狀態S13）。On the resin substrate 1 on which the gate insulating layer 3 is formed as described above, 100 pL of each part on the gate insulating layer 3 as the position of the gate electrode 2 at the projection 18 is coated by inkjet method. The semiconductor solution A10 was heat-treated in an IR drying furnace at 150°C for 30 minutes under a nitrogen stream. Thereby, the semiconductor layer 4 is formed at 18 places on the gate insulating layer 3 (refer to the state S13 of FIG. 19A).

其次，藉由網版印刷於形成有所述閘極絕緣層3的PET膜製的樹脂基材1上塗佈感光性糊A。此時，感光性糊A是以印刷尺寸280 mm×400 mm、以與形成閘極電極2及加強線31～加強線38時的曝光區域重疊的方式，將樹脂基材1的進給量設為420 mm並塗佈100次。繼而，藉由熱風乾燥爐於100℃下對所述塗佈的感光性糊A進行4分鐘預烘烤。之後，介隔設計有源極電極5及汲極電極6的有效遮罩尺寸280 mm×400 mm的光罩，以與塗佈了感光性糊A的區域重疊的方式，以曝光量80 mJ/cm2 （以波長365 nm換算）、樹脂基材1的進給量為420 mm間距進行全線曝光。於曝光後以0.5%的Na2 CO3 溶液進行30秒顯影，於利用超純水清洗60秒後，利用IR乾燥爐於150℃下進行10分鐘固化。藉此，於閘極絕緣層3上形成18處源極電極5及汲極電極6（參照圖19B的狀態S14）。將源極電極5及汲極電極6的寬度設為100 μm，將該些電極間的距離設為20 μm。Next, a photosensitive paste A is applied on the resin substrate 1 made of a PET film on which the gate insulating layer 3 is formed by screen printing. At this time, the photosensitive paste A has a printing size of 280 mm×400 mm, and sets the feed amount of the resin base material 1 so as to overlap with the exposure area when the gate electrode 2 and the reinforcing lines 31 to 38 are formed. It is 420 mm and applied 100 times. Then, the applied photosensitive paste A was pre-baked at 100°C for 4 minutes in a hot-air drying oven. After that, the effective mask size of the source electrode 5 and the drain electrode 6 was designed to be 280 mm×400 mm, so as to overlap the area where the photosensitive paste A was applied, and the exposure amount was 80 mJ/ cm 2 (converted at 365 nm wavelength), the feed rate of the resin substrate 1 is 420 mm pitch for full-line exposure. After exposure, it was developed with a 0.5% Na 2 CO 3 solution for 30 seconds, washed with ultrapure water for 60 seconds, and cured at 150° C. for 10 minutes in an IR drying oven. Thereby, 18 source electrodes 5 and drain electrodes 6 are formed on the gate insulating layer 3 (refer to the state S14 of FIG. 19B). The width of the source electrode 5 and the drain electrode 6 was set to 100 μm, and the distance between these electrodes was set to 20 μm.

（實施例10） 於實施例10中，製作了作為本發明的實施形態6的半導體裝置用基板50H（參照圖13）的一具體例的半導體裝置用基板。所述實施例10的半導體裝置用基板是具有底部閘極-頂部接觸結構的場效型電晶體作為半導體裝置的類型的基板，於藉由輥對輥方式搬運樹脂基材1的同時連續地製作（參照圖19A、圖19B）。(Example 10) In Example 10, a semiconductor device substrate as a specific example of the semiconductor device substrate 50H (see FIG. 13) of the sixth embodiment of the present invention was produced. The semiconductor device substrate of Example 10 is a type of substrate with a field-effect transistor having a bottom gate-top contact structure as a semiconductor device, and is continuously manufactured while transporting the resin substrate 1 by a roll-to-roll method. (Refer to Figure 19A and Figure 19B).

具體而言，首先，於PET膜製的樹脂基材1（寬度300 mm、長度50 m、膜厚50 μm）上，利用電阻加熱法，於100 nm整個面上真空蒸鍍銅。於其上利用狹縫塗佈整個面連續印刷光阻劑（商品名「LC100-10cP」，羅門哈斯（Rohm and Haas）公司製造），並於100℃下藉由熱風乾燥爐加熱乾燥4分鐘。介隔設計有閘極電極2及加強線31～加強線38的有效遮罩尺寸為280 mm×400 mm的光罩，於曝光量為60 mJ/cm2 （以波長365 nm換算）且樹脂基材1的進給量為420 mm的條件下，對藉此製作的光阻劑膜進行100次全線曝光。將設計於所述光罩的閘極電極寬度設為100 μm，將加強線31～加強線38的寬度設為1 mm，將加強線31～加強線34的長度設為370 mm，將加強線35～加強線38的長度設為280 mm。於曝光後，利用2.38重量%的氫氧化四甲基銨水溶液進行30秒顯影，繼而利用水清洗1分鐘。之後，利用混合酸（商品名SEA-5，關東化學公司製造）進行30秒蝕刻處理後，利用水清洗30秒。繼而，於AZ去除劑（AZ REMOVER）100（商品名，安智電子材料（AZ Electronic Materials）公司製造）中浸漬2分鐘，將光阻劑膜剝離，利用水清洗30秒後，利用氣刀去除水滴，之後，於80℃下藉由熱風乾燥爐加熱乾燥60秒。藉此，如圖19A所示，於樹脂基材1的面上每一處曝光區域形成18處閘極電極2與加強線31～加強線38（狀態S11）。Specifically, first, on a resin substrate 1 (width 300 mm, length 50 m, and film thickness 50 μm) made of a PET film, copper was vacuum vapor-deposited on the entire surface of 100 nm by the resistance heating method. Coat the entire surface with a slit to print a photoresist (trade name "LC100-10cP", manufactured by Rohm and Haas), and heat and dry it in a hot air drying oven at 100°C for 4 minutes . The effective mask size is 280 mm×400 mm with gate electrode 2 and reinforcing lines 31～38 designed in the intervening space. The exposure amount is 60 mJ/cm 2 (converted to the wavelength of 365 nm) and resin-based Under the condition that the feed rate of the material 1 is 420 mm, the photoresist film thus produced is subjected to 100 full-line exposures. The width of the gate electrode designed on the mask is set to 100 μm, the width of the reinforcement line 31 to the reinforcement line 38 is set to 1 mm, the length of the reinforcement line 31 to the reinforcement line 34 is set to 370 mm, and the reinforcement line The length of the 35-reinforcement line 38 is set to 280 mm. After the exposure, development was performed with a 2.38% by weight tetramethylammonium hydroxide aqueous solution for 30 seconds, and then washed with water for 1 minute. Then, after performing an etching process for 30 seconds with a mixed acid (trade name SEA-5, manufactured by Kanto Chemical Co., Ltd.), it was washed with water for 30 seconds. Then, immerse in AZ REMOVER 100 (trade name, manufactured by AZ Electronic Materials) for 2 minutes, peel off the photoresist film, rinse with water for 30 seconds, and remove it with an air knife The water droplets are then heated and dried in a hot-air drying oven at 80°C for 60 seconds. As a result, as shown in FIG. 19A, 18 gate electrodes 2 and reinforcing lines 31 to 38 are formed in each exposed area on the surface of the resin substrate 1 (state S11).

之後，利用狹縫塗佈整個面連續印刷作為閘極絕緣層3的閘極絕緣層溶液A20，藉由熱風乾燥爐於大氣環境下、100℃下進行3分鐘熱處理，藉由IR乾燥爐於氮氣環境下、150℃下進行20分鐘熱處理。藉此，如圖19A所示，於樹脂基材1上形成膜厚500 nm的閘極絕緣層3（狀態S12）。After that, the gate insulating layer solution A20 as the gate insulating layer 3 was continuously printed using slit coating on the entire surface, and heat-treated in a hot air drying oven at 100°C for 3 minutes in an atmospheric environment, and an IR drying oven in nitrogen Heat treatment at 150°C for 20 minutes under ambient conditions. Thereby, as shown in FIG. 19A, the gate insulating layer 3 with a film thickness of 500 nm is formed on the resin substrate 1 (state S12).

於如上所述形成有閘極絕緣層3的樹脂基材1上，在作為投影18處閘極電極2的位置的閘極絕緣層3上的各部分，分別利用噴墨法塗佈100 pL的半導體溶液A10，利用IR乾燥爐於氮氣流下、150℃下進行30分鐘熱處理。藉此，如圖19A所示，於閘極絕緣層3上的18處形成半導體層4（狀態S13）。On the resin substrate 1 on which the gate insulating layer 3 is formed as described above, 100 pL of each part on the gate insulating layer 3 as the position of the gate electrode 2 at the projection 18 is coated by inkjet method. The semiconductor solution A10 was heat-treated in an IR drying furnace at 150°C for 30 minutes under a nitrogen stream. Thereby, as shown in FIG. 19A, the semiconductor layer 4 is formed at 18 places on the gate insulating layer 3 (state S13).

其次，藉由網版印刷於形成有所述閘極絕緣層3的PET膜製的樹脂基材1上塗佈感光性糊A。此時，感光性糊A是以印刷尺寸280 mm×400 mm、以與形成閘極電極2及加強線31～加強線38時的曝光區域重疊的方式，將樹脂基材1的進給量設為420 mm並塗佈100次。繼而，藉由熱風乾燥爐於100℃下對所述塗佈的感光性糊A進行4分鐘預烘烤。之後，介隔設計有源極電極5及汲極電極6的有效遮罩尺寸280 mm×400 mm的光罩，以與塗佈了感光性糊A的區域重疊的方式，以曝光量80 mJ/cm2 （以波長365 nm換算）、樹脂基材1的進給量為420 mm間距進行全線曝光。於曝光後以0.5%的Na2 CO3 溶液進行30秒顯影，於利用超純水清洗60秒後，利用IR乾燥爐於150℃下進行10分鐘固化。藉此，如圖19B所示，於閘極絕緣層3上形成18處源極電極5及汲極電極6（狀態S14）。將源極電極5及汲極電極6的寬度設為100 μm，將該些電極間的距離設為20 μm。Next, a photosensitive paste A is applied on the resin substrate 1 made of a PET film on which the gate insulating layer 3 is formed by screen printing. At this time, the photosensitive paste A has a printing size of 280 mm×400 mm, and sets the feed amount of the resin base material 1 so as to overlap with the exposure area when the gate electrode 2 and the reinforcing lines 31 to 38 are formed. It is 420 mm and applied 100 times. Then, the applied photosensitive paste A was pre-baked at 100°C for 4 minutes in a hot-air drying oven. After that, the effective mask size of the source electrode 5 and the drain electrode 6 was designed to be 280 mm×400 mm, so as to overlap the area where the photosensitive paste A was applied, and the exposure amount was 80 mJ/ cm 2 (converted at 365 nm wavelength), the feed rate of the resin substrate 1 is 420 mm pitch for full-line exposure. After exposure, it was developed with a 0.5% Na 2 CO 3 solution for 30 seconds, washed with ultrapure water for 60 seconds, and cured at 150° C. for 10 minutes in an IR drying oven. Thereby, as shown in FIG. 19B, 18 source electrodes 5 and drain electrodes 6 are formed on the gate insulating layer 3 (state S14). The width of the source electrode 5 and the drain electrode 6 was set to 100 μm, and the distance between these electrodes was set to 20 μm.

其次，於形成有所述半導體層4的PET膜製的樹脂基材1上，以覆蓋半導體層4的方式利用滴鑄法將第二絕緣層溶液A30（5 μL）滴加至多個（圖19B中為18處）半導體層4中的一部分半導體層4上。另外，利用相同的方法以包圍半導體裝置的方式連續滴加第二絕緣層溶液A30。於實施例10中，將所述第二絕緣層溶液A30連續滴加至所述加強線31～加強線38上。之後，將該些滴加的第二絕緣層溶液A30於氮氣流下、110℃下進行30分鐘熱處理。藉此，如圖19B所示，於樹脂基材1上形成第二絕緣層7及第二加強線51～第二加強線58（狀態S15）。該些第二絕緣層7及第二加強線51～第二加強線58的厚度為20 μm。Next, on the resin substrate 1 made of PET film on which the semiconductor layer 4 was formed, the second insulating layer solution A30 (5 μL) was dropped to a plurality of portions by a drop casting method so as to cover the semiconductor layer 4 (FIG. 19B 18 locations in the middle) are on a part of the semiconductor layer 4 in the semiconductor layer 4. In addition, the second insulating layer solution A30 was continuously dropped by the same method so as to surround the semiconductor device. In Embodiment 10, the second insulating layer solution A30 is continuously dripped onto the reinforcing wire 31 to the reinforcing wire 38. After that, the dropped second insulating layer solution A30 was heat-treated at 110° C. for 30 minutes under a nitrogen stream. Thereby, as shown in FIG. 19B, the second insulating layer 7 and the second reinforcing wires 51 to 58 are formed on the resin base material 1 (state S15). The thickness of the second insulating layer 7 and the second reinforcing wire 51 to the second reinforcing wire 58 is 20 μm.

以所述方式各自獲得了實施例9、實施例10的半導體裝置用基板。對該些所獲得的半導體裝置用基板進行與實施例2的第一項目的評價相同的評價，結果實施例9、實施例10的各評價結果兩者均為「A」（良好）。另外，將實施例9、實施例10的各半導體裝置用基板（長度50 m）以曝光步驟中實施的進給間距在自第1次至第100次的各部分切出單張紙狀，確認所獲得的各基板樣品的外觀，結果不存在第二絕緣層7剝落的部位。In the manner described above, the semiconductor device substrates of Example 9 and Example 10 were respectively obtained. The obtained semiconductor device substrates were evaluated in the same manner as the evaluation of the first item of Example 2. As a result, the evaluation results of Example 9 and Example 10 were both "A" (good). In addition, each semiconductor device substrate (50 m in length) of Example 9 and Example 10 was cut into a single sheet of paper at each part from the first to the 100th time at the feed pitch implemented in the exposure step, and confirmed As a result of the appearance of each substrate sample obtained, there was no part where the second insulating layer 7 was peeled off.

（比較例5） 於比較例5中，除了於實施例10中的形成第二絕緣層7及第二加強線51～第二加強線58的步驟中未形成第二加強線51～第二加強線58以外，利用與實施例10相同的方法進行與實施例10相同的評價。於比較例5中，進行與實施例2的第一項目的評價相同的評價，結果比較例5的所述第一項目的評價結果為「C」（不合格）。另外，於比較例5的半導體裝置用基板中，亦發生了第二絕緣層7的剝落。 [產業上之可利用性](Comparative Example 5) In Comparative Example 5, except that the second reinforcement line 51 to the second reinforcement line 58 were not formed in the step of forming the second insulating layer 7 and the second reinforcement line 51 to the second reinforcement line 58 in the embodiment 10, the In the same manner as in Example 10, the same evaluation as in Example 10 was performed. In Comparative Example 5, the same evaluation as that of the first item of Example 2 was performed, and as a result, the evaluation result of the first item of Comparative Example 5 was "C" (failure). In addition, in the substrate for a semiconductor device of Comparative Example 5, peeling of the second insulating layer 7 also occurred. [Industrial availability]

如上所述，本發明的半導體裝置用基板、半導體裝置用基板的製造方法及無線通訊裝置的製造方法適合於即使於在基板上形成多個半導體裝置後亦可抑制半導體裝置的特性偏差的半導體裝置用基板、半導體裝置用基板的製造方法及無線通訊裝置的製造方法。As described above, the substrate for a semiconductor device, the method for manufacturing a substrate for a semiconductor device, and a method for manufacturing a wireless communication device of the present invention are suitable for a semiconductor device that can suppress variations in characteristics of the semiconductor device even after a plurality of semiconductor devices are formed on the substrate Substrate for use, method for manufacturing substrate for semiconductor device, and method for manufacturing wireless communication device.

1:樹脂基材 2:閘極電極 3:閘極絕緣層 4:半導體層 5:源極電極 6:汲極電極 7:第二絕緣層 10:半導體裝置 11、11a～11h、12、12a～12h、13～17、31～38:加強線 20～30:FET 41、42、51～58:第二加強線 50、50A、50B、50C、50D、50E、50F、50G、50H:半導體裝置用基板 100:基板 101:天線圖案 102:電路 103:連接配線 110、110A:無線通訊裝置 D1、D1a、D1b、D2、D2a、D2b:設計 S1～S4、S11～S15、S21～S25:狀態1: Resin substrate 2: Gate electrode 3: Gate insulation layer 4: Semiconductor layer 5: Source electrode 6: Drain electrode 7: The second insulating layer 10: Semiconductor device 11, 11a～11h, 12, 12a～12h, 13～17, 31～38: reinforcement line 20～30: FET 41, 42, 51～58: second reinforcement line 50, 50A, 50B, 50C, 50D, 50E, 50F, 50G, 50H: substrates for semiconductor devices 100: substrate 101: Antenna pattern 102: Circuit 103: Connection wiring 110, 110A: wireless communication device D1, D1a, D1b, D2, D2a, D2b: Design S1～S4, S11～S15, S21～S25: status

圖1是表示本發明的實施形態1的半導體裝置用基板的一結構例的示意圖。 圖2是表示本發明的實施形態1的變形例的半導體裝置用基板的一結構例的示意圖。 圖3是表示本發明的實施形態2的半導體裝置用基板的一結構例的示意圖。 圖4是表示本發明的實施形態3的半導體裝置用基板的一結構例的示意圖。 圖5是表示本發明的實施形態4的半導體裝置用基板的一結構例的示意圖。 圖6是表示本發明的實施形態5的半導體裝置用基板的一結構例的示意圖。 圖7是表示本發明的實施形態5的變形例1的半導體裝置用基板的一結構例的示意圖。 圖8是表示本發明的實施形態5的變形例2的半導體裝置用基板的一結構例的示意圖。 圖9是摘選本發明的實施形態1的半導體裝置用基板的一部分而表示的立體圖。 圖10是圖9所示的半導體裝置用基板於I-I'線上的示意剖面圖。 圖11是表示圖10所示的半導體裝置用基板的第一變形例的示意剖面圖。 圖12是表示圖10所示的半導體裝置用基板的第二變形例的示意剖面圖。 圖13是表示本發明的實施形態6的半導體裝置用基板的一結構例的示意圖。 圖14是圖13所示的半導體裝置用基板於II-II'線上的示意剖面圖。 圖15是表示圖13所示的半導體裝置用基板的第一變形例的示意剖面圖。 圖16是表示圖13所示的半導體裝置用基板的第二變形例的示意剖面圖。 圖17是用以說明本發明的實施形態5的半導體裝置用基板的製造方法的一例的立體圖。 圖18A是表示本發明的實施形態5的半導體裝置用基板的製造方法的第一步驟例的部分放大示意圖。 圖18B是表示本發明的實施形態5的半導體裝置用基板的製造方法的第二步驟例的部分放大示意圖。 圖19A是表示本發明的實施形態6的半導體裝置用基板的製造方法的第一步驟例的部分放大示意圖。 圖19B是表示本發明的實施形態6的半導體裝置用基板的製造方法的第二步驟例的部分放大示意圖。 圖20是表示應用本發明的無線通訊裝置的第一結構例的示意圖。 圖21是表示應用本發明的無線通訊裝置的第二結構例的示意圖。 圖22A是表示本發明的實施例1的半導體裝置用基板的製造方法的第一步驟例的示意圖。 圖22B是表示本發明的實施例1的半導體裝置用基板的製造方法的第二步驟例的示意圖。 圖23是表示由實施例2的半導體裝置用基板所獲得的基板樣品的一例的示意圖。FIG. 1 is a schematic diagram showing a configuration example of a substrate for a semiconductor device according to Embodiment 1 of the present invention. 2 is a schematic diagram showing a configuration example of a substrate for a semiconductor device according to a modification of the first embodiment of the present invention. 3 is a schematic diagram showing a configuration example of a semiconductor device substrate according to Embodiment 2 of the present invention. 4 is a schematic diagram showing a configuration example of a semiconductor device substrate according to Embodiment 3 of the present invention. 5 is a schematic diagram showing a configuration example of a semiconductor device substrate according to Embodiment 4 of the present invention. 6 is a schematic diagram showing a configuration example of a semiconductor device substrate according to Embodiment 5 of the present invention. FIG. 7 is a schematic diagram showing a configuration example of a semiconductor device substrate according to Modification 1 of Embodiment 5 of the present invention. 8 is a schematic diagram showing a configuration example of a semiconductor device substrate according to Modification 2 of Embodiment 5 of the present invention. Fig. 9 is a perspective view showing an excerpt of a part of the semiconductor device substrate according to the first embodiment of the present invention. Fig. 10 is a schematic cross-sectional view of the semiconductor device substrate shown in Fig. 9 on line II'. FIG. 11 is a schematic cross-sectional view showing a first modification of the semiconductor device substrate shown in FIG. 10. FIG. 12 is a schematic cross-sectional view showing a second modification of the semiconductor device substrate shown in FIG. 10. FIG. 13 is a schematic diagram showing a configuration example of a semiconductor device substrate according to Embodiment 6 of the present invention. Fig. 14 is a schematic cross-sectional view of the semiconductor device substrate shown in Fig. 13 on line II-II'. 15 is a schematic cross-sectional view showing a first modification example of the semiconductor device substrate shown in FIG. 13. FIG. 16 is a schematic cross-sectional view showing a second modification of the semiconductor device substrate shown in FIG. 13. FIG. 17 is a perspective view for explaining an example of a method of manufacturing a substrate for a semiconductor device according to Embodiment 5 of the present invention. 18A is a partially enlarged schematic diagram showing a first step example of a method of manufacturing a substrate for a semiconductor device according to Embodiment 5 of the present invention. 18B is a partially enlarged schematic diagram showing a second step example of the method of manufacturing a substrate for a semiconductor device according to the fifth embodiment of the present invention. 19A is a partially enlarged schematic diagram showing an example of the first step of the manufacturing method of the semiconductor device substrate according to the sixth embodiment of the present invention. 19B is a partially enlarged schematic diagram showing a second step example of the manufacturing method of the semiconductor device substrate according to the sixth embodiment of the present invention. Fig. 20 is a schematic diagram showing a first configuration example of a wireless communication device to which the present invention is applied. Fig. 21 is a schematic diagram showing a second configuration example of a wireless communication device to which the present invention is applied. 22A is a schematic diagram showing a first step example of the method of manufacturing a substrate for a semiconductor device according to the first embodiment of the present invention. 22B is a schematic diagram showing a second step example of the manufacturing method of the semiconductor device substrate according to the first embodiment of the present invention. 23 is a schematic diagram showing an example of a substrate sample obtained from the semiconductor device substrate of Example 2. FIG.

1:樹脂基材1: Resin substrate

10:半導體裝置10: Semiconductor device

11a~11d、12a~12d:加強線11a~11d, 12a~12d: reinforced line

50:半導體裝置用基板50: Substrate for semiconductor devices

Claims (31)

一種半導體裝置用基板，其特徵在於，具有樹脂基材、以及所述樹脂基材上所包括的多個半導體裝置，且於所述樹脂基材上具有以包圍所述多個半導體裝置的方式設置的加強線， 所述加強線由與構成所述多個半導體裝置中所含的電極層中的至少一者的材料相同的材料構成， 於所述樹脂基材上存在多個所述多個半導體裝置中的一個以上被所述加強線包圍的區域。A substrate for a semiconductor device, characterized by having a resin base material and a plurality of semiconductor devices included on the resin base material, and provided on the resin base material so as to surround the plurality of semiconductor devices The reinforcement line, The reinforcing wire is made of the same material as the material constituting at least one of the electrode layers included in the plurality of semiconductor devices, On the resin base material, there is a region surrounded by the reinforcing line in one or more of the plurality of semiconductor devices. 如請求項1所述的半導體裝置用基板，其中所述加強線以分別包圍所述多個半導體裝置的方式設置。The semiconductor device substrate according to claim 1, wherein the reinforcing wires are provided so as to surround the plurality of semiconductor devices, respectively. 如請求項1或請求項2所述的半導體裝置用基板，其中所述加強線的厚度與所述多個半導體裝置各自的厚度相同，或者比所述多個半導體裝置各自的厚度薄。The substrate for a semiconductor device according to claim 1 or 2, wherein the thickness of the reinforcing wire is the same as the thickness of each of the plurality of semiconductor devices, or is thinner than the thickness of each of the plurality of semiconductor devices. 如請求項1或請求項2所述的半導體裝置用基板，其中所述樹脂基材具有長邊方向與短邊方向， 所述多個半導體裝置以於所述樹脂基材上的長邊方向上形成列的方式形成， 所述加強線的一部分於所述樹脂基材的長邊方向上大致連續地設置。The substrate for a semiconductor device according to claim 1 or 2, wherein the resin base material has a long side direction and a short side direction, The plurality of semiconductor devices are formed in a manner to form rows in the longitudinal direction of the resin substrate, A part of the reinforcing wire is provided substantially continuously in the longitudinal direction of the resin base material. 如請求項1或請求項2所述的半導體裝置用基板，其中所述樹脂基材具有長邊方向與短邊方向， 所述多個半導體裝置以於所述樹脂基材上的長邊方向上形成列的方式形成， 所述加強線的一部分於所述多個半導體裝置的列的兩個外緣部中，於所述樹脂基材的長邊方向上大致連續地設置。The substrate for a semiconductor device according to claim 1 or 2, wherein the resin base material has a long side direction and a short side direction, The plurality of semiconductor devices are formed in a manner to form rows in the longitudinal direction of the resin substrate, A part of the reinforcing wire is provided substantially continuously in the longitudinal direction of the resin base material in the two outer edge portions of the row of the plurality of semiconductor devices. 如請求項1或請求項2所述的半導體裝置用基板，其中所述多個半導體裝置各自包括場效型電晶體， 所述場效型電晶體具有：源極電極、汲極電極及閘極電極；與所述源極電極及所述汲極電極分別接觸的半導體層；以及使所述源極電極、所述汲極電極及所述半導體層與所述閘極電極絕緣的閘極絕緣層。The substrate for a semiconductor device according to claim 1 or 2, wherein each of the plurality of semiconductor devices includes a field-effect transistor, The field-effect transistor has: a source electrode, a drain electrode, and a gate electrode; a semiconductor layer in contact with the source electrode and the drain electrode, respectively; and the source electrode, the drain electrode A gate electrode and a gate insulating layer that insulates the semiconductor layer from the gate electrode. 如請求項6所述的半導體裝置用基板，其中所述半導體層含有碳奈米管。The substrate for a semiconductor device according to claim 6, wherein the semiconductor layer contains a carbon nanotube. 如請求項1或請求項2所述的半導體裝置用基板，其中所述多個半導體裝置各自包括場效型電晶體， 所述加強線由與所述場效型電晶體中所含的源極電極、汲極電極及閘極電極中位於靠近所述樹脂基材的一側的基材側的電極相同的材料，設置於與所述基材側的電極相同的層。The substrate for a semiconductor device according to claim 1 or 2, wherein each of the plurality of semiconductor devices includes a field-effect transistor, The reinforcing wire is made of the same material as the electrode on the substrate side that is located on the side close to the resin substrate among the source electrode, drain electrode, and gate electrode contained in the field-effect transistor, and is provided On the same layer as the electrode on the substrate side. 如請求項1或請求項2所述的半導體裝置用基板，其中所述多個半導體裝置各自包括具有底部閘極結構的場效型電晶體， 所述加強線由與構成所述場效型電晶體中所含的閘極電極的材料相同的材料，設置於與所述閘極電極相同的層。The substrate for a semiconductor device according to claim 1 or 2, wherein each of the plurality of semiconductor devices includes a field-effect transistor having a bottom gate structure, The reinforcing wire is made of the same material as the material constituting the gate electrode included in the field-effect transistor, and is provided on the same layer as the gate electrode. 如請求項6所述的半導體裝置用基板，其中多個所述場效型電晶體的至少一部分具有於相對於所述場效型電晶體的半導體層而與閘極絕緣層相反的一側和所述半導體層接觸的第二絕緣層， 於所述樹脂基材上具有由與構成所述第二絕緣層的材料相同的材料構成的第二加強線。The semiconductor device substrate according to claim 6, wherein at least a part of the plurality of field-effect transistors has a side opposite to the gate insulating layer with respect to the semiconductor layer of the field-effect transistor and The second insulating layer in contact with the semiconductor layer, The resin base material has a second reinforcing wire made of the same material as the material constituting the second insulating layer. 如請求項8所述的半導體裝置用基板，其中多個所述場效型電晶體的至少一部分具有於相對於所述場效型電晶體的半導體層而與閘極絕緣層相反的一側和所述半導體層接觸的第二絕緣層， 於所述樹脂基材上具有由與構成所述第二絕緣層的材料相同的材料構成的第二加強線。The substrate for a semiconductor device according to claim 8, wherein at least a part of the plurality of field-effect transistors has a side opposite to the gate insulating layer with respect to the semiconductor layer of the field-effect transistor and The second insulating layer in contact with the semiconductor layer, The resin base material has a second reinforcing wire made of the same material as the material constituting the second insulating layer. 如請求項9所述的半導體裝置用基板，其中所述場效型電晶體的閘極電極及所述加強線彼此為相同的厚度， 所述厚度為30 nm以上且500 nm以下。The semiconductor device substrate according to claim 9, wherein the gate electrode of the field-effect transistor and the reinforcement line have the same thickness as each other, The thickness is 30 nm or more and 500 nm or less. 如請求項10所述的半導體裝置用基板，其中所述場效型電晶體的閘極電極及所述加強線彼此為相同的厚度， 所述厚度為30 nm以上且500 nm以下。The semiconductor device substrate according to claim 10, wherein the gate electrode of the field-effect transistor and the reinforcement line have the same thickness as each other, The thickness is 30 nm or more and 500 nm or less. 如請求項6所述的半導體裝置用基板，其中所述場效型電晶體是具有頂部接觸結構的場效型電晶體。The semiconductor device substrate according to claim 6, wherein the field effect transistor is a field effect transistor having a top contact structure. 如請求項8所述的半導體裝置用基板，其中所述場效型電晶體是具有頂部接觸結構的場效型電晶體。The substrate for a semiconductor device according to claim 8, wherein the field effect transistor is a field effect transistor having a top contact structure. 如請求項1或請求項2所述的半導體裝置用基板，其中所述多個半導體裝置各自為無線通訊裝置。The semiconductor device substrate according to claim 1 or claim 2, wherein each of the plurality of semiconductor devices is a wireless communication device. 一種半導體裝置用基板的製造方法，其特徵在於，是製造如請求項1至請求項16中任一項所述的半導體裝置用基板的方法，其中， 於同一步驟中進行所述樹脂基材上的所述多個半導體裝置的構成構件中的任一者的形成與所述加強線的形成。A method of manufacturing a substrate for a semiconductor device, characterized in that it is a method of manufacturing the substrate for a semiconductor device according to any one of claims 1 to 16, wherein: The formation of any one of the constituent members of the plurality of semiconductor devices on the resin substrate and the formation of the reinforcement wire are performed in the same step. 如請求項17所述的半導體裝置用基板的製造方法，其中所述多個半導體裝置及所述加強線的形成是於以輥對輥方式搬運所述樹脂基材的同時加以實施。The method of manufacturing a substrate for a semiconductor device according to claim 17, wherein the formation of the plurality of semiconductor devices and the reinforcing wire is carried out while conveying the resin base material by a roll-to-roll method. 如請求項17所述的半導體裝置用基板的製造方法，其中於同一步驟中進行所述多個半導體裝置各自中所含的電極層中的至少一者的形成與所述加強線的形成。The method of manufacturing a substrate for a semiconductor device according to claim 17, wherein the formation of at least one of the electrode layers included in each of the plurality of semiconductor devices and the formation of the reinforcement line are performed in the same step. 如請求項17所述的半導體裝置用基板的製造方法，其中所述多個半導體裝置各自以包括場效型電晶體的方式形成， 於同一步驟中進行所述場效型電晶體中所含的源極電極、汲極電極及閘極電極中位於靠近所述樹脂基材的一側的基材側的電極的形成與所述加強線的形成。The method of manufacturing a substrate for a semiconductor device according to claim 17, wherein each of the plurality of semiconductor devices is formed to include a field-effect transistor, The formation of the source electrode, the drain electrode, and the gate electrode contained in the field-effect transistor and the formation of the electrode on the substrate side close to the resin substrate and the reinforcement are performed in the same step Line formation. 如請求項17所述的半導體裝置用基板的製造方法，其中所述多個半導體裝置各自以包括具有底部閘極結構的場效型電晶體的方式形成， 於同一步驟中進行所述場效型電晶體中所含的閘極電極的形成與所述加強線的形成。The method of manufacturing a substrate for a semiconductor device according to claim 17, wherein each of the plurality of semiconductor devices is formed in a manner including a field-effect transistor having a bottom gate structure, The formation of the gate electrode contained in the field-effect transistor and the formation of the reinforcement line are performed in the same step. 如請求項21所述的半導體裝置用基板的製造方法，其中多個所述場效型電晶體的至少一部分以具有於相對於所述場效型電晶體的半導體層而與閘極絕緣層相反的一側和所述半導體層接觸的第二絕緣層的方式形成， 於同一步驟中進行所述樹脂基材上的由與構成所述第二絕緣層的材料相同的材料構成的第二加強線的形成與所述第二絕緣層的形成。The method of manufacturing a substrate for a semiconductor device according to claim 21, wherein at least a part of the plurality of field-effect transistors has a gate insulating layer opposite to the semiconductor layer of the field-effect transistor Is formed by a second insulating layer that is in contact with the semiconductor layer on one side, The formation of the second reinforcing wire made of the same material as the material constituting the second insulating layer on the resin substrate and the formation of the second insulating layer are performed in the same step. 如請求項21所述的半導體裝置用基板的製造方法，其中於同一步驟中進行所述閘極電極的形成與所述加強線的形成的加強線形成步驟包括圖案化步驟，所述圖案化步驟是加工藉由濺鍍或真空蒸鍍法於所述樹脂基材上成膜的金屬膜，並加工成與所述閘極電極及所述加強線對應的圖案。The method of manufacturing a substrate for a semiconductor device according to claim 21, wherein the step of forming the reinforcement line in which the formation of the gate electrode and the formation of the reinforcement line are performed in the same step includes a patterning step, and the patterning step It is to process a metal film formed on the resin substrate by sputtering or vacuum evaporation, and process it into a pattern corresponding to the gate electrode and the reinforcing line. 如請求項21所述的半導體裝置用基板的製造方法，其中於同一步驟中進行所述閘極電極的形成與所述加強線的形成的加強線形成步驟包括： 成膜步驟，於所述樹脂基材上使用含有導電體粒子與感光性有機成分的感光性糊而形成塗佈膜；以及 圖案化步驟，藉由光微影法將所述塗佈膜加工成與所述閘極電極及所述加強線對應的圖案。The method of manufacturing a substrate for a semiconductor device according to claim 21, wherein the step of forming the reinforcement line in which the formation of the gate electrode and the formation of the reinforcement line are performed in the same step includes: In the film forming step, a photosensitive paste containing conductive particles and photosensitive organic components is used on the resin substrate to form a coating film; and In the patterning step, the coating film is processed into a pattern corresponding to the gate electrode and the reinforcing line by photolithography. 如請求項17所述的半導體裝置用基板的製造方法，其中以分別包圍所述多個半導體裝置的方式設置所述加強線。The method of manufacturing a substrate for a semiconductor device according to claim 17, wherein the reinforcing wires are provided so as to surround the plurality of semiconductor devices, respectively. 如請求項17所述的半導體裝置用基板的製造方法，其中所述樹脂基材具有長邊方向與短邊方向， 以於所述樹脂基材上的長邊方向上形成列的方式形成所述多個半導體裝置， 於所述樹脂基材的長邊方向上大致連續地設置所述加強線的一部分。The method of manufacturing a substrate for a semiconductor device according to claim 17, wherein the resin base material has a long side direction and a short side direction, Forming the plurality of semiconductor devices in such a manner that rows are formed in the longitudinal direction on the resin substrate, A part of the reinforcing thread is provided substantially continuously in the longitudinal direction of the resin base material. 如請求項17所述的半導體裝置用基板的製造方法，其中所述樹脂基材具有長邊方向與短邊方向， 以於所述樹脂基材上的長邊方向上形成列的方式形成所述多個半導體裝置， 於所述多個半導體裝置的列的兩個外緣部中，於所述樹脂基材的長邊方向上大致連續地設置所述加強線的一部分。The method of manufacturing a substrate for a semiconductor device according to claim 17, wherein the resin base material has a long side direction and a short side direction, Forming the plurality of semiconductor devices in such a manner that rows are formed in the longitudinal direction on the resin substrate, In the two outer edge portions of the rows of the plurality of semiconductor devices, a part of the reinforcing wire is provided substantially continuously in the longitudinal direction of the resin base material. 如請求項17所述的半導體裝置用基板的製造方法，其中所述多個半導體裝置各自為無線通訊裝置或無線通訊裝置的電路。The method of manufacturing a substrate for a semiconductor device according to claim 17, wherein each of the plurality of semiconductor devices is a wireless communication device or a circuit of a wireless communication device. 一種無線通訊裝置的製造方法，其特徵在於，包括將藉由如請求項28所述的半導體裝置用基板的製造方法而獲得的半導體裝置用基板按照每個所述無線通訊裝置切分的步驟。A method of manufacturing a wireless communication device, comprising the step of dividing a semiconductor device substrate obtained by the method of manufacturing a semiconductor device substrate according to claim 28 for each wireless communication device. 一種無線通訊裝置的製造方法，其特徵在於，包括： 將藉由如請求項28所述的半導體裝置用基板的製造方法而獲得的半導體裝置用基板按照每個所述無線通訊裝置的電路切分的步驟；以及 將切分的所述無線通訊裝置的電路貼合至天線的步驟。A method for manufacturing a wireless communication device, which is characterized in that it comprises: The step of dividing the substrate for a semiconductor device obtained by the method of manufacturing a substrate for a semiconductor device according to claim 28 according to the circuit of each wireless communication device; and The step of attaching the divided circuit of the wireless communication device to the antenna. 一種無線通訊裝置的製造方法，其特徵在於，包括： 將藉由如請求項28所述的半導體裝置用基板的製造方法而獲得的半導體裝置用基板的所述無線通訊裝置的電路與天線貼合的步驟；以及 將貼合所述無線通訊裝置的電路與所述天線後的所述半導體裝置用基板按照每個包括所述無線通訊裝置的電路與所述天線的無線通訊裝置切分的步驟。A method for manufacturing a wireless communication device, which is characterized in that it comprises: The step of bonding the circuit of the wireless communication device and the antenna of the substrate for a semiconductor device obtained by the method of manufacturing a substrate for a semiconductor device according to claim 28; and The step of dividing the semiconductor device substrate after bonding the circuit of the wireless communication device and the antenna to each wireless communication device including the circuit of the wireless communication device and the antenna.
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