JP2023123360A - Method for manufacturing semiconductor device, semiconductor device, and radio communication device including the same - Google Patents

Abstract

To provide a semiconductor device capable of stabilizing operation of a circuit needing a plurality of kinds of semiconductor elements having different electrical characteristics and reducing a used amount of materials, and provide a method for manufacturing the same.SOLUTION: A semiconductor device 101 includes a first region 10 and a second region 20 in which a plurality of FETs are arranged on a base material 1. An FET 30 of the first region includes a gate insulation layer insulating a semiconductor layer and a gate electrode and a first overcoat layer 11 in contact with the semiconductor layer at a position different from the gate insulation layer on the base material. An FET 40 of the second region includes a gate insulation layer insulating a semiconductor layer and a gate electrode and a second overcoat layer 21 in contact with the semiconductor layer at a position different from the gate insulation layer on the base material. Electric conductivity of the semiconductor element of the first region differs from electric conductivity of the semiconductor element of the second region. A method for manufacturing the semiconductor device forms the second overcoat layer so that a part of the second overcoat layer overlaps the first overcoat layer after forming the first overcoat layer.SELECTED DRAWING: Figure 1

Description

The present invention relates to a semiconductor device, a manufacturing method thereof, and a wireless communication device using the same.

BACKGROUND ART In recent years, with the aim of realizing low-cost, large-area, flexible, and bendable electronic products, field-effect transistors (hereinafter referred to as FETs) using organic semiconductors have been actively studied. As electronic products, for example, displays and sensors, among others, wireless communication systems using RFID (Radio Frequency Identification) technology are attracting attention. An RFID tag has an IC chip having a circuit made up of FETs and an antenna for wireless communication with a reader/writer. An antenna installed in the tag receives carrier waves transmitted from the reader/writer, and drives a drive circuit in the IC chip.

RFID tags are expected to be used in various applications such as physical distribution management, merchandise management, and shoplifting prevention, and have begun to be introduced in some areas, such as IC cards such as transportation cards and product tags.

In order to use RFID tags for all products in the future, it is necessary to reduce manufacturing costs. Therefore, in the manufacturing process of RFID tags, it is being considered to break away from processes using vacuum and high temperature and to use flexible and inexpensive processes using coating and printing techniques. As one example, a field effect transistor (hereinafter referred to as FET) using an organic semiconductor with excellent formability as a semiconductor layer has been proposed for a drive circuit in an IC chip. By using an organic semiconductor as an ink, it becomes possible to form a circuit pattern such as an FET directly on a flexible substrate by inkjet technology, screening technology, or the like. Therefore, instead of conventional inorganic semiconductors, FETs using carbon nanotubes (CNT) or organic semiconductors are being actively studied, and circuits using them are also being studied (see, for example, Patent Document 1).

A drive circuit in an RFID tag is generally composed of a complementary circuit composed of a p-type FET and an n-type FET in order to reduce power consumption. However, it is known that FETs using CNTs usually exhibit the characteristics of p-type semiconductor elements in the atmosphere. Also, the FET using an organic semiconductor is a single channel. Therefore, a complementary circuit cannot be constructed with the same material, and materials must be selected separately for the p-type FET and the n-type FET. This complicates the manufacturing process of the complementary circuits, resulting in problems of reduced efficiency in the production of RFID tags and increased manufacturing costs.

Therefore, for example, in an FET using CNT, after forming a p-type FET, there is a technique of forming an n-type modifying polymer layer on the semiconductor layer to modify the p-type characteristics to n-type characteristics. It has been proposed (see, for example, Patent Document 2). In particular, in the technique of Patent Document 2, FETs to be modified to have n-type characteristics are placed next to each other and an n-type modified layer is formed at once, thereby fabricating a complementary circuit in a relatively easy process. be able to.

WO2009/139339 WO2020/026786

However, as described in Patent Document 2, when FETs for which n-type modification is to be performed are collectively arranged and an n-type modification layer is formed at once, wiring around the FETs, electrode shape, unevenness depending on the circuit function There is a problem that it is difficult to control the amount of wetting and spreading of the n-type modified polymer because the conditions differ from one FET to another. As a result, the film thickness of the n-type modified layer becomes non-uniform for each FET, increasing variations in FET characteristics within the circuit and making it easier for continuous circuit operation failures to occur. However, there is a problem that the amount of the n-type modified layer material required for the method increases.

Accordingly, the present invention provides a semiconductor device capable of stabilizing the circuit operation and reducing the amount of material used in a circuit requiring multiple types of semiconductor elements having different electrical characteristics, as typified by complementary circuits. intended to

In order to solve the above problems, the present invention has the following configurations.
[1] A substrate includes at least a first region in which two or more semiconductor elements are arranged and a second region in which two or more semiconductor elements are arranged, and the semiconductor in the first region The element includes a source electrode, a drain electrode, a gate electrode, a semiconductor layer in contact with the source electrode and the drain electrode, a gate insulating layer insulating the semiconductor layer from the gate electrode, and a semiconductor layer at a position different from the gate insulating layer. a first overcoat layer in contact with a layer on the substrate, wherein the semiconductor element in the second region includes a source electrode, a drain electrode, a gate electrode, a semiconductor layer in contact with the source electrode and the drain electrode, the semiconductor and a second overcoat layer in contact with the semiconductor layer at a position different from the gate insulating layer, the semiconductor element in the first region comprising a gate insulating layer insulating the layer from the gate electrode, and a second overcoat layer contacting the semiconductor layer at a position different from the gate insulating layer. and the semiconductor element in the second region, the semiconductor device manufacturing method comprising: after forming the first overcoat layer, forming the second overcoat layer on the A method of manufacturing a semiconductor device, comprising the step of forming a part of the overcoat layer overlying the first overcoat layer.
[2] According to [1], the semiconductor element in the first region and the semiconductor element in the second region have different electrical conductivity due to the first overcoat layer and the second overcoat layer. A method of manufacturing the semiconductor device described.
[3] The first overcoat layer is arranged in a continuous elongated shape over two or more of the semiconductor elements in the first region, and the second overcoat layer, a part of which is the above The method of manufacturing a semiconductor device according to [1] or [2], wherein the long side of the first overcoat layer is formed so as to overlap the first overcoat layer.
[4] The method of manufacturing a semiconductor device according to [3], wherein the elongated first overcoat layer is arranged in a stripe shape.
[5] Any one of [1] to [4], wherein the semiconductor layer contains one or more semiconductor materials selected from carbon nanotubes, carbon nanocoils, fullerenes, graphene, and nanodiamonds. and a method for manufacturing a semiconductor device.
[6] The method of manufacturing a semiconductor device according to any one of [1] to [5], wherein the semiconductor layer contains carbon nanotubes.
[7] Any one of [1] to [6], wherein the second overcoat layer contains an electron-donating compound having at least one selected from nitrogen atoms and phosphorus atoms. A method of manufacturing a semiconductor device.
[8] The method of manufacturing a semiconductor device according to any one of [1] to [7], wherein the semiconductor device is a wireless communication device.
[9] A semiconductor device including at least a first region in which two or more semiconductor elements are arranged and a second region in which two or more semiconductor elements are arranged on a substrate, The semiconductor element in region 1 includes a source electrode, a drain electrode, a gate electrode, a semiconductor layer in contact with the source electrode and the drain electrode, a gate insulating layer insulating the semiconductor layer from the gate electrode, and the gate insulating layer. a first overcoat layer contacting the semiconductor layer at a position different from the base, wherein the semiconductor element in the second region comprises a source electrode, a drain electrode, a gate electrode, the source electrode and the drain A semiconductor layer in contact with an electrode, a gate insulating layer insulating the semiconductor layer from the gate electrode, and a second overcoat layer in contact with the semiconductor layer at a position different from the gate insulating layer are formed on the base material. In preparation for the above, the semiconductor device in which the electrical conductivity of the semiconductor element in the first region and the semiconductor element in the second region are different due to the first overcoat layer and the second overcoat layer, , a semiconductor device, wherein a portion of the second overcoat layer overlies the first overcoat layer.
[10] The first overcoat layer is arranged in a continuous elongated shape over two or more semiconductor elements in the first region, and the second overcoat layer partially includes the The semiconductor device according to [9], which is arranged in an elongated shape so as to overlap the first overcoat layer along the long sides of the elongated first overcoat layer.
[11] The semiconductor device according to [9] or [10], wherein the width of the second overcoat layer in the short direction is 10 to 50 times the thickness of the second overcoat layer.
[12] The semiconductor device according to any one of [9] to [11], wherein the second overcoat layer has a thickness of 5 μm or more and 30 μm or less.
[13] The semiconductor device according to any one of [9] to [12], wherein the surface of the second overcoat layer opposite to the surface in contact with the semiconductor layer has a bulging curved shape.
[14] The semiconductor device according to any one of [9] to [13], wherein the semiconductor device is a sensor.
[15] A wireless communication device having at least the semiconductor device according to any one of [9] to [13] and an antenna.

According to the method of manufacturing a semiconductor device of the present invention, it is possible to manufacture a semiconductor device having continuous operational stability while suppressing an increase in material and manufacturing costs.

1 is a schematic plan view showing a semiconductor device obtained by a manufacturing method according to Embodiment 1 of the present invention; FIG. Schematic cross-sectional views showing the method for manufacturing the semiconductor device according to the first embodiment of the present invention 1A and 1B are a schematic plan view and a cross-sectional view showing Modification 1 of a semiconductor device obtained by a manufacturing method according to Embodiment 1 of the present invention; FIG. 10 is a schematic plan view and a cross-sectional view showing Modification 2 of the semiconductor device obtained by the manufacturing method according to Embodiment 1 of the present invention; Schematic plan view and cross-sectional view showing a semiconductor device obtained by a manufacturing method according to a second embodiment of the present invention Schematic diagram and schematic plan view showing a semiconductor device obtained by a manufacturing method according to a third embodiment of the present invention Schematic cross-sectional view showing an example of the shape of the second overcoat layer Block diagram showing an example of a wireless communication device Circuit diagram of the ring oscillator used to evaluate the stability of continuous operation Schematic diagrams showing a method for manufacturing a semiconductor device according to Example 1 of the present invention. Schematic diagrams showing a method for manufacturing a semiconductor device according to Example 1 of the present invention. Schematic perspective view for explaining the evaluation method of bending resistance

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments for carrying out the present invention will be described in detail. It should be noted that the present invention is not limited to the following embodiments, and various modifications are naturally possible within the scope of achieving the object of the invention and not departing from the gist of the invention.

A method for manufacturing a semiconductor device according to the present invention includes, on a substrate, at least a first region in which two or more semiconductor elements are arranged, and a second region in which two or more semiconductor elements are arranged, The semiconductor element in the first region includes a source electrode, a drain electrode, a gate electrode, a semiconductor layer in contact with the source electrode and the drain electrode, a gate insulating layer insulating the semiconductor layer from the gate electrode, and a position different from the gate insulating layer. a first overcoat layer in contact with the semiconductor layer in the base material, and the semiconductor element in the second region includes a source electrode, a drain electrode, a gate electrode, a semiconductor layer in contact with the source electrode and the drain electrode, and a semiconductor layer and a second overcoat layer in contact with the semiconductor layer at a position different from that of the gate insulating layer. A method for manufacturing a semiconductor device having an electrical conductivity different from that of the semiconductor element, wherein after the step of forming the first overcoat layer, a second overcoat layer is formed, a part of which is the first It has the process of forming so that it may overlap on an overcoat layer.

<Method for manufacturing a semiconductor device>
(Embodiment 1)
FIG. 1 is a schematic diagram showing the configuration of a semiconductor device obtained by a manufacturing method according to Embodiment 1 of the present invention. FIG. 1(a) shows a schematic plan view before forming the first and second overcoat layers, and FIG. 1(b) shows a schematic plan view after forming the first and second overcoat layers, respectively.

A semiconductor device 101 has two first regions 10 on a substrate 1, in which four FETs 30 are arranged in rows in the longitudinal direction of the substrate 1, and four FETs 40 on the substrate 1. It has one second region 20 arranged in a row in the longitudinal direction. In the semiconductor device 101, two first regions 10 are divided into upper and lower portions in the lateral direction of the substrate 1, and are provided so as to sandwich a second region 20 extending in the longitudinal direction at the center of the substrate 1. As shown in FIG. 1B, the semiconductor device 101 is provided with the first overcoat layer 11 so as to cover the four FETs 30 in the first region 10, and the four FETs 30 in the second region 20. A second overcoat layer 21 is provided to cover the FETs 40 of the .

The FET 30 in the first region and the FET 40 in the second region have different electrical conductivities. The difference in electrical conductivity includes, for example, the difference in conductivity type of transistors, such as n-type semiconductor characteristics and p-type semiconductor characteristics. As a result, for example, the FETs can be connected by wiring so as to perform a desired circuit operation, thereby forming a complementary circuit.

Whether or not there is a difference in electric conductivity between the two FETs can be determined by evaluating the electric conductivity of a single semiconductor element in the semiconductor device, such as transistor characteristics. In addition, by identifying the elements contained in the semiconductor layer, the electrode, and the first and second overcoat layers by X-ray photoelectron spectroscopy (XPS), the electrical conductivity of the semiconductor element can be determined from the combination of these elements. It can be determined whether the two overcoat layers are different.

2A and 2B are schematic cross-sectional views showing a method of manufacturing the semiconductor device shown in FIG. Details thereof will be described below. In the following description, "known coating methods" include, for example, an inkjet method, a printing method, an ion plating method, a blade coating method, a slit die coating method, a screen printing method, and a bar coater method. , the mold method, the print transfer method, the immersion pull-up method, and the like.

First, (a) the lower conductive film 2 is formed on the substrate 1 . Methods for forming the lower conductive film 2 include methods such as a resistance heating vapor deposition method, an electron beam method, a sputtering method, a plating method, and a CVD method. Further, a method of applying a photosensitive conductive paste such as a paste containing a conductor and a photosensitive organic component onto a substrate by a known coating method and then drying the coating film to remove the solvent can be used. As the material of the lower conductive film 2, silver, copper and gold are preferable from the viewpoint of conductivity, and silver is more preferable from the viewpoint of cost and stability.

Next, (b) the lower conductive film 2 is patterned to form the gate electrode 3 . At this time, although not shown, lower wiring for connecting to other circuits and antennas can also be formed. As a patterning method, patterning by known photolithography (photolithography) is preferable. If the lower conductive film 2 does not have photosensitivity, a known patterning process using a photoresist can be used. When the lower conductive film 2 is formed by applying the photosensitive conductive paste onto the substrate 1, the photosensitive conductive film can be photolithographically processed. Thus, the gate electrode 3, which is a conductive pattern, is formed on the substrate 1. As shown in FIG.

Next, (c) a gate insulating layer 4 is formed on the gate electrode 3 . The method for producing the gate insulating layer 4 is not particularly limited. A method of heat-treating according to the At this time, although not shown, the gate insulating layer 4 is removed to form a contact hole in a portion connecting the lower wiring and the upper wiring (to be described later).

Next, (d) a semiconductor layer 5 is formed to cover the channel region on the gate insulating layer 4 . The method for producing the semiconductor layer 5 is not particularly limited, but for example, a method in which droplets of a semiconductor material are applied to the channel region by ink jet coating and dried. The channel region refers to the area where the network formed by the semiconductor material connects the source and drain electrodes. The distance between the source electrode and the drain electrode is the length in the moving direction of carriers, and is called the channel length. On the other hand, the length along the direction perpendicular to the channel length direction between the source electrode and the drain electrode is called the channel width.

Next, (e) an upper conductive film 6 is formed on the gate insulating layer 4 while covering the semiconductor layer 5 . As a method for forming the upper conductive film 6, the same method as the method for forming the lower conductive film 2 can be used. is coated on the substrate by a known coating method, and then the coating film is dried to remove the solvent. Drying methods include drying methods using ovens, hot plates, infrared rays, and the like.

Next, (f) the upper conductive film 6 is patterned to form a source electrode 7 and a drain electrode 8 . At this time, although not shown, upper wirings for connecting to other circuits and antennas can also be formed. When the upper conductive film 6 is formed of a paste containing a conductor and a photosensitive organic component, the source electrode 7 and the drain electrode 8 can be formed through a process including direct exposure and development.

As the exposure method, a method of exposing through a photomask is generally used, as is the case with ordinary photolithography. Alternatively, a method of direct drawing with a laser beam or the like may be used. Examples of exposure devices include stepper exposure machines and proximity exposure machines. Examples of active light sources used in this case include near-ultraviolet rays, ultraviolet rays, electron beams, X-rays, laser beams, and the like, and ultraviolet rays are preferred. Examples of ultraviolet light sources include low-pressure mercury lamps, high-pressure mercury lamps, ultra-high-pressure mercury lamps, halogen lamps, and germicidal lamps, with ultra-high-pressure mercury lamps being preferred.

As a developing method, an alkali developer such as tetramethylammonium hydroxide, potassium hydroxide, or sodium carbonate is used, and the substrate is left stationary or rotated while being sprayed with the developer, or the substrate is immersed in the developer. etc. The pattern obtained by development may be rinsed with water or an aqueous alcohol solution.

Furthermore, it is also preferable to cure the obtained pattern as necessary. Curing methods include, for example, heat drying using an oven, inert oven, hot plate, infrared rays, or the like, or vacuum drying. By this forming method, a fine wiring pattern can be formed easily.

Next, (g) a first overcoat layer 11 is formed so as to cover the semiconductor layer 5 of the FET in the first region 10 . The method for producing the first overcoat layer 11 is not particularly limited, but for example, a method of applying a raw material composition by a known coating method, drying the obtained coating film, and subjecting it to a heat treatment, if necessary, can be mentioned. be done.

Finally, (h) a second overcoat layer 21 is formed to cover the semiconductor layer 5 of the FET in the second region 20 . At this time, the second overcoat layer 21 is formed so as to partially overlap the first overcoat layer 11 . The method for producing the second overcoat layer 21 is not particularly limited, but in the same manner as the first overcoat layer, for example, a coating obtained by applying a raw material composition by a known coating method and drying it A method of heat-treating the film as necessary may be mentioned. Among the known coating methods, blade coating, slit die coating, ink jet, drop casting, dispenser, etc. are preferred because they allow coating without touching the substrate while maintaining a certain clearance. This is because the possibility of breakage or peeling of the first overcoat layer formed in the previous step can be suppressed.

The FET shown in FIG. 2 is a top contact type FET (a type in which the source and drain electrodes are in contact with the top of the semiconductor layer), but a bottom contact type (a type in which the source and drain electrodes are in contact with the bottom of the semiconductor layer). FET may be used. In this case, by performing steps (e) and (f) before step (d), a bottom-contact FET can be manufactured.

In the semiconductor device having the configuration shown in FIGS. It is necessary to apply a second overcoat layer 21 between one overcoat layer 11 . Therefore, the smaller the circuit size is, the more highly accurate coating control is required.

In addition, there is also a problem that it becomes difficult to control the amount of wetting and spreading of the second overcoat layer. When the second overcoat layer is formed by coating, the semiconductor layer of the FET is covered and the electrodes and wiring are also formed at the same time. However, since the electrode size, the number of wirings, and the like change according to the circuit design, the amount of wetting and spreading of the second overcoat layer is affected by the shapes of the electrodes and wirings, as well as the unevenness. Therefore, it is difficult to control the wetting and spreading amount of the overcoat layer for each TFT constituting the circuit.

The second overcoat layer functions as a protective layer that protects the FET and as a hole or electron doping layer for the semiconductor layer. In order to exhibit a sufficient protective effect and doping effect, the second overcoat layer needs to have a certain thickness or more. Since the film thickness of the second overcoat layer tends to vary in a state where the amount of wetting and spreading cannot be controlled, it is necessary to form a layer having a sufficient thickness in consideration of variations. This not only increases the amount of material used, but also increases the size and thickness of the semiconductor device itself.

On the other hand, after forming the first overcoat layer, the second overcoat layer is formed so that a part thereof overlaps with the first overcoat layer, so that the first overcoat layer becomes the second overcoat layer. It can be used as a partition wall that suppresses wetting and spreading of the overcoat layer. As a result, it is possible to form a layer having a thickness necessary for changing the FET characteristics while suppressing the amount of the second overcoat layer material used. In addition, since the first overcoat layer serves as a partition wall, it is possible to suppress the influence of the shapes of the electrodes and wiring of the FET and the unevenness when forming the second overcoat layer by coating. Therefore, it becomes easy to form the second overcoat layer having a more uniform film thickness, and the circuit operation is stabilized.

In the first embodiment, in the steps (g) and (h), the first overcoat layer 11 is formed in a continuous elongated shape over two or more (four in this example) semiconductor elements in the first region 10. , and the second overcoat layer 21 is formed so that a part thereof overlaps the first overcoat layer 11 along the long side of the long first overcoat layer 11 It is This makes it easier to form a uniform film thickness of the second overcoat layer.

Further, in Embodiment 1, the elongated first overcoat layers 11 are arranged in a stripe shape (two rows in this example). Thereby, both long sides of the elongated second overcoat layer 21 can be formed so as to overlap the elongated first overcoat layer 11 . Therefore, it becomes easier to form the second overcoat layer with a uniform thickness than when only one long side of the second overcoat layer 21 overlaps with the first overcoat layer 11 .

The first region FET 30 and the second region FET 40 preferably have different electrical conductivities due to the first overcoat layer and the second overcoat layer. The difference in electrical conductivity includes, for example, the difference in conductivity type of transistors, such as n-type semiconductor characteristics and p-type semiconductor characteristics. The difference in the electrical conductivity of the FET due to the overcoat layer means that the FET having the first overcoat layer and the FET having the second overcoat layer differ in the effect of each overcoat layer on the FET immediately below it. It means that electrical conductivity is different. With such a configuration, the electric conductivity of the FET can be changed without using a different semiconductor material or an electrode material with a different work function. They can be collectively formed from the same material.

(Modification 1)
FIG. 3 is a schematic diagram showing Modification 1 of the semiconductor device obtained by the manufacturing method according to Embodiment 1 of the present invention. FIG. 3(a) is a schematic plan view before the formation of the first and second overcoat layers, (b) is a schematic plan view after the formation of the first and second overcoat layers, and (c) is II-II'. Schematic cross-sectional views along lines are shown respectively.

As shown in FIG. 3A, a semiconductor device 201 has a first region 110 on a substrate 1, in which five FETs 130 are arranged in rows in a zigzag pattern in the longitudinal direction of the substrate 1. There are two locations and one second region 120 in which five FETs 140 are arranged in rows in a staggered manner in the longitudinal direction of the substrate 1 .

In FIG. 3B, the semiconductor device 201 has the first overcoat layer 111 and the second overcoat layer 121 on the FETs 130 and FETs 140 arranged in a zigzag pattern. placed in Then, as shown in FIG. 3(c), the second overcoat layer is formed so as to overlap the first overcoat layer.

The configuration and manufacturing method of such semiconductor device 201 are the same as those in the first embodiment except for the above points.

(Modification 2)
FIG. 4 is a schematic diagram showing Modification 2 of the semiconductor device obtained by the manufacturing method according to Embodiment 1 of the present invention. FIG. 4(a) is a schematic plan view before the formation of the first and second overcoat layers, (b) is a schematic plan view after the formation of the first and second overcoat layers, and (c) is III-III' Schematic cross-sectional views along lines are shown respectively.

As shown in FIG. 4A, a semiconductor device 301 has two first regions 210 on a substrate 1, in which four FETs 230 are arranged in rows in the longitudinal direction of the substrate 1. , has one second region 220 in which four FETs 240 are arranged in a row in the longitudinal direction of the substrate 1 . 4B, the semiconductor device 301 is based on the first overcoat layer 211 so as to cover a total of eight FETs 230 in two first regions 210 on the base 1. It is provided in a meander shape that is bent at the right end of the material 1 . A second overcoat layer 221 is also provided to cover the four FETs 240 in the second region 220 .

The configuration and manufacturing method of such semiconductor device 301 are the same as those in the first embodiment except for the above points.

(Embodiment 2)
FIG. 5 is a schematic diagram showing a semiconductor device obtained by a manufacturing method according to Embodiment 2 of the present invention. FIG. 5(a) is a schematic plan view before the formation of the first and second overcoat layers, (b) is a schematic plan view after the formation of the first and second overcoat layers, and (c) is IV-IV'. Schematic cross-sectional views along lines are shown respectively.

As shown in FIG. 5(a), in the semiconductor device 401, the first region 310 is located on one side of the second region 320 (short side of the base material 1) compared to the configuration of the first embodiment shown in FIG. 1(a). hand direction) only. In this case, as shown in FIGS. 5B and 5C, it is preferable to form a dummy pattern 331 on the side where the first region does not exist. By providing this dummy pattern 331, it is possible to obtain the same effect as the manufacturing method according to the first embodiment.

From the viewpoint of simplifying the manufacturing process, the dummy pattern 331 is preferably formed of the same material as the first overcoat layer 311, and can be formed in the same process as the formation of the first overcoat layer 311. preferable. The fact that the first overcoat layer 311 and the dummy pattern 331 are made of the same material means that the element with the highest molar ratio among the elements contained in each is the same. The types and content ratios of the elements can be identified by X-ray photoelectron spectroscopy (XPS).

(Embodiment 3)
FIG. 6 is a schematic diagram showing one configuration example of a semiconductor device obtained by the manufacturing method according to the third embodiment of the present invention. As shown in FIG. 6A, in the third embodiment, a plurality of semiconductor devices 501 are continuously arranged on a continuous resin base material 9 wound into a roll.

The resin substrate 9 has a longitudinal direction and a lateral direction, and the semiconductor devices 501 are formed in rows on the resin substrate 9 in the longitudinal direction. The number of columns is three in this example.

FIGS. 6B and 6C are schematic diagrams of an excerpted region including two semiconductor devices 501 surrounded by a dashed line region V in FIG. 6A. FIG. 6(b) shows a schematic plan view before forming the first and second overcoat layers, and FIG. 6(c) shows a schematic plan view after forming the first and second overcoat layers.

Each semiconductor device 501 has two first regions 410 on the resin substrate 9, in which four FETs 430 are arranged in rows in the longitudinal direction of the substrate 9, and four FETs 440 are formed by resin. It has one second region 420 arranged in a row in the longitudinal direction of the base material 9 . In the semiconductor device 501 , the two first regions 410 are divided into upper and lower portions in the lateral direction of the resin base material 9 , and are provided so as to sandwich a second region 420 extending in the longitudinal direction at the center of the resin base material 9 . there is

As shown in FIG. 6C, first overcoat layers 411 are formed on the first regions 410 at four locations in the two semiconductor devices 501, respectively. On the other hand, the second overcoat layer 421 is formed over the two second regions 420 in total.

The second overcoat layer 421 is formed so as to overlap the first overcoat layer 411 . Therefore, the second overcoat layer 421 is the uppermost layer in the semiconductor device 501 . Therefore, when the resin base material 9 is wound into a roll, the back side of the resin base material 9 and the second overcoat layer 421 are in contact with each other. Therefore, in general, the second overcoat layer 421 tends to peel off due to rubbing. However, in the third embodiment, since the second overcoat layer 421 is formed in common with the plurality of semiconductor devices 501, the second overcoat layer 421 becomes longer and is less likely to peel off. .

In Embodiment 3, the method of manufacturing individual FETs is the same as in Embodiment 1, except that the base material is elongated. That is, in Embodiment 3, the same process as shown in FIG. 2 is performed while transporting the long resin base material 9 by roll-to-roll.

<Semiconductor device>
A semiconductor device according to an embodiment of the present invention has at least a first region in which two or more semiconductor elements are arranged in a line and a first region in which two or more semiconductor elements are arranged in a line on a substrate. wherein the semiconductor element in the first region includes a source electrode, a drain electrode, a gate electrode, a semiconductor layer in contact with the source electrode and the drain electrode, a semiconductor layer and the gate electrode. and a first overcoat layer in contact with the semiconductor layer at a position different from the gate insulating layer. A base material comprising a gate electrode, a semiconductor layer in contact with the source electrode and the drain electrode, a gate insulating layer insulating the semiconductor layer from the gate electrode, and a second overcoat layer in contact with the semiconductor layer at a position different from the gate insulating layer. A semiconductor device in which electrical conductivity of a semiconductor element in a first region and a semiconductor element in a second region are different from each other due to a first overcoat layer and a second overcoat layer, a portion of the overcoat layer of (1) overlies the first overcoat layer.

In the semiconductor device according to the embodiment of the present invention, the electrical conductivity of the semiconductor element in the first region differs from that in the second region due to the first overcoat layer and the second overcoat layer. Therefore, the electrical conductivity can be varied without using different semiconductor materials or electrode materials with different work functions. Whether the second overcoat layer partially overlaps the first overcoat layer can be determined by examining the cross section of the semiconductor device substrate with a scanning electron microscope (SEM), a transmission electron microscope (TEM), or the like. This can be confirmed by observation.

In the semiconductor device according to the embodiment of the present invention, the first overcoat layer 11 extends over two or more (four in this example) semiconductor elements in the first region 10 like the semiconductor device 101 shown in FIG. The second overcoat layer 21 is arranged in a continuous long shape, and a part of the second overcoat layer 21 is placed on the first overcoat layer 11 along the long side of the long first overcoat layer 11. It is preferable to have a structure overlapping with. By having such a configuration, the first overcoat layer 11 can easily function as a partition wall for the second overcoat layer 21, and the film thickness of the second overcoat layer 21 can be kept more uniform. The operation stability of the semiconductor device is improved.

Further, the semiconductor device according to the embodiment of the present invention has a form such as the semiconductor devices 201, 301, and 401 shown in FIGS. It can take the form of device 501 .

(Base material)
The base material may be of any material as long as at least the surface on which the electrode system is arranged is a base material having insulating properties. As the base material, it is preferable to use a material that is inexpensive, has a low cost per unit area, and is excellent in flexibility, because a roll-to-roll manufacturing process is adopted. For example, polyimide (PI) resin, polyester resin, polyamide resin, epoxy resin, polycarbonate resin, cellulose resin, polyamideimide resin, polyetherimide resin, polyetherketone resin, polysulfone resin, polyphenylene sulfide (PPS) resin, cycloolefin A resin such as a resin or a resin substrate containing polypropylene (PP) is preferably used, but is not limited to these.

Among these, it is preferable to contain at least one resin selected from polyethylene terephthalate (PET), polyethylene naphthalate, PPS, polyphenylene sulfone, cycloolefin polymer, polyamide or PI, and from the viewpoint of low cost PET film is preferred.

Polysulfone resin and PPS resin are also preferable from the viewpoint of adhesion between the resin substrate and the electrodes and wiring. It is presumed that this is because metal atoms in the electrodes and wiring strongly interact with sulfur atoms contained in these resins.

The thickness of the resin substrate is preferably 25 μm or more and 100 μm or less. Within this range, durability and moderate flexibility can be achieved.

(gate electrode, source electrode, drain electrode and wiring)
The gate electrode, source electrode, drain electrode and wiring may be of any conductive material that can be generally used as electrodes. Such conductive materials include, for example, conductive metal oxides such as tin oxide, indium oxide, and indium tin oxide (ITO). In addition, metals such as platinum, gold, silver, copper, iron, tin, zinc, aluminum, indium, chromium, lithium, sodium, potassium, cesium, calcium, magnesium, palladium, molybdenum, amorphous silicon and polysilicon, among these Inorganic conductive materials such as alloys of multiple metals selected from, copper iodide, copper sulfide, and the like. Further examples include polythiophene, polypyrrole, polyaniline, a complex of polyethylenedioxythiophene and polystyrenesulfonic acid, and a conductive polymer whose conductivity is improved by doping with iodine or the like. Further examples include carbon materials, materials containing an organic component and a conductor, and the like.

A material containing an organic component and a conductor increases the flexibility of the electrode and provides good adhesion and electrical connection even when bent. Examples of organic components include, but are not limited to, monomers, oligomers or polymers, photopolymerization initiators, plasticizers, leveling agents, surfactants, silane coupling agents, antifoaming agents, pigments, and the like. From the viewpoint of improving the bending resistance of the electrode, oligomers or polymers are preferred. However, the conductive materials for the electrodes and wiring are not limited to these. These conductive materials may be used alone, or may be used by laminating or mixing a plurality of materials.

Moreover, the width and thickness of the electrodes and the spacing between the electrodes (for example, the spacing between the source electrode and the drain electrode) can be arbitrarily set according to the specifications of the FET. For example, it is preferable to set the width of each electrode to 5 μm or more and 1 mm or less. It is preferable to set the thickness of each electrode to 0.01 μm or more and 100 μm or less. The distance between the source electrode and the drain electrode is preferably set to 1 μm or more and 500 μm or less. However, these sizes are not limited to those mentioned above.

Furthermore, the width and thickness of the wiring are also arbitrary. Specifically, the thickness of the wiring is preferably set to 0.01 μm or more and 100 μm or less. It is preferable to set the width of the wiring to 5 μm or more and 500 μm or less. However, these sizes are not limited to those mentioned above.

(gate insulating layer)
The material used for the gate insulating layer is not particularly limited as long as insulation between the gate electrode 3 and the source electrode 7 and the drain electrode 8 can be ensured. Inorganic materials such as silicon oxide and alumina; polyimide, polyvinyl alcohol, polyvinyl chloride, Organic polymeric materials such as polyethylene terephthalate, polyvinylidene fluoride, polysiloxane, polyvinylphenol (PVP); or mixtures of inorganic powders and organic materials. Among them, those containing an organic compound containing a silicon-carbon bond are preferred, and polysiloxane is particularly preferred.

The insulating layer preferably contains a photosensitive organic component in order to impart pattern processability by photolithography. Photosensitive organic components include radically polymerizable compounds, photopolymerization initiators, photoacid generators, sensitizers, chain transfer agents, polymerization inhibitors, and the like.

The film thickness of the insulating layer is preferably 0.05 to 5 μm, more preferably 0.1 to 1 μm. A uniform thin film can be easily formed by setting the film thickness within this range. The film thickness can be measured by an atomic force microscope, an ellipsometry method, a spectral reflectance method, or the like.

The insulating layer may be a single layer or multiple layers. Also, one layer may be formed from a plurality of insulating materials, or a plurality of insulating materials may be laminated to form a plurality of insulating layers.

(semiconductor layer)
The material used for the semiconductor layer is not particularly limited as long as it exhibits semiconductor properties, and any material to which an inkjet coating process can be applied may be used. Preferred examples include organic semiconductors and/or carbon materials. Carbon materials are particularly preferred, and specific examples thereof include carbon nanotubes (hereinafter referred to as CNTs), graphene, and fullerenes. CNTs are preferred in terms of suitability for coating processes and high mobility.

The CNTs include a single-walled CNT in which one carbon film (graphene sheet) is cylindrically wound, a two-layered CNT in which two graphene sheets are concentrically wound, and a plurality of concentric graphene sheets. Any of the multi-layered CNTs wound on the surface may be used, and two or more kinds thereof may be used. Single-walled CNTs are preferably used from the viewpoint of exhibiting semiconductor properties, and among them, it is more preferable that the single-walled CNTs contain semiconducting single-walled CNTs in an amount of 90% by weight or more. More preferably, the single-walled CNTs contain 95% by weight or more of semiconducting single-walled CNTs.

The content ratio of semiconducting single-walled CNTs can be calculated from the absorption area ratio of the visible-near infrared absorption spectrum. CNTs can be obtained by methods such as an arc discharge method, a chemical vapor deposition method (CVD method), and a laser ablation method.

Among them, CNT is preferable as the material used for the semiconductor layer because of the ease of forming the semiconductor layer. Furthermore, CNTs having a conjugated polymer attached to at least a portion of the surface (hereinafter referred to as a CNT composite) are particularly preferred because they have excellent dispersion stability in a solution and provide high mobility. Here, the conjugated polymer refers to a compound whose repeating unit has a conjugated structure and whose degree of polymerization is 2 or more.

The state in which the conjugated polymer adheres to at least part of the surface of the CNT means a state in which the conjugated polymer covers part or all of the surface of the CNT. The reason why the conjugated polymer can cover the CNTs is presumed to be that the π electron clouds derived from the respective conjugated structures overlap and interact with each other. Whether or not the CNTs are coated with the conjugated polymer can be determined by making the reflected color of the coated CNTs closer to the color of the conjugated polymer than the color of the uncoated CNTs. Quantitatively, elemental analysis such as X-ray photoelectron spectroscopy (XPS) can identify the presence of deposits and the mass ratio of deposits to CNTs.

By attaching a conjugated polymer to at least part of the CNT surface, the CNT composite can uniformly disperse the CNTs in a solution without impairing the high electrical properties of the CNTs. In addition, it is possible to form a uniformly dispersed CNT film by a coating method using a dispersion liquid in which CNTs are uniformly dispersed. Thereby, high semiconductor characteristics can be realized.

The method of adhering the conjugated polymer to the CNTs includes (I) a method of adding CNTs to the molten conjugated polymer and mixing them, and (II) dissolving the conjugated polymer in a solvent and dissolving the CNTs therein. (III) A method of adding and mixing a conjugated polymer to a place where CNTs have been pre-dispersed in a solvent using ultrasonic waves, etc. (IV) A method of adding a conjugated polymer to a solvent and CNTs, and irradiating this mixed system with ultrasonic waves for mixing. In the present invention, multiple methods may be combined.

In the present invention, the length of the CNT is preferably shorter than the set distance between the source electrode and the drain electrode. The average length of CNTs is preferably 2 μm or less, more preferably 0.5 μm or less, depending on the distance between the source electrode and the drain electrode. Commercially available CNTs generally have a distribution in length, and some CNTs are longer than the distance between the source electrode and the drain electrode. . For example, it is effective to cut into short fibers by acid treatment with nitric acid or sulfuric acid, ultrasonic treatment, or freeze pulverization. In addition, it is more preferable to use separation by a filter together in order to improve the purity.

Although the diameter of the CNT is not particularly limited, it is preferably 0.5 nm or more and 100 nm or less, more preferably 1 nm or more and 50 nm or less.

Examples of the conjugated polymer that coats the CNT include polythiophene-based polymer, polypyrrole-based polymer, polyaniline-based polymer, polyacetylene-based polymer, poly-p-phenylene-based polymer, and poly-p-phenylenevinylene-based polymer. A thiophene-heteroarylene polymer having a thiophene unit and a heteroaryl unit in a repeating unit, etc., may be mentioned, and two or more of these may be used. As the above polymer, one in which single monomer units are arranged, one obtained by block copolymerization of different monomer units, one obtained by random copolymerization, one obtained by graft polymerization, or the like can be used.

Moreover, a CNT composite and an organic semiconductor may be mixed and used for the semiconductor layer. By uniformly dispersing the CNT complex in the organic semiconductor, it is possible to achieve high mobility while maintaining the characteristics of the organic semiconductor itself.

Moreover, the semiconductor layer may further contain an insulating material. The insulating material used here includes, but is not limited to, the insulating material composition of the present invention and polymeric materials such as poly(methyl methacrylate), polycarbonate, and polyethylene terephthalate.

The semiconductor layer may be a single layer or multiple layers, and the film thickness is preferably 1 nm or more and 200 nm or less, more preferably 100 nm or less. By setting the film thickness within this range, it is possible to easily form a uniform thin film, suppress the source-drain current that cannot be controlled by the gate voltage, and increase the on/off ratio of the FET. The film thickness can be measured by an atomic force microscope, an ellipsometry method, or the like.

(First overcoat layer)
The first overcoat layer is formed on the side opposite to the side on which the gate insulating layer is formed with respect to the semiconductor layer of the semiconductor element in the first region. The side opposite to the side where the gate insulating layer is formed with respect to the semiconductor layer refers to, for example, the upper side of the semiconductor layer when the gate insulating layer is provided below the semiconductor layer. By forming the first overcoat layer, the semiconductor element is protected from physical damage such as rubbing, moisture and oxygen in the atmosphere, and for example, the on-current and off-current of CNT-FETs exhibiting p-type semiconductor characteristics are reduced. can be adjusted. That is, the first overcoat layer can function as a protective layer and a property-adjusting layer.

The first overcoat layer as a protective layer includes, for example, polyimide, polyvinyl alcohol, polyvinyl chloride, polyethylene terephthalate, polyvinylidene fluoride, polysiloxane, polyvinylphenol, polyester, polycarbonate, polysulfone, polyethersulfone, polyethylene, polyphenylene sulfide, It is preferably composed of an organic polymer such as polyparaxylene, polyacrylonitrile, cycloolefin polymer, or the like.

Moreover, the first overcoat layer as a property-adjusting layer preferably contains an electron-withdrawing compound. The electron-withdrawing compound has at least two groups selected from a halogen atom, a carbonyl group, a cyano group, a nitro group, a sulfinyl group, a sulfonyl group and an imide group in one carbon-carbon double bond or one conjugated system. It is preferable to contain a compound having a structure in which two or more are linked. The structures described above greatly affect the electron density of the π orbitals of one carbon-carbon double bond or one conjugated system. Structures such as one carbon-carbon double bond or one conjugated system are likely to have π-π interactions and charge transfer interactions with semiconductor materials such as CNTs or graphene, so the compounds can interact with semiconductor materials such as CNTs or graphene. It is presumed that they can interact strongly electronically.

A conjugated system is a system in which two or more multiple bonds are conjugated. π electrons in multiple bonds interact and delocalize through single bonds. Conjugated structures are, for example, structures in which double and/or triple bonds are linked by single bonds, atoms with lone pairs of electrons or atoms with empty p-orbitals.

The first overcoat layer preferably further contains a polymer. Examples of the polymer include the polymer described above for the protective layer, polypropylene, polystyrene, polyvinyl acetate, and acrylic resin. By distributing the compound in the polymer, the amount and strength of the compound interacting with the semiconductor material can be adjusted, making it easier to adjust the semiconductor properties.

The first overcoat layer may contain other compounds in addition to the organic polymer and the electron-withdrawing compound. Other compounds include, for example, thickeners and thixotropic agents for adjusting the viscosity and rheology of the solution when forming the first overcoat layer by coating.

(Second overcoat layer)
The second overcoat layer is formed on the side opposite to the side on which the gate insulating layer is formed with respect to the semiconductor layer of the semiconductor element in the second region. The side opposite to the side where the gate insulating layer is formed with respect to the semiconductor layer refers to, for example, the upper side of the semiconductor layer when the gate insulating layer is provided below the semiconductor layer. By forming the second overcoat layer, for example, a CNT-FET that normally exhibits p-type semiconductor properties can be converted into a semiconductor device that exhibits n-type semiconductor properties.

The second overcoat layer preferably contains an electron-donating compound having at least one selected from nitrogen atoms and phosphorus atoms. Any organic compound may be used as such an organic compound, and examples include amide-based compounds, imide-based compounds, urea-based compounds, amine-based compounds, imine-based compounds, aniline-based compounds, nitrile-based compounds, and alkylphosphine-based compounds. can be mentioned.

The second overcoat layer preferably further contains a polymer. This is because the polymer enhances the oxygen shielding property, and in the process of forming the second overcoat layer by the coating method, it is possible to form a film by drying under mild annealing conditions, and the adhesion is also improved. is. Polymers contained in the second overcoat layer include acrylic resins, methacrylic resins, olefin polymers, cycloolefin polymers, polystyrene, polysiloxane, polyimide, polycarbonate, vinyl alcohol resins, phenol resins, and the like.

The second overcoat layer may contain other compounds in addition to the electron-donating compound and polymer. Other compounds include, for example, thickeners and thixotropic agents for adjusting the viscosity and rheology of the solution when the second overcoat layer is formed by coating. When applying a composition containing an electron-donating compound having at least one selected from nitrogen atoms and phosphorus atoms, the electron-donating compound does not affect FETs that do not form an overcoat layer. influence the transistor characteristics. Although the detailed mechanism is unknown, it is thought that a part of the electron-donating compound is liberated from the coating film in the drying process during coating formation and adheres to the semiconductor layer of the FET that does not form the overcoat layer. Therefore, by applying a composition containing these electron-donating compounds to the second overcoat layer, the first overcoat layer in the previous step protects the FETs for which the second overcoat layer is not formed. Therefore, the variation in transistor characteristics can be suppressed, and the semiconductor device can easily operate stably.

The first overcoat layer is arranged in a continuous elongated shape over two or more semiconductor elements in the first region, and the second overcoat layer is partially elongated in the first overcoat layer When the overcoat layer is arranged in a long shape so as to overlap the first overcoat layer along the long side of the overcoat layer, the width of the second overcoat layer is 10 times the thickness of the second overcoat layer. It is preferably more than twice and less than 50 times. The width of the second overcoat layer refers to the thickness of the second overcoat layer in the direction perpendicular to the continuous direction of the continuous second overcoat layer formed on the adjacent semiconductor elements. Point.

When the second overcoat layer is arranged in a long shape as described above, the width of the second overcoat layer in the short direction is preferably 10 times or more and 50 times or less. With this range, it is possible to obtain a semiconductor device with a reduced circuit area while suppressing variations in transistor characteristics. Moreover, the flexibility of the second overcoat layer can be ensured, and the adhesion to the semiconductor layer is improved even when bent. Therefore, when an external force such as bending is applied to the semiconductor element, voids or cracks are generated in the second insulating layer, and a phenomenon that the oxygen shielding property is lowered can be suppressed.

More preferably, the thickness of the second overcoat layer is 5.0 μm or more. By setting the film thickness within this range, the oxygen shielding property can be enhanced, and fluctuations in transistor characteristics can be easily suppressed. Also, the upper limit of the thickness of the second overcoat layer is preferably 30 μm or less. With the film thickness in this range, the second overcoat layer has better flexibility.

Setting the upper limit of the thickness of the second overcoat layer to 30 μm or less is particularly effective when a plurality of semiconductor devices are formed on a long resin substrate as in the third embodiment. . The resin substrate wound into a roll is wound so that the second overcoat layer is superimposed thereon. At that time, tight winding occurs inside the roll due to changes over time, and the second overcoat layer rubs and becomes easy to peel off. It is preferable because the flexibility, bendability, and adhesion of the layer can be maintained, and peeling can be suppressed. In addition, by setting the film thickness within this range, it is possible to suppress the occurrence of gauge bands that occur when the second overcoat layer is wound while being overlapped.

The film thickness of the second overcoat layer means the film thickness from the surface in contact with the semiconductor layer to the surface on the opposite side. When the surface of the second overcoat layer has a curved shape, the thickness of the second overcoat layer is the maximum thickness in the vertical direction from the surface in contact with the semiconductor layer. The film thickness of the second overcoat layer can be measured by observing its cross section with an electron microscope.

The second overcoat layer preferably has a curved shape such that the surface opposite to the surface in contact with the semiconductor layer swells. When the second overcoat layer is arranged in a continuous long shape, in the cross section of the second overcoat layer on the semiconductor layer in the short direction, the surface opposite to the surface in contact with the semiconductor layer is curved like a bow, and it is preferable to have a shape in which similar cross sections are continuous in the longitudinal direction at least on the region in contact with the semiconductor layer.

However, the vicinity of both ends of the second overcoat layer in the longitudinal direction does not necessarily have to have the same cross-sectional shape, and it may be curved in the longitudinal direction and the film thickness may gradually decrease. By having such a curved shape that the surface opposite to the surface in contact with the semiconductor layer swells, the volume of the second overcoat layer can be reduced compared to a rectangular shape having the same thickness. The amount of material used can be reduced. Moreover, since the surface area of the second overcoat layer can be reduced, the area exposed to the outside air is reduced, and the oxygen shielding property can be improved.

FIG. 7 shows an example of a cross section in the case where the surface of the second overcoat layer opposite to the surface in contact with the semiconductor layer has a bulging curved shape. In addition, the present invention is not limited by these cross-sectional examples. In FIG. 7A, the surface shape of the second overcoat layer 121 is an (elliptical) arc shape. In FIG. 7(b), the surface shape of the second overcoat layer 121 is such that the end overlapping the first overcoat layer has a linear shape and the upper portion has an (elliptic) arc. In FIG. 7C, the surface shape of the second overcoat layer 121 is a shape formed by combining a plurality of circular arcs with different radii. In FIG. 7(d), the surface shape of the second overcoat layer 121 is an arc shape having two bumps. The number of bumps is not limited to two, and may be three or more.

<Applicability of semiconductor device>
The method of manufacturing a semiconductor device according to the embodiment of the present invention can be applied to ICs of various electronic devices, wireless communication devices such as RFID tags, TFT arrays for displays, sensors, unsealing detection systems, and the like.

<Wireless communication device>
Next, a wireless communication device including a semiconductor device manufactured using the manufacturing method according to the embodiment of the present invention will be described. This wireless communication device is a device that communicates information using radio waves, such as product tags, shoplifting prevention tags, various tickets, and smart cards.

A wireless communication device includes at least the semiconductor device described above and an antenna. This wireless communication device is a device that operates using radio waves received by an antenna. Examples of the wireless communication device are not particularly limited, but (1) a power feeding device that supplies energy in a contactless manner without using a wired connection using an adapter, (2) a carrier that partially modulates a carrier wave used for sensing, and (3) a device that exchanges information by receiving a carrier wave transmitted from an antenna mounted on a reader/writer; More specific examples of (3) include RFID (Radio Frequency Identification) tags, which are contactless tags such as product tags, shoplifting prevention tags, various tickets and smart cards.

A specific operation of the wireless communication device will be described using an RFID tag as an example. For example, the one shown in FIG. 8 can be mentioned. This includes a power generation unit that rectifies the modulated wave signal from the outside received by the antenna 50 and supplies power to each unit, a demodulation circuit that demodulates the modulated wave signal and transmits it to the control circuit, and a a modulation circuit that modulates the data obtained by the demodulation circuit and transmits the data to the antenna; Each circuit section is electrically connected.

The demodulation circuit, control circuit, modulation circuit, and memory circuit may include the above-described semiconductor devices, and may further include capacitors, resistors, and diodes. The power generation unit is composed of a capacitor and a diode.

The antenna, capacitor, resistive element, and diode may be those commonly used, and the materials and shapes used are not particularly limited. Also, the material for electrically connecting the components described above may be any conductive material that can be generally used. Any method may be used to connect each component as long as it can establish electrical continuity. The width and thickness of the connecting portion of each component are arbitrary.

<product tag>
Next, a product tag containing a wireless communication device including a semiconductor device manufactured using the manufacturing method according to the embodiment of the present invention will be described. This product tag has, for example, a base and the wireless communication device covered by this base.

The substrate is formed of a non-metallic material such as paper, which is formed in a flat plate shape, for example. For example, the base has a structure in which two flat sheets of paper are pasted together, and the wireless communication device is arranged between the two sheets of paper. For example, individual identification information for individual identification of products is stored in advance in the memory circuit of the wireless storage device.

Wireless communication is performed between the product tag and the reader/writer. A reader/writer is a device that wirelessly reads and writes data from a product tag. The reader/writer exchanges data with the product tag during the product distribution process and payment. The reader/writer includes, for example, a portable type and a fixed type installed at a cash register. A known reader/writer can be used for the product tag according to the embodiment of the present invention.

A product tag according to an embodiment of the present invention has an identification information reply function. This is a function in which the product tag wirelessly returns the individual identification information stored therein when receiving a command requesting transmission of the individual identification information from a predetermined reader/writer. With one command from the reader/writer, the individual identification information of each tag is transmitted from many product tags. This function makes it possible, for example, to simultaneously identify a large number of products in a non-contact manner at a product checkout. Therefore, settlement processing can be facilitated and speeded up compared to identification by bar code.

Further, for example, when checking out a product, the reader/writer can transmit the product information read from the product tag to a POS (Point of sale system, point of sale information management) terminal. With this function, it is possible to register sales of products specified by the product information at the POS terminal, so that inventory management can be facilitated and speeded up.

<Sensor>
Various sensors can be obtained by using the semiconductor device manufacturing method according to the embodiment of the present invention. Various sensors include, for example, sensors that detect temperature, moisture, gas, light, electromagnetic waves, radiation, pressure, and the like. INDUSTRIAL APPLICABILITY The present invention is preferably used when the sensor is a semiconductor sensor and the semiconductor sensor is manufactured.

EXAMPLES The present invention will now be described more specifically based on examples. It should be noted that the present invention should not be construed as being limited to the following examples. Each evaluation method in the examples will be described in the following [1] to [3].

[1] Measurement of thickness The thickness of the second overcoat layer was measured. For the measurement, a scanning electron microscope (SEM) was used to observe five cross sections of an arbitrary FET in which the second overcoat layer was formed in the semiconductor device, and the thickness of the second overcoat layer was measured. Measurements were taken and the mean and standard deviation were calculated.

[2] Evaluation of stability of continuous operation As a semiconductor device, the ring oscillator of the circuit diagram shown in FIG. NF circuit design block, WF1974) is used to input a square wave (1 kHz, 5 V) as an input signal, and an oscilloscope (Keysight Technologies, DSOX1204A) is used to measure the output waveform in the atmosphere (23 ° C., humidity 40%). Observed. When the amplitude of the output waveform became 4.5 V or less, the operation was determined to be NG, and the continuous operation time from the start of application of the input signal until the output waveform became NG was determined as follows. Evaluations A to D indicate that the semiconductor device has a long continuous operation time and good stability of continuous operation.
(continuous operation time)
A: 30 minutes or more B: 30 minutes or less, 15 minutes or more C: 15 minutes or more, 10 minutes or more D: 10 minutes or more, 5 minutes or more E: 2 minutes or more, 1 minute or more F: 1 minute or more short.

[3] Bend resistance evaluation Description will be made with reference to FIG. 11 . A metal cylinder 29 having a diameter of 30 mm was fixed to the center of the surface of the substrate 1 on which the semiconductor device was formed. (see FIG. 11(a)), and the folding operation was performed until the embrace angle to the cylinder reached 180° (the state where the cylinder was folded back) (see FIG. 11(b)). The bending resistance was evaluated by observing the first overcoat layer and the second overcoat layer of the semiconductor device before and after the bending operation with an optical microscope, and evaluating according to the following criteria.
A (Good): No peeling or chipping is observed in the first overcoat layer and the second overcoat layer even after the bending operation is repeated 500 times.
B (acceptable): No peeling or chipping was observed in the first overcoat layer and the second overcoat layer even after the bending operation was repeated 100 times.
C (improper): When the bending operation was repeated less than 100 times, at least part of the first overcoat layer and the second overcoat layer were peeled off and chipped.

[4] Measurement of Width The width of the second overcoat layer was measured. For the measurement, an optical microscope ECLIPSE L200N (manufactured by Nikon Instech Co., Ltd.) was used to observe the width of five arbitrary FETs on which the second overcoat layer was formed in the semiconductor device using an optical microscope. Then, the width of the second overcoat layer was measured and the average value was calculated.

Preparation Example 1: Polysiloxane solution A
13.12 g (0.05 mol) of 3-trimethoxysilylpropylsuccinic anhydride (SucSi), 93.73 g (0.40 mol) of 3-acryloxypropyltrimethoxysilane (AcrSi) and phenyltrimethoxysilane (PheSi) ) was dissolved in 215.91 g of propylene glycol monomethyl ether acetate (PGMEA, boiling point 146° C.), and 54.90 g of water and 0.864 g of phosphoric acid were added with stirring. The resulting solution was heated at a bath temperature of 105° C. for 2 hours to raise the internal temperature to 90° C., thereby distilling off a component mainly composed of methanol as a by-product. Next, the mixture was heated at a bath temperature of 130° C. for 2 hours to raise the internal temperature to 118° C. to distill out components mainly composed of water and methanol, and then cooled to room temperature to obtain a polysiloxane having a solid content of 26.0% by mass. A solution A was obtained. 10 g of the resulting polysiloxane solution A was weighed out, mixed with 0.83 g of PGMEA, and stirred at room temperature for 2 hours to obtain a polysiloxane solution A (solid concentration: 24% by mass).

Preparation Example 2: Gate insulating layer material solution A
10 g of polysiloxane solution A is weighed, 1.04 g of DPHA (trade name “KAYARAD”, manufactured by Nippon Kayaku Co., Ltd.; dipentaerythritol hexaacrylate), OXE-01 (trade name “Irgacure”, BASF Corporation) 0.15 g of PGMEA) and 4.60 g of PGMEA were mixed and stirred at room temperature for 2 hours to obtain an insulating layer material solution A (solid concentration: 23% by mass) having negative photosensitivity.

Preparation Example 3: Synthesis of compound A having a carboxyl group Copolymerization ratio (based on mass): ethyl acrylate (hereinafter “EA”)/2-ethylhexyl methacrylate (hereinafter “2-EHMA”)/styrene (hereinafter “ St”)/glycidyl methacrylate (hereinafter “GMA”)/acrylic acid (hereinafter “AA”)=20/40/20/5/15.

150 g of diethylene glycol monoethyl ether acetate (hereinafter referred to as "DMEA") was introduced into a reaction vessel in a nitrogen atmosphere, and the temperature was raised to 80°C using an oil bath. To this was added a mixture consisting of 20 g EA, 40 g 2-EHMA, 20 g St, 15 g AA, 0.8 g 2,2′-azobisisobutyronitrile and 10 g DMEA dropwise over 1 hour. did. After the dropwise addition was completed, the polymerization reaction was continued for another 6 hours. After that, 1 g of hydroquinone monomethyl ether was added to stop the polymerization reaction. A mixture of 5 g GMA, 1 g triethylbenzylammonium chloride and 10 g DMEA was subsequently added dropwise over 0.5 hours. After the dropwise addition was completed, the addition reaction was carried out for another 2 hours. The obtained reaction solution was purified with methanol to remove unreacted impurities, and further vacuum-dried for 24 hours to obtain compound A having a carboxyl group.

Preparation Example 4: Photosensitive conductive paste A
In a 100 ml clean bottle, 10 g of the compound A obtained above, 1.5 g of light acrylate BP-4EA (manufactured by Kyoeisha Chemical Co., Ltd.), which is a compound having a carbon-carbon double bond, and a photopolymerization initiator OXE-01. 0.5 g (manufactured by BASF Japan Ltd.) and 10 g of γ-butyrolactone (manufactured by Mitsubishi Gas Chemical Co., Ltd.) are added, and a rotation-revolution vacuum mixer "Awatori Mixer" (registered trademark) (ARE-310; Thinky Co., Ltd.) ) to obtain 22 g of a photosensitive resin solution. 13.0 g of the resulting photosensitive resin solution and 30.0 g of Ag particles having an average particle size of 0.20 μm are mixed and kneaded using a three-roller “EXAKT M-50” (trade name, manufactured by EXAKT). and 43 g of photosensitive conductive paste A was obtained.

Preparation Example 5: Semiconductor solution A
In the preparation of the semiconductor solution, first, CNT (manufactured by CNI, single-wall CNT, purity 95%) was added to a chloroform solution (10 ml) containing 2.0 mg of P3HT (manufactured by Aldrich Co., Ltd., poly(3-hexylthiophene)). was added, and the mixture was ultrasonically stirred for 4 hours at an output of 20% using an ultrasonic homogenizer (manufactured by Tokyo Rikakikai Co., Ltd., VCX-500) while cooling with ice. As a result, CNT dispersion A11 (having a CNT complex concentration of 0.96 g/l with respect to the solvent) was obtained.

Next, using a membrane filter (pore size 10 μm, diameter 25 mm, Omnipore membrane manufactured by Millipore), the CNT dispersion A11 was filtered to remove CNT composites having a length of 10 μm or more. After adding 5 ml of o-DCB (manufactured by Wako Pure Chemical Industries, Ltd.) to the filtrate thus obtained, chloroform, which is a low boiling point solvent, is distilled off using a rotary evaporator, thereby removing the solvent from o- Substitution with DCB gave CNT Dispersion B11. 3 ml of o-DCB was added to CNT dispersion B11 (1 ml) to obtain semiconductor solution A (having a CNT complex concentration of 0.03 g/l with respect to the solvent).

Preparation Example 6: Overcoat layer solution A
A polymer solution A was prepared by dissolving 7.5 g of polymethyl methacrylate (manufactured by Fuji Film Wako Pure Chemical Industries, Ltd.) in 22.5 g of cyclohexanone. Next, 0.225 g of p-benzoquinone (manufactured by Tokyo Kasei Kogyo Co., Ltd.) was added to the polymer solution A and treated with a hybrid mixer to obtain an overcoat layer solution A.

Preparation Example 7: Overcoat layer solution B
An overcoat layer solution B was obtained in the same manner as in Composition Preparation Example 7, except that p-chloranil (manufactured by Tokyo Chemical Industry Co., Ltd.) was used instead of p-benzoquinone.

Preparation Example 8: Overcoat layer solution C
Polymethyl methacrylate (manufactured by Fujifilm Wako Pure Chemical Industries, Ltd. 4.5 g was dissolved in N,N-dimethylformamide 25.5 g to prepare a polymer solution B. Next, N, N, N', N'- 1 g of tetramethyl-1,4-phenylenediamine (manufactured by Tokyo Chemical Industry Co., Ltd.) was dissolved in 9.0 g of N,N-dimethylformamide to prepare compound solution A. 6.0 g of compound solution A was added to 13.6 g of polymer solution B. was added to obtain an overcoat layer solution C.

Preparation Example 9: Overcoat layer solution D
Adjustment except that N,N,N',N'-tetramethylbenzidine (manufactured by Tokyo Chemical Industry Co., Ltd.) was used instead of N,N,N',N'-tetramethyl-1,4-phenylenediamine An overcoat layer solution D was obtained in the same manner as in Example 8.

Preparation Example 10: Overcoat layer solution E
Instead of polymer solution B, polymethyl methacrylate (10 g manufactured by Fujifilm Wako Pure Chemical Industries, Ltd. was dissolved in 20 g of N,N-dimethylformamide, and polymer solution C was used in the same manner as in Preparation Example 7. Overcoat Layer solution E was obtained.

Preparation Example 11: Overcoat layer solution F
Instead of polymer solution B, polymethyl methacrylate (12 g manufactured by Fujifilm Wako Pure Chemical Industries, Ltd. was dissolved in 18 g of N,N-dimethylformamide, and polymer solution D was used in the same manner as in Preparation Example 7. Overcoat A layer solution F was obtained.

(Example 1)
In Example 1, in the semiconductor device shown in FIG. 5, a semiconductor device was manufactured in which the circuit portion had a ring oscillator formed by combining field-effect transistors with a bottom-gate/top-contact structure.

In the fabrication of the semiconductor device of Example 1, as exemplified in the second embodiment described above, after forming the FET, a first overcoat layer is formed on the FET in the first region to form a p-type semiconductor device. and a second overcoat layer was formed on the FET in the second region to form an n-type FET. Then, an inverter including them was formed, and using this inverter, a ring oscillator, which is an oscillation circuit, was manufactured.

FIG. 8 is a schematic plan view showing the configuration of the ring oscillator according to the first embodiment. The ring oscillator 27 is configured by connecting 21 stages of inverters 26 in series. In FIG. 8, in order to simply show the configuration of the ring oscillator 27, among the 21 inverters 26, the illustration of the inverter 26 having a repeated configuration is omitted. A plurality of sets of FETs forming each of these inverters 26 are connected by wiring (not shown).

A specific method for manufacturing a semiconductor device will be described with reference to FIGS. First, copper was vapor deposited on the entire surface of a PET film substrate 1 (width 35 mm, length 120 mm, film thickness 50 μm) by resistance heating. A photoresist (trade name “LC100-10cP”, manufactured by Rohm and Haas Co., Ltd.) was printed on the entire surface by slit coating, and dried by heating at 100° C. for 4 minutes in a hot air drying oven. The prepared photoresist film was subjected to full-line exposure at an exposure amount of 40 mJ/cm ² (converted to a wavelength of 365 nm) through a photomask on which the gate electrode 3 was designed. The width of the gate electrode designed on the photomask was set to 50 μm. After exposure, the film was developed with a 2.38% by weight tetramethylammonium hydroxide aqueous solution for 30 seconds and then washed with water for 1 minute. After that, it was etched with a mixed acid (trade name: SEA-5, manufactured by Kanto Kagaku Co., Ltd.) for 30 seconds, and then washed with water for 30 seconds. The resist was removed by immersion in a photoresist remover (trade name: AZ Remover 100, manufactured by Merck Performance Materials Co., Ltd.) for 2 minutes, washed with water for 30 seconds, and then water droplets were removed with an air knife. After that, it was dried by heating in a hot air drying oven at 80° C. for 60 seconds to form the gate electrode 3 (FIG. 10(a)).

After that, the gate insulating layer solution A to be the gate insulating layer was printed by spin coating, and dried by heating in a hot air drying oven at 100° C. for 2 minutes. The produced gate insulating layer film was fully exposed through a photomask with an exposure amount of 80 mJ/cm ² (converted to a wavelength of 365 nm). After the exposure, the film was developed with a 2.38% by weight tetramethylammonium hydroxide aqueous solution for 30 seconds, and then washed with water for 1 minute to expose the electrode in the contact hole portion from the gate insulating layer. Thereafter, a heat treatment was performed in an IR drying oven at 150° C. for 10 minutes in a nitrogen atmosphere to form a gate insulating layer 4 with a thickness of 0.5 μm (FIG. 10B).

On the substrate on which the gate insulating layer is formed as described above, 100 pl of the semiconductor solution A is applied by an ink jet method to each of the gate insulating layers positioned on the projection of the gate electrode, and is placed in an IR drying oven under a nitrogen stream. A semiconductor layer 5 was formed by performing heat treatment at 150° C. for 30 minutes (FIG. 10(c)).

Next, the photosensitive conductive paste A was applied by screen printing onto the substrate made of PET film on which the gate insulating layer was formed, and prebaked at 100° C. for 4 minutes in a hot air drying oven. After that, full line exposure was performed at an exposure amount of 80 mJ/cm ² (converted to a wavelength of 365 nm) through a photomask on which the source electrode 7 and the drain electrode 8 were designed. After exposure, the film was developed with a 0.5% Na ₂ CO ₃ solution for 30 seconds, washed with ultrapure water for 60 seconds, and cured in an IR drying oven at 150° C. for 10 minutes. Thus, a source electrode 7 and a drain electrode 8 were formed (FIG. 10(d)). The width of the source and drain electrodes was 1000 μm, and the distance between these electrodes was 20 μm. Hereinafter, the upper row of the substrate 1 will be referred to as the first region 10 and the lower row will be referred to as the second region 20 . Further, the inter-device distance L1 between the FET 30 in the first region and the FET 40 in the second region was set to 600 μm.

Next, on the PET film substrate on which the semiconductor layer is formed, the overcoat layer solution A is applied onto the semiconductor layer 5 in the first region 10 by screen printing so as to cover the semiconductor layer 5. applied in a shape. Thereafter, heat treatment was performed at 110° C. for 30 minutes under a nitrogen stream to form the first overcoat layer 11 and the dummy pattern 31 (FIG. 10(e)).

Next, the overcoat layer solution C is applied onto the PET film substrate on which the semiconductor layer is formed, onto the semiconductor layer 5 in the second region 20, the semiconductor layer 5 is covered, and a portion of the semiconductor layer 5 is covered with the first layer. It was coated in a long shape by a dispenser coating method so as to overlap the overcoat layer. Thereafter, heat treatment was performed at 110° C. for 30 minutes in a nitrogen stream to form a second overcoat layer 21 (FIG. 10(f)). A semiconductor device was thus obtained. Using the obtained semiconductor device, evaluation was performed according to the above evaluation methods [1] to [3]. Table 1 shows the results of [1] to [4]. Further, a cross section of the manufactured semiconductor device was observed with an SEM, and it was observed that the second overcoat layer overlapped with the first overcoat layer.

(Examples 2-4)
In Examples 2 to 4, the semiconductor was prepared in the same manner as in Example 1 except that the overcoat layer solutions for forming the first overcoat layer and the second overcoat layer were used as shown in Table 1. A device was produced and evaluated in the same manner as in [1] to [4] of Example 1. Table 1 shows the evaluation results. In addition, the cross section of each of the semiconductor devices of Examples 2 to 4 manufactured using SEM was observed, and in the semiconductor devices of Examples 2 to 4, the second overcoat layer 21 overlapped the first overcoat layer 11. observed that

(Example 5)
In Example 5, a semiconductor device was fabricated in the same manner as in Example 1 except that the dummy pattern 31 was not formed when the first overcoat layer 11 was formed. ] was evaluated in the same way. Table 1 shows the evaluation results. Further, the cross section of the semiconductor device of Example 5 manufactured using SEM was observed, and it was observed that the second overcoat layer 21 overlapped the first overcoat layer 11 in the semiconductor device of Example 5. did.

(Examples 6 and 7)
In Examples 6 and 7, the inter-device distance L1 between the FET 30 in the first region and the FET 40 in the second region was changed by 0.2 mm. A semiconductor device was produced in the same manner as in Example 1 except that the overcoat layer solutions at the time of formation were used as shown in Table 1, and the same evaluations as in [1] to [4] of Example 1 were performed. Did. Table 1 shows the evaluation results. Further, the cross section of each of the semiconductor devices of Examples 6 and 7 manufactured using SEM was observed, and in the semiconductor devices of Examples 6 and 7, the second overcoat layer 21 overlapped the first overcoat layer 11. observed that

(Example 8)
In Example 8, a semiconductor device was fabricated in the same manner as in Example 7 except that the dispenser coating and heat treatment steps of the second overcoat layer were repeated twice to form an overcoat. - Evaluation similar to [4] was performed. Table 1 shows the evaluation results. Further, by observing the cross section of each of the semiconductor devices of Example 8 produced using SEM, it was found that the semiconductor device of Example 8 had the second overcoat layer 21 overlaid on the first overcoat layer 11 . Observed.

(Comparative example 1)
In Comparative Example 1, considering the wetting and spreading of the overcoat layer solution C so that the overcoat layer solution C does not overlap the overcoat layer 11, the gap between the elements of the FET 30 in the first region and the FET 40 in the second region A semiconductor device was produced in the same manner as in Example 5 except that the design was changed so that the distance L1 was 0.8 mm wider than in Example 5, and the same evaluations as in [1] to [4] of Example 1 were performed. did. Table 1 shows the evaluation results. Further, the cross section of the semiconductor device of Comparative Example 1 manufactured using SEM was observed, and it was observed that the second overcoat layer 21 did not overlap the first overcoat layer 11 in the semiconductor device of Comparative Example 1. did. In Comparative Example 1, when the coating amount of the second overcoat layer solution was the same as in Example 1, the film thickness became thin due to wetting and spreading.

(Comparative example 2)
In Comparative Example 2, the inter-device distance L1 between the FET 30 in the first region and the FET 40 in the second region was changed to be 1.2 mm wider than in Example 1. A semiconductor device was produced in the same manner as in Comparative Example 1 except that the discharge amount was changed to be twice that of Example 1, and the same evaluations as in [1] to [4] of Example 1 were performed. Table 1 shows the evaluation results. Further, the cross section of each of the semiconductor devices of Comparative Example 2 manufactured using SEM was observed, and it was found that the second overcoat layer 21 did not overlap the first overcoat layer 11 in the semiconductor device of Comparative Example 2. Observed. In Comparative Example 2, as in Comparative Example 1, the film thickness was uneven due to the wetting and spreading of the solution of the second overcoat layer 21 . Also, since the second overcoat layer was formed thick enough to reduce the influence of its film thickness variation, the operation stability was improved, but the amount of material used was increased. The circuit size was about twice as large as that of the first embodiment due to the spread of L1.

1 base material 2 lower conductive film 3 gate electrode 4 gate insulating layer 5 semiconductor layer 6 upper conductive film 7 source electrode 8 drain electrode 9 resin base material 10 first region 11 first overcoat layer 20 second region 21 second region 2 overcoat layer 26 inverter 27 ring oscillator 29 metal cylinder 30 FET
31 dummy pattern 40 FET
50 antenna 101 semiconductor device 110 first region 111 first overcoat layer 120 second region
121 second overcoat layer 130 FET
140 FETs
201 semiconductor device 210 first region 211 first overcoat layer 220 second region
221 second overcoat layer 230 FET
240 FETs
301 semiconductor device 310 first region 311 first overcoat layer 320 second region
321 second overcoat layer 330 FET
340 FETs
401 semiconductor device 410 first region 411 first overcoat layer 420 second region
421 second overcoat layer 430 FET
440 FETs
501 semiconductor devices

Claims (15)

including at least a first region in which two or more semiconductor elements are arranged and a second region in which two or more semiconductor elements are arranged on the substrate;
The semiconductor element in the first region includes a source electrode, a drain electrode, a gate electrode, a semiconductor layer in contact with the source electrode and the drain electrode, a gate insulating layer insulating the semiconductor layer from the gate electrode, and the gate. a first overcoat layer in contact with the semiconductor layer at a position different from the insulating layer on the base;
The semiconductor element in the second region includes a source electrode, a drain electrode, a gate electrode, a semiconductor layer in contact with the source electrode and the drain electrode, a gate insulating layer insulating the semiconductor layer from the gate electrode, and the gate. a second overcoat layer in contact with the semiconductor layer at a position different from the insulating layer on the base;
A method for manufacturing a semiconductor device, wherein the semiconductor element in the first region and the semiconductor element in the second region have different electrical conductivity,
After the step of forming the first overcoat layer, forming the second overcoat layer so that a portion thereof overlaps the first overcoat layer.
A method of manufacturing a semiconductor device. 2. The semiconductor according to claim 1, wherein said first overcoat layer and said second overcoat layer provide different electrical conductivity between said semiconductor element in said first region and said semiconductor element in said second region. Method of manufacturing the device. The first overcoat layer is arranged in a continuous elongated shape over two or more semiconductor elements in the first region, and a part of the second overcoat layer is in the elongated shape. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the first overcoat layer is formed along the long side of the first overcoat layer so as to overlap the first overcoat layer. 4. The method of manufacturing a semiconductor device according to claim 3, wherein said elongated first overcoat layer is arranged in a stripe shape. 3. The method of manufacturing a semiconductor device according to claim 1, wherein said semiconductor layer contains at least one semiconductor material selected from carbon nanotubes, carbon nanocoils, fullerenes, graphene, and nanodiamonds. 3. The method of manufacturing a semiconductor device according to claim 1, wherein said semiconductor layer contains carbon nanotubes. 3. The method of manufacturing a semiconductor device according to claim 1, wherein said second overcoat layer contains an electron-donating compound having at least one selected from nitrogen atoms and phosphorus atoms. 3. The method of manufacturing a semiconductor device according to claim 1, wherein said semiconductor device is a wireless communication device. A semiconductor device including at least a first region in which two or more semiconductor elements are arranged and a second region in which two or more semiconductor elements are arranged on a substrate,
The semiconductor element in the first region includes a source electrode, a drain electrode, a gate electrode, a semiconductor layer in contact with the source electrode and the drain electrode, a gate insulating layer insulating the semiconductor layer from the gate electrode, and the gate. a first overcoat layer in contact with the semiconductor layer at a position different from the insulating layer on the base;
The semiconductor element in the second region includes a source electrode, a drain electrode, a gate electrode, a semiconductor layer in contact with the source electrode and the drain electrode, a gate insulating layer insulating the semiconductor layer from the gate electrode, and the gate. a second overcoat layer in contact with the semiconductor layer at a position different from the insulating layer on the base;
A semiconductor device in which the electrical conductivity of the semiconductor element in the first region and the semiconductor element in the second region are different due to the first overcoat layer and the second overcoat layer,
a portion of the second overcoat layer overlies the first overcoat layer;
semiconductor device. The first overcoat layer is arranged in a continuous elongated shape over two or more semiconductor elements in the first region, and the second overcoat layer has a part thereof in the elongated shape 10. The semiconductor device according to claim 9, arranged in an elongated shape so as to overlap on said first overcoat layer along the long side of said first overcoat layer. 11. The semiconductor device according to claim 10, wherein the width of said second overcoat layer in the short direction is 10 to 50 times the thickness of said second overcoat layer. 12. The semiconductor device according to claim 9, wherein said second overcoat layer has a thickness of 5 μm or more and 30 μm or less. 12. The semiconductor device according to claim 9, wherein the surface of said second overcoat layer opposite to the surface in contact with said semiconductor layer has a bulging curved shape. 12. The semiconductor device according to claim 9, wherein said semiconductor device is a sensor. A wireless communication device comprising at least the semiconductor device according to any one of claims 9 to 11 and an antenna.

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