TW202113997A - 半導體結構及其製造方法 - Google Patents
半導體結構及其製造方法 Download PDFInfo
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- TW202113997A TW202113997A TW109132101A TW109132101A TW202113997A TW 202113997 A TW202113997 A TW 202113997A TW 109132101 A TW109132101 A TW 109132101A TW 109132101 A TW109132101 A TW 109132101A TW 202113997 A TW202113997 A TW 202113997A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 108
- 238000004519 manufacturing process Methods 0.000 title abstract description 19
- 229910052751 metal Inorganic materials 0.000 claims abstract description 97
- 239000002184 metal Substances 0.000 claims abstract description 97
- 239000000758 substrate Substances 0.000 claims abstract description 91
- 230000008878 coupling Effects 0.000 abstract 1
- 238000010168 coupling process Methods 0.000 abstract 1
- 238000005859 coupling reaction Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 262
- 238000000034 method Methods 0.000 description 47
- 230000008569 process Effects 0.000 description 38
- 239000003989 dielectric material Substances 0.000 description 18
- 238000009826 distribution Methods 0.000 description 18
- 239000000463 material Substances 0.000 description 17
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 14
- 230000035882 stress Effects 0.000 description 11
- 238000002161 passivation Methods 0.000 description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- 150000001875 compounds Chemical class 0.000 description 8
- 238000013461 design Methods 0.000 description 8
- 238000012545 processing Methods 0.000 description 8
- 229910052710 silicon Inorganic materials 0.000 description 8
- 239000010703 silicon Substances 0.000 description 8
- 239000012790 adhesive layer Substances 0.000 description 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 6
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 6
- 239000004020 conductor Substances 0.000 description 6
- 229910052802 copper Inorganic materials 0.000 description 6
- 239000010949 copper Substances 0.000 description 6
- 238000012360 testing method Methods 0.000 description 6
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 5
- 229910052814 silicon oxide Inorganic materials 0.000 description 5
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- 229910045601 alloy Inorganic materials 0.000 description 4
- 239000000956 alloy Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 238000007667 floating Methods 0.000 description 4
- 239000011521 glass Substances 0.000 description 4
- 238000005304 joining Methods 0.000 description 4
- 238000004806 packaging method and process Methods 0.000 description 4
- 229920002577 polybenzoxazole Polymers 0.000 description 4
- 235000012239 silicon dioxide Nutrition 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 238000004088 simulation Methods 0.000 description 4
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 3
- 206010011469 Crying Diseases 0.000 description 3
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 3
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 238000000231 atomic layer deposition Methods 0.000 description 3
- 238000005520 cutting process Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 238000000465 moulding Methods 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- 238000012795 verification Methods 0.000 description 3
- 229910000881 Cu alloy Inorganic materials 0.000 description 2
- 229910005540 GaP Inorganic materials 0.000 description 2
- 229910000673 Indium arsenide Inorganic materials 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 238000004026 adhesive bonding Methods 0.000 description 2
- 230000002411 adverse Effects 0.000 description 2
- FTWRSWRBSVXQPI-UHFFFAOYSA-N alumanylidynearsane;gallanylidynearsane Chemical compound [As]#[Al].[As]#[Ga] FTWRSWRBSVXQPI-UHFFFAOYSA-N 0.000 description 2
- 238000005452 bending Methods 0.000 description 2
- 239000005380 borophosphosilicate glass Substances 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000009977 dual effect Effects 0.000 description 2
- -1 etc.) Inorganic materials 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 230000004927 fusion Effects 0.000 description 2
- HZXMRANICFIONG-UHFFFAOYSA-N gallium phosphide Chemical compound [Ga]#P HZXMRANICFIONG-UHFFFAOYSA-N 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- WPYVAWXEWQSOGY-UHFFFAOYSA-N indium antimonide Chemical compound [Sb]#[In] WPYVAWXEWQSOGY-UHFFFAOYSA-N 0.000 description 2
- 230000001788 irregular Effects 0.000 description 2
- 230000000670 limiting effect Effects 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 230000007246 mechanism Effects 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 239000005360 phosphosilicate glass Substances 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 229920000642 polymer Polymers 0.000 description 2
- 239000000523 sample Substances 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 230000001360 synchronised effect Effects 0.000 description 2
- 238000009827 uniform distribution Methods 0.000 description 2
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 241000737241 Cocos Species 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- HMDDXIMCDZRSNE-UHFFFAOYSA-N [C].[Si] Chemical compound [C].[Si] HMDDXIMCDZRSNE-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 229920000800 acrylic rubber Polymers 0.000 description 1
- AJGDITRVXRPLBY-UHFFFAOYSA-N aluminum indium Chemical compound [Al].[In] AJGDITRVXRPLBY-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 238000013473 artificial intelligence Methods 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 239000003575 carbonaceous material Substances 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 239000008393 encapsulating agent Substances 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 238000005272 metallurgy Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 239000005011 phenolic resin Substances 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229920000058 polyacrylate Polymers 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000002829 reductive effect Effects 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 230000001568 sexual effect Effects 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000010998 test method Methods 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3185—Partial encapsulation or coating the coating covering also the sidewalls of the semiconductor body
-
- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
-
- H—ELECTRICITY
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/4824—Pads with extended contours, e.g. grid structure, branch structure, finger structure
-
- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5383—Multilayer substrates
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
-
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- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
-
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68359—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0231—Manufacturing methods of the redistribution layers
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0233—Structure of the redistribution layers
- H01L2224/02331—Multilayer structure
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
- H01L2224/02371—Disposition of the redistribution layers connecting the bonding area on a surface of the semiconductor or solid-state body with another surface of the semiconductor or solid-state body
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
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- H01L2224/0237—Disposition of the redistribution layers
- H01L2224/02372—Disposition of the redistribution layers connecting to a via connection in the semiconductor or solid-state body
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
- H01L2224/02379—Fan-out arrangement
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Abstract
提供一種半導體結構及一種半導體結構的製造方法。所述半導體結構包括積體電路元件、在側向上包封積體電路元件的側壁的絕緣層、設置在絕緣層及積體電路元件上的重佈線結構、以及與重佈線結構相對地耦合到積體電路元件的背側的翹曲控制部分。重佈線結構電性連接到積體電路元件。翹曲控制部分包括基板、設置在基板與積體電路元件之間的圖案化介電層、以及嵌入在圖案化介電層中且與積體電路元件電性隔離的金屬圖案。
Description
本發明的實施例是有關於一種半導體結構及其製造方法,特別是有關於一種包含翹曲控制部分的半導體結構及其製造方法。
由於各種電子元件(例如電晶體、二極體、電阻器、電容器等)的積體密度的不斷改進,半導體工業已經歷快速增長。在很大程度上,積體密度的這些改進來自於最小特徵尺寸(minimum feature size)的不斷減小,此使得更多的元件能被整合到給定的區域中。積體電路(integrated circuit,IC)設計的技術進步已生產出一代又一代的IC,其中每一代的電路設計均比前一代更小且更複雜。半導體裝置封裝類型的實例包括三維積體電路(three-dimensional integrated circuit,3DIC)。這些相對較新類型的半導體封裝技術面臨著製造挑戰。
根據一些實施例,一種半導體結構包括積體電路(integrated circuit,IC)元件、在側向上包封IC元件的側壁的絕緣層、設置在絕緣層及IC元件上的重佈線結構、以及與重佈線結構相對地耦合到IC元件的背側的翹曲控制部分。重佈線結構電性連接到IC元件。翹曲控制部分包括基板、設置在基板與IC元件之間的圖案化介電層、以及嵌入在圖案化介電層中且與IC元件電性隔離的金屬圖案。
根據一些替代性實施例,一種半導體結構包括積體電路(IC)部分及貼合到IC部分的翹曲控制部分。IC部分包括嵌入在絕緣層中的IC元件、以及設置在IC元件及絕緣層上的重佈線結構,其中IC元件的接合連接件接合到重佈線結構的接合連接件,IC元件的接合連接件在IC元件與重佈線結構的接合介面處的接觸面積實質上等於重佈線結構的接合連接件的表面積。翹曲控制部分包括第一基板及嵌入在第一介電層中的第一金屬圖案。第一金屬圖案夾置在第一基板與IC部分之間。
根據一些替代性實施例,一種半導體結構的製造方法包括至少以下步驟。形成積體電路(IC)部分且形成IC部分包括分析IC部分的翹曲特性。基於IC部分的翹曲特性形成翹曲控制部分且形成IC部分包括在基板之上、圖案化介電層的開口中形成金屬圖案。藉由將IC部分接合到翹曲控制部分來使IC部分平整。
以下公開內容提供用於實施所提供主題的不同特徵的許多不同的實施例或實例。以下闡述元件及佈置的具體實例以簡化本公開。當然,這些僅為實例而非旨在進行限制。舉例來說,在以下說明中,在第二特徵之上或第二特徵上形成第一特徵可包括其中第一特徵與第二特徵被形成為直接接觸的實施例,且也可包括其中第一特徵與第二特徵之間可形成附加特徵從而使得第一特徵與第二特徵可不直接接觸的實施例。另外,本公開在各種實例中可重複使用參考標號及/或文字。這種重複使用是為了簡明及清晰起見且自身並不表示所論述的各個實施例及/或配置之間的關係。
另外,為易於說明,本文中可能使用例如“下方(beneath)”、“下面(below)”、“下部的(lower)”、“上方(above)”、“上部的(upper)”等空間相對性用語來闡述圖中所示的一個元件或特徵與另一(其他)元件或特徵的關係。所述空間相對性用語旨在除圖中所繪示的取向外還涵蓋裝置在使用或操作中的不同取向。裝置可具有其他取向(旋轉90度或處於其他取向)且本文中所用的空間相對性描述語可同樣相應地進行解釋。
還可包括其他特徵及製程。舉例來說,可包括測試結構以說明對三維(three-dimensional,3D)封裝或3DIC裝置進行驗證測試。所述測試結構可包括例如在重佈線層中或基板上形成的測試接墊(test pad),以便能夠對3D封裝或3DIC裝置進行測試、使用探針及/或探針卡(probe card)以及類似操作。可對中間結構以及最終結構執行驗證測試。另外,本文中所公開的結構及方法可與包含對已知良好晶粒(known good die)進行中間驗證的測試方法接合使用以提高良率(yield)並降低成本。
本公開的實施例是在半導體製造的背景下論述,具體來說,是在形成三維(3D)半導體結構的背景下論述。3D半導體結構包括積體電路(IC)部分及接合到IC部分的翹曲控制部分。藉由配置翹曲控制部分,可有效地減少3D半導體結構的翹曲。論述了實施例的一些變型。應理解,所有圖式中的圖例是示意性的,而不是按比例的。在所有各種圖及例示性實施例中,相同或相似的標號指代相同或相似的元件。
圖1A到圖1E示出根據一些實施例的積體電路(IC)部分在各種製作階段的示意性剖視圖。參照圖1A,在臨時載體TC之上形成重佈線結構110。臨時載體TC可包含在隨後的處理中為形成在上面的結構提供機械支撐的任何適合的材料。此後,一旦製造製程完成,可從所得結構移除臨時載體TC。舉例來說,臨時載體TC包含玻璃、陶瓷、金屬、矽或類似物。在一些實施例中,在臨時載體TC之上形成重佈線結構110,重佈線結構110與臨時載體TC之間夾置有黏合層(未示出)。舉例來說,黏合層是當曝露於輻射源(例如紫外(ultra-violet,UV)光或雷射)時會降低或失去其黏性的光熱轉換(light-to-heat conversion,LTHC)膜。因此,為在隨後的處理中移除臨時載體TC,可對黏合層施加紫外(UV)光或外部能量,以容易地從所得結構移除臨時載體TC及黏合層。可使用例如晶粒貼合膜(die attach film,DAF)等其他適合的黏合層,臨時載體TC的移除製程可包括機械剝除製程(mechanical peel-off process)、研磨製程(grinding process)或蝕刻製程(etching process)且可包括額外的清潔製程(cleaning process)。在其他實施例中,省略黏合層。
重佈線結構110可包括形成在一個或多個介電層112中的一個或多個導電特徵114(例如導線、通孔及接墊)。重佈線結構110的介電層112可包含氧化矽、氮化矽、低介電常數(low-k)介電質(例如摻雜碳的氧化物)、極低介電常數(extremely low-k)介電質(例如摻雜多孔碳的二氧化矽)、這些材料的組合或類似物,並且可藉由例如化學氣相沉積(chemical vapor deposition,CVD)、電漿增強型化學氣相沉積(plasma-enhanced chemical vapor deposition,PECVD)、原子層沉積(atomic layer deposition,ALD)或任何其他適合的沉積方法等製程形成重佈線結構110的介電層112。重佈線結構110的導電特徵114可由例如鋁、銅、鎢、鈦、合金或其組合等金屬形成,並且可藉由圖案化及金屬化技術或其他適合的沉積方法形成重佈線結構110的導電特徵114。
在一些實施例中,在臨時載體TC之上沉積最底介電層112b,然後在最底介電層112b上沉積導電特徵114的最底層114b。接下來,在最底介電層112b上形成中間介電層112m,以覆蓋導電特徵114的最底層,其中導電特徵114的最底層114b的部分藉由中間介電層112m的開口以可觸及的方式顯露出。然後,在中間介電層112m的開口中形成導電特徵114的中間層114m且導電特徵114的中間層114m延伸到中間介電層112m的頂表面。基於電路設計要求,可重複進行形成中間介電層112m及導電特徵114的中間層114m的步驟。
隨後,在中間介電層112m上形成最頂介電層112t以覆蓋導電特徵114的中間層114m,然後在最頂介電層112t的開口中形成導電特徵114的最頂層114t。可藉由鑲嵌製程(例如單鑲嵌(single damascene)或雙鑲嵌(dual damascene))或其他適合的製程形成導電特徵114的最頂層114t。在一些實施例中,導電特徵114的最頂層114t作為接合連接件,最頂介電層112t作為接合介電質。舉例來說,導電特徵114的最頂層114t的至少部分與導電特徵114的中間層114m物理接觸及電性接觸。在一些實施例中,導電特徵114的最頂層114t的部分是虛設連接件且可為電性浮置的。在一些實施例中,使用導電特徵114的最頂層114t及最頂介電層112t在混合接合製程中將半導體晶粒接合在一起。
參照圖1B,將多個積體電路(IC)元件120接合到重佈線結構110。應注意,儘管示出兩個IC元件120,然而IC元件120的數目在本公開中不受限制。IC元件120的類型可為相同的或可為不同的。舉例來說,相應的IC元件120包括邏輯電路、處理電路、儲存電路、偏置電路、參考電路及/或類似物。在一些實施例中,IC元件120被稱作從裝置晶圓單體化出來的晶粒或晶片。
在一些實施例中,每一IC元件120包括半導體基板122及形成在半導體基板122上的內連線結構124。半導體基板122可包括在前段製程(front-end-of-line,FEOL)中形成的電路(未示出),內連線結構124可在後段製程(back-end-of-line,BEOL)中形成。在一些實施例中,內連線結構124包括形成在半導體基板122之上的層間介電(inter-layer dielectric,ILD)層以及形成在ILD層之上的金屬間介電(inter-metallization dielectric,IMD)層。在一些實施例中,ILD層及IMD層由例如磷矽酸鹽玻璃(phosphosilicate glass,PSG)、硼磷矽酸鹽玻璃(borophosphosilicate glass,BPSG)、SiOxCy、旋塗玻璃(Spin-On-Glass)、旋塗聚合物(Spin-On-Polymer)、矽碳材料、其化合物、其複合物、其組合或類似物等低K介電材料形成。ILD層及IMD層可包括不限於此的任何適合數目的介電材料層。
舉例來說,半導體基板122包括可為摻雜的或未摻雜的塊狀半導體、絕緣體上半導體(semiconductor-on-insulator,SOI)基板、其他支撐基板(例如石英、玻璃等)、其組合或類似物。在一些實施例中,半導體基板122包含元素半導體(例如呈晶體、多晶體或非晶結構等的矽或鍺)、化合物半導體(例如碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦及/或銻化銦等)、合金半導體(例如矽鍺(silicon-germanium,SiGe)、磷化鎵砷(gallium arsenide phosphide,GaAsP)、砷化鋁銦(aluminum indium arsenide,AlInAs)、砷化鋁鎵(aluminum gallium arsenide,AlGaAs)、砷化鎵銦(gallium indium arsenide,GaInAs)、磷化鎵銦(gallium indium phosphide,GaInP)等)、其組合、或其他合適的材料。舉例來說,化合物半導體基板可具有多層結構,或者基板可包括多層化合物半導體結構。在一些實施例中,在矽基板之上形成合金SiGe。在其他實施例中,SiGe基板是應變的。
在一些實施例中,在半導體基板122的背側122b上設置晶粒貼合膜DAF。舉例來說,在將IC元件120接合到重佈線結構110之前,提供晶粒貼合膜DAF。作為另外一種選擇,省略晶粒貼合膜DAF。在一些實施例中,在半導體基板122的前側122a上形成由一個方塊象徵的多個半導體裝置123,內連線結構124可對半導體裝置123進行內連。舉例來說,半導體裝置123可為或可包括主動裝置(例如電晶體、二極體等)及/或被動裝置(例如電容器、電阻器、電感器等)或其他適合的電性元件。舉例來說,內連線結構124包括形成在半導體基板122之上的介電層1241及嵌入在介電層1241中的內連電路1242。內連電路1242可包括導線、導電接墊、導通孔等。內連電路1242的材料可包括銅或銅合金,但也可使用其他導電材料(例如鋁、銀、金及其組合)。在一些實施例中,內連電路1242的兩層或更多層導線藉由內連電路1242的導通孔垂直內連。嵌入在介電層1241中的內連電路1242可電耦合到形成在半導體基板122中及/或半導體基板122上的半導體裝置123。
在一些實施例中,內連線結構124包括嵌入在介電層1241中的接合連接件1243。舉例來說,接合連接件1243使用鑲嵌製程(例如單鑲嵌或雙鑲嵌)或其他適合的技術形成。在一些實施例中,介電層1241的其中埋置有接合連接件1243的部分作為接合介電質。介電層1241的接合表面可與接合連接件1243的接合表面實質上齊平。舉例來說,接合連接件1243的至少部分與內連電路1242物理接觸及電性接觸。在一些實施例中,接合連接件1243的部分是虛設連接件且可為電性浮置的。在一些實施例中,IC元件120的內連線結構124與重佈線結構110物理接觸及電性接觸。舉例來說,藉由將介電層1241和最頂介電層112t接合在一起的接合機制(joint bonding mechanism)來實現IC元件120與重佈線結構110的接合,此外,各個接合連接件1243與導電特徵114的最頂層114t對準且接合在一起。在一些實施例中,接合連接件1243與導電特徵114的最頂層114t直接接觸,其中接合連接件1243在導電特徵114的最頂層114t與接合連接件1243的接合介面IF處的接觸面積實質上等於導電特徵114的最頂層114t的表面積。舉例來說,接合連接件1243的接觸面積與導電特徵114的最頂層114t的接觸面積在接合介面1F處實質上對準。
在其中介電層1241與最頂介電層112t二者均為氧化物材料的一些實施例中,在介電層1241與最頂介電層112t之間形成氧化物-氧化物接合(oxide-oxide bond)。在其中接合連接件1243與114t二者均由銅形成的實施例中,接合連接件(1243及114t)中的銅形成銅-銅接合(copper-copper bond)。因此,IC元件120與重佈線結構110藉由設置在IC元件120的內連線結構124的最頂部分中的接合連接件1243以及重佈線結構110的導電特徵114的最頂層114t進行混合接合(hybrid bonding)。舉例來說,接合連接件(1243及114t)的連接部的至少部分提供IC元件120與重佈線結構110之間的垂直電性連接。在一些實施例中,所述接合可在晶粒到晶圓級(die-to-wafer level)上執行。作為另外一種選擇,所述接合可在晶圓級(wafer level)上進行,其中重佈線結構110與IC元件120呈晶圓形式且接合在一起,然後經接合的結構被單體化成單獨的封裝。
參照圖1C,在重佈線結構110上形成絕緣層130,以至少在側向上覆蓋IC元件120。舉例來說,在重佈線結構110的最頂介電層112t上形成絕緣層130且絕緣層130沿IC元件120的側壁120s延伸。絕緣層130可填充在相鄰的IC元件120之間的間隙,並且相鄰的IC元件120可藉由絕緣層130在空間上彼此分隔開。在一些實施例中,絕緣層130可包含氧化矽、氮化矽及/或四乙氧基矽烷(tetraethoxysilane,TEOS)。在一些實施例中,可藉由CVD、PECVD、ALD或類似製程形成絕緣層130。在一些實施例中,絕緣層130可被稱作“間隙填充氧化物(gap fill oxide)”。在一些其他實施例中,絕緣層130包含模塑化合物、模塑底部填充膠、樹脂(例如環氧樹脂)或類似物。可使用可為IC元件120提供一定程度的保護的其他適合的絕緣材料。
在一些實施例中,接下來可採用化學機械拋光(chemical mechanical polishing,CMP)步驟來對絕緣層130的頂表面130a進行平坦化。在一些實施例中,設置在半導體基板122的背側122b上的晶粒貼合膜DAF至少在側向上被絕緣層130覆蓋。舉例來說,絕緣層130的頂表面130a與晶粒貼合膜DAF的頂表面Dt實質上齊平。在一些實施例中,可選地在IC元件120及絕緣層130之上形成接合層(如圖4中所指的標號15)。在一些實施例中,接合層與絕緣層130的頂表面130a及晶粒貼合膜DAF的頂表面Dt物理接觸。作為另外一種選擇,省略晶粒貼合膜DAF,絕緣層130的頂表面130a可與半導體基板122的背側122b實質上齊平。
參照圖1D及圖1E,移除臨時載體TC以顯露出重佈線結構110的最底介電層112b,然後與IC元件120相對地在重佈線結構110上形成電性連接部。舉例來說,使用微影及蝕刻技術或其他適合的移除製程移除最底介電層112b的部分以形成開口112o。最底介電層112b的開口112o可以可觸及的方式暴露出導電特徵114的最底層114b的至少部分。接下來,可在最底介電層112b的開口112o中形成導電材料,並且在最底介電層112b的表面上將所述導電材料圖案化,從而形成最底介電層112b的開口112o中的穿孔142及最底介電層112b的表面上的接觸接墊144。舉例來說,將接觸接墊144及連接到接觸接墊144的穿孔142電性連接到最底介電層112b。在一些實施例中,接觸接墊144包括用於進一步電性連接的凸塊下金屬(under-bump metallurgy,UBM)圖案。
在一些實施例中,可選地在最底介電層112b上形成鈍化層146,以便為下伏的結構提供一定程度的保護。鈍化層146可由例如氧化矽、氮化矽、低k介電質(例如摻雜碳的氧化物)、極低k介電質(例如摻雜多孔碳的二氧化矽)、這些材料的組合或其他適合的介電材料等一種或多種適合的介電材料製成。儘管可利用任何適合的製程,然而可藉由例如CVD等製程形成鈍化層146。舉例來說,鈍化層146包括以可觸及的方式顯露出接觸接墊144的至少部分的開口。
隨後,在鈍化層146的開口中形成多個導電端子150,並且所述多個導電端子150可與藉由鈍化層146暴露出的接觸接墊144物理接觸及電性接觸。在一些實施例中,相應的導電端子150是上面形成有焊料頂蓋(solder cap)154的金屬柱152。在一些實施例中,導電端子150包括受控塌陷晶片連接(controlled collapse chip connection,C4)凸塊及/或可包含例如焊料、錫或其他適合材料(例如銀、無鉛錫、銅等)等材料。可使用其他端子結構(例如球柵陣列(ball grid array,BGA)球、微凸塊(micro-bump)及/或類似物)。至此,製作出半導體結構的IC部分10A。以上實例是僅出於例示目的而提供,其他實施例可在IC部分中利用更少的或額外的元件。
圖2A到圖2B示出根據一些實施例的IC部分的示意性翹曲輪廓,圖3A到圖3B示出根據一些實施例的IC部分的示意性輪廓圖。出於例示目的,IC部分的翹曲輪廓在所有圖式中可為示意性的及誇大的且IC部分的細節未被示出。參照圖2A到圖2B及圖1E,作為製造製程的結果,圖1E中所示的IC部分10A可能發生翹曲。舉例來說,材料之間的熱膨脹係數(coefficients of thermal expansion,CTE)的不匹配、熱量的施加、溫度波動及/或類似情況會導致發生翹曲。應理解,結構的翹曲可能不利地影響形成在IC部分10A中的裝置/電路的電性能且翹曲問題可能影響隨後的處理及/或產品可靠性。
IC部分10A的彎曲(bowing)導致接合表面BS(例如與導電端子150相對的表面)位於彎曲面上。在一些實施例中,IC部分10A具有其中IC部分10A的接合表面BS如圖2A中所示朝上彎曲的凹型翹曲(即笑臉輪廓)。在一些其他實施例中,IC部分10A具有其中IC部分10A的接合表面BS如圖2B中所示朝下彎曲的凸型翹曲(即哭臉輪廓)。在一些實施例中,在高溫(例如接合溫度約攝氏250度)下,IC部分10A的接合表面BS中的高度差H1可為約80μm或小於80μm。在以上所述的實例中,IC部分的翹曲可為對稱的。由於複雜的半導體處理,IC部分10A可能呈現更複雜的翹曲,而不是簡單的凸型翹曲或簡單的凹型翹曲。
參照圖3A到圖3B,在一些實施例中,IC部分10A的一些區域呈凸型翹曲,IC部分10A的一些其他區域呈現凹型翹曲,其中接合表面BS的部分可朝上彎曲,並且接合表面BS的另一部分可朝下彎曲。在一些實施例中,IC部分10A可能具有非對稱翹曲。如圖3A及圖3B中分別所示,當IC部分10A處於室溫(例如約攝氏25度)以及當IC部分10A暴露於高溫(例如約攝氏250度或高於攝氏250度)時,各種因素可能導致翹曲。
在一些實施例中,在室溫下,所遇到的翹曲情況是IC部分10A的隅角區如由箭頭A1所示朝下彎折,而IC部分10A的中心區如由箭頭A2所示朝上突起。翹曲方向可從中心區到隅角區變化。在一些實施例中,在高溫條件下,IC部分10A可具有不規則的翹曲輪廓,如圖7B中所示。所遇到的翹曲情況可為IC部分10A的隅角區如由箭頭A2所示朝上彎折,而IC部分10A的中心區如由箭頭A1所示朝下凹陷。
IC部分10A的彎曲面難以將導電端子150中的所有導電端子150接合到另一封裝元件(未示出)的相應的接觸接墊,因為一些導電端子150將不會接觸封裝元件的相應接觸接墊。此可能導致導電端子150與封裝元件的接觸接墊之間的冷焊(cold joint)且冷焊會導致有缺陷的半導體結構並降低半導體製造的良率。在一些實施例中,為減少及/或消除IC部分10A的翹曲,將翹曲控制部分接合到IC部分10A以用於翹曲管理。在下文中將論述其細節。
圖4A到圖4B示出根據一些實施例的翹曲控制部分在各種製作階段的示意性剖視圖。參照圖4A,在基板210之上形成第一介電層220。舉例來說,基板210是矽基板。在一些實施例中,基板210可包含另一種元素半導體,例如鍺;化合物半導體,包括碳化矽、鎵砷、磷化鎵、磷化銦、砷化銦及/或銻化銦;合金半導體,包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP及/或GaInAsP;或者其組合。可使用例如多層式基板(multi-layered substrate)或梯度基板(gradient substrate)等其他基板。在一些實施例中,基板210由玻璃、陶瓷、金屬或具有一定程度的剛性的其他適合的材料製成。
在一些實施例中,第一介電層220為氧化物層。在一些實施例中,第一介電層220可由例如氧化矽、未摻雜的矽酸鹽玻璃、氮氧化矽及類似物等非有機材料形成。也可使用其他適合的介電材料(例如聚醯亞胺(polyimide)、聚苯並惡唑(polybenzoxazole,PBO)、苯並環丁烯(benzocyclobutene,BCB)、這些材料的組合或類似物)。舉例來說,基板210與第一介電層220之間的介面可為矽到矽、矽到氧化物、氧化物到氧化物或任何其他共價接合機制。可改變基板210的厚度210t及第一介電層220的厚度220t,以控制翹曲控制部分的翹曲程度,稍後將在其他實施例中闡釋。
參照圖4B,在第一介電層220上形成第二介電層222及嵌入在第二介電層222中的金屬圖案224A。在一些實施例中,藉由例如旋轉塗布、CVD、PECVD、疊層(lamination)或其他適合的沉積製程等適合的製作技術形成介電材料,然後使用微影及/或蝕刻、雷射鑽孔或其他適合的移除製程移除介電材料的部分以形成具有開口的第二介電層222。第二介電層222可被稱作圖案化介電層。
第一介電層220及第二介電層222可由例如氧化矽、氮化矽、低k介電質(例如摻雜碳的氧化物)、極低k介電質(例如摻雜多孔碳的二氧化矽)、這些材料的組合等一種或多種適合的介電材料製成。在其他實施例中,第一介電層220及/或第二介電層222可由例如聚醯亞胺、聚苯並惡唑(PBO)、苯並環丁烯(BCB)、這些材料的組合或類似物等聚合物製成。在一些實施例中,第一介電層220與第二介電層222二者均為氧化物,第一介電層220與第二介電層222之間夾置有蝕刻終止層(etch stop layer)(未示出)。
接下來,可在第二介電層222的開口中形成金屬圖案224A。舉例來說,在第二介電層222上共形地形成晶種層且使用鍍覆或其他適合的製程將導電材料(例如銅、銅合金、鋁、鋁合金或其組合)填充在開口中。可執行平坦化製程(例如CMP、機械研磨等),而使第二介電層222的頂表面與金屬圖案224A的頂表面實質上齊平。在一些實施例中,可重複地形成額外的第二介電層222及額外的金屬圖案224A,以控制翹曲控制部分的翹曲程度,如稍後將結合圖9到圖10闡述。金屬圖案224A可包括傾斜的側壁或垂直的側壁,此取決於製程要求。金屬圖案224A的具體配置是基於欲接合的IC部分的翹曲特性,稍後將在其他實施例中闡述關於金屬圖案224A的配置的細節。
在一些實施例中,可選地在第二介電層222及金屬圖案224A上形成接合層(如圖5中所標示的15)。舉例來說,如果在製作IC部分10A期間形成接合層,則可不在第二介電層222及金屬圖案224A上形成接合層。如果在IC部分10A中不存在接合層,則對第二介電層222及金屬圖案224A執行接合層的形成製程。在一些實施例中,在IC部分10A與翹曲控制部分20A二者中均形成接合層。至此,製作出半導體結構的翹曲控制部分20A。
圖5示出根據一些實施例的包括IC部分及翹曲控制部分的半導體結構的示意性剖視圖。參照圖5,提供包括彼此堆疊的IC部分10A與翹曲控制部分20A的半導體結構S1。舉例來說,IC部分10A與翹曲控制部分20A藉由例如熱接合製程、膠合製程、壓力接合製程、其組合或其他類型的接合製程接合在一起。在一些實施例中,IC部分10A與翹曲控制部分20A藉由夾置在其間的接合層15接合在一起。舉例來說,接合層15是氧化物系介電層,以用於在隨後的製程中形成與另一部分之間的氧化物到氧化物的接合(氧化物熔融接合)。可在接合製程之後執行退火製程(anneal process),以增加IC部分10A與翹曲控制部分20A之間的接合強度。在其他實施例中,接合層15是用於物理連接的黏合層或膠層。舉例來說,接合層15包括可由環氧樹脂(epoxy resin)、酚醛樹脂(phenol resin)、丙烯酸橡膠(acrylic rubber)、矽石填料(silica filler)、其組合或類似物製成的晶粒貼合膜。
在一些實施例中,接合層15的底表面15b與翹曲控制部分20A的第二介電層222及金屬圖案224A物理接觸。翹曲控制部分20A的金屬圖案224A可藉由介電材料電性隔離。舉例來說,金屬圖案224A的側壁被第二介電層222覆蓋,金屬圖案224A的底表面被第一介電層220覆蓋,並且金屬圖案224A的頂表面被接合層15覆蓋。翹曲控制部分20A的金屬圖案224A可在半導體結構S1中電性浮置。金屬圖案224A可被稱作虛設圖案或虛設導電特徵。在一些實施例中,接合層15的頂表面15a連接到IC部分10A。舉例來說,絕緣層130及和絕緣層130實質上齊平的晶粒貼合膜DAF與接合層15的頂表面15a物理接觸。在其中省略晶粒貼合膜DAF的一些實施例中,接合層15的頂表面15a與絕緣層130以及IC元件120的半導體基板122物理接觸。
在一些實施例中,IC部分10A與翹曲控制部分20A的接合可在晶圓級進行,在接合步驟之後,所得的結構被單體化以形成各別的半導體結構S1。舉例來說,單體化涉及切穿例如鈍化層146、重佈線結構110、絕緣層130、接合層15、第二介電層222、第一介電層220及基板210等連續的層。因此,在單體化之後,這些連續的層的側壁可彼此實質上齊平。
在一些實施例中,翹曲控制部分20A的功能中的一者是控制IC部分10A的翹曲。如上所述,IC部分10A可能由於幾個因素(例如CTE不匹配、熱應力過大、溫度波動及/或類似因素)而經歷翹曲。如所知,IC部分的翹曲可能不利地影響電性能。另外,IC部分的低平面性(或嚴重翹曲)可能對經封裝的IC元件造成應力且干擾單體化製程。藉由將翹曲控制部分20A貼合到IC部分10A,可解決IC部分10A的翹曲問題。舉例來說,接合到IC部分10A的翹曲控制部分20A具有固有應力(inherent stress),所述固有應力可使IC部分10A朝著與現有的翹曲方向相反的方向翹曲,因此補償現有的翹曲。在一些實施例中,在被鋸切成各別的半導體結構S1之前,翹曲的IC部分10A要藉由接合到翹曲控制部分20A來實現平整,以使得能夠實現恰當的鋸切及良好的封裝平面性(planarity)。
圖6示出根據一些實施例的圖5中的翹曲控制部分的示意性俯視圖。參照圖5及圖6,金屬圖案224A可包括形成在第二介電層222的開口中的多個第一特徵2241。舉例來說,第一特徵2241排列成陣列。在一些實施例中,第一特徵2241排列成線性陣列。作為另外一種選擇,第一特徵2241例如以非線性方式、曲線方式、幾何順序方式或其他均勻分佈方式進行排列。在其他實施例中,第一特徵2241例如以均勻分佈方式、以隨機方式或以另外一種不規則分佈方式進行排列。
儘管在俯視圖中所示的第一特徵2241在形狀上均為矩形的,然而應理解,在其他實施例中,第一特徵2241可具有例如圓形、橢圓形、三角形、正方形、十字形、多邊形、這些形狀的組合等任何形狀。在一些實施例中,第一特徵2241包括虛設金屬通孔、虛設金屬線及/或虛設金屬接墊。相應的第一特徵2241可在空間上彼此分開。舉例來說,第一特徵2241不進行電性連接且可彼此隔離。在一些實施例中,為特定線寬W的金屬線在其間具有一定量的線距S。第一特徵2241可被設計成具有分散式的線及線距,以符合設計規則及提供所預期的翹曲效果及程度。在一些實施例中,相應的第一特徵2241的線寬W為約15 μm或可小於15 μm。舉例來說,線寬W在約0.3 μm到約15 μm範圍內。在一些實施例中,相鄰的第一特徵2241的線距S為至少0.3 μm或大於0.3 μm。
在一些實施例中,第一特徵2241是根據設計規則形成,其中改變金屬線之間的線距S以實現預期的全域圖案密度(global pattern density)。舉例來說,全域圖案密度的範圍介於約10%到約80%。在一些實施例中,第一特徵2241佈局在其中局部圖案密度在約10%到約90%範圍內的製程容許範圍中。在一些實施例中,製程容許範圍之間的密度差實質上等於或小於40%,其中相應的製程容許範圍可具有為250 μm×250 μm的長度及寬度。應理解,本文所述的尺寸僅為實例,如果使用不同的形成技術或如果模擬結果顯示不同的尺寸是優選的,則可改變本文中所陳述的尺寸。
第一特徵2241的形成可藉由將局部應力重布到翹曲控制部分20A的特定區來增加或減少應力。舉例來說,第一特徵2241位於被選擇來更有效地控制IC部分10A的翹曲的區域中。在一些實施例中,翹曲控制部分20A包括第一區R1及環繞第一區R1的第二區R2。第一特徵2241可分佈在第一區R1內,第一區R1可對應於IC部分10A中的IC元件120的區域。舉例來說,各個IC元件120的正投影區域可與對應的第一區R1實質上交疊。在其他實施例中,IC元件120的正投影區域與第一區R1部分地交疊。作為另外一種選擇,IC元件120的正投影區域與第一區R1完全錯開。第一區R1的分佈區域可基於翹曲輪廓來確定,以抵消或補償IC部分10A的非預期的翹曲。稍後將在其他實施例中闡述關於翹曲控制的細節。
在一些實施例中,金屬圖案224A包括設置在第二區R2內的至少一個第二特徵2242。舉例來說,第二區R2在俯視圖中是翹曲控制部分20A的邊界區。舉例來說,第一特徵2241被限制在對應於IC元件120的第一區R1中,第二區R2中的第二特徵2242位於翹曲控制部分20A的周邊處。第一特徵2241及第二特徵2242在半導體結構S1中可不具有電性功能且可不電性連接到上覆的IC部分10A。在一些實施例中,第二特徵2242由與第一特徵2241的導電材料相同的導電材料形成,第二特徵2242可與形成第一特徵2241實質上同時地形成。在一些實施例中,在第二區R2中以對角線排列方式設置有多個第二特徵2242。可使用其他排列方式來形成第二特徵2242。
在一些實施例中,第二特徵2242可作為對準標記,以使第二特徵2242可被稱作對準特徵。第二特徵2242可形成到在切割道(未示出)內部的翹曲控制部分20A上的空白區域中,以使第二特徵2242在單體化之後保留在翹曲控制部分20A中。在一些實施例中,第二特徵2242可形成在與切割道(未示出)交疊的邊緣區域中,以使第二特徵2242在單體化之後被切穿並部分地保留在翹曲控制部分20A中。在其他實施例中,第二特徵2242可形成在切割道(未示出)之外的區域中,以使得第二特徵2242在單體化之後被移除。用作對準標記的第二特徵2242可為幾何形狀(例如三角形、矩形、正方形、十字形、圓形、橢圓形、多邊形)或任何適合的形狀。所示的第二特徵2242不旨在進行限制,此是因為第二特徵2242可具有任何數目、形狀或大小。應理解,圖5到圖6中所示的金屬圖案224A僅為實例且不應限制本公開的範圍。
圖7A到圖7B示出根據一些實施例的半導體結構的組裝的示意圖。應注意,圖7A到圖7B中所示的翹曲程度被誇大了且出於例示目的,省略IC部分的細節。參照圖7A,半導體結構S1包括IC部分10A及翹曲控制部分20A。在一些實施例中,IC部分10A呈現凹型翹曲(即笑臉輪廓)且可製作具有預先決定的凸型翹曲(即哭臉輪廓)的翹曲控制部分20A以抵消導致IC部分10A的凹型翹曲的內應力,從而減少製造缺陷。
在一些實施例中,在進行接合之前先決定IC部分10A的翹曲特性。舉例來說,藉由模擬或實驗來估算IC部分10A的接合表面BS中的高度差H1(示出在圖2A到圖2B中)。在一些實施例中,基於IC部分10A的設計來執行翹曲模擬,以產生翹曲輪廓(warpage profile)的輪廓圖(contour diagram)。藉由分析IC部分10A的翹曲,可估算翹曲控制部分20A的配置。舉例來說,翹曲控制部分20A的金屬圖案的圖案密度、線寬及線距可取決於所要補償的翹曲程度。在一些實施例中,可藉由在基板210上形成介電材料(例如圖3B中所示的第一介電層220及/或第二介電層222)來實現翹曲控制部分20A的翹曲,其中介電材料具有固有應力,此會提供預期的翹曲效果及程度。在一些實施例中,可基於IC部分10A的翹曲特性決定基板210的厚度,以允許對IC部分10A的翹曲控制進行微調。
參照圖7B,半導體結構S1包括IC部分10A及翹曲控制部分20A。在一些實施例中,IC部分10A呈現凸型翹曲(即哭臉輪廓)且翹曲控制部分20A可具有凹型翹曲(即笑臉輪廓),以使IC部分10A與翹曲控制部分20A的接合可實現半導體結構的平整度的要求。如上所述,翹曲控制部分20A的配置可基於翹曲輪廓而變化。在一些實施例中,使用IC部分10A的模擬翹曲特性來決定用於接合IC部分10A的翹曲控制部分20A的預期的翹曲程度。
舉例來說,填充第二介電層的開口的金屬圖案可具有誘發凹型翹曲的效果。翹曲控制部分20A的金屬圖案的更大圖案密度可導致更大的翹曲補償效果。圖案密度可被視為在俯視圖中佔用翹曲控制部分的區的第一特徵的密度。圖案密度可為由第一特徵在第一區中佔用的面積相對於翹曲控制部分的總面積的比例。可選擇形成在基板210上的介電材料(例如圖3B中所示的第一介電層220及/或第二介電層222)來引起翹曲控制部分20A的凹型翹曲或凸型翹曲。在一些實施例中,選擇翹曲控制部分20A的介電材料以減輕由翹曲控制部分20A的金屬圖案224A提供的彎折力。在一些實施例中,具有較厚介電材料的翹曲控制部分20A易於因由這些介電材料施加的應力而翹曲。在一些實施例中,改變基板210的厚度以控制翹曲控制部分20A的翹曲。舉例來說,使用較厚的基板210來減小翹曲控制部分20A的凹度(concavity)。
在上述的實例中,IC部分10A的翹曲可為對稱的,翹曲控制部分20A也可為對稱的。在一些實施例中,由於複雜的半導體處理,IC部分10A呈現更複雜的翹曲輪廓。在此種實施例中,可對翹曲的IC部分10A進行模擬及分析。可基於模擬結果(例如圖3A到圖3B中所示的三維輪廓圖)來定製翹曲補償,以形成具有與翹曲的IC部分對應的特定配置的翹曲控制部分20A。因此,IC部分10A的翹曲由翹曲控制部分20A所預先規劃的內應力進行補償,從而防止半導體結構S1整體的翹曲。
圖8示出根據一些實施例的包括IC部分及翹曲控制部分的半導體結構的示意性剖視圖,圖9A到圖9B示出根據一些實施例的具有不同配置的圖8中的翹曲控制部分的示意性俯視圖。在本公開的所有各種圖式及例示性實施例中,相同的標號用於表示相同的元件。
參照圖8,半導體結構S2包括IC部分10B及貼合到IC部分10B的翹曲控制部分20B。半導體結構S2可類似於圖5中所闡述的半導體結構S1。半導體結構S1與半導體結構S2之間的不同之處包括半導體結構S2中設置有單個IC元件120且重佈線結構110’的導電特徵114’的最頂層114t’被對應地修改。同樣,IC元件120的數目在本公開中不受限制且實例僅用於例示性目的。
除金屬圖案224B的配置被修改以外,翹曲控制部分20B可類似於圖5中所闡述的半導體結構S1的翹曲控制部分20A。舉例來說,參照圖8及圖9A,翹曲控制部分20B包括第一區R1、位於第一區R1的相對兩側處的第三區R3與第四區R4以及環繞第一區R1、第三區R3及第四區R4的第二區R2。第一特徵2241可分佈在與IC部分10B中的IC元件120的區對應的第一區R1內。
金屬圖案224B可進一步包括分佈在第三區R3內的多個第三特徵2243及分佈在第四區R4內的多個第四特徵2244。第三特徵2243及第四特徵2244可藉由基於規則的工序產生。在一些實施例中,第一區R1中的第一特徵2241的圖案密度比第三區R3中的第三特徵2243的圖案密度稀疏。在一些實施例中,第一區R1中的第一特徵2241的圖案密度也比第四區R4中的第四特徵2244的圖案密度稀疏。在一些實施例中,第三特徵2243與第四特徵2244的圖案密度實質上相同。作為另外一種選擇,第三區R3中的第三特徵2243的圖案密度可比第四區R4中的第四特徵2244的圖案密度稠密或稀疏。
相對於圖8來參照圖9B,提供翹曲控制部分20C的另一種配置。舉例來說,第一區R1中的第一特徵2241的圖案密度比第三區R3中的第三特徵2243的圖案密度稠密。在一些實施例中,第一區R1中的第一特徵2241的圖案密度也比第四區R4中的第四特徵2244的圖案密度稠密。在一些實施例中,第三特徵2243與第四特徵2244的圖案密度實質上相同。作為另外一種選擇,第三區R3中的第三特徵2243的圖案密度可比第四區R4中的第四特徵2244的圖案密度稠密或稀疏。在其他實施例中,第一區R1中的第一特徵2241的圖案密度在第三特徵2243的圖案密度與第四特徵2244的圖案密度之間。舉例來說,第一區R1中的第一特徵2241的圖案密度比第三區R3中的第三特徵2243的圖案密度稠密,但比第四區R4中的第四特徵2244的圖案密度稀疏。作為另外一種選擇,第一區R1中的第一特徵2241的圖案密度可比第三區R3中的第三特徵2243的圖案密度稀疏,但比第四區R4中的第四特徵2244的圖案密度稠密。
第二特徵2242可分佈在第二區R2內,在俯視圖中,第二區R2可為翹曲控制部分20B的邊界區。在一些實施例中,第二特徵2242’作為對準標記且可設置在第四區R4及第三區R3旁邊。舉例來說,在俯視圖中,第二特徵2242’設置在翹曲控制部分20C的周邊的中間處。儘管所示的第二特徵2242’是十字形標記,然而應理解,其他實施例中的第二特徵可具有任何形狀且不應限制本公開的範圍。應理解,本文中所示的金屬圖案(224B、224C)的特性(例如密度、尺寸、形狀、排列等)僅為實例且如果要接合其他類型的IC部分,則所述特性可有所改變。
圖10及圖11示出根據一些實施例的半導體結構的變型的示意性剖視圖。在本公開的所有各種圖式及例示性實施例中,相同的標號用於表示相同的元件。參照圖10,半導體結構S3包括IC部分10A及貼合到IC部分10A的翹曲控制部分20D。除半導體結構S3的翹曲控制部分20D包括多個彼此堆疊的金屬圖案以外,半導體結構S3可類似於圖5中所闡述的半導體結構S1。舉例來說,在如圖4B中所述在第二介電層222中形成金屬圖案224A之後,隨後在介電層222及金屬圖案224A之上形成附加介電層226及附加金屬圖案228。附加介電層226及附加金屬圖案228的形成製程可類似於第二介電層222及金屬圖案224A的形成製程,因此為簡潔起見,不再予以贅述。舉例來說,隨著在基板210之上形成的介電層及金屬圖案的數目增加,由這些層提供的彎折力導致翹曲控制部分20D的顯著翹曲。附加介電層226及附加金屬圖案228的數目取決於翹曲控制部分20D及所要接合的IC部分10A的設計。
在一些實施例中,附加金屬圖案228的圖案分佈可不同於下伏的金屬圖案224A的圖案分佈。在一些其他實施例中,附加金屬圖案228具有與下伏的金屬圖案224A的圖案分佈相似或相同的圖案分佈。可使用各種金屬圖案的圖案分佈類型的任何組合。附加金屬圖案228可與或可不與下伏的金屬圖案224A物理接觸。在一些實施例中,附加金屬圖案228與下伏的金屬圖案224A彼此錯開。舉例來說,金屬圖案224A與附加金屬圖案228彼此電性隔離。可調整附加介電層226的厚度,以施加適當的抵消應力。在一些實施例中,如結合圖8、圖9A及圖9B所述,金屬圖案224A被金屬圖案224B或224C替代。在一些實施例中,如結合圖8所示,IC部分10A被IC部分10B替代。應理解,IC部分可用其他類型的裝置(例如積體電路上系統(system on integrated circuit,SoIC)裝置、系統晶片(system on a chip,SoC)、封裝結構或類似物)替代。
參照圖11,半導體結構S4包括IC部分10A及貼合到IC部分10A的翹曲控制部分20E。除翹曲控制部分20E的配置以外,半導體結構S4可類似於圖5中所闡述的半導體結構S3。舉例來說,翹曲控制部分20E包括第一層級T1及接合到第一層級T1的第二層級T2。第一層級T1的配置可類似於圖4B中所闡述的翹曲控制部分20A的配置。第二層級T2可與IC部分10A相對地接合到第一層級T1。第一層級T1與第二層級T2的接合可包括黏合接合、藉由氧化物到氧化物接合進行的熔融接合、藉由例如苯並環丁烯(BCB)等膠合介質進行的接合及類似接合方式。在一些實施例中,第二層級T2藉由接合層16接合到第一層級T1的基板210。接合層16的材料可類似於接合層15的材料,為簡潔起見,不再予以贅述。
第二層級T2可包括基板310、形成在基板310上的第一介電層320、形成在第一介電層320上的第二介電層322、嵌入在第二介電層322中的第一金屬圖案324、形成在第二介電層322上的第三介電層326以及嵌入在第三介電層326中的第二金屬圖案328。基板310可類似於基板210。在一些實施例中,第一層級T1的基板210與第二層級T2的基板310是由不同的材料構成。在一些實施例中,基板210與基板310可具有不同的厚度。基板210可比基板310厚或薄,基板的厚度可取決於所要補償的翹曲。介電層(例如320、322及326)的堆疊以及接合層16可夾置在第一層級T1的基板210與第二層級T2的基板310之間。介電層(例如320、322及326)的堆疊以及接合層16的材料及厚度可基於翹曲設計要求而改變。第一金屬圖案324可類似於金屬圖案(224A、224B或224C)。第二金屬圖案328可類似於附加金屬圖案228。在一些實施例中,第二層級T2的配置可類似於圖10中所闡述的翹曲控制部分20D的配置。可使用其他配置,只要翹曲控制部分20E施加適當的抵消應力即可。
圖12示出根據一些實施例的半導體結構的應用的示意性剖視圖。參照圖12,提供包括第一元件C1及設置在第一元件C1之上的第二元件C2的元件裝配件SC。第一元件C1可為或可包括中介層(interposer)、封裝基板、印刷電路板(printed circuit board,PCB)、印刷配線板(printed wiring board)及/或能夠承載積體電路的其他載體。第二元件C2可為或可包括半導體結構S5。
舉例來說,半導體結構S5包括IC部分10C及貼合到IC部分10C的翹曲控制部分20A。在一些實施例中,IC部分10C包括載體晶粒L1及堆疊在載體晶粒L1上且電性連接到載體晶粒L1的晶粒堆疊L2。在一些實施例中,載體晶粒L1可被配置成執行讀取、程式設計、抹除及/或其他操作,晶粒堆疊L2可為包括彼此堆疊且由載體晶粒L1程式設計的記憶體晶粒的記憶體堆疊。舉例來說,載體晶粒可為或可包括系統晶片(SoC)、中央處理器(central processing unit,CPU)、圖形處理單元(graphics processing unit,GPU)或其他類型的IC元件。晶粒堆疊L2可包括動態隨機存取記憶體(dynamic random access memory,DRAM)晶粒、靜態隨機存取記憶體(static random access memory,SRAM)晶粒、同步動態隨機存取記憶體(synchronous dynamic random access memory,SDRAM)晶粒、NAND快閃記憶體晶粒(NAND flash die)或其他類型的IC元件。
在一些實施例中,載體晶粒L1包括上面形成有半導體裝置的半導體基板410、設置在半導體基板410的前側410a之上以電性連接到半導體裝置的重佈線結構420、穿透過半導體基板410以電性連接到重佈線結構420的多個基板穿孔(through substrate via,TSV)430、設置在半導體基板410的背側410b上的接合介電層442以及嵌入在接合介電層442中且電性連接到TSV 430的多個接合接墊440。導電端子150與半導體基板410相對地形成在重佈線結構420上。
晶粒堆疊L2包括彼此堆疊的多個層級(例如M1到M4),其中每一層級可包括被絕緣層130在側向上覆蓋的IC元件(例如520、620)。上覆層級中的IC元件與下伏層級中的IC元件物理接觸及電性接觸。最頂層級M4處的IC元件620藉由接合層15貼合到翹曲控制部分20A。IC元件620可類似於IC元件120。除IC元件520包括基板穿孔(TSV)522以外,最底IC元件520可類似於最頂層級M4處的IC元件620。舉例來說,IC元件520的相應TSV 522穿透過半導體基板122以與內連線結構124物理接觸及電性接觸。在一些實施例中,接合介電層442夾置在相鄰層級(例如M1與M2、M2與M3、或M3與M4)之間。多個接合接墊440可嵌入在接合介電層442中的每一者中以物理連接到及電性連接到下伏層級處的IC元件520的TSV 522且還連接到上覆層級處的內連線結構124的接合連接件1243。應理解,四層級式堆疊(four-tier stack)是出於例示目的而提供,其他實施例可在晶粒堆疊中利用更少的或額外的層級。
應注意,IC部分10C及翹曲控制部分20A可用以上論述的任何IC部分及翹曲控制部分替代。安裝在第一元件C1上的第二元件C2可類似於以上所述的半導體結構(例如S1、S2、S3、S4)。舉例來說,以上所述的一個或多個半導體結構可藉由多個端子CT電性耦合到第一元件C1。端子CT可為導電端子150。在處理的情形中,溫度升高,而使端子CT變形且接合到第一元件C1的接觸墊(未示出)。藉由使用翹曲控制部分,經接合的封裝元件(C1與C2)可不發生翹曲。在一些實施例中,在第一元件C1與第二元件C2的間隙之間形成有底部填充層UF,以至少在側向上覆蓋端子CT。作為另外一種選擇,省略底部填充層UF。
在一些其他實施例中,安裝在第一元件C1上的第二元件C2可為包括封裝在其中的至少一個半導體結構(例如S1到S5)的積體扇出型(integrated fan-out,InFO)封裝。舉例來說,第二元件C2包括並排設置且由封裝包封體(未示出;例如模塑化合物)環繞的多個半導體結構(例如半導體結構S1到S5的任何組合)。可使用其他封裝技術來形成元件裝配件SC,這些技術在本公開中不受限制。舉例來說,使用晶圓級封裝(wafer level packaging,WLP)、基板上晶圓上晶片(chip-on-wafer-on-substrate,CoWoS)製程、基板上晶片上晶片(chip-on-chip-on-substrate,CoCoS)製程等來形成元件裝配件SC。元件裝配件SC可為例如電腦(例如高性能電腦)、結合人工智慧系統使用的計算裝置、無線通訊裝置、電腦相關周邊裝置、娛樂裝置等電子系統的一部分。應注意,其他電子應用也是可能的。
根據一些實施例,一種半導體結構包括:積體電路(IC)元件、在側向上包封IC元件的側壁的絕緣層、設置在絕緣層及IC元件上的重佈線結構、以及與重佈線結構相對地耦合到IC元件的背側的翹曲控制部分。重佈線結構電性連接到IC元件。翹曲控制部分包括基板、設置在基板與IC元件之間的圖案化介電層、以及嵌入在圖案化介電層中且與IC元件電性隔離的金屬圖案。
在一些實施例中,半導體結構進一步包括接合層,接合層將所述翹曲控制部分耦合到所述積體電路元件及所述絕緣層。在一些實施例中,所述翹曲控制部分進一步包括氧化物層,氧化物層夾置於所述基板與所述圖案化介電層之間。在一些實施例中,所述翹曲控制部分的所述金屬圖案位於在所述積體電路元件的區之下的分佈區內,所述翹曲控制部分的所述金屬圖案包括設置在環繞所述分佈區的邊界區中的對準特徵。在一些實施例中,所述積體電路元件的接合連接件接合到所述重佈線結構的接合連接件,所述積體電路元件的在側向上覆蓋所述積體電路元件的所述接合連接件的接合介電層接合到所述重佈線結構的在側向上覆蓋所述重佈線結構的所述接合連接件的接合介電層。在一些實施例中,所述翹曲控制部分的所述金屬圖案包括多個第一特徵及多個第二特徵,所述多個第一特徵分佈在位於所述積體電路元件的區之下的第一區內,所述多個第二特徵分佈在位於所述絕緣層的區之下的第二區內,其中所述多個第一特徵的圖案分佈密度比所述多個第二特徵稀疏。在一些實施例中,所述翹曲控制部分的所述金屬圖案包括多個第一特徵及多個第二特徵,所述多個第一特徵分佈在位於所述積體電路元件的區之下的第一區內,所述多個第二特徵分佈在位於所述絕緣層的區之下的第二區內,其中所述多個第一特徵的圖案分佈密度比所述多個第二特徵稠密。在一些實施例中,所述翹曲控制部分進一步包括附加基板、附加圖案化介電層、附加金屬圖案及接合層,附加圖案化介電層設置在所述基板與所述附加基板之間,附加金屬圖案嵌入在所述附加圖案化介電層中,接合層將所述附加圖案化介電層及所述附加金屬圖案耦合到所述基板。
根據一些替代性實施例,一種半導體結構包括積體電路(IC)部分及貼合到IC部分的翹曲控制部分。IC部分包括嵌入在絕緣層中的IC元件、以及設置在IC元件及絕緣層上的重佈線結構,其中IC元件的接合連接件接合到重佈線結構的接合連接件,IC元件的接合連接件在IC元件與重佈線結構的接合介面處的接觸面積實質上等於重佈線結構的接合連接件的表面積。翹曲控制部分包括第一基板及嵌入在第一介電層中的第一金屬圖案。第一金屬圖案夾置在第一基板與IC部分之間。
在一些實施例中,半導體結構進一步包括接合層,接合層夾置在所述翹曲控制部分與所述積體電路部分之間。在一些實施例中,所述第一金屬圖案與所述第一介電層實質上齊平。在一些實施例中,所述第一金屬圖案在所述翹曲控制部分中電性浮置。在一些實施例中,所述翹曲控制部分的所述第一金屬圖案位於與所述積體電路元件的正投影區域交疊的分佈區內,所述翹曲控制部分的所述第一金屬圖案被電性隔離。在一些實施例中,所述翹曲控制部分的所述第一金屬圖案包括第一特徵及第二特徵,其中所述第一特徵分佈在與所述積體電路元件的正投影區域交疊的分佈區內,所述第二特徵分佈在所述分佈區之外且具有比所述第一特徵的圖案分佈密度稠密的圖案分佈密度。在一些實施例中,所述翹曲控制部分的所述第一金屬圖案包括第一特徵及第二特徵,其中所述第一特徵分佈在與所述積體電路元件的正投影區域交疊的分佈區內,所述第二特徵分佈在所述分佈區之外且具有比所述第一特徵的圖案分佈密度稀疏的圖案分佈密度。在一些實施例中,所述翹曲控制部分進一步包括第二基板、第二金屬圖案及接合層,第二金屬圖案嵌入在第二介電層中且夾置在所述第一基板與所述第二基板之間,接合層將所述第二介電層及所述第二金屬圖案耦合到所述第一基板。
根據一些替代性實施例,一種半導體結構的製造方法包括至少以下步驟。形成積體電路(IC)部分,形成IC部分包括分析IC部分的翹曲特性。基於IC部分的翹曲特性形成翹曲控制部分,且形成IC部分包括在基板之上、圖案化介電層的開口中形成金屬圖案。藉由將IC部分接合到翹曲控制部分來使IC部分平整。
在一些實施例中,形成所述金屬圖案包括在第一區中形成多個第一特徵,在除所述第一區以外的第二區中形成多個第二特徵,其中所述第一區位於所述積體電路部分的晶粒之下,所述第一區中的所述多個第一特徵的圖案密度比所述第二區中的所述多個第二特徵的圖案密度稀疏。在一些實施例中,形成所述金屬圖案包括在第一區中形成多個第一特徵,在除所述第一區以外的第二區中形成多個第二特徵,其中所述第一區位於所述積體電路部分的晶粒之下,所述第一區中的所述多個第一特徵的圖案密度比所述第二區中的所述多個第二特徵的圖案密度稠密。在一些實施例中,形成所述積體電路部分包括將晶粒接合到重佈線結構,其中所述晶粒的接合連接件中的每一者接合到所述重佈線結構的接合連接件中的一者以及在所述重佈線結構上形成絕緣層以覆蓋所述晶粒。
雖然本發明已以實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明的精神和範圍內,當可作些許的更動與潤飾,故本發明的保護範圍當視後附的申請專利範圍所界定者為準。
10A、10B、10C:IC部分
15、16:接合層
15a、130a、Dt:頂表面
15b:底表面
20A、20B、20C、20D、20E:翹曲控制部分
110、420:重佈線結構
112:介電層
112b:最底介電層
112m:中間介電層
112o:開口
112t:最頂介電層
114:導電特徵
114b:最底層
114m:中間層
114t:最頂層/接合連接件
114t’:最頂層
120、620:積體電路(IC)元件
120s:側壁
122、410:半導體基板
122a、410a:前側
122b、410b:背側
123:半導體裝置
124:內連線結構
130:絕緣層
142:穿孔
144:接觸接墊
146:鈍化層
150:導電端子
152:金屬柱
154:焊料頂蓋
210:基板
210t:厚度
220:第一介電層
220t:厚度
222、322:介電層/第二介電層
224A、224B、224C:金屬圖案
226:附加介電層
228:附加金屬圖案
310:基板
320:介電層/第一介電層
324:第一金屬圖案
326:介電層/第三介電層
328:第二金屬圖案
430、522:基板穿孔(TSV)
440:接合接墊
442:接合介電層
520:IC元件
1241:介電層
1242:內連電路
1243:接合連接件
2241:第一特徵
2242、2242’:第二特徵
2243:第三特徵
2244:第四特徵
A1、A2:箭頭
BS:接合表面
C1:第一元件
C2:第二元件
CT:端子
DAF:晶粒貼合膜
H1:高度差
IF:接合介面
L1:載體晶粒
L2:晶粒堆疊
M1、M2、M3、M4:層級
R1:第一區
R2:第二區
R3:第三區
R4:第四區
S:線距
S1、S2、S3、S4、S5:半導體結構
SC:元件裝配件
T1:第一層級
T2:第二層級
TC:臨時載體
UF:底部填充層
W:線寬
為讓本發明的上述特徵和優點能更明顯易懂,下文特舉實施例,並配合所附圖式作詳細說明如下。
圖1A到圖1E示出根據一些實施例的積體電路(IC)部分在各種製作階段的示意性剖視圖。
圖2A到圖2B示出根據一些實施例的IC部分的示意性翹曲輪廓。
圖3A到圖3B示出根據一些實施例的IC部分的示意性輪廓圖。
圖4A到圖4B示出根據一些實施例的翹曲控制部分在各種製作階段的示意性剖視圖。
圖5示出根據一些實施例的包括IC部分及翹曲控制部分的半導體結構的示意性剖視圖。
圖6示出根據一些實施例的圖5中的翹曲控制部分的示意性俯視圖。
圖7A到圖7B示出根據一些實施例的半導體結構的組裝的示意圖。
圖8示出根據一些實施例的包括IC部分及翹曲控制部分的半導體結構的示意性剖視圖。
圖9A到圖9B示出根據一些實施例的具有不同配置的圖8中的翹曲控制部分的示意性俯視圖。
圖10到圖11示出根據一些實施例的半導體結構的變型的示意性剖視圖。
圖12示出根據一些實施例的半導體結構的應用的示意性剖視圖。
10A:IC部分
15:接合層
15a:頂表面
15b:底表面
20A:翹曲控制部分
110:重佈線結構
120:積體電路(IC)元件
130:絕緣層
146:鈍化層
150:導電端子
210:基板
220:第一介電層
222:介電層/第二介電層
224A:金屬圖案
DAF:晶粒貼合膜
S1:半導體結構
Claims (1)
- 一種半導體結構,包括: 積體電路元件; 絕緣層,在側向上包封所述積體電路元件的側壁; 重佈線結構,設置在所述絕緣層及所述積體電路元件上,所述重佈線結構電性連接到所述積體電路元件;以及 翹曲控制部分,與所述重佈線結構相對地耦合到所述積體電路元件的背側,所述翹曲控制部分包括: 基板; 圖案化介電層,設置在所述基板與所述積體電路元件之間;以及 金屬圖案,嵌入在所述圖案化介電層中且與所述積體電路元件電性隔離。
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2020
- 2020-07-01 US US16/919,068 patent/US11410948B2/en active Active
- 2020-09-17 TW TW109132101A patent/TW202113997A/zh unknown
- 2020-09-24 CN CN202011016394.1A patent/CN112563218A/zh active Pending
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2022
- 2022-07-03 US US17/857,026 patent/US20220336392A1/en active Pending
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TWI807522B (zh) * | 2021-04-22 | 2023-07-01 | 台灣積體電路製造股份有限公司 | 內連接結構的形成方法 |
TWI828035B (zh) * | 2021-08-27 | 2024-01-01 | 台灣積體電路製造股份有限公司 | 半導體封裝 |
US11862549B2 (en) | 2021-08-27 | 2024-01-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor packages having conductive patterns of redistribution structure having ellipse-like shape |
US11610878B1 (en) | 2021-09-02 | 2023-03-21 | Nanya Technology Corporation | Semiconductor device with stacked chips and method for fabricating the same |
TWI809607B (zh) * | 2021-09-02 | 2023-07-21 | 南亞科技股份有限公司 | 具有堆疊晶片的半導體元件及其製備方法 |
US11996327B2 (en) | 2021-09-13 | 2024-05-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interconnect structure and methods of forming the same |
TWI803321B (zh) * | 2022-03-03 | 2023-05-21 | 南亞科技股份有限公司 | 具有去耦合單元的半導體元件及其製造方法 |
Also Published As
Publication number | Publication date |
---|---|
CN112563218A (zh) | 2021-03-26 |
US20210091022A1 (en) | 2021-03-25 |
US11410948B2 (en) | 2022-08-09 |
US20220336392A1 (en) | 2022-10-20 |
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