TW202113857A - Embeded non-volatile memory device and method for fabricating the same - Google Patents

Abstract

An embedded non-volatile memory (ENVM) device includes a substrate, a conductive plug, a first electrode, a memory layer and a second electrode. The substrate has a through-hole passing through a surface of the substrate. The conductive plug is disposed in the through hole and defines a recess in the substrate extending form an opening of the through-hole to a top surface of the conductive plug. The first electrode is disposed on the substrate and partially extends into the recess. The memory layer is disposed on the first conductive layer and has a protrusion aligning to the through-hole. The second electrode is disposed on the memory layer.

Description

Embedded non-volatile memory element and manufacturing method thereof

This disclosure is about a memory device and its manufacturing method. In particular, it relates to an Embedded Non-Volatile Memory (ENVM) and its manufacturing method.

The non-volatile memory device has the characteristic of not losing the information stored in the memory unit even when the power is removed. At present, the most widely used memory device is a charge trap flash (CTF) memory device that uses a charge trap. However, as the accumulation density of memory devices increases, the critical size and pitch of the devices shrink, and the charge storage flash memory devices face their physical limits and cannot operate.

Embedded non-volatile memory devices, taking Resistive random-access memory (Resistive random-access memory, ReRAM) as an example, apply a pulse voltage to the metal oxide film of the memory device to generate a resistance difference Used as the basis for the interpretation of information storage status such as "0" and "1". It is superior to flash memory in terms of device density, power consumption, programming/erasing speed, or three-dimensional space stacking characteristics. Therefore, it has become one of the memory devices that have attracted much attention in the industry.

However, typical variable resistance memory devices usually have a higher forming voltage than the operating voltage, which is not conducive to low-voltage operation and cannot provide low-power solutions for electronic devices that require low-voltage operation, such as the Internet of Things ( Internet of Things (IoT), wearable devices or portable electronic devices, such as laptops, tablets, smart watches, mobile phones, etc., to increase battery life.

Therefore, there is a need to provide an advanced embedded non-volatile memory device and a manufacturing method thereof to solve the problems faced by the conventional technology.

An embodiment of this specification discloses an embedded non-volatile memory device, including: a substrate, a conductive plug, a first electrode, a memory layer, and a second electrode. The substrate has a through hole through the surface of the substrate. The conductive plug is located in the through hole, and a recess is defined in the base material, which extends from the opening of the through hole to the top surface of the conductive plug. The first electrode is located above the substrate and partially extends into the recessed portion. The memory layer is located above the first electrode and has a protrusion aligned with the recess. The second electrode is located above the memory layer.

Another embodiment of this specification discloses a manufacturing method of an embedded non-volatile memory device, which includes the following steps: first, a substrate is provided, and a through hole is formed in the substrate to pass through the surface of the substrate. Then, a conductive plug is formed in the through hole, and the conductive plug is etched back, so that the conductive plug defines a recess in the base material, which extends from the opening of the through hole to the top surface of the conductive plug. Then, a first electrode is formed above the substrate and partially extends into the recessed portion, and then a memory layer is formed above the first electrode so that it has a protruding portion aligned with the recessed portion. Subsequently, a second electrode is formed on the memory layer.

According to the above-mentioned embodiments, this specification is to provide an embedded non-volatile memory device and a manufacturing method thereof. It forms a through hole in the base material and forms a conductive plug in the through hole. The conductive plug located in the through hole of the base material is etched back to form a cavity in the through hole. Subsequently, a first electrode layer, a memory layer, and a second electrode layer are sequentially formed on the conductive plugs, and are filled in the recesses, so that the memory layer has at least one protrusion, which is self-aligned to the conductive plugs in the through holes. Stuffed. Wherein, the memory layer may include transition metal oxides (TMO) or phase change materials (Phase Change Material, PCM).

Because the protrusions of the memory layer will have a more concentrated electric field due to the corner effect, it can improve the formation of conductive paths of excessive metal oxides or phase change materials in the memory layer and reduce the embedment. The formation voltage of non-volatile memory can provide a low-power solution for electronic devices that require low-voltage operation and increase battery life.

This specification provides an embedded non-volatile memory device and a manufacturing method thereof, which can reduce the forming voltage of the embedded non-volatile memory and provide a low-power solution for electronic devices that require low-voltage operation. In order to make the above-mentioned embodiments and other purposes, features, and advantages of this specification more comprehensible, a plurality of embodiments are specifically listed in the following, which are described in detail in conjunction with the accompanying drawings.

However, it must be noted that these specific implementation cases and methods are not intended to limit the present invention. The present invention can still be implemented using other features, elements, methods, and parameters. The preferred embodiments are only used to illustrate the technical features of the present invention, and not to limit the scope of the patent application of the present invention. Those with ordinary knowledge in this technical field will be able to make equivalent modifications and changes based on the description in the following specification without departing from the spirit of the present invention. In different embodiments and drawings, the same elements will be represented by the same element symbols.

Please refer to FIG. 1A to FIG. 1F. FIG. 1A to FIG. 1F are cross-sectional schematic diagrams of a series of process structures for manufacturing the embedded non-volatile memory device 100 according to an embodiment of the present specification. In this embodiment, the method of manufacturing the embedded non-volatile memory device 100 includes the following steps:

First, a substrate 101 is provided. Among them, the substrate 101 may include a low dielectric constant material. For example, in some embodiments of this specification, the substrate 101 may be a silicon-containing dielectric layer, or a plasticized material, such as polyimide (PI), polyethylene naphthalate A flexible dielectric material layer of polyethylene naphthalate (polyethylene naphthalate two formic acid glycol ester, PEN) or polyethylene terephthalate (PET). In this embodiment, the substrate 101 may be a multi-layer structure including an ultra-low dielectric constant (ULD) material layer 101A, a buffer layer 101B, and an interlayer dielectric (ILD) 101C (such as the first 1A pictured).

Wherein, the ultra-low dielectric constant material layer 101A may be a silicon oxide (SiO _x ) layer with a porous structure. The buffer layer 101B is located between the polysilicon base layer 101A and the interlayer dielectric layer 101C, and may include Nitrogen Doped Silicon Carbide (NDC). The interlayer dielectric layer 101C may be a silicon oxide layer deposited by tetraethoxysilane (TEOS) using a plasma-enhanced CVD (Remote plasma-enhanced CVD, RPECVD) process. In addition, in this embodiment, the step of providing the substrate 101 further includes forming a metal interconnection structure (not shown) including the first wire 102 in the ultra-low-k material layer 101A.

Next, at least one through hole 103 is formed in the substrate 101, and a conductive plug 104 is formed in the through hole 103, so that the conductive plug 104 is in electrical contact with the first wire 102 of the metal interconnection structure (such as 1B Pictured). The formation of the conductive plug 104 includes the following steps: first, a patterning process, such as reactive ion etching (Reactive-Ion Etching, RIE), is performed to form a through hole 103 in the substrate 101, and a part of the metal The first wire 102 in the connection structure (not shown) is exposed to the outside.

Next, a barrier layer 105 of titanium nitride and a conductive material layer containing tungsten (Tungsten, W) (not shown) are formed on the surface 101 s of the substrate, and filled into the through hole 103. Then use the substrate surface 101s as a stop layer to perform a planarization process, such as Chemical-Mechanical Planarization (CMP), to remove a part of the barrier layer 105 and the tungsten-containing conductive material layer above the substrate surface 101s , To form the conductive plug 104 in the through hole 103, so that the bottom surface 104a of the conductive plug 104 (through the barrier layer 105) is in electrical contact with the first wire 102 of the metal interconnection structure, and the conductive plug 104 The top surface 104b is coplanar with the substrate surface 101s.

Then, the conductive plug 104 is etched back to remove it so that the conductive plug 104 defines a recess 104r in the base material 101, which extends upward from the top surface 104b of the conductive plug to the opening of the through hole 103, making it back The top surface 104b' of the etched conductive plug 104 serves as the bottom surface of the recess 104r, and there is a height difference H between the bottom surface of the recess 104r and the substrate surface 101s (as shown in FIG. 1C). In some embodiments of this specification, the etchant for etching back the conductive plug 104 includes hydrogen peroxide (H ₂ O ₂ ) and/or ammonium hydroxide (NH ₄ OH).

After that, a first electrode layer 110, a memory layer 106, and a second electrode layer 107 are sequentially formed on the surface 101s of the substrate, so that a part of the first electrode layer 110 extends into the recess 104r and is placed in the first electrode layer 110. A recess 110r is also formed on the top surface 110a of the electrode layer 110. When the memory layer 106 is formed, a part of the memory layer 106 can be extended into the recess 110r to form a protrusion 106a aligned with the through hole 103. The top surface 106b of the memory layer 106 may also have a recess 106r. When the second electrode layer 107 is formed, a part of the second electrode layer 107 also extends into the recess 106r. In order to take into account the stability of the subsequent process, it is preferable to increase the thickness of the second electrode layer 107 so that the top 107a has a flat surface. However, in this embodiment, the top 107a of the second electrode layer 107 may still have a recess 107r (as shown in FIG. 1D).

In some embodiments of this specification, a low-pressure chemical vapor deposition (LPCVD) method may be used to sequentially form the first electrode layer 110, the memory layer 106, and the second electrode on the surface 101s of the substrate 101. Layer 107. The material constituting the first electrode layer 105 can be selected from tungsten, titanium nitride (TiN), tantalum nitride (TaN), copper (Copper, Cu), aluminum (Aluminum, Al), Gold (Au), silver (Silver, Ag), platinum (Platinum, Pt), titanium (Titanium, Ti), iridium (Iridium, Ir), and any combination of the foregoing are a group. In this embodiment, the first electrode layer 110 may be a composite metal layer composed of titanium nitride/tantalum nitride/platinum/iridium.

The material constituting the memory layer 106 may be a transition metal oxide (TMO) or a phase change material (Phase Change Material). The transition metal oxide may be, for example, Tantalum Oxide (TaO _x ) , Titanium oxide, nickel oxide, hafnium oxide (HfO _x ), zirconium oxide (ZrO _x ), tungsten oxide (Tungsten Oxide, WO _x ), zinc oxide (Zinc Oxide) , ZnO _x ), aluminum oxide (Aluminum Oxide, AlO _x ), molybdenum oxide (Molybdenum Oxide, MnO _x ), copper oxide (Copper Oxide, CuO _x ) or any combination of the above. The phase change material can be, for example, germanium, antimony, tellurium (Ge _x Sb _y Te _z , where x, y, and z may be integers, respectively, GST) and other chalcogen compounds, silver indium antimony tellurium (AgInSbTe) or a combination of the above. In this embodiment, the memory layer 106 A titanium oxide (TiOx) layer.

The material constituting the second electrode layer 107 may be the same as or different from the material constituting the first electrode layer 105. In this embodiment, the second electrode layer 107 may be the same as the first electrode layer 105, and is a composite metal layer composed of titanium nitride/tantalum nitride/platinum/iridium.

The first electrode layer 110, the memory layer 106, and the second electrode layer 107 are patterned again, so that the remaining parts of the first electrode layer 110, the memory layer 106, and the second electrode layer 107 are aligned with the through holes 103. A dielectric capping layer 111 is formed on the surface 101s of the substrate to cover the remaining portions of the first electrode layer 110, the memory layer 106, and the second electrode layer 107 (as shown in Figure 1E) .

In some embodiments of this specification, the patterning of the first electrode layer 110, the memory layer 106, and the second electrode layer 107 includes forming a patterned hard mask layer (not shown) on the second electrode layer 107 Align the through holes 103; then use a hard mask layer (not shown) as an etching mask, and use an etching process, such as reactive ion etching, to remove a part of the first electrode layer 110, the memory layer 106, and the second The electrode layer 107 aligns the remaining parts of the first electrode layer 110, the memory layer 106, and the second electrode layer 107 with the through hole 103, and exposes a part of the substrate surface 102s to the outside.

Then, a low pressure chemical vapor deposition method is used to form a dielectric covering layer 111, covering the exposed portion of the substrate surface 102s and the remaining portions of the first electrode layer 110, the memory layer 106, and the second electrode layer 107. In some embodiments of this specification, the material constituting the dielectric covering layer 111 may be silicon nitride (SiN), aluminum nitride (AlN), silicon oxynitride (SiON), or any combination of the foregoing.

Subsequently, a back-end-of-line (BEOL) process is performed to form the embedded non-volatile memory device 100 as shown in FIG. 1F. The back-end manufacturing process described here may be a standard manufacturing process in the art, and may be implemented according to the structure of the embedded non-volatile memory device 100. In this embodiment, the subsequent process includes: forming a passivation layer 108 on the dielectric covering layer 111, and forming a second wire 109 connecting the embedded non-volatile memory device 100 and the peripheral circuit, so that the second wire 109 and the second wire 109 The two electrode layers 107 are in electrical contact. Wherein, the material constituting the passivation layer 108 may include silicon oxide or silicon nitride.

Please refer to FIG. 1E again, the embedded non-volatile memory device 100 includes: a substrate 101, a conductive plug 104, a first electrode 110, a memory layer 106, and a second electrode 107. The substrate 101 has a through hole 103 passing through the surface 101s of the substrate. The conductive plug 104 is located in the through hole 103, and a recess 104r is defined in the substrate 101, which extends from the opening of the through hole 103 to the top surface 104b' of the conductive plug 104. The first electrode 110 is located above the substrate 101 and partially extends into the recess 104r. The memory layer 106 is located above the first electrode 110 and has a protrusion 106a aligned with the recess 1004r. The second electrode 107 is located above the memory layer 106.

According to the above-mentioned embodiments, this specification is to provide an embedded non-volatile memory device and a manufacturing method thereof. It forms a through hole in the base material and forms a conductive plug in the through hole. The conductive plug located in the through hole of the base material is etched back to form a cavity in the through hole. Subsequently, a first electrode layer, a memory layer, and a second electrode layer are sequentially formed on the conductive plugs, and are filled in the recesses, so that the memory layer has at least one protrusion, which is self-aligned to the conductive plugs in the through holes. Stuffed. Among them, the memory layer may include a transition metal oxide or a phase change material.

Because the protrusions of the memory layer will have a more concentrated electric field due to the corner effect, it can improve the formation of the conductive path of the resistance wire of the excessive metal oxide or phase change material in the memory layer, and reduce the formation of embedded non-volatile memory. In order to provide low-power solutions for electronic devices that require low-voltage operation, and increase battery life.

Although the present invention has been disclosed as above in the preferred embodiment, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to those defined by the attached patent application scope.

100: Embedded non-volatile memory components 101: Substrate 101A: Ultra-low dielectric coefficient material layer 101B: buffer layer 101C: Interlayer dielectric layer 101s: substrate surface 102: The first wire 103: Through hole 104: Conductive plug 104a: bottom surface of conductive plug 104b, 104b’: The top surface of the conductive plug 104r: The recessed part of the conductive plug 105: Barrier layer 106: memory layer 106a: The prominent part of the memory layer 106b: the top surface of the memory layer 107: The second electrode layer 107a: the top of the second electrode layer 107r: The recessed part of the second electrode layer 109: second wire 110: The first electrode layer 110a: The top surface of the first electrode layer 110r: The recessed part of the first electrode layer 111: Dielectric cover layer H: height difference

In order to have a better understanding of the above and other aspects of this specification, the following specific examples are given in conjunction with the accompanying drawings to describe in detail as follows: 1A to 1F are schematic cross-sectional diagrams of a series of process structures for fabricating embedded non-volatile memory devices according to an embodiment of this specification.

100: Embedded non-volatile memory components

101: Substrate

101A: Ultra-low dielectric constant material layer

101B: buffer layer

101C: Interlayer dielectric layer

101s: substrate surface

102: first wire

103: Through hole

104: Conductive plug

104a: bottom surface of conductive plug

104b’: Top surface of conductive plug

105: barrier layer

106: memory layer

106a: protrusion of the memory layer

106b: the top surface of the memory layer

107: second electrode layer

109: second wire

110: first electrode layer

110r: Depressed portion of the first electrode layer

111: Dielectric cover layer

Claims (10)

An embedded non-volatile memory (Embedded Non-Volatile Memory, ENVM) component includes: A substrate with a through hole passing through a surface of the substrate; A conductive plug is located in the through hole and defines a recess in the substrate, extending from an opening of the through hole to a top surface of the conductive plug; A first electrode located above the substrate and partially extending into the recessed portion; A memory layer located above the first electrode and having a protruding portion aligned with the recessed portion; and A second electrode is located above the memory layer. The embedded non-volatile memory device described in claim 1, wherein the memory layer includes a transition metal oxide (TMO) or a phase change material (Phase Change Material). The embedded non-volatile memory device described in claim 1, wherein the top surface of the conductive plug and the surface of the substrate have a height difference. The embedded non-volatile memory device described in item 1 of the scope of patent application further includes: A first wire located on the opposite side of the top surface of the conductive plug and in electrical contact with the conductive plug; and A second wire is located above the second electrode and is in electrical contact with the second electrode. The embedded non-volatile memory device as described in claim 1, wherein the conductive plug includes tungsten (W), and the first electrode and the second electrode include titanium (Ti) A manufacturing method of embedded non-volatile memory components, including: Providing a substrate with a surface; A through hole is formed in the substrate, passing through the surface; Forming a conductive plug in the through hole; Etch back the conductive plug so that the conductive plug defines a recess in the substrate, extending from an opening of the through hole to a top surface of the conductive plug; Forming a first electrode above the substrate and partially extending into the recessed portion; Forming a memory layer above the first electrode so that it has a protruding portion aligned with the recessed portion; and A second electrode is formed on the memory layer. According to the manufacturing method of the embedded non-volatile memory device described in claim 6, wherein the step of forming the through hole includes exposing a first wire located under the substrate to the outside through the through hole According to the manufacturing method of the embedded non-volatile memory device described in claim 6, wherein the step of etching back the conductive plug includes removing a part of the conductive plug so that the conductive plug is The top surface serves as a bottom surface of the recess and has a height difference with the surface of the substrate. The manufacturing method of the embedded non-volatile memory device described in item 6 of the scope of patent application further includes: Patterning the first electrode, the memory layer and the second electrode; Forming a dielectric capping layer to cover the remaining parts of the first electrode, the memory layer and the second electrode; and A second wire is formed above the second electrode, so that the second wire is in electrical contact with the second electrode. According to the manufacturing method of embedded non-volatile memory device described in item 6 of the scope of patent application, the conductive plug includes tungsten, and the step of etching back the conductive plug includes using an etchant containing ammonium hydroxide (NH ₄ OH).

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