TWI662696B - Semiconductor structure and manufacturing method thereof - Google Patents

Abstract

The invention provides a semiconductor structure including a substrate, a first insulation layer, a conductive connection element, a resistance change element, a second insulation layer, and a first metal layer. The surface of the substrate has a doped region, and the first insulating layer is disposed on the substrate. The conductive connection element is disposed through the first insulating layer and contacts the surface of the doped region. The resistance change element is disposed on the conductive connection element and is in contact with the conductive connection element. The second insulating layer is disposed on the first insulating layer. The first metal layer is disposed on the conductive connection element and the resistance change element. The first metal layer includes a first metal pattern, and the first metal pattern is electrically connected to the resistance change element.

Description

Semiconductor structure and manufacturing method thereof

The present invention relates to a semiconductor structure and a method for manufacturing the same, and more particularly, to a semiconductor structure having a variable resistance element and a method for manufacturing the same.

In today's electronic products, electronic chips with a semiconductor structure have been widely used in various electronic products, such as computers, mobile phones, electronic watches and other electronic products. In the semiconductor structure, variable resistors can be provided to provide specific Functions, such as resistive random access memory (RRAM), make manufactured electronic products have the function of storing and storing data. Among them, resistive random access memory changes its variable resistance by applying current or voltage. The resistance value is used to switch between the memory state “0” (set state) and the memory state “1” (reset state) according to different resistance values, thereby achieving the effect of storing data.

An object of the present invention is to provide a semiconductor structure and a manufacturing method thereof, which improve the reliability of the semiconductor structure, increase the density of the resistance change element, and reduce the manufacturing cost by changing the setting position of the conventional resistance change element.

An embodiment of the present invention provides a semiconductor structure including a substrate, a first insulating layer, A conductive plug, a variable resistance element, a second insulating layer, and a first metal layer. The surface of the substrate has a doped region, and the first insulating layer is disposed on the substrate. The conductive connection element is disposed through the first insulating layer and contacts the surface of the doped region. The resistance change element is disposed on the conductive connection element and is in contact with the conductive connection element. The second insulating layer is disposed on the first insulating layer. The first metal layer is disposed on the conductive connection element and the resistance change element. The first metal layer includes a first metal pattern, and the first metal pattern is electrically connected to the resistance change element.

Another embodiment of the present invention provides a method for manufacturing a semiconductor structure, which includes the following steps. A first insulating layer is formed on the substrate. A first connection hole is formed in the first insulation layer, and the first connection hole exposes a doped region on the surface of the substrate. A conductive plug is formed in the first connection hole, and the conductive plug contacts the surface of the doped region. A resistance change element is formed on the conductive connection element, and the resistance change element is in contact with the conductive connection element. A second insulating layer is formed on the first insulating layer. A second connection hole is formed in the second insulation layer, and the second connection hole exposes the conductive connection element or the resistance change element. A first metal layer is formed on the conductive connection element and the variable resistance element. The first metal layer includes a first metal pattern. At least a portion of the first metal pattern is located in the second connection hole and is electrically connected to the variable resistance element.

The resistance change element of the semiconductor structure of the present invention is disposed between the conductive connection element and the first metal layer, and directly contacts the conductive connection element. Therefore, it is not necessary to additionally provide other conductive parts which are in contact with the resistance change element and are used to electrically connect other conductive layers. Components, thereby reducing the manufacturing cost, and simultaneously achieving the effects of increasing the density of the variable resistance element and reducing the resistance value. On the other hand, since the first insulating layer with a higher dielectric constant and no holes is located under the variable resistance element, it can provide a better etch blocking effect in the process of manufacturing the variable resistance element.

100‧‧‧Semiconductor Structure

110‧‧‧ substrate

112‧‧‧ doped region

120‧‧‧The first insulation layer

122‧‧‧Gate insulation

130‧‧‧resistance change element

130’‧‧‧ resistance variable element layer

132‧‧‧resistance change layer

134‧‧‧first electrode layer

136‧‧‧ ion collection layer

138‧‧‧Second electrode layer

140‧‧‧Second insulation layer

150‧‧‧third insulating layer

160‧‧‧Fourth insulation layer

CP‧‧‧ conductive connection element

G‧‧‧Gate

H1‧‧‧First connection hole

H2‧‧‧Second connection hole

H3‧‧‧Third connection hole

H4‧‧‧Fourth connection hole

M1‧‧‧First metal layer

M1p‧‧‧First metal pattern

M2‧‧‧Second metal layer

M2p‧‧‧Second metal pattern

SP‧‧‧ spacer

ST1 ~ ST7‧‧‧‧steps

V‧‧‧ metal layer connection element

1 to 7 are schematic cross-sectional views illustrating a method for manufacturing a semiconductor structure according to an embodiment of the present invention.

FIG. 8 is a schematic cross-sectional view of a resistance change element according to another embodiment of the present invention.

FIG. 9 is a flowchart of a method for manufacturing a semiconductor structure according to an embodiment of the present invention.

In order to enable those of ordinary skill in the art to further understand the present invention, the embodiments of the present invention are enumerated below, and the contents of the present invention and the effects to be achieved are described in detail in conjunction with the drawings. It should be noted that the drawings are simplified schematic diagrams. Therefore, only the elements and combinations related to the present invention are shown to provide a clearer description of the basic architecture or implementation method of the present invention, and the actual elements and layout may be more As complicated. In addition, for convenience of explanation, the elements shown in the drawings of the present invention are not drawn in proportion to the actual number, shape, and size, and the detailed proportions can be adjusted according to design requirements.

Please refer to FIG. 1 to FIG. 7, which are schematic cross-sectional views illustrating a method for manufacturing a semiconductor structure according to an embodiment of the present invention, and FIG. 7 also illustrates a semiconductor structure according to an embodiment of the present invention Schematic cross-section of 100. As shown in FIG. 1, in the method for manufacturing a semiconductor structure in this embodiment, first, a substrate 110 is provided. The substrate 110 may be a substrate including a semiconductor material, such as a silicon substrate, a silicon-containing substrate, or a silicon-clad insulation. (silicon-on-insulator, SOI) substrate and other semiconductor substrates, but not limited to this. The substrate 110 in this embodiment is a silicon substrate, and the substrate 110 may have one of an N-type semiconductor material and a P-type semiconductor material. As an example, the substrate 110 herein has a P-type semiconductor material. In this embodiment, the surface of the substrate 110 may optionally have a gate insulating layer 122 and a patterned conductive layer used as a gate of a transistor, as shown by the gate G in FIG. 1. On the gate insulation layer 122. The gate insulating layer 122 may include silicon oxide, for example, but is not limited thereto. In addition, A spacer SP is selectively formed around the gate insulating layer 122 and the gate G. The material of the spacer SP may include silicon oxide, silicon nitride, or a stack thereof, or other suitable materials.

Next, a first insulating layer 120 is formed on the substrate 110 and covers the gate insulating layer 122 and the gate G. The first insulating layer 120 can be used as an interlayer dielectric layer (ILD) in the semiconductor structure of the present invention. ), But not limited to this. Examples of the material of the first insulating layer 120 may include silicon oxide or fluorosilicate glass (FSG), but it is not limited thereto. In this embodiment, after the formation of the first insulating layer 120 is completed, a first connection hole H1 may be formed vertically in the first insulating layer 120. For example, in this embodiment, a vertical penetration through the first insulating layer 120 may be formed through an etching process. The first connection hole H1 is exposed to expose the doped region 112 on the surface of the substrate 110, where vertical means a direction substantially perpendicular to the surface of the substrate 110. The doped region 112 may be formed by ion implantation before the first insulating layer 120 is formed or after the first connection hole H1 is formed, but the manufacturing process is not limited thereto. In this embodiment, the doped region 112 may be used as a source doped region or a drain doped region of a transistor, and a channel region is formed on the surface of the substrate 110 between the two doped regions 112, so that the channel region, The doped region 112, the gate G, and the gate insulating layer 122 form a transistor, but are not limited thereto. In addition, the doped region 112 may have one of an N-type semiconductor material and a P-type semiconductor material. In this embodiment, the type of the semiconductor material included in the doped region 112 may be different from the type of the semiconductor material included in the substrate 110. That is, the doped region 112 of this embodiment is exemplified by an N-type semiconductor material, but is not limited thereto.

As shown in FIG. 2, after the formation of the first connection hole H1 and the doped region 112 is completed, a conductive plug CP is formed in the first connection hole H1, and the conductive connection element CP contacts the surface of the doped region 112. The doped region 112 is electrically connected, that is, the conductive connection element CP passes through the first insulating layer 120 and the gate insulation layer 122 vertically, and the conductive connection element CP contacting the surface of the doped region 112 can be used as a source electrode or Is the drain electrode, where the vertical penetration of the conductive connection element CP indicates that the conductive connection element CP does not have The horizontally extending part. In this embodiment, for example, the conductive connection element CP can be made by a deposition process, and the conductive connection element CP can include tungsten (W), but is not limited thereto.

Next, a variable resistance element 130 is formed on the conductive connection element CP, and the variable resistance element 130 is brought into contact with the conductive connection element CP. For example, as shown in FIG. 3, in this embodiment, the resistance change can be comprehensively formed first. The element layer 130 'is on the first insulating layer 120 and the conductive connection element CP, and the resistance change element layer 130' is brought into contact with the conductive connection element CP. Then, as shown in FIG. 4, an etching process is performed to change part of the resistance. The element layer 130 'is removed to form a resistance change element 130 in contact with the conductive connection element CP. The resistance change element 130 in this embodiment does not contact all the conductive connection elements CP, but the manufacturing method is not limited thereto. It can be made in other suitable ways. It should be noted that the resistance change element 130 may have a single-layer structure or a multilayer structure. The resistance change element 130 in this embodiment uses a single-layer structure as an example. In addition, the resistance change element 130 in this embodiment may be used as a resistive memory cell (RRAM cell), that is, the resistance change element 130 may include a resistance change layer 132, and when a current or voltage is applied to the resistance change layer 132 , Its resistance value will change, thereby changing the memory state of resistive memory cells. In detail, one of the high-resistance state and the low-resistance state can be regarded as digital data “0” and the other as the digital data “1”, for example, the high-resistance state can be regarded as digital data “0” and the low-resistance state can be regarded as digital. The data "1", that is, the resistance change layer 132 is set to a low resistance state as a memory state through a set operation, and the resistance change layer 132 is set to a high resistance state as a memory state through a reset operation. "0"", And the setting operation example is to provide the resistance change layer 132 with a set voltage, and the reset operation example is to provide the resistance change layer 132 with a reset voltage. Therefore, when a reading is applied to the resistance change element 130 When the voltage is applied, the resistance value of the variable resistance layer 132 can be read, and the data stored in the variable resistance element 130 can be obtained. In addition, the variable resistance layer 132 may include hafnium oxide (HfO _x ), tantalum oxide (TaO _x ), titanium oxide (TiO _x ), nickel oxide (NiO _x ), niobium oxide (NbO _x ), and aluminum oxide (AlO _x ). At least one of tungsten oxide (WO _x ), zinc oxide (ZnO _x ), cobalt oxide (CoO _x ), lanthanum oxide (LaO _x ), zirconium oxide (ZrO _x ), or a combination thereof, wherein hafnium oxide may be two HfO ₂ and tantalum oxide may be tantalum pentoxide (Ta ₂ O ₅ ), but the material is not limited thereto.

Next, as shown in FIG. 5, a second insulating layer 140 is formed on the first insulating layer 120 and the resistance change element 130. Then, as shown in FIG. 6, the second insulating layer 140 is patterned, for example, by a photolithography and etching process. A second connection hole H2 is formed in the second insulating layer 140, and the second connection hole H2 exposes the conductive connection element CP or the resistance change element 130, and then a first metal is formed on the conductive connection element CP and the resistance change element 130. Layer M1, where the first metal layer M1 includes a first metal pattern M1p, at least a portion of the first metal pattern M1p is located in the second connection hole H2, and is electrically connected to at least one of the resistance change element 130 and the conductive connection element CP In this embodiment, the resistance change element 130 is in contact with the first metal pattern M1p, but is not limited thereto. In addition, more metal layers, conductive layers, or insulating layers may be provided according to actual needs. For example, as shown in FIG. 7, a third insulating layer 150 may be formed on the first metal layer M1, and then A third connection hole H3 is formed in the third insulation layer 150, and the third connection hole H3 exposes a part of the first metal pattern M1p of the first metal layer M1. Then, a metal layer connection element (via) is formed in the third connection hole H3. ) V, that is, the metal layer connection element V is disposed in the third insulation layer 150 and is electrically connected to the first metal pattern M1p. Then, a fourth insulation layer is formed on the third insulation layer 150 and the metal layer connection element V. 160 and a fourth connection hole H4 located in the fourth insulation layer 160. Next, a second metal layer M2 is formed on the third insulation layer 150 and the metal layer connection element V, wherein the second metal layer M2 includes a second metal pattern M2p, at least a part of the second metal pattern M2p is located in the fourth connection hole H4 and is electrically connected to the metal layer connection element V, but the type of the film layer provided, the number of the film layers provided, and the sequence of the film layers are not limited to this . In the above manufacturing process, an example of a method of forming the second connection hole H2, the third connection hole H3, the fourth connection hole H4, or more connection holes can be through an etching process, but is not limited thereto. In this embodiment, the first metal pattern M1p of the first metal layer M1 and the second metal pattern M2p of the second metal layer M2 can be used as metal traces for transmitting signals in the semiconductor structure 100, and in order to reduce the metal traces Parasitic For the capacitor, the second insulating layer 140, the third insulating layer 150, the fourth insulating layer 160, or other stacked insulating layers can be designed as a film with a lower dielectric constant, for example, by making holes in the insulating layer. In order to reduce the dielectric constant, the dielectric constants of the first insulating layer 120 and the gate insulating layer 122 in this embodiment are larger than those of the second insulating layer 140, the third insulating layer 150, the fourth insulating layer 160, and other stacks. The dielectric constant of the insulating layer on the fourth insulating layer 160, and the first insulating layer 120 and the gate insulating layer 122 are relatively strong in structure. In addition, in this embodiment, the second insulating layer 140, the third insulating layer 150, and the fourth insulating layer 160 may include, for example, a black diamond (BD) material and serve as an intermetal dielectric layer of the semiconductor structure 100. (inter-metal dielectric, IMD), but not limited to this, other insulating materials with holes can also be used, and examples of the first metal layer M1 and the second metal layer M2 may include copper (Cu) or other suitable metal material.

In addition, the second insulating layer 140, the third insulating layer 150, the fourth insulating layer 160, or other insulating layers stacked on the fourth insulating layer 160 may also be a multi-layered insulating structure, for example, as an inter-metal dielectric. As an example, the second insulating layer 140 of the solid layer may include an etch stop layer and a hole layer. The hole layer is disposed on the etch stop layer, and the hole layer has a plurality of holes for reducing Holes with a dielectric constant may include, for example, a black diamond material, and the etch stop layer is a denser film layer than the hole layer. For example, it may include silicon nitride (Si ₃ N ₄ ) to block etching substances in the etching process. Therefore, the structure under the second insulating layer 140 is prevented from being damaged, but the material and quantity of the film layer are not limited thereto. In addition, since the relatively dense etch-stop layer in the second insulating layer 140 is located on the resistance change element 130, the resistance change element 130 can be reduced from being affected by free ions of other insulation layers or the resistance change element 130 can be reduced. Escape of charged substances (eg ions, electrons) generated during operation.

Please refer to FIG. 7 again. The semiconductor structure 100 of this embodiment includes a substrate 110, a first insulating layer 120, a conductive connection element CP, a resistance change element 130, a second insulating layer 140, and a first metal layer. M1. The surface of the substrate 110 has a doped region 112. The first insulating layer 120 is disposed on the substrate 110 and has a first connection hole H1 exposing the doped region 112 on the surface of the substrate 110. The conductive connection element CP is disposed in the first connection hole H1. That is, the first insulation layer 120 is penetrated and the conductive connection element CP is in contact with the surface of the doped region 112. The resistance change element 130 is disposed on and in contact with the conductive connection element CP. The second insulation layer 140 is provided. The first insulating layer 120 and the variable resistance element 130 have second connection holes H2 exposing the conductive connection element CP or the variable resistance element 130. The first metal layer M1 is disposed on the conductive connection element CP, the variable resistance element 130, and the first On the two insulating layers 140, the first metal layer M1 may include a first metal pattern M1p. At least a part of the first metal pattern M1p is located in the second connection hole H2, and is connected to at least one of the resistance change element 130 and the conductive connection element CP. Electrical connection. In addition, the semiconductor structure 100 may optionally include more metal layers, conductive layers, or insulation layers. The semiconductor structure 100 of FIG. 7 may include a third insulation layer 150, a fourth insulation layer 160, and a metal layer connection element. V and the second metal layer M2, the third insulating layer 150 is disposed on the first metal layer M1, and has a third connection hole H3 exposing a part of the first metal pattern M1p of the first metal layer M1, and the metal layer connection element V The third connection hole H3 is disposed in the third insulation layer 150 and is electrically connected to the first metal pattern M1p. The fourth insulation layer 160 having the fourth connection hole H4 is disposed in the third insulation layer 150. On the connecting element V with the metal layer, a second metal layer M2 is disposed on the connecting element V and the fourth insulating layer 160. The second metal layer M2 includes a second metal pattern M2p, and at least a part of the second metal pattern M2p is located in the first The four connection holes H4 are electrically connected to the metal layer connection element V.

In a conventional semiconductor structure, a resistance change element generally used as a resistive memory cell is disposed between two metal layers, for example, between the first metal layer M1 and the second metal layer M2, or It is disposed between the second metal layer M2 and the metal layer above the second metal layer M2. When the resistance change element is disposed between the first metal layer M1 and the second metal layer M2 by way of example, since the thickness of the resistance change element will be smaller than the thickness of the metal layer connection element V between the two metal layers, the resistance will be required. A conductive plug is additionally provided above or below the change element 130, and the conductive element is in contact with the first metal layer M1 or the second metal layer M2, so that the resistance change element 130 can be electrically connected to the first metal layer M1 or The second metal layer M2, that is, under the traditional design, additional conductive parts need to be manufactured, and the manufacturing cost of the semiconductor structure (such as material cost, mask cost, and process cost) must be additionally added. In contrast, in this embodiment, since the resistance change element 130 is disposed between the conductive connection element CP and the first metal layer M1, and directly contacts the conductive connection element CP, or even directly contacts the first metal layer M1, it is not necessary Other conductive members in contact with the variable resistance element 130 are additionally provided, thereby reducing manufacturing costs.

On the other hand, when the variable resistance element layer 130 'is etched, the insulating layer provided below the variable resistance element layer 130' is used as an etching stop layer. In the conventional semiconductor structure 100, due to the variable resistance element layer Below 130 'is a third insulating layer 150 having a lower dielectric constant and having holes, so its effect of blocking etching will be affected by the presence of holes. On the contrary, in the embodiment of the present invention, the resistance change element Below the layer 130 'is a first dielectric layer 120 having a high dielectric constant and having no holes, and therefore, can provide a better etch blocking effect. In addition, since the resistance change element 130 in this embodiment is located closer to the substrate 110, compared with the conventional semiconductor structure 100, the space reserved for preventing errors can be reduced, and the distance between the two elements can be reduced. Thereby, the density of the variable resistance element 130 is increased, and at the same time, the length of the conductive path can be shortened because the distance between the variable resistance element 130 and the substrate 110 is shortened to reduce the resistance value.

In another embodiment, the variable resistance element 130 may have a multilayer structure. As shown in FIG. 8, the variable resistance element 130 may further include a first electrode layer 134, an ion collection layer 136, and a second electrode layer 138, which is a variable resistance layer. 132 is disposed on the first electrode layer 134, the ion collection layer 136 is disposed on the resistance change layer 132, and the second electrode layer 138 is disposed on the ion collection layer 136, but the film layer included in the resistance change element 130 is not limited thereto . The ion collection layer 136 is used to receive ions diffused from the variable resistance layer 132 or transfer internal ions to the variable resistance layer 132 so that the variable resistance layer 132 changes the voltage when the variable resistance element 130 is supplied with voltage. The resistor, wherein the ion collection layer 136 may include at least one of a metal and a metal oxide material. Examples of the metal may include tantalum (Ta), titanium (Ti), or hafnium (Hf). Examples of the metal oxide material may include hafnium (Hf), magnesium. (Mg), aluminum (Al), niobium (Nb), lanthanum (La), zirconium (Zr), tantalum (Ta), and titanium (Ti) or a combination of metal oxides such as tantalum oxide (TaO _x ), oxide Titanium (TiO _x ), titanium oxynitride (TiO _x N _y ), hafnium oxide (HfO _x ). The first electrode layer 134 and the second electrode layer 138 can be used as the lower electrode and the upper electrode of the resistance change element 130, respectively, to avoid the materials used in the conductive connection element CP and the first metal layer M1 in the semiconductor structure 100 being unsuitable as The lower electrode and the upper electrode of the resistance change element 130. Examples of the first electrode layer 134 and the second electrode layer 138 in this embodiment may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride ( TaN), tungsten nitride (TaW), tungsten (W), aluminum (Al), platinum (Pt), or a combination thereof, such as titanium aluminum nitride (TiAlN), but the material is not limited thereto. In addition, in the manufacturing process, the resistance change element layer 130 'having a multilayer structure can still be formed comprehensively, and then the etching process is performed to etch the resistance change element layer 130' having a multilayer structure to form a resistance change having a multilayer structure. Element 130, but the manufacturing process is not limited to this. In a modified embodiment, layer 130 may be formed and etched layer by layer.

Please refer to FIG. 9, which illustrates a flowchart of a method for manufacturing a semiconductor structure according to an embodiment of the present invention. As shown in FIG. 9, a method for manufacturing a semiconductor structure according to an embodiment of the present invention includes the following steps.

Step ST1: forming a first insulating layer on a substrate.

Step ST2: A first connection hole is formed in the first insulating layer, and the first connection hole exposes a doped region on the surface of the substrate.

Step ST3: A conductive connection element is formed in the first connection hole, and the conductive connection element contacts the surface of the doped region.

Step ST4: forming a variable resistance element on the conductive connection element, and the variable resistance element and the conductive element Electrical connection elements are in contact.

Step ST5: forming a second insulating layer on the first insulating layer.

Step ST6: A second connection hole is formed in the second insulation layer, and the second connection hole exposes the conductive connection element or the resistance change element.

Step ST7: forming a first metal layer on the conductive connection element and the variable resistance element. The first metal layer includes a first metal pattern, at least a part of the first metal pattern is located in the second connection hole, and is electrically connected to the variable resistance element.

In addition, more metal layers, conductive layers, or insulating layers may be provided in the semiconductor structure 100 according to actual needs, such as the third insulating layer 150, the fourth insulating layer 160, the metal layer connecting element V, and the first insulating layer. The second metal layer M2, and the steps of the flowchart in FIG. 9 do not necessarily follow the above sequence, and other steps may also be between the above steps.

In summary, the resistance change element of the semiconductor structure of the present invention is disposed between the conductive connection element and the first metal layer, and directly contacts the conductive connection element. Therefore, it is not necessary to additionally provide another contact with the resistance change element and use it for electrical connection. The conductive members of other conductive layers can reduce the manufacturing cost, and simultaneously achieve the effects of increasing the density of the resistance change element and reducing the resistance value. On the other hand, since the first insulating layer with a higher dielectric constant and no holes is located under the variable resistance element, it can provide a better etch blocking effect in the process of manufacturing the variable resistance element.

The above description is only a preferred embodiment of the present invention, and all equivalent changes and modifications made in accordance with the scope of patent application of the present invention shall fall within the scope of the present invention.

Claims (9)

A semiconductor structure includes: a substrate having a doped region on a surface of the substrate; a first insulating layer disposed on the substrate; a contact plug disposed through the first insulating layer and contacting A surface of the doped region; a resistance change element disposed on the conductive connection element and in contact with the conductive connection element; a second insulating layer disposed on the first insulating layer; and a first metal layer disposed On the conductive connection element and the resistance change element, the first metal layer includes a first metal pattern, and the first metal pattern is electrically connected to the resistance change element. The semiconductor structure according to claim 1, further comprising a gate of a transistor, the gate is disposed on the substrate, and the doped region is a source-doped region or a drain-doped region of the transistor. A miscellaneous region, and the first insulating layer covers the gate of the transistor. The semiconductor structure according to claim 1, further comprising: a third insulating layer disposed on the first metal layer; a metal layer connecting element (via) disposed through the third insulating layer and communicating with the third insulating layer; The first metal pattern is electrically connected; and a second metal layer is disposed on the third insulating layer and the metal layer connecting element, the second metal layer includes a second metal pattern, the second metal pattern and the metal The layer connection elements are electrically connected. The semiconductor structure according to claim 1, wherein the resistance change element includes a resistance change layer. The semiconductor structure according to claim 4, wherein the resistance change element further comprises: a first electrode layer, the resistance change layer is disposed on the first electrode layer; an ion collection layer is provided on the resistance change layer; And a second electrode layer disposed on the ion collection layer. The semiconductor structure according to claim 5, wherein the ion collection layer includes at least one of a metal and a metal oxide material. The semiconductor structure according to claim 4, wherein the resistance change layer includes hafnium oxide (HfO _x ), tantalum oxide (TaO _x ), titanium oxide (TiO _x ), nickel oxide (NiO _x ), and niobium oxide (NbO _x ) , aluminum oxide (AlO _x), tungsten oxide (WO _x), zinc oxide (ZnO _x), cobalt oxide (CoO _x), lanthanum oxide (LaO _x), zirconium oxide (ZrO _x), wherein at least one or a combination thereof . A method for manufacturing a semiconductor structure includes: forming a first insulating layer on a substrate; forming a first connection hole in the first insulating layer, the first connection hole exposing a doped region on a surface of the substrate; A contact plug is formed in the first connection hole, and the conductive connection element contacts the surface of the doped region; a resistance change element is formed on the conductive connection element, and the resistance change element is in contact with the conductive connection element Forming a second insulating layer on the first insulating layer; forming a second connection hole in the second insulating layer, the second connection hole exposing the conductive connection element or the resistance change element; and forming a first A metal layer is formed on the conductive connection element and the resistance change element. The first metal layer includes a first metal pattern. At least a part of the first metal pattern is located in the second connection hole and is electrically connected to the resistance change element. . The method for manufacturing a semiconductor structure according to claim 8, further comprising: forming a third insulation layer on the first metal layer; forming a third connection hole in the third insulation layer, and the third connection hole is exposed A part of the first metal pattern of the first metal layer; forming a metal layer connection element (via) in the third connection hole, and the metal layer connection element is electrically connected to the first metal pattern; and forming a second A metal layer is on the third insulating layer and the metal layer connection element, and the second metal layer includes a second metal pattern, and the second metal pattern is electrically connected to the metal layer connection element.