TW202112043A - Step-up power converter that responds to variation of input voltage quickly and electronic device using same comprising an energy transfer unit, a ramp signal generation unit, an error-mean circuit, and a PWM signal generation unit - Google Patents

Abstract

A step-up power converter that responds to variation of input voltage quickly is disclosed, comprising an energy transfer unit that allows an input voltage to periodically charge an inductor according to the control of a PWM signal, and allows the inductor to discharge to an output terminal to generate an output voltage, the inductor having an equivalent inductance and an inductor parasitic resistance connected in series thereto; a ramp signal generation unit that modulates a ramp signal according to the cross voltage of the inductor; an error-mean circuit that generates an error-mean voltage according to a mean value of the difference between a feedback voltage of the output voltage and a reference voltage; and a PWM signal generation unit that determines a starting point of the PWM signal according to a result of comparison between the ramp signal and the error-mean voltage.

Description

Boost power converter capable of quickly responding to changes in input voltage and electronic equipment using the same

The invention relates to a boost power converter, in particular to a boost power converter capable of quickly responding to changes in input voltage.

Please refer to FIG. 1, which shows a circuit diagram of a conventional boost power converter. As shown in Figure 1, the boost power converter has an input capacitor 11, an inductor 12a and an inductor parasitic resistance 12b, an NMOS transistor 13a, a PMOS transistor 13b, a first voltage divider resistor 14a, and a second Voltage dividing resistor 14b, an output capacitor 15, a ramp signal generating unit 16, a transconductance amplifier 17, a filter resistor 18a and a filter capacitor 18b, a comparator 19, an oscillator 20, a flip-flop 21 and a The PWM control driving unit 22.

The input capacitor 11 is used to provide a filtering function at the input end.

The inductance 12a is connected in series with the inductance parasitic resistance 12b to represent an actual inductance.

The NMOS transistor 13a is used for turning on under the control of the PWM control driving unit 22 to make an input voltage V _IN charge the inductor 12a during the charging (ON) period of a PWM cycle.

The PMOS transistor 13b is used for turning on under the control of the PWM control driving unit 22 to discharge the inductor 12a to the output terminal during the discharge (OFF) period of a PWM cycle.

The first voltage dividing resistor 14a and the second voltage dividing resistor 14b are used to form a voltage dividing circuit to generate a feedback voltage V _{FB according to a ratio of the output voltage V OUT} established on the output capacitor 15.

The ramp signal generating unit 16 is used to generate a ramp signal V _RAMP .

The transconductance amplifier 17, the filter resistor 18a, and the filter capacitor 18b are used to form an error average circuit to _{generate an error average voltage V EA} according to the average value of the difference between the _{feedback voltage V FB} and a reference voltage V _REF .

The comparator 19 is used to generate a charging start signal CHGON according to the comparison result of the _{ramp signal V RAMP} and the error average voltage V _EA.

The oscillator 20 is used to generate a clock signal CLK.

The flip-flop 21 is used to generate a PWM signal. The start point of the charging period of the PWM signal is determined by the charging start signal CHGON, and the end point of the charging period is determined by the clock signal CLK.

The PWM control driving unit 22 is used to generate a first switch signal SW1 to control the NMOS transistor 13a and a second switch signal SW2 to control the PMOS transistor 13b according to the PWM signal.

In steady state, the error average voltage V _EA will approach the DC level to determine a duty cycle of the PWM signal, so that the output voltage V _OUT = (1+R1/R2)V _REF , where R1 is the first point The resistance value of the piezoresistor 14a, R2 is the resistance value of the second voltage divider 14b.

However, when the input voltage V _IN changes and jumps and the output current does not change abruptly, the feedback path of the conventional circuit needs to pass through a voltage divider circuit and an error averaging circuit, and the capacitance value of the filter capacitor 18b of the error averaging circuit The transconductance gain of the transconductance amplifier 17 is relatively large and the transconductance gain of the transconductance amplifier 17 is limited. Therefore, the conventional circuit must wait a period of response time (on the order of tens of microseconds) to _{change the error average voltage V EA} to a new corresponding level. The PWM signal generates a new duty cycle, thereby _{pulling the output voltage V OUT} back to a predetermined level, and the output voltage V _OUT may have changed a lot (overshoot or undershoot) within the response time , And often exceed the range required by the specifications (SPEC). The whole process can be simply described as:

V _IN →V _OUT →V _FB →V _EA →CHGON→PWM→V _OUT

In order to solve the above-mentioned problems, a novel boost power converter architecture is urgently needed in the art.

An object of the present invention is to provide a boost power converter that can quickly respond to changes in input voltage and reduce the amount of change in output voltage.

Another object of the present invention is to provide a boost power converter, which can quickly change the duty cycle of a PWM signal by adjusting the slope of a ramp signal by the cross-voltage of an inductor, so that an output voltage can respond quickly Changes in input voltage.

Another object of the present invention is to provide a boost power converter, which can automatically measure the parasitic resistance of an inductor at the initial stage of power-on to determine the resistance in a resistance-capacitance compensation circuit.

In order to achieve the aforementioned purpose, a boost power converter that can quickly respond to changes in input voltage is proposed, which has:

An inductor, having an equivalent inductance and a parasitic resistance of an inductance in series with it;

An NMOS transistor, which is turned on under the control of a first switch signal to charge the inductor with an input voltage during the charging period of a PWM cycle;

A PMOS transistor for turning on under the control of a second switch signal to discharge the inductor to an output terminal during the discharge period of the PWM period;

A voltage divider circuit for generating a feedback voltage according to a ratio of an output voltage established on an output capacitor;

A ramp signal generating unit for modulating a ramp signal according to a cross voltage of the inductor;

An error average circuit for generating an error average voltage according to the average value of the difference between the feedback voltage and a reference voltage;

A comparator for generating a charging start signal according to the comparison result of the ramp signal and the error average voltage V _EA;

An oscillator is used to generate a clock signal;

A flip-flop is used to generate a PWM signal, wherein the starting point of the charging period of the PWM signal is determined by the charging start signal, and the end point of the charging period is determined by the clock signal ；

A PWM control driving unit is used to generate the first switch signal to control the NMOS transistor and the second switch signal to control the PMOS transistor according to the PWM signal.

In one embodiment, the ramp signal generating unit has a certain current source, a switch, a first capacitor, a second capacitor, a transconductance amplifier, a first resistor, and a second resistor; it is characterized by:

The constant current source is coupled between the input voltage and an upper electrode of the first capacitor to provide a certain current, the first resistor is coupled between a lower electrode of the first capacitor and a reference ground, the The channel of the switch is connected in parallel with the first capacitor, and the control terminal of the switch is coupled with a reset signal;

The second capacitor and the second resistor form a series circuit, and the series circuit is connected in parallel with the inductance. The second capacitor and the second resistor are based on a formula: L/R _DCR =R _AUX ∙ C _AUX determines its value, where L is the equivalent inductance of the inductor, R _{DCR is} the resistance value of the parasitic resistance of the inductor, R _{AUX is} the resistance value of the second resistor, and C _{AUX is} the capacitance value of the second capacitor;

The input port of the transconductance amplifier is coupled to the second capacitor, and the output terminal is coupled to the bottom electrode of the first capacitor;

During operation, the reset signal periodically resets the cross voltage of the first capacitor to zero so that the ramp signal is periodically generated.

In one embodiment, the ramp signal generating unit has a certain current source, a first switch, a first capacitor, a second capacitor, a transconductance amplifier, a first resistor, a control module, and a plurality of second capacitors. The switch, a plurality of compensation resistors, a third switch and a current source for measurement are characterized by:

The constant current source is coupled between the input voltage and an upper electrode of the first capacitor to provide a certain current, the first resistor is coupled between a lower electrode of the first capacitor and a reference ground, the The channel of the first switch is connected in parallel with the first capacitor, and the control terminal of the first switch is coupled with a reset signal;

The configuration of the second capacitor and one of the plurality of compensation resistors forms a series circuit, and the series circuit is connected in parallel with the inductor, wherein the equivalent resistance of the second capacitor and the configuration is based on a formula: L/R _DCR = R _AUX ∙C _AUX determines its value, where L is the equivalent inductance of the inductor, R _{DCR is} the resistance value of the parasitic resistance of the inductor, R _AUX is the resistance value of the equivalent resistance, and C _AUX is The capacitance value of the second capacitor, and the configuration is formed as follows: when power is just turned on, the control module outputs a plurality of switch signals to power on the measurement current source and make the plurality of compensation resistors Short circuit, the cross voltage of the parasitic resistance of the inductor is converted into a current through the transconductance amplifier, and then the current generates a cross voltage at the first resistance; the control module calculates the resistance value of the parasitic resistance of the inductor according to the cross voltage And the control module determines a number of the plurality of switching signals according to the resistance value R _DCR so that the plurality of compensation resistors form the configuration and disconnect the measurement current source; and

The input port of the transconductance amplifier is coupled to the second capacitor, and the output terminal is coupled to the bottom electrode of the first capacitor;

During operation, the reset signal periodically resets the cross voltage of the first capacitor to zero so that the ramp signal is periodically generated.

To achieve the above objective, the present invention further provides a boost power converter capable of quickly responding to changes in input voltage, which has:

An energy transfer unit for periodically charging an inductor with an input voltage and discharging the inductor to an output terminal to generate an output voltage according to the control of a PWM signal. The inductor has an equivalent inductance and is connected in series with it One of inductance parasitic resistance;

A ramp signal generating unit for modulating a ramp signal according to a cross voltage of the inductor;

An error average circuit for generating an error average voltage according to the average value of the difference between a feedback voltage of the output voltage and a reference voltage; and

A PWM signal generating unit is used to determine the starting point of the PWM signal according to the comparison result of the ramp signal and the error average voltage.

In order to achieve the above objective, the present invention further provides an electronic device having a boost power converter and an information processing circuit, wherein the boost power converter is used to generate an output voltage according to an input voltage for the information The processing circuit is powered, and the boost power converter has:

An inductor, having an equivalent inductance and a parasitic resistance of an inductance in series with it;

An NMOS transistor, which is turned on under the control of a first switch signal to charge the inductor with the input voltage during the charging period of a PWM cycle;

A PMOS transistor for turning on under the control of a second switch signal to discharge the inductor to an output terminal during the discharge period of the PWM period;

A voltage divider circuit for generating a feedback voltage according to a ratio of the output voltage established on an output capacitor;

A ramp signal generating unit for modulating a ramp signal according to a cross voltage of the inductor;

An error average circuit for generating an error average voltage according to the average value of the difference between the feedback voltage and a reference voltage;

A comparator for generating a charging start signal according to the comparison result of the ramp signal and the error average voltage V _EA;

An oscillator is used to generate a clock signal;

A flip-flop is used to generate a PWM signal, wherein the starting point of the charging period of the PWM signal is determined by the charging start signal, and the end point of the charging period is determined by the clock signal ；

A PWM control driving unit is used to generate the first switch signal to control the NMOS transistor and the second switch signal to control the PMOS transistor according to the PWM signal.

In one embodiment, the ramp signal generating unit has a certain current source, a switch, a first capacitor, a second capacitor, a transconductance amplifier, a first resistor, and a second resistor; it is characterized by:

The constant current source is coupled between the input voltage and an upper electrode of the first capacitor to provide a certain current, the first resistor is coupled between a lower electrode of the first capacitor and a reference ground, the The channel of the switch is connected in parallel with the first capacitor, and the control terminal of the switch is coupled with a reset signal;

The second capacitor and the second resistor form a series circuit, and the series circuit is connected in parallel with the inductance. The second capacitor and the second resistor are based on a formula: L/R _DCR =R _AUX ∙ C _AUX determines its value, where L is the equivalent inductance of the inductor, R _{DCR is} the resistance value of the parasitic resistance of the inductor, R _{AUX is} the resistance value of the second resistor, and C _{AUX is} the capacitance value of the second capacitor;

The input port of the transconductance amplifier is coupled to the second capacitor, and the output terminal is coupled to the bottom electrode of the first capacitor;

During operation, the reset signal periodically resets the cross voltage of the first capacitor to zero so that the ramp signal is periodically generated.

In one embodiment, the ramp signal generating unit has a certain current source, a first switch, a first capacitor, a second capacitor, a transconductance amplifier, a first resistor, a control module, and a plurality of second capacitors. The switch, a plurality of compensation resistors, a third switch and a current source for measurement are characterized by:

The constant current source is coupled between the input voltage and an upper electrode of the first capacitor to provide a certain current, the first resistor is coupled between a lower electrode of the first capacitor and a reference ground, the The channel of the first switch is connected in parallel with the first capacitor, and the control terminal of the first switch is coupled with a reset signal;

The configuration of the second capacitor and one of the plurality of compensation resistors forms a series circuit, and the series circuit is connected in parallel with the inductor, wherein the equivalent resistance of the second capacitor and the configuration is based on a formula: L/R _DCR = R _AUX ∙C _AUX determines its value, where L is the equivalent inductance of the inductor, R _{DCR is} the resistance value of the parasitic resistance of the inductor, R _AUX is the resistance value of the equivalent resistance, and C _AUX is The capacitance value of the second capacitor, and the configuration is formed as follows: when power is just turned on, the control module outputs a plurality of switch signals to power on the measurement current source and make the plurality of compensation resistors Short circuit, the cross voltage of the parasitic resistance of the inductor is converted into a current through the transconductance amplifier, and then the current generates a cross voltage at the first resistance; the control module calculates the resistance value of the parasitic resistance of the inductor according to the cross voltage And the control module determines a number of the plurality of switching signals according to the resistance value R _DCR so that the plurality of compensation resistors form the configuration and disconnect the measurement current source; and

The input port of the transconductance amplifier is coupled to the second capacitor, and the output terminal is coupled to the bottom electrode of the first capacitor;

During operation, the reset signal periodically resets the cross voltage of the first capacitor to zero so that the ramp signal is periodically generated.

In order to achieve the above objective, the present invention further provides an electronic device having a boost power converter and an information processing circuit, wherein the boost power converter is used to generate an output voltage according to an input voltage for the information The processing circuit is powered, and the boost power converter has:

An energy transfer unit for periodically charging an inductor with an input voltage and discharging the inductor to an output terminal to generate an output voltage according to the control of a PWM signal. The inductor has an equivalent inductance and is connected in series with it One of inductance parasitic resistance;

A ramp signal generating unit for modulating a ramp signal according to a cross voltage of the inductor;

An error average circuit for generating an error average voltage according to the average value of the difference between a feedback voltage of the output voltage and a reference voltage; and

A PWM signal generating unit is used to determine the starting point of the PWM signal according to the comparison result of the ramp signal and the error average voltage.

In possible embodiments, the electronic device may be a display, a smart phone or a portable computer.

Please refer to FIG. 2, which shows a circuit diagram of an embodiment of a boost power converter capable of quickly responding to changes in input voltage of the present invention. As shown in FIG. 2, a boost power converter 100 has an input capacitor 101, an inductor 102a, and an inductor parasitic resistance 102b, an NMOS transistor 103a, a PMOS transistor 103b, a first voltage divider 104a, and a The second voltage dividing resistor 104b, an output capacitor 105, a ramp signal generating unit 106, a transconductance amplifier 107, a filter resistor 108a and a filter capacitor 108b, a comparator 109, an oscillator 110, and a flip-flop 111 And a PWM control driving unit 112.

The input capacitor 101 is used to provide a filtering function at the input end.

The inductor 102a is connected in series with the inductor parasitic resistance 102b to represent an actual inductor.

The NMOS transistor 103a is used to turn on under the control of the PWM control driving unit 112 to make an input voltage V _IN charge the inductor 102a during the charging (ON) period of a PWM cycle.

The PMOS transistor 103b is used for turning on under the control of the PWM control driving unit 112 to discharge the inductor 102a to the output terminal during the discharge (OFF) period of a PWM cycle.

The first voltage dividing resistor 104a and the second voltage dividing resistor 104b are used to form a voltage dividing circuit to generate a feedback voltage V _{FB according to a ratio of the output voltage V OUT} established on the output capacitor 105.

The ramp signal generating unit 106 is used to generate a ramp signal V _RAMP , which includes a certain current source 106a, a switch 106b, a first capacitor 106c, a second capacitor 106d, a transconductance amplifier 106e, a first resistor 106f, and A second resistor 106g.

The constant current source 106a is coupled between the input voltage V _IN and an upper electrode of the first capacitor 106c to provide a certain current I _{C. The} first resistor 106f is coupled between a lower electrode of the first capacitor 106c and a reference ground. Meanwhile, the channel of the switch 106b is connected in parallel with the first capacitor 106c, and the control terminal of the switch 106b is coupled to a reset signal RESET.

The second capacitor 106d and the second resistor 106g form a series circuit, and the series circuit is connected in parallel with the actual inductor (having the inductor 102a and the inductor parasitic resistance 102b in series with it), wherein the second capacitor 106d and the second resistor 106g is based on a formula: L/R _DCR = R _AUX ∙C _AUX determines its value, where L is the inductance value of the inductor 102a, R _DCR is the resistance value of the inductor parasitic resistance 102b, and R _AUX is the resistance value of the second resistor 106g , And C _AUX are the capacitance values of the second capacitor 106d.

The input port of the transconductance amplifier 106e is coupled to the second capacitor 106d, and the output terminal thereof is coupled to the lower electrode of the first capacitor 106c to provide an input voltage sensing current I _SENSE . During operation, the reset signal RESET periodically resets the voltage across the first capacitor 106c to zero so that the ramp signal V _RAMP periodically generates an upward ramp voltage.

The transconductance amplifier 107, the filter resistor 108a and the filter capacitor 108b are used to form an error average circuit to _{generate an error average voltage V EA} according to the average value of the difference between the _{feedback voltage V FB} and a reference voltage V _REF .

The comparator 109 is used to generate a charging start signal CHGON according to the comparison result of the _{ramp signal V RAMP} and the error average voltage V _EA.

The oscillator 110 is used to generate a clock signal CLK.

The flip-flop 111 is used to generate a PWM signal, wherein the start point of the charging period of the PWM signal is determined by the charging start signal CHGON, and the end point of the charging period is determined by the clock signal CLK.

The PWM control driving unit 112 is used to generate a first switch signal SW1 to control the NMOS transistor 103a and a second switch signal SW2 to control the PMOS transistor 103b according to the PWM signal.

In steady state, the error average voltage V _EA will approach the DC level to determine a duty cycle of the PWM signal, so that the output voltage V _OUT = (1+R1/R2)V _REF , where R1 is the first point The resistance value of the piezoresistor 104a, R2 is the resistance value of the second voltage divider 104b.

The feature of the present invention is that during the discharge (OFF) period of the PWM cycle, the ramp _{voltage of the ramp signal V RAMP} can be expressed as (I _C +I _SENSE ) ∙R _RAMP + I _C ∙t/C _RAMP , where R _RAMP is For the resistance value of the first resistor 106f, C _RAMP is the capacitance value of the first capacitor 106c, and I _C /(R _RAMP ∙ C _RAMP )>-d I _SENSE /dt.

Accordingly, if _{there is any change in V IN} , the cross-voltage of the second capacitor 106d and the output current I _{SENSE of the} transconductance amplifier 106e will follow the changes in order, which will be immediately reflected on V _RAMP to quickly adjust the PWM duty cycle (or Duty cycle), so that the output voltage V _OUT can quickly respond to the change of _{V IN.} The whole process can be simply described as:

V _IN →V _RAMP →CHGON→PWM→V _OUT .

Please refer to FIG. 3, which shows a circuit diagram of another embodiment of a boost power converter capable of quickly responding to changes in input voltage of the present invention. As shown in FIG. 3, a boost power converter 100 has an input capacitor 101, an inductor 102a, and an inductor parasitic resistance 102b, an NMOS transistor 103a, a PMOS transistor 103b, a first voltage divider 104a, and a The second voltage dividing resistor 104b, an output capacitor 105, a ramp signal generating unit 106, a transconductance amplifier 107, a filter resistor 108a and a filter capacitor 108b, a comparator 109, an oscillator 110, and a flip-flop 111 And a PWM control driving unit 112.

The input capacitor 101 is used to provide a filtering function at the input end.

The inductor 102a is connected in series with the inductor parasitic resistance 102b to represent an actual inductor.

The NMOS transistor 103a is used to turn on under the control of the PWM control driving unit 112 to make an input voltage V _IN charge the inductor 102a during the charging (ON) period of a PWM cycle.

The PMOS transistor 103b is used for turning on under the control of the PWM control driving unit 112 to discharge the inductor 102a to the output terminal during the discharge (OFF) period of a PWM cycle.

The first voltage dividing resistor 104a and the second voltage dividing resistor 104b are used to form a voltage dividing circuit to generate a feedback voltage V _{FB according to a ratio of the output voltage V OUT} established on the output capacitor 105.

The ramp signal generating unit 106 is used to generate a ramp signal V _RAMP , which includes a certain current source 106a, a switch 106b, a first capacitor 106c, a second capacitor 106d, a transconductance amplifier 106e, a first resistor 106f, A control module 106g1, n switches 106g2, n compensation resistors 106g3, a switch 106g4, and a measurement current source 106g5.

The constant current source 106a is coupled between the input voltage V _IN and an upper electrode of the first capacitor 106c to provide a certain current I _{C. The} first resistor 106f is coupled between a lower electrode of the first capacitor 106c and a reference ground. Meanwhile, the channel of the switch 106b is connected in parallel with the first capacitor 106c, and the control terminal of the switch 106b is coupled to a reset signal RESET.

The second capacitor 106d and one of the n compensation resistors 106g3 are configured to form a series circuit, and the series circuit is connected in parallel with the actual inductor (having an inductor 102a and an inductor parasitic resistance 102b connected in series with it), wherein the second capacitor The equivalent resistance of 106d and the configuration is based on a formula: L/R _DCR = R _AUX ∙C _AUX determines its value, where L is the inductance value of the inductor 102a, R _DCR is the resistance value of the inductor parasitic resistance 102b, R _AUX Is the resistance value of the equivalent resistance, and C _AUX is the capacitance value of the second capacitor 106d. The configuration method is as follows: (1) When the boost power converter 100 is just powered on, the control module 106g1 outputs switching signals S ₀ , S ₁ , S ₂ … S _n to power up the measuring current source 106g5 And short-circuit the n compensation resistors 106g3 to convert the cross voltage of the inductance parasitic resistance 102b into a current through the transconductance amplifier 106e, and then the current will generate a cross voltage in the first resistor 106f; (2) the control module 106g1 follows this _{The resistance value R DCR} of the inductance parasitic resistance 102b is calculated across the voltage; (3) Then, the control module 106g1 can determine one of the switching signals S ₁ , S ₂ … S _{n according to the resistance value R DCR} to make n compensation resistors 106g3 forms the configuration, and makes the switch signal S ₀ output a disconnection level to disconnect the measurement current source 106g5.

The input port of the transconductance amplifier 106e is coupled to the second capacitor 106d, and the output terminal thereof is coupled to the lower electrode of the first capacitor 106c to provide an input voltage sensing current I _SENSE . During operation, the reset signal RESET periodically resets the voltage across the first capacitor 106c to zero so that the ramp signal V _RAMP periodically generates an upward ramp voltage.

The transconductance amplifier 107, the filter resistor 108a and the filter capacitor 108b are used to form an error average circuit to _{generate an error average voltage V EA} according to the average value of the difference between the _{feedback voltage V FB} and a reference voltage V _REF .

The comparator 109 is used to generate a charging start signal CHGON according to the comparison result of the _{ramp signal V RAMP} and the error average voltage V _EA.

The oscillator 110 is used to generate a clock signal CLK.

The flip-flop 111 is used to generate a PWM signal, wherein the start point of the charging period of the PWM signal is determined by the charging start signal CHGON, and the end point of the charging period is determined by the clock signal CLK.

The PWM control driving unit 112 is used to generate a first switch signal SW1 to control the NMOS transistor 103a and a second switch signal SW2 to control the PMOS transistor 103b according to the PWM signal.

In steady state, the error average voltage V _EA will approach the DC level to determine a duty cycle of the PWM signal, so that the output voltage V _OUT = (1+R1/R2)V _REF , where R1 is the first point The resistance value of the piezoresistor 104a, R2 is the resistance value of the second voltage divider 104b. In other words, the boost power converter capable of quickly responding to changes in input voltage of the present invention has: an energy transfer unit for periodically charging an inductor with an input voltage and causing the inductor to be charged with an input voltage under the control of a PWM signal Discharge an output terminal to generate an output voltage. The inductor has an equivalent inductance and a parasitic resistance of an inductor in series with it; a ramp signal generating unit for modulating a ramp signal according to a cross-voltage of the inductor; an error An averaging circuit for generating an error average voltage according to the average value of the difference between a feedback voltage of the output voltage and a reference voltage; and a PWM signal generating unit for generating an error average voltage according to the comparison result of the ramp signal and the error average voltage Determine the starting point of the PWM signal.

Based on the above description, the present invention further provides an electronic device. Please refer to FIG. 4, which shows a block diagram of an embodiment of the electronic device of the present invention. As shown in FIG. 4, an electronic device 200 has a boost power converter 210 that can quickly respond to changes in input voltage and an information processing circuit 220. The boost power converter 210 is composed of the aforementioned boost power converter 100. It is implemented to generate an output voltage V _OUT according to an input voltage V _IN to supply power to the information processing circuit 220.

In addition, in possible embodiments, the electronic device 200 may be a display, a smart phone or a portable computer.

According to the above description, the present invention can provide the following advantages:

1. The boost power converter of the present invention can quickly respond to changes in input voltage and reduce the amount of change in output voltage.

2. The boost power converter of the present invention can quickly change the duty cycle of a PWM signal by adjusting the slope of a ramp signal through the cross-voltage of an inductor, so that an output voltage can quickly respond to changes in the input voltage.

3. The boost power converter of the present invention can automatically measure the parasitic resistance value of an inductor at the initial stage of power-on to determine the resistance value in a resistance-capacitance compensation circuit.

The disclosure of the present invention is one of the preferred embodiments. Any partial change or modification that is derived from the technical idea of the present invention and can be easily deduced by those skilled in the art does not deviate from the scope of the patent right of the present invention.

In summary, regardless of the purpose, means and effects of this case, it is shown that it is very different from the conventional technology, and its first invention is suitable for practicality, and it does meet the patent requirements of the invention. I implore the examiner to observe it and grant the patent as soon as possible. Society is for the best prayer.

11: Input capacitance 12a: Inductance 12b: Inductor parasitic resistance 13a: NMOS transistor 13b: PMOS transistor 14a: The first voltage divider resistor 14b: Second voltage divider resistor 15: output capacitor 16: Ramp signal generation unit 17: Transduction amplifier 18a: filter resistance 18b: filter capacitor 19: Comparator 20: Oscillator 21: Flip-flop 22: PWM control drive unit 100: Boost power converter 101: Input capacitance 102a: Inductance 102b: Inductor parasitic resistance 103a: NMOS transistor 103b: PMOS transistor 104a: The first voltage divider resistor 104b: second voltage divider resistor 105: output capacitor 106: Ramp signal generation unit 106a: constant current source 106b: switch 106c: first capacitor 106d: second capacitor 106e: transconductance amplifier 106f: first resistor 106g: second resistor 106g1: control module 106g2: switch 106g3: Compensation resistance 106g4: switch 106g5: current source for measurement 107: Transconductance amplifier 108a: filter resistor 108b: filter capacitor 109: Comparator 110: Oscillator 111: Flip-flop 112: PWM control drive unit 200: electronic equipment 210: Boost power converter that can quickly react to changes in input voltage 220: Information Processing Circuit

Figure 1 shows a circuit diagram of a conventional boost power converter. 2 is a circuit diagram of an embodiment of the boost power converter capable of quickly responding to changes in input voltage of the present invention. 3 is a circuit diagram of another embodiment of the boost power converter capable of quickly responding to input voltage changes according to the present invention. Fig. 4 is a block diagram of an embodiment of the electronic device of the present invention.

100: Boost power converter

101: Input capacitance

102a: Inductance

102b: Inductor parasitic resistance

103a: NMOS transistor

103b: PMOS transistor

104a: The first voltage divider resistor

104b: second voltage divider resistor

105: output capacitor

106: Ramp signal generation unit

106a: constant current source

106b: switch

106c: first capacitor

106d: second capacitor

106e: transconductance amplifier

106f: first resistor

106g: second resistor

107: Transconductance amplifier

108a: filter resistor

108b: filter capacitor

109: Comparator

110: Oscillator

111: Flip-flop

112: PWM control drive unit

Claims (13)

A boost power converter capable of quickly responding to changes in input voltage, which has: An inductor, having an equivalent inductance and a parasitic resistance of an inductance in series with it; An NMOS transistor, which is turned on under the control of a first switch signal to charge the inductor with an input voltage during the charging period of a PWM cycle; A PMOS transistor for turning on under the control of a second switch signal to discharge the inductor to an output terminal during the discharge period of the PWM period; A voltage divider circuit for generating a feedback voltage according to a ratio of an output voltage established on an output capacitor; A ramp signal generating unit for modulating a ramp signal according to a cross voltage of the inductor; An error average circuit for generating an error average voltage according to the average value of the difference between the feedback voltage and a reference voltage; A comparator for generating a charging start signal according to the comparison result of the ramp signal and the error average voltage; An oscillator is used to generate a clock signal; A flip-flop is used to generate a PWM signal, wherein the starting point of the charging period of the PWM signal is determined by the charging start signal, and the end point of the charging period is determined by the clock signal ； A PWM control driving unit is used to generate the first switch signal to control the NMOS transistor and the second switch signal to control the PMOS transistor according to the PWM signal. As described in item 1 of the scope of patent application, the boost power converter capable of quickly responding to input voltage changes, wherein the ramp signal generating unit has a certain current source, a switch, a first capacitor, a second capacitor, and a transconductor Amplifier, a first resistor and a second resistor; characterized by: The constant current source is coupled between the input voltage and an upper electrode of the first capacitor to provide a certain current, the first resistor is coupled between a lower electrode of the first capacitor and a reference ground, the The channel of the switch is connected in parallel with the first capacitor, and the control terminal of the switch is coupled with a reset signal; The second capacitor and the second resistor form a series circuit, and the series circuit is connected in parallel with the inductor; The input port of the transconductance amplifier is coupled to the second capacitor, and the output terminal is coupled to the bottom electrode of the first capacitor; During operation, the reset signal periodically resets the cross voltage of the first capacitor to zero so that the ramp signal is periodically generated. As described in item 2 of the scope of patent application, the boost power converter capable of quickly responding to changes in input voltage, wherein the second capacitor and the second resistor are determined by a formula: L/R _DCR = R _AUX ∙C _AUX Its value, where L is the equivalent inductance of the inductor, R _{DCR is} the resistance value of the parasitic resistance of the inductor, R _{AUX is} the resistance value of the second resistor, and C _{AUX is} the capacitance value of the second capacitor. As described in item 1 of the scope of patent application, the boost power converter capable of quickly responding to changes in input voltage, wherein the ramp signal generating unit has a certain current source, a first switch, a first capacitor, a second capacitor, and a The transconductance amplifier, a first resistor, a control module, a plurality of second switches, a plurality of compensation resistors, a third switch and a current source for measurement are characterized by: The constant current source is coupled between the input voltage and an upper electrode of the first capacitor to provide a certain current, the first resistor is coupled between a lower electrode of the first capacitor and a reference ground, the The channel of the first switch is connected in parallel with the first capacitor, and the control terminal of the first switch is coupled with a reset signal; The configuration of the second capacitor and one of the plurality of compensation resistors forms a series circuit, the series circuit is connected in parallel with the inductance, and the configuration is formed as follows: when power is just turned on, the control module outputs A plurality of switching signals are used to power up the measurement current source and short-circuit the plurality of compensation resistors, and convert the cross voltage of the parasitic resistance of the inductor into a current through the transconductance amplifier, and then the current will flow through the first resistor Generate a cross voltage; the control module calculates the resistance value of the parasitic resistance of the inductor according to the cross voltage; and the control module determines a number of the plurality of switching signals according to the resistance value to make the plurality of compensation resistors Form the configuration and disconnect the current source for measurement; and The input port of the transconductance amplifier is coupled to the second capacitor, and the output terminal is coupled to the bottom electrode of the first capacitor; During operation, the reset signal periodically resets the cross voltage of the first capacitor to zero so that the ramp signal is periodically generated. As described in item 4 of the scope of patent application, the boost power converter capable of quickly responding to changes in input voltage, wherein the equivalent resistance of the second capacitor and the configuration is based on a formula: L/R _DCR = R _AUX ∙ C _AUX determines its value, where L is the equivalent inductance of the inductor, R _{DCR is} the resistance value of the parasitic resistance of the inductor, R _AUX is the resistance value of the equivalent resistance, and C _{AUX is} the capacitance value of the second capacitor. A boost power converter capable of quickly responding to changes in input voltage, which has: An energy transfer unit for periodically charging an inductor with an input voltage and discharging the inductor to an output terminal to generate an output voltage according to the control of a PWM signal. The inductor has an equivalent inductance and is connected in series with it One of inductance parasitic resistance; A ramp signal generating unit for modulating a ramp signal according to a cross voltage of the inductor; An error average circuit for generating an error average voltage according to the average value of the difference between a feedback voltage of the output voltage and a reference voltage; and A PWM signal generating unit is used to determine the starting point of the PWM signal according to the comparison result of the ramp signal and the error average voltage. An electronic device having a boost power converter and an information processing circuit, wherein the boost power converter is used to generate an output voltage according to an input voltage to power the information processing circuit, and the boost power conversion The device has: An inductor, having an equivalent inductance and a parasitic resistance of an inductance in series with it; An NMOS transistor, which is turned on under the control of a first switch signal to charge the inductor with the input voltage during the charging period of a PWM cycle; A PMOS transistor for turning on under the control of a second switch signal to discharge the inductor to an output terminal during the discharge period of the PWM period; A voltage divider circuit for generating a feedback voltage according to a ratio of the output voltage established on an output capacitor; A ramp signal generating unit for modulating a ramp signal according to a cross voltage of the inductor; An error average circuit for generating an error average voltage according to the average value of the difference between the feedback voltage and a reference voltage; A comparator for generating a charging start signal according to the comparison result of the ramp signal and the error average voltage; An oscillator is used to generate a clock signal; A flip-flop is used to generate a PWM signal, wherein the starting point of the charging period of the PWM signal is determined by the charging start signal, and the end point of the charging period is determined by the clock signal ； A PWM control driving unit is used to generate the first switch signal to control the NMOS transistor and the second switch signal to control the PMOS transistor according to the PWM signal. For the electronic device described in item 7 of the scope of patent application, the ramp signal generating unit has a certain current source, a switch, a first capacitor, a second capacitor, a transconductance amplifier, a first resistor and a second Resistance; is characterized by: The constant current source is coupled between the input voltage and an upper electrode of the first capacitor to provide a certain current, the first resistor is coupled between a lower electrode of the first capacitor and a reference ground, the The channel of the switch is connected in parallel with the first capacitor, and the control terminal of the switch is coupled with a reset signal; The second capacitor and the second resistor form a series circuit, and the series circuit is connected in parallel with the inductor; The input port of the transconductance amplifier is coupled to the second capacitor, and the output terminal is coupled to the bottom electrode of the first capacitor; During operation, the reset signal periodically resets the cross voltage of the first capacitor to zero so that the ramp signal is periodically generated. For example, the electronic device described in item 8 of the scope of patent application, wherein the second capacitor and the second resistance are determined by a formula: L/R _DCR = R _AUX ∙C _AUX , where L is the equivalent of the inductance Effective inductance, R _{DCR is} the resistance value of the parasitic resistance of the inductance, R _{AUX is} the resistance value of the second resistor, and C _{AUX is} the capacitance value of the second capacitor. For the electronic device described in item 7 of the scope of patent application, the ramp signal generating unit has a certain current source, a first switch, a first capacitor, a second capacitor, a transconductance amplifier, a first resistor, and a The control module, a plurality of second switches, a plurality of compensation resistors, a third switch and a measuring current source are characterized in that: the constant current source is coupled to one of the input voltage and the first capacitor A certain current is provided between the electrodes. The first resistor is coupled between a lower electrode of the first capacitor and a reference ground. The channel of the first switch is connected in parallel with the first capacitor. The control terminal is coupled to a reset signal; the configuration of the second capacitor and one of the plurality of compensation resistors forms a series circuit, the series circuit is connected in parallel with the inductor, and the configuration is formed as follows: When the power is just turned on, the control module outputs a plurality of switch signals to power on the measurement current source and short-circuit the plurality of compensation resistors, and convert the cross voltage of the parasitic resistance of the inductance through the transconductance amplifier into Current, and then the current generates a cross voltage across the first resistor; the control module calculates the resistance value of the parasitic resistance of the inductor according to the cross voltage; and the control module determines the plurality of _{resistors according to the resistance value R DCR} A number of the switch signal is used to enable the plurality of compensation resistors to form the configuration and disconnect the measurement current source; and the input port of the transconductance amplifier is coupled to the second capacitor, and the output terminal is Is coupled to the bottom electrode of the first capacitor; during operation, the reset signal periodically resets the cross voltage of the first capacitor to zero so that the ramp signal is periodically generated. For the electronic device described in item 10 of the scope of patent application, the equivalent resistance of the second capacitor and the configuration is determined by a formula: L/R _DCR = R _AUX ∙C _AUX , where L is the The equivalent inductance of the inductor, R _{DCR is} the resistance value of the parasitic resistance of the inductor, R _AUX is the resistance value of the equivalent resistance, and C _{AUX is} the capacitance value of the second capacitor. An electronic device having a boost power converter and an information processing circuit, wherein the boost power converter is used to generate an output voltage according to an input voltage to power the information processing circuit, and the boost power conversion The device has: An energy transfer unit for periodically charging an inductor with an input voltage and discharging the inductor to an output terminal to generate an output voltage according to the control of a PWM signal. The inductor has an equivalent inductance and is connected in series with it One of inductance parasitic resistance; A ramp signal generating unit for modulating a ramp signal according to a cross voltage of the inductor; An error average circuit for generating an error average voltage according to the average value of the difference between a feedback voltage of the output voltage and a reference voltage; and A PWM signal generating unit is used to determine the starting point of the PWM signal according to the comparison result of the ramp signal and the error average voltage. For example, the electronic device described in items 7 to 12 of the scope of patent application is a display, a smart phone or a portable computer.

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