TW202111967A - Light-emitting device - Google Patents

Abstract

A light-emitting device comprises a semiconductor stack comprising a first semiconductor layer, a second semiconductor layer, and an active layer between the first semiconductor layer and the second semiconductor layer; a first bonding pad formed on the semiconductor stack; a second bonding pad formed on the semiconductor stack and separated from the first bonding pad by a distance to define a region therebetween on the semiconductor stack; and multiple vias penetrating through the active layer to expose the first semiconductor layer, wherein the first bonding pad and the second bonding pad are formed on regions outside of the multiple vias in top view.

Description

Light-emitting element

The present invention relates to a light emitting device, and more particularly to a light emitting device, which includes a semiconductor stack and a bonding pad on the semiconductor stack.

Light-Emitting Diode (LED) is a solid-state semiconductor light-emitting element. Its advantages are low power consumption, low heat generation, long working life, shockproof, small size, fast response speed and good photoelectric characteristics, such as Stable emission wavelength. Therefore, light-emitting diodes are widely used in household appliances, equipment indicators, and optoelectronic products.

A light emitting device includes a semiconductor stack with a first semiconductor layer, a second semiconductor layer, and an active layer located between the first semiconductor layer and the second semiconductor layer; a first bonding pad is located on the semiconductor stack; The second soldering pad is located on the semiconductor stack, wherein the first soldering pad and the second soldering pad are separated by a distance, and a region is defined on the semiconductor stack to be located between the first soldering pad and the second soldering pad; and a plurality of The hole passes through the active layer to expose the first semiconductor layer. In the top view of the light-emitting device, the first bonding pad and the second bonding pad are formed in regions other than the positions of the plurality of holes.

A light-emitting element includes a semiconductor stack with a first semiconductor layer, a second semiconductor layer, and an active layer located between the first semiconductor layer and the second semiconductor layer; a first contact layer is located on the second semiconductor layer , Surrounding a sidewall of the second semiconductor layer and connected to the first semiconductor layer; a second contact layer is located on the second semiconductor layer and connected to the second semiconductor layer; a first bonding pad is located on the semiconductor stack On and connected with the first contact layer; a second solder pad is located on the semiconductor stack and connected with the second contact layer, wherein the first solder pad and the second solder pad are separated by a distance and defined on the semiconductor stack A region is located between the first bonding pad and the second bonding pad, wherein in the top view of the light-emitting element, the first contact layer on the second semiconductor layer surrounds the second contact layer.

In order to make the description of the present invention more detailed and complete, please refer to the description of the following embodiments and related illustrations. However, the examples shown below are used to illustrate the light-emitting element of the present invention, and the present invention is not limited to the following examples. In addition, the dimensions, materials, shapes, relative arrangement, etc. of the constituent parts described in the embodiments in this specification are not limited to the description, and the scope of the present invention is not limited thereto, but is merely a description. In addition, the size or positional relationship of the components shown in each figure will be exaggerated for clear description. Furthermore, in the following description, in order to appropriately omit detailed descriptions, components of the same or similar nature are shown with the same names and symbols.

FIGS. 1A to 11B are a method of manufacturing a light-emitting element 1 or a light-emitting element 2 disclosed in an embodiment of the present invention.

As shown in the top view of FIG. 1A and the cross-sectional view of FIG. 1B along the line AA' of FIG. 1A, the method of manufacturing the light-emitting element 1 or the light-emitting element 2 includes a platform formation step, which includes providing a substrate 11a; and A semiconductor stack 10a is formed on the substrate 11a, wherein the semiconductor stack 10a includes a first semiconductor layer 101a, a second semiconductor layer 102a, and an active layer 103a located between the first semiconductor layer 101a and the second semiconductor layer 102a . The semiconductor stack 10a can be patterned by lithography and etching to remove part of the second semiconductor layer 102a and the active layer 103a to form one or more semiconductor structures 1000a; and a surrounding portion 111a surrounds one or more Semiconductor structure 1000a. The surrounding portion 111a exposes a first surface 1011a of the first semiconductor layer 101a. The one or more semiconductor structures 1000a each include a plurality of first outer sidewalls 1003a, a second outer sidewall 1001a, and a plurality of inner sidewalls 1002a, wherein the first outer sidewall 1003a is the sidewall of the first semiconductor layer 101a, and the second outer sidewall 1001a Is the sidewall of the active layer 103a and/or the second semiconductor layer 102a, one end of the second outer sidewall 1001a is connected to one surface 102s of the second semiconductor layer 102a, and the other end of the second outer sidewall 1001a is connected to the first semiconductor layer 101a. One surface 1011a is connected; one end of the inner side wall 1002a is connected to the surface 102s of the second semiconductor layer 102a, and the other end of the inner side wall 1002a is connected to the second surface 1012a of the first semiconductor layer 101a; The layers 101a are connected to each other. As can be seen from FIG. 1B, there is an obtuse angle between the inner sidewall 1002a of the semiconductor structure 1000a and the second surface 1012a of the first semiconductor layer 101a, and there is an obtuse angle between the first outer sidewall 1003a of the semiconductor structure 1000a and the surface 11s of the substrate 11a. Obtuse angle or right angle, there is an obtuse angle between the second outer sidewall 1001a of the semiconductor structure 1000a and the first surface 1011a of the first semiconductor layer 101a. The surrounding portion 111a surrounds the periphery of the semiconductor structure 1000a, and the surrounding portion 111a is a rectangle or a polygon in the top view of the light emitting element 1 or the light emitting element 2.

In an embodiment of the present invention, the light-emitting element 1 or the light-emitting element 2 includes a side length of less than 30 mils. When an external current is injected into the light-emitting element 1 or the light-emitting element 2, the surrounding portion 111a surrounds the semiconductor structure 1000a, so that the light field distribution of the light-emitting element 1 or the light-emitting element 2 can be made uniform, and the forward direction of the light-emitting element can be reduced. Voltage.

In an embodiment of the present invention, the light-emitting element 1 or the light-emitting element 2 includes a side length greater than 30 mils. The semiconductor stack 10a can be patterned by lithography and etching to remove part of the second semiconductor layer 102a and the active layer 103a, forming one or more holes 100a through the second semiconductor layer 102a and the active layer 103a , One or more of the holes 100a expose one or more of the second surfaces 1012a of the first semiconductor layer 101a. When an external current is injected into the light-emitting element 1 or the light-emitting element 2, the scattered arrangement of the surrounding portion 111a and the plurality of holes 100a can make the light field distribution of the light-emitting element 1 or the light-emitting element 2 uniform, and reduce the number of light-emitting elements. The forward voltage.

In an embodiment of the present invention, the light-emitting element 1 or the light-emitting element 2 includes a side length of less than 30 mils, and the light-emitting element 1 or the light-emitting element 2 may not include one or more holes 100a.

In an embodiment of the present invention, the opening shape of the one or more holes 100a includes a circle, an ellipse, a rectangle, a polygon, or any shape. The plurality of holes 100a can be arranged in a plurality of rows, and the holes 100a on two adjacent rows can be aligned or staggered with each other.

In an embodiment of the present invention, the substrate 11a may be a growth substrate, including a gallium arsenide (GaAs) wafer used to grow aluminum gallium indium phosphide (AlGaInP), or used to grow indium gallium nitride (InGaN) Of sapphire (Al ₂ O ₃ ) wafers, gallium nitride (GaN) wafers or silicon carbide (SiC) wafers. On this substrate 11a, a metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), hydride vapor deposition (HVPE), vapor deposition or ion plating method can be used to form a semiconductor stack with optoelectronic properties. The layer 10a is, for example, a light-emitting stack.

In an embodiment of the present invention, the first semiconductor layer 101a and the second semiconductor layer 102a are, for example, a cladding layer or a confinement layer, and the two have different conductivity types, electrical properties, The polarity may provide electrons or holes depending on the doped element. For example, the first semiconductor layer 101a is an n-type semiconductor, and the second semiconductor layer 102a is a p-type semiconductor. The active layer 103a is formed between the first semiconductor layer 101a and the second semiconductor layer 102a. Electrons and holes are recombined in the active layer 103a under a current drive to convert electrical energy into light energy to emit a light. The wavelength of light emitted by the light-emitting element 1 or the light-emitting element 2 can be adjusted by changing the physical and chemical composition of one or more layers in the semiconductor stack 10a. The material of the semiconductor stack 10a includes III-V group semiconductor materials, such as Al _x In _y Ga _(1-xy) N or Al _x In _y Ga _(1-xy) P, where 0≦x, y≦1; (x +y)≦1. According to the material of the active layer 103a, when the material of the semiconductor stack 10a is AlInGaP series material, it can emit red light with a wavelength between 610 nm and 650 nm, and green light with a wavelength between 530 nm and 570 nm. When the material of the semiconductor stack 10a is an InGaN series material, it can emit blue light with a wavelength between 450 nm and 490 nm, or when the material of the semiconductor stack 10a is an AlGaN series material, it can emit a wavelength between 400 nm and 250 nm Between the ultraviolet light. The active layer 103a can be a single heterostructure (SH), a double heterostructure (DH), a double-side double heterostructure (DDH), or a multi-quantum well structure (multi-quantum well, MQW ). The material of the active layer 103a can be a neutral, p-type or n-type semiconductor.

The step of forming the connection platform, as shown in the top view of Figure 2A and the cross-sectional view of Figure 2B along the line AA' in Figure 2A, the method of manufacturing the light-emitting element 1 or the light-emitting element 2 includes a first insulating layer Formation steps. A first insulating layer 20a can be formed on the semiconductor structure 1000a by evaporation or deposition, and then patterned by lithography and etching to cover the first surface 1011a of the surrounding portion 111a and the hole 100a The second surface 1012a of the semiconductor structure 1000a covers the second semiconductor layer 102a of the semiconductor structure 1000a, the second outer sidewall 1001a and the inner sidewall 1002a of the active layer 103a, wherein the first insulating layer 20a includes a first insulating layer surrounding area 200a to cover The surrounding portion 111a makes the first surface 1011a of the first semiconductor layer 101a located at the surrounding portion 111a covered by the surrounding area 200a of the first insulating layer; a first group of the first insulating layer covering area 201a covers the hole portion 100a , So that the second surface 1012a of the first semiconductor layer 101a in the hole 100a is covered by the first insulating layer covering region 201a of the first group; and the first insulating layer opening 202a of a second group is to expose the first insulating layer The surface 102s of the second semiconductor layer 102a. The first insulating layer covering regions 201a of the first group are separated from each other and respectively correspond to a plurality of holes 100a. The first insulating layer 20a may have a single-layer or multi-layer structure. When the first insulating layer 20a is a single-layer film, the first insulating layer 20a can protect the sidewall of the semiconductor structure 1000a to prevent the active layer 103a from being damaged by subsequent processes. When the first insulating layer 20a is a multilayer film, the first insulating layer 20a may include two or more materials with different refractive indexes alternately stacked to form a Bragg reflector (DBR) structure, which selectively reflects light of a specific wavelength. The first insulating layer 20a is formed of a non-conductive material, including organic materials, such as Su8, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), epoxy resin (Epoxy), acrylic resin (Acrylic Resin) ), cycloolefin polymer (COC), polymethyl methacrylate (PMMA), polyethylene terephthalate (PET), polycarbonate (PC), polyetherimide (Polyetherimide), fluorocarbon Polymer (Fluorocarbon Polymer), or inorganic material, such as silicon (Silicone), glass (Glass), or dielectric material, such as aluminum oxide (Al ₂ O ₃ ), silicon nitride (SiN _x ), silicon oxide ( SiO _x ), titanium oxide (TiO _x ), or magnesium fluoride (MgF _x ).

In one embodiment of the present invention, the step of forming the first insulating layer is continued, as shown in the top view of FIG. 3A and the cross-sectional view of FIG. 3B along the line A-A' of FIG. 3A, the light-emitting element 1 or The manufacturing method of the light-emitting element 2 includes a step of forming a transparent conductive layer. A transparent conductive layer 30a can be formed in the first insulating layer opening 202a of the second group by evaporation or deposition, wherein the outer edge 301a of the transparent conductive layer 30a is separated from the first insulating layer 20a by a distance to expose the first insulating layer 20a. The surface 102s of the second semiconductor layer 102a. Since the transparent conductive layer 30a is formed on substantially the entire surface of the second semiconductor layer 102a and is in contact with the second semiconductor layer 102a, the transparent conductive layer 30a can evenly diffuse current across the entire second semiconductor layer 102a. The material of the transparent conductive layer 30a includes a material that is transparent to the light emitted by the active layer 103a, such as indium tin oxide (ITO) or indium zinc oxide (IZO).

In another embodiment of the present invention, after the platform forming step, the transparent conductive layer forming step may be performed first, and then the first insulating layer forming step may be performed.

In another embodiment of the present invention, after the step of forming the platform, the step of forming the first insulating layer can be omitted, and the step of forming the transparent conductive layer can be directly performed.

In one embodiment of the present invention, the step of forming the transparent conductive layer is continued, as shown in the top view of FIG. 4A and the cross-sectional view of FIG. 4B along the line A-A' of FIG. 4A, the light-emitting element 1 or the light-emitting element The manufacturing method of 2 includes a step of forming a reflective structure. The reflective structure includes a reflective layer 40a and/or a barrier layer 41a, which can be directly formed on the transparent conductive layer 30a by evaporation or deposition, wherein the reflective layer 40a is located between the transparent conductive layer 30a and the barrier layer 41a . On the top view of the light-emitting element 1 or the light-emitting element 2, the outer edge 401a of the reflective layer 40a can be arranged inside or outside the outer edge 301a of the transparent conductive layer 30a, or arranged to coincide with the outer edge 301a of the transparent conductive layer 30a The outer edge 411a of the barrier layer 41a can be arranged inside or outside of the outer edge 401a of the reflective layer 40a, or arranged to coincide with the outer edge 401a of the reflective layer 40a.

In another embodiment of the present invention, the step of forming the transparent conductive layer can be omitted, and the step of forming the reflective structure, such as the reflective layer 40a and/or the barrier layer, is directly performed after the step of forming the platform or the step of forming the first insulating layer. 41a is directly formed on the second semiconductor layer 102a, and the reflective layer 40a is located between the second semiconductor layer 102a and the barrier layer 41a.

The reflective layer 40a can be a one or a multi-layer structure, such as a Bragg reflective structure. The material of the reflective layer 40a includes metal materials with high reflectivity, such as metals such as silver (Ag), aluminum (Al), or rhodium (Rh), or alloys of the foregoing materials. The high reflectivity mentioned here means that the light emitting element 1 or the light emitting element 2 has a reflectance of over 80% at the wavelength of light emitted by the light emitting element 2. In an embodiment of the present invention, the barrier layer 41a covers the reflective layer 40a to avoid oxidation of the surface of the reflective layer 40a and deterioration of the reflectivity of the reflective layer 40a. The material of the barrier layer 41a includes metal materials, such as metals such as titanium (Ti), tungsten (W), aluminum (Al), indium (In), tin (Sn), nickel (Ni), platinum (Pt), or the above materials The alloy. The barrier layer 41a can be a one or a multi-layer structure, and the multi-layer structure is, for example, titanium (Ti)/aluminum (Al), and/or titanium (Ti)/tungsten (W). In an embodiment of the present invention, the barrier layer 41a includes a stacked structure of titanium (Ti)/aluminum (Al) on the side away from the reflective layer 40a, and a stacked structure of titanium (Ti)/tungsten (W) On the side close to the reflective layer 40a. In an embodiment of the present invention, the materials of the reflective layer 40a and the barrier layer 41a preferably include metal materials other than gold (Au) or copper (Cu).

In an embodiment of the present invention, the step of forming the continuous reflective structure, such as the top view of 5A, the cross-sectional view of FIG. 5B along A-A', and the cross-sectional view of FIG. 5C along the line of FIG. 5A. As shown in the cross-sectional view of BB', the manufacturing method of the light-emitting element 1 or the light-emitting element 2 includes a second insulating layer forming step. A second insulating layer 50a can be formed on the semiconductor structure 1000a by evaporation or deposition, and then patterned by lithography and etching to form a first group of second insulating layer openings 501a. The first semiconductor layer 101a is exposed, and a second group of second insulating layer openings 502a are exposed to expose the reflective layer 40a or the barrier layer 41a. In the process of patterning the second insulating layer 50a, In the insulating layer forming step, the first insulating layer surrounding area 200a covering the surrounding portion 111a and the first insulating layer covering area 201a of the first group in the hole portion 100a are partially etched and removed to expose the first semiconductor layer 101a; A first group of first insulating layer openings 203a are formed in the hole portion 100a to expose the first semiconductor layer 101a. In this embodiment, on the cross-sectional view of the light-emitting element 1 or the light-emitting element 2, as shown in FIG. 5B, the second insulating layer openings 501a of the first group and the second insulating layer openings 502a of the second group have Different widths and numbers. The opening shapes of the second insulating layer openings 501a of the first group and the second insulating layer openings 502a of the second group include circular, elliptical, rectangular, polygonal, or any shape. In this embodiment, as shown in FIG. 5A, the second insulating layer openings 501a of the first group are separated from each other, arranged in a plurality of rows, and respectively correspond to the plurality of holes 100a and the first insulating layer of the first group Openings 203a, the second insulating layer openings 502a of the second group are all close to one side of the substrate 11a, such as the left or right side of the center line of the substrate 11a, and the second insulating layer openings 502a of the second group are separated from each other and located opposite Between the second insulating layer openings 501a of the first group in two adjacent rows. The second insulating layer 50a may have a single-layer or multi-layer structure. When the second insulating layer 50a is a single-layer film, the second insulating layer 50a can protect the sidewall of the semiconductor structure 1000a to prevent the active layer 103a from being damaged by subsequent processes. When the second insulating layer 50a is a multilayer film, the second insulating layer 50a may include two or more materials with different refractive indexes alternately stacked to form a Bragg reflector (DBR) structure, which selectively reflects light of a specific wavelength. The second insulating layer 50a is formed of a non-conductive material, including organic materials, such as Su8, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), epoxy resin (Epoxy), acrylic resin (Acrylic Resin) ), cycloolefin polymer (COC), polymethyl methacrylate (PMMA), polyethylene terephthalate (PET), polycarbonate (PC), polyetherimide (Polyetherimide), fluorocarbon Polymer (Fluorocarbon Polymer), or inorganic material, such as silicon (Silicone), glass (Glass), or dielectric material, such as aluminum oxide (Al ₂ O ₃ ), silicon nitride (SiN _x ), silicon oxide ( SiO _x ), titanium oxide (TiO _x ), or magnesium fluoride (MgF _x ).

Following the step of forming the second insulating layer, in one embodiment of the present invention, as shown in the top view of FIG. 6A, FIG. 6B is a cross-sectional view along the line A-A' of FIG. 6A, and FIG. 6C is along the line As shown in the cross-sectional view of the line segment BB' in FIG. 6A, the manufacturing method of the light-emitting element 1 or the light-emitting element 2 includes a step of forming a contact layer. A contact layer 60a can be deposited on the first semiconductor layer 101a and the second semiconductor layer 102a by evaporation or deposition, and then patterned by lithography and etching to form the second insulating layer in the second group. One or more contact layer openings 602a are formed on the opening 502a to expose the reflective layer 40a or the barrier layer 41a, and a thimble area 600a is defined at the geometric center of the light-emitting element 1 or the light-emitting element 2. In the cross-sectional view of the light-emitting element 1 or the light-emitting element 2, the contact layer opening 602a includes a width greater than the width of any of the second insulating layer openings 502a of the second group. In the top view of the light-emitting element 1 or the light-emitting element 2, the plurality of contact layer openings 602a are all close to one side of the substrate 11a, such as the left side or the right side of the center line of the substrate 11a. The contact layer 60a can be one or multiple layers. In order to reduce the resistance in contact with the first semiconductor layer 101a, the material of the contact layer 60a includes metal materials, such as chromium (Cr), titanium (Ti), tungsten (W), gold (Au), aluminum (Al), and indium ( In), tin (Sn), nickel (Ni), platinum (Pt) and other metals or alloys of the above materials. In an embodiment of the present invention, the material of the contact layer 60a preferably includes metal materials other than gold (Au) and copper (Cu). In an embodiment of the present invention, the material of the contact layer 60a preferably includes a metal with high reflectivity, such as aluminum (Al) and platinum (Pt). In an embodiment of the present invention, the side of the contact layer 60a in contact with the first semiconductor layer 101a preferably contains chromium (Cr) or titanium (Ti) to increase the bonding strength with the first semiconductor layer 101a.

In an embodiment of the present invention, the contact layer 60a covers all the holes 100a and extends to cover the second semiconductor layer 102a. The contact layer 60a is insulated from the second semiconductor layer 102a through the second insulating layer 50a, and the contact layer 60a is in contact with the first semiconductor layer 101a through the hole 100a. When an external current is injected into the light-emitting element 1 or the light-emitting element 2, the current is conducted to the first semiconductor layer 101a through the plurality of holes 100a. In this embodiment, there is a first shortest distance between two adjacent holes 100a on the same row, and between any hole 100a adjacent to the edge of the light-emitting element and the first outer sidewall 1003a of the first semiconductor layer 101a It includes a second shortest distance, where the first shortest distance is greater than the second shortest distance.

In another embodiment of the present invention, the contact layer 60a covers the surrounding portion 111a and the hole portion 100a, and extends to cover the second semiconductor layer 102a, wherein the contact layer 60a is in contact with the second semiconductor layer 102a through the second insulating layer 50a Insulation, the contact layer 60a is in contact with the first semiconductor layer 101a through the surrounding portion 111a and the hole portion 100a. When an external current is injected into the light-emitting element 1 or the light-emitting element 2, part of the current is conducted to the first semiconductor layer 101a through the surrounding portion 111a, and another part of the current is conducted to the first semiconductor layer 101a through the plurality of holes 100a. In this embodiment, there is a first shortest distance between two adjacent holes 100a on the same row, and between any hole 100a adjacent to the edge of the light-emitting element and the first outer sidewall 1003a of the first semiconductor layer 101a It includes a second shortest distance, where the first shortest distance is less than or equal to the second shortest distance.

In another embodiment of the present invention, a plurality of holes 100a may be arranged in a first row and a second row, and there is a first shortest distance between two adjacent holes 100a in the same row, which are located in the first row. There is a second shortest distance between the holes 100a on the row and the holes 100a on the second row, wherein the first shortest distance is greater than or less than the second shortest distance.

In an embodiment of the present invention, the plurality of holes 100a may be arranged in a first row, a second row and a third row, the holes 100a on the first row and the holes 100a on the second row There is a first shortest distance therebetween, and a second shortest distance is included between the holes 100a on the second row and the holes 100a on the third row, where the first shortest distance is smaller than the second shortest distance.

In an embodiment of the present invention, following the contact layer forming steps shown in FIGS. 6A, 6B, and 6C, the manufacturing method of the light-emitting element 1 or the light-emitting element 2 includes a third insulating layer forming step, such as The top view of Figure 7A, Figure 7B is a cross-sectional view along the line A-A' of Figure 7A, and Figure 7C is a cross-sectional view along the line B-B' of Figure 7A, a third The insulating layer 70a can be formed on the semiconductor structure 1000a by evaporation or deposition, and then patterned by lithography and etching to form a first group of third insulating layer openings 701a on the contact layer 60a To expose the contact layer 60a shown in FIG. 6A, and form a second group of third insulating layer openings 702a on one or more contact layer openings 602a to expose the reflective layer 40a or barrier shown in FIG. 6A Layer 41a, wherein the contact layer 60a on the second semiconductor layer 102a is sandwiched between the second insulating layer 50a and the third insulating layer 70a, the third insulating layer openings 701a of the first group and the first group The two insulating layer openings 501a are staggered and do not overlap each other. The above-mentioned thimble area 600a is surrounded and covered by the third insulating layer. In this embodiment, as shown in FIG. 7A, the openings 701a of the third insulating layer of the first group are separated from each other and staggered from the plurality of holes 100a. The third insulating layer openings 702a of the second group are separated from each other, and respectively correspond to a plurality of contact layer openings 602a. In the top view of FIG. 7A, the third insulating layer opening 701a of the first group is close to one side of the substrate 11a, such as the right side, and the third insulating layer opening 702a of the second group is close to the other side of the substrate 11a, such as The left side of the center line of the substrate 11a. On the cross-sectional view of the light-emitting element 1 or the light-emitting element 2, the third insulating layer opening 702a of any second group includes a width smaller than that of any contact layer opening 602a, and the third insulating layer 70a conforms to the contact layer opening 602a. Into the side wall of the covering contact layer opening 602a, the reflective layer 40a or the barrier layer 41a is exposed, forming the third insulating layer opening 702a of the second group. The third insulating layer 70a may have a single-layer or multi-layer structure. When the third insulating layer 70a is a multilayer film, the third insulating layer 70a may include two or more materials with different refractive indexes stacked alternately to form a Bragg reflector (DBR) structure, which selectively reflects light of a specific wavelength. The third insulating layer 70a is formed of a non-conductive material, including organic materials, such as Su8, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), epoxy resin (Epoxy), acrylic resin (Acrylic Resin) ), cycloolefin polymer (COC), polymethyl methacrylate (PMMA), polyethylene terephthalate (PET), polycarbonate (PC), polyetherimide (Polyetherimide), fluorocarbon Polymer (Fluorocarbon Polymer), or inorganic material, such as silicon (Silicone), glass (Glass), or dielectric material, such as aluminum oxide (Al ₂ O ₃ ), silicon nitride (SiN _x ), silicon oxide ( SiO _x ), titanium oxide (TiO _x ), or magnesium fluoride (MgF _x ).

Following the third insulating layer forming step, the manufacturing method of the light-emitting element 1 or the light-emitting element 2 includes a step of forming a bonding pad. As shown in the top view of FIG. 8, a first bonding pad 80a and a second bonding pad 90a can be formed on one or more semiconductor structures 1000a by electroplating, evaporation, or deposition, and then by lithography , Patterning by etching. In the top view of FIG. 8, the first bonding pad 80a is close to one side of the center line of the substrate 11a, such as the right side, and the second bonding pad 90a is close to the other side of the center line of the substrate 11a, such as the left side. The first bonding pad 80a covers all the third insulating layer openings 701a of the first group to contact the contact layer 60a, and form an electrical connection with the first semiconductor layer 101a through the contact layer 60a and the hole portion 100a. The second bonding pad 90a covers all the third insulating layer openings 702a of the second group, is in contact with the reflective layer 40a or the barrier layer 41a, and passes through the reflective layer 40a or the barrier layer 41a to form an electrical connection with the second semiconductor layer 102a. connection. The first pad 80a has one or more first pad openings 800a; and a first side 802a and a plurality of first recesses 804a extend from the first side 802a in a direction away from the second pad 90a. The second pad 90a has one or more second pad openings 900a; and a second side 902a and a plurality of second recesses 904a extend from the second side 902a in a direction away from the first pad 80a. The position of the first pad opening 800a and the position of the second pad opening 900a roughly correspond to the position of the hole 100a, and the position of the first concave portion 804a and the position of the second concave portion 904a roughly correspond to the position of the hole 100a. In other words, the first solder pad 80a and the second solder pad 90a do not cover any hole 100a, and the first solder pad 80a and the second solder pad 90a go around the hole 100a and are formed around the hole 100a to As for the first pad opening 800a or the second pad opening 900a, it includes a diameter greater than that of any hole 100a, and the first recess 804a or the second recess 904a includes a width greater than the diameter of any hole 100a. In an embodiment of the present invention, the plurality of first recesses 804a are substantially aligned with the plurality of second recesses 904a in the top view. In another embodiment of the present invention, the plurality of first recesses 804a are offset from the plurality of second recesses 904a in the top view. In an embodiment of the present invention, in the top view of the light-emitting element 1 or the light-emitting element 2, the shape of the first bonding pad 80a is the same as or different from the shape of the second bonding pad 90a.

Figure 9A is a cross-sectional view along the line AA' in Figure 8, and Figure 9B is a cross-sectional view along the line B-B' in Figure 8. The light-emitting device 1 disclosed according to this embodiment is a flip-chip light-emitting diode device. The light emitting device 1 includes a substrate 11a; one or more semiconductor structures 1000a are located on the substrate 11a; a surrounding portion 111a surrounds the one or more semiconductor structures 1000a; and a first bonding pad 80a and a second bonding pad 90a are located on the semiconductor stack 10a. The one or more semiconductor structures 1000a each include a semiconductor stack 10a. The semiconductor stack 10a includes a first semiconductor layer 101a, a second semiconductor layer 102a, and an active layer 103a located between the first semiconductor layer 101a and the second semiconductor layer 102a. The plurality of semiconductor structures 1000a are connected to each other through the first semiconductor layer 101a. As shown in Figure 8, Figure 9A and Figure 9B, the second semiconductor layer 102a and the active layer 103a around one or more semiconductor structures 1000a are removed to expose the first surface 1011a of the first semiconductor layer 101a. In other words, the surrounding portion 111a includes the first surface 1011a of the first semiconductor layer 101a to surround the periphery of the semiconductor structure 1000a.

The light emitting element 1 further includes one or more holes 100a passing through the second semiconductor layer 102a and the active layer 103a to expose one or more second surfaces 1012a of the first semiconductor layer 101a; and a contact layer 60a is formed on the first semiconductor layer The first surface 1011a of 101a surrounds the semiconductor structure 1000a and contacts the first semiconductor layer 101a to form an electrical connection, and is formed on one or more second surfaces 1012a of the first semiconductor layer 101a to cover one or more Each hole 100a is in contact with the first semiconductor layer 101a to form an electrical connection. In this embodiment, in the top view of the light-emitting element 1, the contact layer 60a includes a total surface area greater than that of the active layer 103a, or the contact layer 60a includes a peripheral side length greater than that of the active layer 103a.

In an embodiment of the present invention, the first bonding pad 80a and/or the second bonding pad 90a cover the plurality of semiconductor structures 1000a.

In an embodiment of the present invention, the first solder pad 80a has one or more first solder pad openings 800a, and the second solder pad 90a has one or more second solder pad openings 900a. The formation position of the first pad 80a and the second pad 90a is around the formation position of the opening portion 100a, so that the formation position of the first pad opening 800a and the second pad opening 900a is the same as the formation position of the hole portion 100a overlapping.

In an embodiment of the present invention, in the top view of the light emitting device 1, the shape of the first pad 80a is the same as the shape of the second pad 90a, for example, the shape of the first pad 80a and the second pad 90a are Comb-shaped, as shown in Figure 8, a radius of curvature of the first pad opening 800a of the first pad 80a and a radius of curvature of the first concave portion 804a are respectively larger than a radius of curvature of the hole portion 100a, so that the first welding pad The pad 80a is formed in an area other than the position of the plurality of holes 100a. The radius of curvature of the second pad opening 900a of the second pad 90a and the radius of curvature of the second concave portion 904a are respectively larger than the radius of curvature of the hole portion 100a, so that the second pad 90a is formed at the positions of the plurality of hole portions 100a Outside the area.

In an embodiment of the present invention, in the top view of the light-emitting element 1, the shape of the first pad 80a is different from the shape of the second pad 90a. For example, the shape of the first pad 80a is rectangular, and the shape of the second pad When the shape of 90a is a comb shape, the first pad 80a includes a first pad opening 800a so that the first pad 80a is formed in an area other than the plurality of holes 100a, and the second pad 90a includes a second recess 904a or At the same time, the second concave portion 904a and the second pad opening 900a are included, so that the second pad 90a is formed in an area other than the plurality of holes 100a.

In an embodiment of the present invention, the size of the first solder pad 80a is different from the size of the second solder pad 90a, for example, the area of the first solder pad 80a is larger than the area of the second solder pad 90a. The first bonding pad 80a and the second bonding pad 90a may be one or more structures including metal materials. The material of the first pad 80a and the second pad 90a includes metal materials, such as chromium (Cr), titanium (Ti), tungsten (W), aluminum (Al), indium (In), tin (Sn), nickel ( Ni), platinum (Pt) and other metals or alloys of the above materials. When the first solder pad 80a and the second solder pad 90a have a multilayer structure, the first solder pad 80a includes a first upper layer solder pad 805a and a first lower layer solder pad 807a, and the second solder pad 90a includes a second upper layer The bonding pad 905a and a second lower-layer bonding pad 907a. The upper layer pad and the lower layer pad have different functions. The function of the upper layer pad is mainly used for welding and forming leads. With the upper bonding pad, the light-emitting element 1 can be mounted on the package substrate in the form of flip chip using solder solder or AuSn eutectic bonding. The specific metal material of the upper layer pad includes highly ductile materials, such as nickel (Ni), cobalt (Co), iron (Fe), titanium (Ti), copper (Cu), gold (Au), tungsten (W), Zirconium (Zr), molybdenum (Mo), tantalum (Ta), aluminum (Al), silver (Ag), platinum (Pt), palladium (Pd), rhodium (Rh), iridium (Ir), ruthenium (Ru), Osmium (Os). The upper layer pad can be a single layer, alloy or multilayer film of the above-mentioned materials. In an embodiment of the present invention, the material of the upper layer pad preferably includes nickel (Ni) and/or gold (Au), and the upper layer pad is a single layer or multiple layers. The function of the lower layer pad is to form a stable interface with the contact layer 60a, the reflective layer 40a, or the barrier layer 41a, such as improving the interface bonding strength of the first lower layer pad 807a and the contact layer 60a, or improving the second lower layer welding The bonding strength of the interface between the pad 907a and the reflective layer 40a or the barrier layer 41a. Another function of the lower layer pad is to prevent the solder solder or the tin (Sn) in the AuSn eutectic from diffusing into the reflective structure and destroying the reflectivity of the reflective structure. Therefore, the lower layer pad preferably contains metal materials other than gold (Au) and copper (Cu), such as nickel (Ni), cobalt (Co), iron (Fe), titanium (Ti), tungsten (W), zirconium ( Zr), molybdenum (Mo), tantalum (Ta), aluminum (Al), silver (Ag), platinum (Pt), palladium (Pd), rhodium (Rh), iridium (Ir), ruthenium (Ru), osmium ( Os), the lower layer pad can be a single layer, alloy or multilayer film of the above materials. In an embodiment of the present invention, the lower layer pad preferably comprises a multilayer film of titanium (Ti), aluminum (Al), or a multilayer film of chromium (Cr) and aluminum (Al).

In an embodiment of the present invention, under the cross-sectional view of the light emitting device 1, the part of the contact layer 60a connected to the first semiconductor layer 101a is located under the second bonding pad 90a.

In an embodiment of the present invention, under the cross-sectional view of the light emitting device 1, the part of the contact layer 60a connected to the first semiconductor layer 101a is located above the reflective layer 40a and/or the barrier layer 41a.

In an embodiment of the present invention, in the top view of the light-emitting element 1, the hole portion 100a includes a maximum width smaller than a maximum width of the first pad opening 800a; and/or the hole portion 100a includes a maximum width smaller than the second One of the largest widths of the pad opening 900a.

In an embodiment of the present invention, in the top view of the light-emitting element 1, the plurality of holes 100a are respectively located in the plurality of first recesses 804a of the first pad 80a and the plurality of second recesses 904a of the second pad 90a in.

FIG. 10 is a cross-sectional view of the light-emitting element 2 disclosed in an embodiment of the present invention. Compared with the light-emitting element 1 in the above embodiment, the light-emitting element 2 further includes a first buffer pad 810a and a second buffer pad 910a located under the first bonding pad 80a and the second bonding pad 90a, respectively. In addition, the light-emitting element 2 and the light-emitting element 1 have substantially the same structure. Therefore, the light-emitting element 2 in Fig. 10 and the light-emitting element 1 in Fig. 9 have the same names and structures, which represent the same structure and have the same structure. Materials or have the same function, the description will be omitted or not repeated here. In this embodiment, the light-emitting element 2 includes a first buffer pad 810a located between the first bonding pad 80a and the semiconductor stack 10a, and a second buffer pad 910a located between the second bonding pad 90a and the semiconductor stack 10a, wherein The first buffer pad 810a and the second buffer pad 910a cover part or all of the hole 100a; in this embodiment, since the bonding pads 80a, 90a and the semiconductor stack 10a include multiple insulating layers, the bonding pads of the light-emitting element 2 The stress generated when 80a, 90a is joined with solder or AuSn eutectic will cause cracks between the solder pads 80a, 90a and the insulating layer, so the buffer pads 810a, 910a are located between the solder pads 80a, 90a and the third insulating layer 70a, respectively The first cushion pad 810a and the second cushion pad 910a cover all the holes 100a. The first pad 80a and the second pad 90a are formed around the position where the hole 100a is formed. By selecting the material of the cushion , And reduce the thickness to reduce the stress between the pad and the insulating layer. In other words, the first pad 80a and the second pad 90a do not cover the hole portion 100a.

In an embodiment of the present invention, as shown in FIG. 10, in the top view of the light-emitting element 2, the shapes of the buffer pads 810a, 910a are the same as the shapes of the solder pads 80a, 90a, for example, the first buffer pads 810a and The shape of the first pad 80a is a comb shape.

In an embodiment of the present invention, in the top view of the light-emitting element 2 (not shown), the shape of the buffer pads 810a, 910a is different from the shape of the solder pads 80a, 90a, for example, the shape of the first buffer pad 810a is Rectangle, the shape of the first pad 80a is comb shape.

In another embodiment of the present invention, the sizes of the buffer pads 810a, 910a are different from the sizes of the solder pads 80a, 90a, for example, the area of the first buffer pad 810a is larger than the area of the first solder pad 80a, and the second buffer pad 910a The area of is greater than the area of the second pad 90a.

In another embodiment of the present invention, a distance between the first solder pad 80a and the second solder pad 90a is greater than a distance between the first buffer pad 810a and the second buffer pad 910a.

In another embodiment of the present invention, compared to the solder pads 80a, 90a, the buffer pads 810a, 910a have a larger area to relieve the pressure of the solder pads 80a, 90a during die bonding. Under the cross-sectional view of the light-emitting element 2, the first buffer pad 810a includes a width of 1.5 to 2.5 times, preferably 2 times, a width of the first bonding pad 80a.

In another embodiment of the present invention, compared to the solder pads 80a, 90a, the buffer pads 810a, 910a have a larger area to relieve the pressure of the solder pads 80a, 90a during die bonding. In the cross-sectional view of the light-emitting element 2, the outward expansion distance of the first cushion pad 810a is more than 1 time of its own thickness, preferably more than 2 times of its own thickness.

In another embodiment of the present invention, the solder pads 80a, 90a include a thickness between 1-100 μm, preferably 2-6 μm, and the buffer pads 810a, 910a include a thickness greater than 0.5 μm to release the solder pads. The pressure of 80a, 90a during solid crystal bonding.

In another embodiment of the present invention, the first cushion pad 810a and the second cushion pad 910a may be one or more structures including metal materials. The function of the first cushion pad 810a and the second cushion pad 910a is to form a stable interface with the contact layer 60a, the reflective layer 40a, or the barrier layer 41a. For example, the first cushion pad 810a is in contact with the contact layer 60a, and the second cushion pad 910a is in contact with the reflective layer 40a or the barrier layer 41a. The buffer pads 810a, 910a preferably contain metal materials other than gold (Au) and copper (Cu), such as chromium (Cr), nickel (Ni), cobalt (Co), iron (Fe), titanium (Ti), tungsten ( W), zirconium (Zr), molybdenum (Mo), tantalum (Ta), aluminum (Al), silver (Ag), platinum (Pt), palladium (Pd), rhodium (Rh), iridium (Ir), ruthenium ( Ru) and osmium (Os) to prevent the tin (Sn) in the solder or AuSn eutectic from diffusing into the light-emitting element.

In another embodiment of the present invention, the first cushion pad 810a and/or the second cushion pad 910a is a multi-layer structure including a metal material, wherein the multi-layer structure includes a high ductility layer and a low ductility layer to prevent welding The stress generated when the pads 80a, 90a and solder solder or AuSn eutectic are bonded can cause cracks in the insulating layer between the pads 80a, 90a and the semiconductor stack 10a. The high ductility layer and the low ductility layer include metals having different Young's modulus.

In another embodiment of the present invention, the high ductility layers of the first cushion pad 810a and the second cushion pad 910a include a thickness greater than or equal to that of the low ductility layer.

In another embodiment of the present invention, the first cushion pad 810a and the second cushion pad 910a are a multi-layer structure containing a metal material, and when the first pad 80a and the second bonding pad 90a are a multi-layer structure containing a metal material, the first The side of a buffer pad 810a that meets the first pad 80a contains the same metal material, and the side of the second pad 910a that meets the second pad 90a contains the same metal material, such as chromium (Cr), nickel (Ni) ), titanium (Ti), platinum (Pt) to improve the interface bonding strength between the solder pad and the buffer pad.

As shown in FIGS. 11A and 11B, a fourth insulating layer 110a can be formed on the first buffer pad 810a and the second buffer pad 910a by evaporation or deposition, and then by lithography and etching. After patterning, the first solder pad 80a and the second solder pad 90a are formed on the first buffer pad 810a and the second buffer pad 910a respectively by the above-mentioned method, wherein the fourth insulating layer 110a surrounds the first buffer pad 810a and The side wall of the second cushion 910a. The fourth insulating layer 110a may have a single-layer or multi-layer structure. When the fourth insulating layer 110a is a multilayer film, the fourth insulating layer 110a may include two or more materials with different refractive indexes alternately stacked to form a Bragg reflector (DBR) structure, which selectively reflects light of a specific wavelength. The material of the fourth insulating layer 110a is formed of non-conductive materials, including organic materials, such as Su8, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), epoxy resin (Epoxy), acrylic resin (Acrylic Resin), cycloolefin polymer (COC), polymethyl methacrylate (PMMA), polyethylene terephthalate (PET), polycarbonate (PC), polyetherimide (Polyetherimide), fluorine Fluorocarbon Polymer, or inorganic materials, such as silicon, glass, or dielectric materials, such as aluminum oxide (Al ₂ O ₃ ), silicon nitride (SiN _x ), silicon oxide (SiO _x ), titanium oxide (TiO _x ), or magnesium fluoride (MgF _x ).

In an embodiment of the present invention, the manufacturing process of the first bonding pad 80a and the second bonding pad 90a can be directly followed by the manufacturing process of the first cushioning pad 810a and the second cushioning pad 910a. In another embodiment of the present invention, after the manufacturing process of the first buffer pad 810a and the second buffer pad 910a, the step of forming the fourth insulating layer 110a is performed first, and then the first pad 80a and the second pad are connected 90a manufacturing process.

FIGS. 12A to 22 are a method of manufacturing a light-emitting element 3 or a light-emitting element 4 disclosed in an embodiment of the present invention.

As shown in the top view of FIG. 12A and the cross-sectional view of FIG. 12B along the line AA' of FIG. 12A, the method of manufacturing the light-emitting element 3 or the light-emitting element 4 includes a platform formation step, which includes providing a substrate 11b; and A semiconductor stack 10b is formed on the substrate 11b, wherein the semiconductor stack 10b includes a first semiconductor layer 101b, a second semiconductor layer 102b, and an active layer 103b located between the first semiconductor layer 101b and the second semiconductor layer 102b . The semiconductor stack 10b can be patterned by lithography and etching to remove part of the second semiconductor layer 102b and the active layer 103b to form one or more semiconductor structures 1000b; and a surrounding portion 111b surrounds one or more Semiconductor structure 1000b. The surrounding portion 111b exposes a first surface 1011b of the first semiconductor layer 101b. The one or more semiconductor structures 1000b each include a plurality of first outer sidewalls 1003b, a second outer sidewall 1001b, and a plurality of inner sidewalls 1002b, wherein the first outer sidewall 1003b is the sidewall of the first semiconductor layer 101b, and the second outer sidewall 1001b Is the sidewall of the active layer 103b and/or the second semiconductor layer 102b, one end of the second outer sidewall 1001b is connected to one surface 102s of the second semiconductor layer 102b, and the other end of the second outer sidewall 1001b is connected to the first semiconductor layer 101b. One surface 1011b is connected; one end of the inner side wall 1002b is connected to the surface 102s of the second semiconductor layer 102b, and the other end of the inner side wall 1002b is connected to the second surface 1012b of the first semiconductor layer 101b; The layers 101b are connected to each other. Viewed from FIG. 12B, there is an obtuse angle between the inner sidewall 1002b of the semiconductor structure 1000b and the second surface 1012b of the first semiconductor layer 101b, and there is an obtuse angle between the first outer sidewall 1003b of the semiconductor structure 1000b and the surface 11s of the substrate 11b. Obtuse angle or right angle, there is an obtuse angle between the second outer sidewall 1001b of the semiconductor structure 1000b and the first surface 1011b of the first semiconductor layer 101b. The surrounding portion 111b surrounds the periphery of the semiconductor structure 1000b, and the surrounding portion 111b is a rectangle or a polygon in the top view of the light emitting element 3 or the light emitting element 4.

In an embodiment of the present invention, the light-emitting element 3 or the light-emitting element 4 includes a side length of less than 30 mils. When an external current is injected into the light-emitting element 3 or the light-emitting element 4, the surrounding portion 111b surrounds the semiconductor structure 1000b, so that the light field distribution of the light-emitting element 3 or the light-emitting element 4 can be made uniform, and the forward direction of the light-emitting element can be reduced. Voltage.

In an embodiment of the present invention, the light-emitting element 3 or the light-emitting element 4 includes a side length greater than 30 mils. The semiconductor stack 10b can be patterned by photolithography and etching to remove part of the second semiconductor layer 102b and the active layer 103b, forming one or more holes 100b through the second semiconductor layer 102b and the active layer 103b , One or more of the holes 100b expose one or more of the second surfaces 1012b of the first semiconductor layer 101b. When an external current is injected into the light-emitting element 3 or the light-emitting element 4, the scattered arrangement of the surrounding portion 111b and the plurality of holes 100b can make the light field distribution of the light-emitting element 3 or the light-emitting element 4 uniform, and reduce the number of light-emitting elements. The forward voltage.

In an embodiment of the present invention, the opening shape of the one or more holes 100b includes a circle, an ellipse, a rectangle, a polygon, or any shape. The plurality of holes 100b can be arranged in a plurality of rows, and the holes 100b on two adjacent rows can be aligned or staggered with each other.

In one embodiment of the present invention, the substrate 11b may be a growth substrate, including a gallium arsenide (GaAs) wafer used to grow aluminum gallium indium phosphide (AlGaInP), or used to grow indium gallium nitride (InGaN) Of sapphire (Al ₂ O ₃ ) wafers, gallium nitride (GaN) wafers or silicon carbide (SiC) wafers. On this substrate 11b, a metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), hydride vapor deposition (HVPE), vapor deposition or ion plating method can be used to form a semiconductor stack with optoelectronic properties. The layer 10b is, for example, a light-emitting stack.

In an embodiment of the present invention, the first semiconductor layer 101b and the second semiconductor layer 102b are, for example, a cladding layer or a confinement layer, and the two have different conductivity types, electrical properties, The polarity may provide electrons or holes depending on the doped element. For example, the first semiconductor layer 101b is an n-type semiconductor, and the second semiconductor layer 102b is a p-type semiconductor. The active layer 103b is formed between the first semiconductor layer 101b and the second semiconductor layer 102b. Electrons and holes are recombined in the active layer 103b under a current drive to convert electrical energy into light energy to emit a light. The wavelength of light emitted by the light emitting element 3 or the light emitting element 4 can be adjusted by changing the physical and chemical composition of one or more layers of the semiconductor stack 10b. The material of the semiconductor stack 10b includes III-V group semiconductor materials, such as Al _x In _y Ga _(1-xy) N or Al _x In _y Ga _(1-xy) P, where 0≦x, y≦1; (x +y)≦1. According to the material of the active layer 103b, when the material of the semiconductor stack 10b is AlInGaP series material, it can emit red light with wavelengths between 610 nm and 650 nm, and green light with wavelengths between 530 nm and 570 nm. When the material of the semiconductor stack 10b is an InGaN series material, it can emit blue light with a wavelength between 450 nm and 490 nm, or when the material of the semiconductor stack 10b is an AlGaN series material, it can emit a wavelength between 400 nm and 250 nm Between the ultraviolet light. The active layer 103b can be a single heterostructure (SH), a double heterostructure (DH), a double-side double heterostructure (DDH), or a multi-quantum well structure (multi-quantum well, MQW ). The material of the active layer 103b can be a neutral, p-type or n-type semiconductor.

The step of forming the connection platform, as shown in the top view of FIG. 13A and FIG. 13B is a cross-sectional view along the line AA' of FIG. 13A, the method of manufacturing the light-emitting element 3 or the light-emitting element 4 includes a first insulating layer Formation steps. A first insulating layer 20b can be formed on the semiconductor structure 1000b by evaporation or deposition, and then patterned by lithography and etching to cover the first surface 1011b of the surrounding portion 111b and the hole 100b The second surface 1012b of the semiconductor structure 1000b covers the second semiconductor layer 102b of the semiconductor structure 1000b, the second outer sidewall 1001b and the inner sidewall 1002b of the active layer 103b. The first insulating layer 20b includes a first insulating layer surrounding area 200b to cover The surrounding portion 111b makes the first surface 1011b of the first semiconductor layer 101b located at the surrounding portion 111b covered by the surrounding area 200b of the first insulating layer; a first group of the first insulating layer covering area 201b covers the hole portion 100b , So that the second surface 1012b of the first semiconductor layer 101b located in the hole 100b is covered by the first insulating layer covering region 201b of the first group; and the first insulating layer opening 202b of a second group is to expose the first insulating layer The surface 102s of the second semiconductor layer 102b. The first insulating layer covering regions 201b of the first group are separated from each other and respectively correspond to a plurality of holes 100b. The first insulating layer 20b may have a single-layer or multi-layer structure. When the first insulating layer 20b is a single-layer film, the first insulating layer 20b can protect the sidewalls of the semiconductor structure 1000b to prevent the active layer 103b from being damaged by subsequent processes. When the first insulating layer 20b is a multilayer film, the first insulating layer 20b may include two or more materials with different refractive indexes alternately stacked to form a Bragg reflector (DBR) structure, which selectively reflects light of a specific wavelength. The first insulating layer 20b is formed of a non-conductive material, including organic materials, such as Su8, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), epoxy resin (Epoxy), acrylic resin (Acrylic Resin) ), cycloolefin polymer (COC), polymethyl methacrylate (PMMA), polyethylene terephthalate (PET), polycarbonate (PC), polyetherimide (Polyetherimide), fluorocarbon Polymer (Fluorocarbon Polymer), or inorganic material, such as silicon (Silicone), glass (Glass), or dielectric material, such as aluminum oxide (Al ₂ O ₃ ), silicon nitride (SiN _x ), silicon oxide ( SiO _x ), titanium oxide (TiO _x ), or magnesium fluoride (MgF _x ).

In one embodiment of the present invention, following the first insulating layer forming step, as shown in the top view of FIG. 14A and FIG. 14B are cross-sectional views along the line A-A' of FIG. 14A, the light-emitting element 3 or The manufacturing method of the light-emitting element 4 includes a step of forming a transparent conductive layer. A transparent conductive layer 30b can be formed on the semiconductor structure 1000b by evaporation or deposition, and is in contact with the second semiconductor layer 102, wherein the transparent conductive layer 30b does not cover the hole 100b. On the top view of the light emitting element 3 or the light emitting element 4, the transparent conductive layer 30b is formed on substantially the entire surface of the second semiconductor layer 102b. Specifically, the transparent conductive layer 30b can be formed in the first insulating layer opening 202b of the second group by evaporation or deposition, wherein the outer edge 301b of the transparent conductive layer 30b is separated from the first insulating layer 20b by a distance To expose the surface 102s of the second semiconductor layer 102b. The transparent conductive layer 30b includes one or more transparent conductive layer openings 300b respectively corresponding to one or more holes 100b and/or respectively corresponding to the first insulating layer covering area 201b of the first group, wherein the transparent conductive layer opening 300b has an outer edge 301b A distance from the inner sidewall 1002b of the semiconductor structure 1000b and/or the outer edge of the hole 100b, the outer edge of the transparent conductive layer opening 300b surrounds the outer edge of the hole 100b or the first insulating layer covering area 201b of the first group. The material of the transparent conductive layer 30b includes a material that is transparent to the light emitted by the active layer 103b, such as indium tin oxide (ITO) or indium zinc oxide (IZO).

In another embodiment of the present invention, after the platform forming step, the transparent conductive layer forming step may be performed first, and then the first insulating layer forming step may be performed.

In another embodiment of the present invention, after the step of forming the platform, the step of forming the first insulating layer can be omitted, and the step of forming the transparent conductive layer can be directly performed.

In an embodiment of the present invention, the step of forming the transparent conductive layer is continued, as shown in the top view of FIG. 15A and the cross-sectional view along the line AA' of FIG. 15A in FIG. 15B, the light-emitting element 3 or the light-emitting element The manufacturing method of 4 includes a step of forming a reflective structure. The reflective structure includes a reflective layer 40b and/or a barrier layer 41b, which can be directly formed on the transparent conductive layer 30b by evaporation or deposition, wherein the reflective layer 40b is located between the transparent conductive layer 30b and the barrier layer 41b . On the top view of the light-emitting element 3 or the light-emitting element 4, the reflective layer 40b and/or the barrier layer 41b are formed on substantially the entire surface of the second semiconductor layer 102b. The outer edge 401b of the reflective layer 40b can be arranged inside or outside the outer edge 301b of the transparent conductive layer 30b, or arranged to coincide with the outer edge 301b of the transparent conductive layer 30b, and the outer edge 411b of the barrier layer 41b can be arranged on the reflective layer. The inner side, the outer side, or the outer edge 401b of the layer 40b is arranged to coincide with the outer edge 401b of the reflective layer 40b. The reflective layer 40b includes one or more reflective layer openings 400b corresponding to one or more holes 100b, and the barrier layer 41b includes one or more barrier layer openings 410b corresponding to one or more holes 100b, respectively. The transparent conductive layer opening 300b, the reflective layer opening 400b, and the barrier layer opening 410b overlap each other. The outer edge of the reflective layer opening 400b and/or the outer edge of the barrier layer opening 410b is separated from the outer edge of the hole 100b, and the outer edge of the reflective layer opening 400b and/or the outer edge of the barrier layer opening 410b surrounds the outer edge of the hole 100b .

In another embodiment of the present invention, the step of forming the transparent conductive layer can be omitted, and the step of forming the reflective structure, such as the reflective layer 40b and/or the barrier layer, is directly performed after the step of forming the platform or the step of forming the first insulating layer. 41b is directly formed on the second semiconductor layer 102b, and the reflective layer 40b is located between the second semiconductor layer 102b and the barrier layer 41b. The reflective layer 40b can be a one- or multi-layer structure, such as a Bragg reflective structure. The material of the reflective layer 40b includes metal materials with high reflectivity, such as metals such as silver (Ag), aluminum (Al), or rhodium (Rh), or alloys of the foregoing materials. The high reflectivity mentioned here means that the light emitting element 3 has a reflectivity of more than 80% for the wavelength of light emitted by the light-emitting element 3. In an embodiment of the present invention, the barrier layer 41b covers the reflective layer 40b to avoid oxidation of the surface of the reflective layer 40b and deterioration of the reflectivity of the reflective layer 40b. The material of the barrier layer 41b includes metal materials, such as metals such as titanium (Ti), tungsten (W), aluminum (Al), indium (In), tin (Sn), nickel (Ni), platinum (Pt), or the above materials The alloy. The barrier layer 41b may have a one- or multi-layer structure, and the multi-layer structure is, for example, titanium (Ti)/aluminum (Al), and/or titanium (Ti)/tungsten (W). In an embodiment of the present invention, the barrier layer 41b includes a stacked structure of titanium (Ti)/aluminum (Al) on the side close to the reflective layer 40b, and a stacked structure of titanium (Ti)/tungsten (W) On the side away from the reflective layer 40b. In an embodiment of the present invention, the materials of the reflective layer 40b and the barrier layer 41b preferably include metal materials other than gold (Au) or copper (Cu).

In one embodiment of the present invention, the step of forming the continuous reflective structure, as shown in the top view of 16A and the cross-sectional view of the line A-A' of 16A, as shown in the top view of 16A, the light-emitting element 3 or the light-emitting element 4 The manufacturing method includes a step of forming a second insulating layer. A second insulating layer 50b can be formed on the semiconductor stack 10b by evaporation or deposition, and then patterned by lithography and etching to form a first group of second insulating layer openings 501b The first semiconductor layer 101b and a second group of second insulating layer openings 502b are exposed to expose the reflective layer 40b or the barrier layer 41b. In the process of patterning the second insulating layer 50b, In the insulating layer forming step, the first insulating layer surrounding area 200b covering the surrounding portion 111b and the first insulating layer covering area 201b of the first group on the hole portion 100b are etched and removed to expose the first semiconductor layer 101b, and A first group of first insulating layer openings 203b are formed on the hole portion 100b to expose the first semiconductor layer 101b. In an embodiment of the present invention, as shown in FIG. 16A, the second insulating layer openings 501b of the first group are separated from each other and correspond to a plurality of holes 100b, and the second insulating layer openings 502b of the second group They are all close to one side of the substrate 11b, such as the left or right side of the center line of the substrate 11b. In one embodiment, the number of the second insulating layer openings 502b in the second group includes one or more. In this embodiment, the first The two groups of second insulating layer openings 502b are connected to each other to jointly form a ring-shaped opening 5020b. The ring-shaped opening 5020b can be comb-shaped, rectangular, elliptical, circular, or polygonal in the top view of the light-emitting element 3. In an embodiment of the present invention, the second insulating layer 50b may be a single-layer or multi-layer structure. When the second insulating layer 50b is a multilayer film, the second insulating layer 50b may include two or more materials with different refractive indexes alternately stacked to form a Bragg reflector (DBR) structure, which selectively reflects light of a specific wavelength. The second insulating layer 50b is formed of a non-conductive material, including organic materials, such as Su8, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), epoxy resin (Epoxy), acrylic resin (Acrylic Resin) ), cycloolefin polymer (COC), polymethyl methacrylate (PMMA), polyethylene terephthalate (PET), polycarbonate (PC), polyetherimide (Polyetherimide), fluorocarbon Polymer (Fluorocarbon Polymer), or inorganic material, such as silicon (Silicone), glass (Glass), or dielectric material, such as aluminum oxide (Al ₂ O ₃ ), silicon nitride (SiN _x ), silicon oxide ( SiO _x ), titanium oxide (TiO _x ), or magnesium fluoride (MgF _x ).

Following the step of forming the second insulating layer, in one embodiment of the present invention, as shown in the cross-sectional view of the top view of FIG. 17A and the cross-sectional view of FIG. 17B, the manufacturing method of the light-emitting element 3 or the light-emitting element 4 includes a contact Layer formation step. A contact layer 60b can be deposited on the semiconductor stack 10b by evaporation or deposition, and then patterned by lithography and etching to form a first contact layer 601b and a second contact layer 602b. The first contact layer 601b covers all the second insulating layer openings 501b of the first group, is filled in one or more holes 100b to contact the first semiconductor layer 101b, and extends to cover the second insulating layer 50b and On the second semiconductor layer 102b, the first contact layer 601b is insulated from the second semiconductor layer 102b through the second insulating layer 50b. The second contact layer 602b is formed in the annular opening 5020b of the second insulating layer 50b to contact the reflective layer 40b and/or the barrier layer 41b, wherein the sidewall 6021b of the second contact layer 602b and the sidewall 5021b of the annular opening 5020b Separated by a distance. The sidewall 6011b of the first contact layer 601b is separated from the sidewall 6021b of the second contact layer 602b by a distance, so that the first contact layer 60 1b does not connect with the second contact layer 602b, and the first contact layer 601b and the second contact layer 602b Part of the second insulating layer 50b is electrically isolated. In the top view, the first contact layer 601b covers the surrounding portion 111b of the semiconductor stack 10b, so that the first contact layer 601b surrounds the second contact layer 602b. In the top view of FIG. 17A, the second contact layer 602b is close to a side of the substrate 11b, such as the left or right side of the center line of the substrate 11b. The contact layer 60b defines a thimble area 600b at the geometric center of the semiconductor stack 10b. The ejector pin area 600b is not connected to the first contact layer 601b and the second contact layer 602b and is electrically isolated from each other. The ejector pin area 600b includes the same material as the first contact layer 601b and/or the second contact layer 602b. The thimble area 600b is used as a structure to protect the epitaxial layer to prevent the epitaxial layer from being damaged by the probes in the subsequent processes, such as die separation, die testing, and packaging. The contact layer 60b can be one or multiple layers. In order to reduce the resistance in contact with the first semiconductor layer 101b, the material of the contact layer 60b includes metal materials, such as chromium (Cr), titanium (Ti), tungsten (W), gold (Au), aluminum (Al), and indium ( In), tin (Sn), nickel (Ni), platinum (Pt) and other metals or alloys of the above materials. In an embodiment of the present invention, the material of the contact layer 60b preferably includes metal materials other than gold (Au) and copper (Cu). In an embodiment of the present invention, the material of the contact layer 60b preferably includes a metal with high reflectivity, such as aluminum (Al) and platinum (Pt). In an embodiment of the present invention, the side of the contact layer 60b in contact with the first semiconductor layer 101b preferably contains chromium (Cr) or titanium (Ti) to increase the bonding strength with the first semiconductor layer 101b.

In one embodiment of the present invention, following the steps of forming the contact layer shown in FIGS. 17A and 17B, the method of manufacturing the light-emitting element 3 or the light-emitting element 4 includes a third insulating layer forming step, as shown in FIG. 18A The view and Fig. 18B are cross-sectional views along the line A-A' of Fig. 18A. A third insulating layer 70b can be formed on the semiconductor stack 10b by evaporation or deposition, and then by lithography. , Patterning by etching, a third insulating layer opening 701b is formed on the first contact layer 601b to expose the first contact layer 601b shown in FIG. 17A, and another third layer is formed on the second contact layer 602b The insulating layer opening 702b exposes the second contact layer 602b shown in FIG. 17A, and a part of the first contact layer 601b on the second semiconductor layer 102b is sandwiched between the second insulating layer 50b and the third insulating layer 70b. In this embodiment, as shown in FIG. 18A, the third insulating layer opening 701b and the other third insulating layer opening 702b bypass one or more holes 100b. In this embodiment, the third insulating layer opening 701b and/or the other third insulating layer opening 702b is a ring-shaped opening, and the ring-shaped opening can be comb-shaped, rectangular, oval, circular, Or polygon. In the top view of FIG. 18A, the third insulating layer opening 701b is close to one side of the center line of the substrate 11b, such as the right side, and the other third insulating layer opening 702b is close to the other side of the center line of the substrate 11b, such as the left side. In the cross-sectional view, the third insulating layer opening 701b includes a width greater than that of the other third insulating layer opening 702b. The third insulating layer 70b may have a single-layer or multi-layer structure. When the third insulating layer 70b is a multilayer film, the third insulating layer 70b may include two or more materials with different refractive indexes alternately stacked to form a Bragg reflector (DBR) structure, which selectively reflects light of a specific wavelength. The third insulating layer 70b is formed of a non-conductive material, including organic materials, such as Su8, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), epoxy resin (Epoxy), acrylic resin (Acrylic Resin) ), cycloolefin polymer (COC), polymethyl methacrylate (PMMA), polyethylene terephthalate (PET), polycarbonate (PC), polyetherimide (Polyetherimide), fluorocarbon Polymer (Fluorocarbon Polymer), or inorganic material, such as silicon (Silicone), glass (Glass), or dielectric material, such as aluminum oxide (Al ₂ O ₃ ), silicon nitride (SiN _x ), silicon oxide ( SiO _x ), titanium oxide (TiO _x ), or magnesium fluoride (MgF _x ).

Following the third insulating layer forming step, the manufacturing method of the light-emitting element 3 or the light-emitting element 4 includes a step of forming a bonding pad. As shown in the top view of Figure 19, a first bonding pad 80b and a second bonding pad 90b can be formed on the semiconductor stack 10b by electroplating, evaporation, or deposition, and then by lithography and etching. Way to pattern. In the top view of FIG. 19, the first bonding pad 80b is close to one side of the center line of the substrate 11b, such as the right side, and the second bonding pad 90b is close to the other side of the center line of the substrate 11b, such as the left side. The first bonding pad 80b is in contact with the first contact layer 601b through the third insulating layer opening 701b, and is electrically connected to the first semiconductor layer 101b through the first contact layer 601b. The second bonding pad 90b is in contact with the reflective layer 40b and/or the barrier layer 41b through another third insulating layer opening 702b, and is electrically connected to the second semiconductor layer 102b through the reflective layer 40b and/or the barrier layer 41b . The first pad 80b has a plurality of first protrusions 801b and a plurality of first recesses 802b alternately connected to each other. The second solder pad 90b has a plurality of second protrusions 901b and a plurality of second recesses 902b alternately connected to each other. The position of the first recess 802b of the first pad 80b and the position of the second recess 902b of the second pad 90b roughly correspond to the position of the hole 100b. In other words, the first solder pad 801b and the second solder pad 802b do not cover any hole 100b, and the first concave portion 802b of the first solder pad 80b and the second concave portion 902b of the second solder pad 90b surround the opening 100b. , And formed around the hole 100b so that the width of the first recess 802b of the first pad 80b or the width of the second recess 902b of the second pad 90b is greater than the diameter of any hole 100b. In an embodiment of the present invention, the plurality of first recesses 802b are substantially aligned with the plurality of second recesses 902b in the top view. In another embodiment of the present invention, the plurality of first recesses 802b are offset from the plurality of second recesses 902b in the top view.

In an embodiment of the present invention, as shown in FIG. 19, the first solder pad 80b covers the third insulating layer opening 701b, and the second solder pad 90b covers the other third insulating layer opening 702b. The three insulating layer openings 701b include a maximum width greater than one of the maximum widths of the other third insulating layer opening 702b, so that the first bonding pad 80b includes a maximum width greater than one of the maximum widths of the second bonding pad 90b. The first soldering pad 80b and the second soldering pad 90b of different sizes can facilitate the identification of the electrical properties of the corresponding connection of the soldering pads during package soldering, so as to avoid soldering to the wrong electrical soldering pads.

In an embodiment of the present invention, in the top view of the light emitting device, the third insulating layer opening 701b includes an area larger or smaller than an area of the first bonding pad 80b.

In another embodiment of the present invention, the shortest distance between the first convex portion 801b and the second convex portion 901b is smaller than the maximum distance between the first concave portion 802b and the second concave portion 902b.

In another embodiment of the present invention, the first solder pad 80b includes a first flat side 803b opposite to the first protrusion 801b and the first recess 802b, and the second solder pad 90b includes a second flat side 903b and a second flat side 903b. The convex portion 901b and the second concave portion 902b face each other. A maximum distance between the first flat side 803b of the first pad 80b and the first protrusion 801b is greater than the shortest distance between the first protrusion 801b and the second protrusion 901b. A maximum distance between the second flat side 903b of the second pad 90b and the second protrusion 901b is greater than the shortest distance between the first protrusion 801b and the second protrusion 901b.

In another embodiment of the present invention, the radius of curvature of the plurality of first concave portions 802b of the first pad 80b is different from a radius of curvature of the plurality of first convex portions 801b of the first pad 80b, such as the first pad A radius of curvature of the plurality of first concave portions 802b of 80b is larger or smaller than a radius of curvature of the plurality of first convex portions 801b of the first pad 80b. In another embodiment of the present invention, the radius of curvature of the plurality of second concave portions 902b of the second pad 90b is larger or smaller than one of the radius of curvature of the plurality of second convex portions 901b of the second pad 90b.

In another embodiment of the present invention, a radius of curvature of the first protrusion 801b of the first pad 80b is larger or smaller than a radius of curvature of the second protrusion 901b of the second pad 90b of the second pad 90b.

In another embodiment of the present invention, the plurality of first concave portions 802b of the first pad 80b are opposite to the plurality of second concave portions 902b of the second pad 90b, and one of the plurality of first concave portions 802b has a radius of curvature greater than or less than A radius of curvature of one of the plurality of second recesses 902b.

In another embodiment of the present invention, the shape of the first pad 80b is different from the shape of the second pad 90b. For example, the shape of the first pad 80b is rectangular, and the shape of the second pad 90b is comb-shaped.

In another embodiment of the present invention, the size of the first pad 80b is different from the size of the second pad 90b, for example, the area of the first pad 80b is larger than the area of the second pad 90b.

Figure 20 is a cross-sectional view of Figure 19 along AA'. The light-emitting element 3 disclosed according to this embodiment is a flip-chip light-emitting diode element. The light-emitting element 3 includes a substrate 11b; one or more semiconductor structures 1000b are located on the substrate 11b, wherein the semiconductor structure 1000b includes a semiconductor stack 10, and the semiconductor stack 1011 includes a first semiconductor layer 101b and a second semiconductor layer 102b, And an active layer 103b is located between the first semiconductor layer 101b and the second semiconductor layer 102b, the plurality of semiconductor structures 1000b are connected to each other by the first semiconductor layer 101b; a surrounding portion 111b surrounds one or more semiconductor structures 1000b, which surrounds The portion 111b exposes a first surface 1011b of the first semiconductor layer 101b; and a first bonding pad 80b and a second bonding pad 90b are located on one or more semiconductor structures 1000b. As shown in FIGS. 19 and 20, one or more semiconductor structures 1000b each include a plurality of outer sidewalls 1001b and a plurality of inner sidewalls 1002b, wherein one end of the outer sidewall 1001b is connected to a surface 102s of the second semiconductor layer 102b, The other end of the outer sidewall 1001b is connected to the first surface 1011b of the first semiconductor layer 101b; one end of the inner sidewall 1002b is connected to the surface 102s of the second semiconductor layer 102b, and the other end of the inner sidewall 1002b is connected to the second surface of the first semiconductor layer 101b. The surfaces 1012b are connected.

In an embodiment of the present invention, when the light-emitting element 3 includes one side longer than 30 mils, the light-emitting element 3 further includes one or more holes 100b passing through the second semiconductor layer 102b and the active layer 103b to expose the first semiconductor layer 101b One or more second surfaces 1012b; and a contact layer 60b is located on a first surface 1011b of the first semiconductor layer 101b to surround the circumference of the one or more semiconductor structures 1000b and contact the first semiconductor layer 101b to form an electrical connection , And formed on one or more of the second surfaces 1012b of the first semiconductor layer 101b to cover the one or more holes 100b and contact the first semiconductor layer 101b to form an electrical connection, wherein the contact layer 60b includes the first contact layer 601b and the second contact layer 602b. The first contact layer 601b is located on the second semiconductor layer, surrounds a sidewall of the second semiconductor layer, and is connected to the first semiconductor layer, and the second contact layer is located on the second semiconductor layer , And connected to the second semiconductor layer, the second contact layer 602b is surrounded by the first contact layer 601b, and the first contact layer 601b and the second contact layer 602b do not overlap each other.

In an embodiment of the present invention, when the light-emitting element 3 includes a side length of less than 30 mils, in order to obtain more light-emitting area, the light-emitting element 3 may not include any holes 100b.

In an embodiment of the present invention, in the top view of the light-emitting element 3, the total surface area of the contact layer 60b is greater than the total surface area of the active layer 103b.

In an embodiment of the present invention, in the top view of the light-emitting element 3, the total side length of the periphery of the contact layer 60b is greater than the total side length of the periphery of the active layer 103b.

In an embodiment of the present invention, in the top view of the light-emitting element 3, the first contact layer 601b includes an area larger than that of the second contact layer 602b.

In one embodiment of the present invention, the first pad 80b and the second pad 90b are formed around the opening portion 100b, so that any hole portion 100b is not covered by the first pad 80b or the second pad 90b. Covered.

In an embodiment of the present invention, under the cross-sectional view of the light-emitting element 3, the first contact layer 601b connected to the first semiconductor layer 101b is not located under the second bonding pad 90b.

In an embodiment of the present invention, the minimum distance between the first bonding pad 80b and the second bonding pad 90b is greater than 50 μm.

In an embodiment of the present invention, the distance between the first bonding pad 80b and the second bonding pad 90b is less than 300 μm.

In an embodiment of the present invention, the first bonding pad 80b and the second bonding pad 90b may be one or more structures including metal materials. The material of the first pad 80b and the second pad 90b includes metal materials, such as chromium (Cr), titanium (Ti), tungsten (W), aluminum (Al), indium (In), tin (Sn), nickel ( Ni), platinum (Pt) and other metals or alloys of the above materials. When the first solder pad 80b and the second solder pad 90b have a multilayer structure, the first solder pad 80b includes a first lower layer solder pad (not shown) and a first upper layer solder pad (not shown), and a second solder pad 90b includes a second lower layer bonding pad (not shown) and a second upper layer bonding pad (not shown). The upper layer pad and the lower layer pad have different functions. The function of the upper layer pad is mainly used for soldering and forming leads. With the upper layer pad, the light-emitting element 3 can be mounted on the mounting substrate in the form of flip chip using solder solder or AuSn eutectic bonding. The specific metal material of the upper layer pad includes highly ductile materials, such as nickel (Ni), cobalt (Co), iron (Fe), titanium (Ti), copper (Cu), gold (Au), tungsten (W), Zirconium (Zr), molybdenum (Mo), tantalum (Ta), aluminum (Al), silver (Ag), platinum (Pt), palladium (Pd), rhodium (Rh), iridium (Ir), ruthenium (Ru), Osmium (Os). The upper layer pad can be a single layer, alloy or multilayer film of the above-mentioned materials. In an embodiment of the present invention, the material of the upper layer pad preferably includes nickel (Ni) and/or gold (Au), and the upper layer pad is a single layer or multiple layers. The function of the lower layer pad is to form a stable interface with the contact layer 60b, the reflective layer 40b, or the barrier layer 41b, such as improving the bonding strength of the interface between the first lower layer pad and the contact layer 60b, or improving the second lower layer welding The bonding strength of the interface between the pad and the reflective layer 40b and/or the barrier layer 41b. Another function of the lower layer pad is to prevent the solder solder or the tin (Sn) in the AuSn eutectic from diffusing into the reflective structure and destroying the reflectivity of the reflective structure. Therefore, the lower layer pad preferably contains metal materials other than gold (Au) and copper (Cu), such as nickel (Ni), cobalt (Co), iron (Fe), titanium (Ti), tungsten (W), zirconium ( Zr), molybdenum (Mo), tantalum (Ta), aluminum (Al), silver (Ag), platinum (Pt), palladium (Pd), rhodium (Rh), iridium (Ir), ruthenium (Ru), osmium ( Os), the lower layer pad can be a single layer, alloy or multilayer film of the above materials. In an embodiment of the present invention, the lower layer pad preferably comprises a multilayer film of titanium (Ti), aluminum (Al), or a multilayer film of chromium (Cr) and aluminum (Al).

In an embodiment of the present invention, when the light-emitting element 3 is mounted on the package substrate in the form of flip chip by solder solder, there may be a height difference H between the first bonding pad 80b and the second bonding pad 90b. As shown in Figure 20, because the second insulating layer 50b under the first bonding pad 80b covers the reflective layer 40b, and the second insulating layer 50b under the second bonding pad 90b includes the second insulating layer opening 502b to expose the reflection Layer 40b or barrier layer 41b, so when the first bonding pad 80b and the second bonding pad 90b are formed in the third insulating layer opening 701b and the other third insulating layer opening 702b, the top of the first bonding pad 80b Compared with the top surface 90s of the second pad 90b, the top surface 80s of the first pad 80b is higher than the top surface 90s of the second pad 90b. In other words, there is a height difference H between the topmost surface 80s of the first bonding pad 80b and the topmost surface 90s of the second bonding pad 90b, and the height difference H between the first bonding pad 80b and the second bonding pad 90b It is approximately the same thickness as the second insulating layer 50b. In one embodiment, the height difference between the first bonding pad 80b and the second bonding pad 90b may be between 0.5 μm and 2.5 μm, for example, 1.5 μm. When the first bonding pad 80b and the second bonding pad 90b are formed in the third insulating layer opening 701b and the other third insulating layer opening 702b, the first bonding pad 80b is connected to the first insulating layer opening 701b through the third insulating layer opening 701b. When the contact layer 601b is in contact, it extends from the third insulating layer opening 701b to cover part of the surface of the third insulating layer 70b, and the second bonding pad 90b is connected to the second contact layer through another third insulating layer opening 702b. 602b is in contact with each other and extends from another third insulating layer opening 702b to cover part of the surface of the third insulating layer 70b.

FIG. 21 is a top view of the light-emitting element 4 disclosed in an embodiment of the present invention. FIG. 22 is a cross-sectional view of the light-emitting element 4 disclosed in an embodiment of the present invention. Compared with the light-emitting element 3 in the above-mentioned embodiment, the light-emitting element 4 has substantially the same structure as the light-emitting element 3, except for the structure of the first and second bonding pads. The light-emitting element 4 and the light-emitting element 3 Elements with the same label will not be repeated here. When the light-emitting element 4 is mounted on the package substrate in the form of flip chip by AuSn eutectic bonding, the height difference between the first bonding pad 80b and the second bonding pad 90b is as small as possible, so as to increase the bonding pad and the package. The stability between the substrates. As shown in Figure 22, the second insulating layer 50b under the first pad 80b covers the reflective layer 40b, and the second insulating layer 50b under the second pad 90b includes a second insulating layer opening 502b to expose the reflective layer 40b or barrier layer 41b. In this embodiment, in order to reduce the height difference between the top surface 80s of the first bonding pad 80b and the top surface 90s of the second bonding pad 90b, the third insulating layer opening 701b includes a third insulating layer with a width larger than that of the other third insulating layer. One width of the layer opening 702b. When the first bonding pad 80b and the second bonding pad 90b are formed in the third insulating layer opening 701b and the other third insulating layer opening 702b, the whole of the first bonding pad 80b is formed in the third insulating layer opening 701b to In contact with the first contact layer 601b, a second solder pad 90b is formed in another third insulating layer opening 702b in contact with the reflective layer 40b and/or barrier layer 41b, and the second solder pad 90b is formed from the third insulating layer The opening 702b extends to cover a part of the surface of the third insulating layer 70b. In other words, the third insulating layer is not formed under the first bonding pad 80b, but a part of the third insulating layer is formed under the second bonding pad 90b. In this embodiment, the height difference between the first bonding pad 80b and the second bonding pad 90b is less than 0.5 μm, preferably less than 0.1 μm, and more preferably less than 0.05 μm.

FIG. 23 is a cross-sectional view of the light-emitting element 5 disclosed in an embodiment of the present invention. Compared with the light-emitting element 3 and the light-emitting element 4 in the above embodiment, the light-emitting element 5 has substantially the same structure as the light-emitting element 3 and the light-emitting element 4 except for the structure of the second pad. Elements with the same reference numerals of the light-emitting element 3 and the light-emitting element 4 will not be repeated here. When the light emitting element 5 is mounted on the package substrate in the form of flip chip by AuSn eutectic bonding, the height difference between the first bonding pad 80b and the second bonding pad 90b is as small as possible, so as to increase the bonding pad and the package. The stability between the substrates. As mentioned above, in addition to forming part of the third insulating layer under the second bonding pad 90b, it is also possible to reduce the top surface of the first bonding pad 80b by forming a second buffer pad 910b under the second bonding pad 90b. And the height difference between the top surface of the second pad 90b. As shown in Figure 23, the second insulating layer 50b under the first bonding pad 80b covers the reflective layer 40b, and the second insulating layer 50b under the second bonding pad 90b includes a second insulating layer opening 502b to expose the reflective layer 40b or barrier layer 41b. In this embodiment, the whole of the first pad 80b is formed in the third insulating layer opening 701b to contact the first contact layer 601b, and the whole of the second pad 90b is formed in the other third insulating layer opening 702b In order to be in contact with the second contact layer 602b, in other words, the third insulating layer is not formed under the first bonding pad 80b and under the second bonding pad 90b. In this embodiment, the second buffer pad 910b located between the second pad 90b and the second contact layer 602b reduces the gap between the top surface of the first pad 80b and the top surface of the second pad 90b. Height difference, wherein the second cushion pad 910b preferably contains metal materials other than gold (Au) and copper (Cu), such as chromium (Cr), nickel (Ni), cobalt (Co), iron (Fe), titanium (Ti) ), tungsten (W), zirconium (Zr), molybdenum (Mo), tantalum (Ta), aluminum (Al), silver (Ag), platinum (Pt), palladium (Pd), rhodium (Rh), iridium (Ir) ), ruthenium (Ru), and osmium (Os) to prevent tin (Sn) in the AuSn eutectic from diffusing into the light-emitting element 5. In this embodiment, the height difference between the top surface of the first bonding pad 80b and the top surface of the second bonding pad 90b is less than 0.5 μm, preferably less than 0.1 μm, and more preferably less than 0.05 μm. In this embodiment, the second buffer pad 910b includes a thickness substantially the same as the thickness of the second insulating layer 50b.

FIG. 24 is a cross-sectional view of the light-emitting element 6 disclosed in an embodiment of the present invention. Compared with the light-emitting element 3 and the light-emitting element 4 in the above-mentioned embodiment, the light-emitting element 6 differs from the light-emitting element 3 and the light-emitting element 4 except for the structure of the third insulating layer 70b under the first pad 80b. For the structure of the light-emitting element 6 and the light-emitting element 3 and the light-emitting element 4, the elements with the same reference numbers will not be repeated here. As shown in FIG. 24, the third insulating layer 70b can be formed on the semiconductor stack 10b by evaporation or deposition, and then patterned by lithography and etching to be formed on the first contact layer 601b A third insulating layer opening 701b is used to expose the first contact layer 601b, and another third insulating layer opening 702b is formed on the second contact layer 602b to expose the second contact layer 602b. The first bonding pad 80b and the second bonding pad 90b can be formed on the semiconductor stack 10b by means of electroplating, evaporation or deposition, and then patterned by means of photolithography and etching. The first bonding pad 80b is in contact with the first contact layer 601b through the third insulating layer opening 701b, and is electrically connected to the first semiconductor layer 101b through the first contact layer 601b. In order to prevent the first contact layer 601b and the second insulating layer 50b under the first pad 80b from being over-etched and removed during the etching of the third insulating layer 70b during the etching process for forming the third insulating layer opening 701b, the reflective layer is exposed 40b and/or barrier layer 41b, thus reducing the area where the third insulating layer 70b is etched to form the third insulating layer opening 701b under the first pad 80b, leaving the first part of the third insulating layer 70b located on the first pad 80b and the first pad 80b Between a contact layer 601b and completely covered by the first bonding pad 80b, another second part of the third insulating layer 70b is located around the first bonding pad 80b, between the first part and the second part of the third insulating layer 70b The gap therebetween constitutes the third insulating layer opening 701b. Specifically, the first part of the third insulating layer 70b completely covered by the first bonding pad 80b includes a width greater than the width of the third insulating layer opening 701b under the bonding pad 80b. In this embodiment, in the top view of the light-emitting element, the third insulating layer opening 701b is a ring-shaped opening.

FIG. 25 is a schematic diagram of a light-emitting device according to an embodiment of the present invention. The semiconductor light-emitting element 1, light-emitting element 2, light-emitting element 3, light-emitting element 4, light-emitting element 5, or light-emitting element 6 in the foregoing embodiment are mounted on the first pad 511 and the second pad 511 of the package substrate 51 in the form of a flip chip. On the gasket 512. The first gasket 511 and the second gasket 512 are electrically insulated by an insulating portion 53 containing an insulating material. In the flip-chip mounting system, one side of the growth substrates 11a, 11b facing the electrode formation surface is used as the main light extraction surface. In order to increase the light extraction efficiency of the light-emitting device, a reflective structure 54 can be provided around the semiconductor light-emitting element 1, the light-emitting element 2, the light-emitting element 3, the light-emitting element 4, the light-emitting element 5, or the light-emitting element 6.

FIG. 26 is a schematic diagram of a light-emitting device according to an embodiment of the present invention. A bulb lamp 600 includes a lampshade 602, a reflector 604, a light-emitting module 610, a lamp holder 612, a heat sink 614, a connecting portion 616, and an electrical connecting element 618. The light-emitting module 610 includes a supporting portion 606, and a plurality of light-emitting elements 608 are located on the supporting portion 606, wherein the plurality of light-emitting elements 608 can be the semiconductor light-emitting element 1, the light-emitting element 2, the light-emitting element 3, and the light-emitting element in the foregoing embodiment. 4. Light-emitting element 5 or light-emitting element 6.

The embodiments listed in the present invention are only used to illustrate the present invention, and are not used to limit the scope of the present invention. Any obvious modification or alteration made to the present invention by anyone does not depart from the spirit and scope of the present invention.

1, 2, 3, 4, 5, 6: light-emitting element 11a, 11b: substrate 10a, 10b: Semiconductor stack 101a, 101b: the first semiconductor layer 102a, 102b: second semiconductor layer 103a, 103b: active layer 100a, 100b: hole 102s: surface 1011a, 1011b: first surface 1012a, 1012b: second surface 110a: fourth insulating layer 111a, 111b: Surrounding part 20a, 20b: first insulating layer 200a, 200b: Surrounding area of the first insulating layer 201a, 201b: Covered area of the first insulating layer 202a, 202b: first insulating layer opening 203a, 203b: first insulating layer opening 30a, 30b: transparent conductive layer 300b: Transparent conductive layer opening 301a, 301b: outer edge of transparent conductive layer 40a, 40b: reflective layer 400b: Reflective layer opening 401a, 401b: outer edge of reflective layer 41a, 41b: barrier layer 410b: Barrier layer opening 411a, 411b: outer edge of barrier layer 50a, 50b: second insulating layer 501a, 501b: second insulating layer opening 502a, 502b: second insulating layer opening 5020b: ring opening 5021b: sidewall 60a, 60b: contact layer 600a, 600b: thimble area 602a: contact layer opening 601b: first contact layer 6011b: first contact layer sidewall 602b: second contact layer 6021b: Sidewall of the second contact layer 70a, 70b: third insulating layer 701a, 702a: third insulating layer opening 701b, 702b: third insulating layer opening 80a, 80b: the first pad 90a, 90b: the second pad 800a: the first pad opening 801b: the first convex part 802a: first side 802b: The first recess 803b: The first flat side 804a: The first recess 805a: The first upper layer pad 807a: the first lower layer pad 810a: The first cushion 900a: The second pad opening 901b: second convex part 902a: second side 902b: second recess 903b: second flat side 904a: second recess 905a: The second upper layer pad 907a: The second lower layer pad 910a, 910b: second cushion 1000a, 1000b: semiconductor structure 1001a, 1001b: second outer wall 1002a, 1002b: inner wall 1003a, 1003b: the first outer side wall 51: Package substrate 511: first gasket 512: second gasket 53: Insulation 54: reflective structure 600: Bulb light 602: Lampshade 604: Mirror 606: Bearing Department 608: light-emitting element 610: Light-emitting module 612: Lamp holder 614: heat sink 616: connection part 618: Electrical connection element

Figures 1A to 7C show the manufacturing method of the light-emitting element 1 or the light-emitting element 2 disclosed in an embodiment of the present invention.

FIG. 8 is a top view of the light-emitting element 1 disclosed in an embodiment of the present invention.

FIG. 9A is a cross-sectional view of the light-emitting device 1 disclosed in an embodiment of the present invention.

FIG. 9B is a cross-sectional view of the light-emitting device 1 disclosed in an embodiment of the present invention.

FIG. 10 is a top view of the light-emitting element 2 disclosed in an embodiment of the present invention.

FIG. 11A is a cross-sectional view of the light-emitting element 2 disclosed in an embodiment of the present invention.

FIG. 11B is a cross-sectional view of the light-emitting element 2 disclosed in an embodiment of the present invention.

Figures 12A to 18B show the method of manufacturing the light-emitting element 3 or the light-emitting element 4 disclosed in an embodiment of the present invention.

Fig. 19 is a top view of the light-emitting element 3 disclosed in an embodiment of the present invention.

FIG. 20 is a cross-sectional view of the light-emitting element 3 disclosed in an embodiment of the present invention.

FIG. 21 is a top view of the light-emitting element 4 disclosed in an embodiment of the present invention.

FIG. 22 is a cross-sectional view of the light-emitting element 4 disclosed in an embodiment of the present invention.

FIG. 23 is a cross-sectional view of the light-emitting element 5 disclosed in an embodiment of the present invention.

FIG. 24 is a cross-sectional view of the light-emitting element 6 disclosed in an embodiment of the present invention.

FIG. 25 is a schematic diagram of the structure of a light-emitting device according to an embodiment of the present invention.

FIG. 26 is a schematic diagram of the structure of a light-emitting device according to an embodiment of the present invention.

1: Light-emitting element

11a: substrate

10a: Semiconductor stack

101a: the first semiconductor layer

102a: second semiconductor layer

103a: active layer

100a: Hole

1011a: first surface

1012a: second surface

111a: Surrounding part

20a: first insulating layer

30a: Transparent conductive layer

40a: reflective layer

41a: Barrier layer

50a: second insulating layer

60a: contact layer

70a: third insulating layer

80a: the first pad

90a: second pad

600a: thimble area

800a: the first pad opening

900a: The second pad opening

805a: The first upper layer pad

807a: the first lower layer pad

905a: The second upper layer pad

907a: The second lower layer pad

1000a: semiconductor structure

1003a: the first outer side wall

1001a: second outer wall

1002a: inner wall

Claims (10)

A light-emitting element, including: A substrate with a centerline; A semiconductor stack having a first semiconductor layer, a second semiconductor layer, and an active layer located between the first semiconductor layer and the second semiconductor layer; A plurality of holes passing through the second semiconductor layer and the active layer to expose the first semiconductor layer; A first contact layer covering the plurality of holes; A second contact layer located on the second semiconductor layer; A first bonding pad is located on the semiconductor stack to contact the first contact layer, form an electrical connection with the first semiconductor layer, and is located on one side of the center line of the substrate; and A second bonding pad is located on the semiconductor stack to contact the second contact layer, form an electrical connection with the second semiconductor layer, and is located on the other side of the center line of the substrate, the first bonding pad is connected to the The second bonding pads are separated by a distance, and a region is defined on the semiconductor stack to be located between the first bonding pad and the second bonding pad, wherein in a top view of the light emitting element, the plurality of holes It includes two adjacent holes in the same row, a first shortest distance between the two adjacent holes, the plurality of holes further includes a hole adjacent to the edge of the light-emitting element, the hole and the first A second shortest distance is included between the first outer sidewalls of the semiconductor layer, wherein the first shortest distance is greater than the second shortest distance. A light-emitting element, including: A substrate with a centerline; A semiconductor stack having a first semiconductor layer, a second semiconductor layer, and an active layer located between the first semiconductor layer and the second semiconductor layer; A plurality of holes passing through the second semiconductor layer and the active layer to expose the first semiconductor layer; A first contact layer covering the plurality of holes; A second contact layer located on the second semiconductor layer; A first bonding pad is located on the semiconductor stack to contact the first contact layer, form an electrical connection with the first semiconductor layer, and is located on one side of the center line of the substrate; and A second bonding pad is located on the semiconductor stack to contact the second contact layer, form an electrical connection with the second semiconductor layer, and is located on the other side of the center line of the substrate, the first bonding pad is connected to the The second bonding pads are separated by a distance, and a region is defined on the semiconductor stack to be located between the first bonding pad and the second bonding pad, wherein in a top view of the light emitting element, the plurality of holes It includes two adjacent holes in the same row, a first shortest distance between the two adjacent holes, the plurality of holes further includes a hole adjacent to the edge of the light-emitting element, the hole and the first A second shortest distance is included between the first outer sidewalls of the semiconductor layer, wherein the first shortest distance is less than or equal to the second shortest distance. A light-emitting element, including: A substrate with a centerline; A semiconductor stack having a first semiconductor layer, a second semiconductor layer, and an active layer located between the first semiconductor layer and the second semiconductor layer; A plurality of holes passing through the second semiconductor layer and the active layer to expose the first semiconductor layer; A first contact layer covering the plurality of holes; A second contact layer located on the second semiconductor layer; A first bonding pad is located on the semiconductor stack to contact the first contact layer, form an electrical connection with the first semiconductor layer, and is located on one side of the center line of the substrate; and A second bonding pad is located on the semiconductor stack to contact the second contact layer, form an electrical connection with the second semiconductor layer, and is located on the other side of the center line of the substrate, the first bonding pad is connected to the The second bonding pads are separated by a distance, and a region is defined on the semiconductor stack to be located between the first bonding pad and the second bonding pad, wherein in a top view of the light emitting element, the plurality of holes Arranged in a plurality of rows, the plurality of rows includes a first row and a second row, a first shortest distance between two adjacent holes in the same row, and the hole in the first row and the hole in the first row A second shortest distance is included between the holes on the second row, wherein the first shortest distance is greater than or less than the second shortest distance. A light-emitting element, including: A substrate with a centerline; A semiconductor stack having a first semiconductor layer, a second semiconductor layer, and an active layer located between the first semiconductor layer and the second semiconductor layer; A plurality of holes passing through the second semiconductor layer and the active layer to expose the first semiconductor layer; A first contact layer covering the plurality of holes; A second contact layer located on the second semiconductor layer; A first bonding pad is located on the semiconductor stack to contact the first contact layer, form an electrical connection with the first semiconductor layer, and is located on one side of the center line of the substrate; and A second bonding pad is located on the semiconductor stack to contact the second contact layer, form an electrical connection with the second semiconductor layer, and is located on the other side of the center line of the substrate, the first bonding pad is connected to the The second bonding pads are separated by a distance, and a region is defined on the semiconductor stack to be located between the first bonding pad and the second bonding pad, wherein in a top view of the light emitting element, the plurality of holes Arranged in a plurality of rows, the plurality of rows includes a first row, a second row, and a third row. The holes located in the first row and the holes located in the second row include a first shortest The distance includes a second shortest distance between the holes on the second row and the holes on the third row, and the first shortest distance is smaller than the second shortest distance. The light-emitting element described in item 1, 2, 3, or 4 of the scope of patent application further includes a surrounding portion surrounding the semiconductor stack, wherein the surrounding portion exposes the first semiconductor stack, and the first contact layer covers The surrounding part. According to the light-emitting device described in item 1, 2, 3, or 4 of the scope of patent application, in a cross-sectional view of the light-emitting device, the first contact layer is not located under the second bonding pad. According to the light-emitting element described in item 1, 2, 3 or 4 of the scope of patent application, in the top view of the light-emitting element, the area of the first contact layer is larger than the area of the second contact layer. According to the light-emitting element described in item 1, 2, 3, or 4 of the scope of patent application, the first contact layer and the second contact layer do not overlap each other. According to the light-emitting element described in item 1, 2, 3 or 4 of the scope of patent application, in the top view of the light-emitting element, the first contact layer surrounds the second contact layer. A light-emitting device includes the light-emitting element described in any one of items 1 to 9 in the scope of the patent application, and further includes a packaging substrate, a first gasket and a second gasket, wherein the light-emitting element is a flip chip The form is mounted on the first gasket and the second gasket of the packaging substrate.

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