TW202111877A - Method for producing semiconductor device, semiconductor device and production system - Google Patents

Abstract

A method for producing a semiconductor device according to the present invention comprises a hole formation step, a first embedding step, a first stacking step, and a second embedding step. In the hole formation step, a hole is formed in a region where an electrode that is to be connected to a capacitor is formed, said region being adjacent to a bit line, with a spacer layer being interposed therebetween. In the first embedding step, a first electroconductive material is embedded in the bottom part of the hole. In the first stacking step, a barrier film containing an alignment control film is superposed on the lateral wall of the hole. In the second embedding step, an electrode is formed within the hole by embedding a second electroconductive material within the hole where the barrier film has been superposed.

Description

Semiconductor device manufacturing method, semiconductor device and manufacturing system

The present invention relates to a method for manufacturing a semiconductor device, a semiconductor device and a manufacturing system.

In semiconductor devices such as DRAM (Dynamic Random Access Memory, dynamic random access memory), either the source or drain of the transistor is connected to a capacitor as a storage node via a storage node contact (SNC). Either the source or the drain of the transistor is connected to the bit line. Around the SNC, barrier metal is provided in order to prevent the diffusion of the metal contained in the SNC. [Prior Technical Literature] [Patent Literature]

[Patent Document 1] Specification of U.S. Patent Application Publication No. 2016/0211215

[The problem to be solved by the invention]

The present invention provides a method for manufacturing a semiconductor device, a semiconductor device, and a manufacturing system that can reduce the resistance of SNC. [Technical means to solve the problem]

A method of manufacturing a semiconductor device in one aspect of the present invention includes a hole formation process, a first embedding process, a first build-up process, and a second embedding process. In the hole formation process, a hole is formed in the area between the spacer layer and the bit line adjacent to the area where the electrode connected to the capacitor is formed. In the first embedding process, the first conductive material is embedded at the bottom of the electric hole. In the first build-up process, a barrier film including an alignment control film is build-up on the sidewall of the hole. In the second embedding process, the second conductive material is embedded in the holes with the barrier film layered, thereby forming electrodes in the holes. [Effects of Invention]

According to various aspects and embodiments of the present invention, the resistance value of SNC can be reduced.

Hereinafter, embodiments of the disclosed semiconductor device manufacturing method, semiconductor device, and manufacturing system will be described in detail based on the drawings. Furthermore, the manufacturing method of the semiconductor device, the semiconductor device, and the manufacturing system disclosed in the following embodiments are not limited.

However, as the miniaturization of semiconductor devices such as DRAM is progressing day by day, CD (Critical Dimension) for forming SNC holes tends to become smaller. Since it is difficult to reduce the thickness of the barrier metal provided around the SNC, if the CD for forming the holes of the SNC becomes smaller, the CD of the SNC must be reduced. If the CD of the SNC decreases, the resistance value of the SNC increases, heat generation increases, and power consumption increases.

In this regard, the present invention provides a technology that can reduce the resistance of SNC.

(First embodiment) [Method of Manufacturing Semiconductor Device] FIG. 1 is a flowchart showing an example of a method of manufacturing a semiconductor device according to the first embodiment of the present invention. The main processing illustrated in FIG. 1 is implemented by, for example, the manufacturing system 10 shown in FIG. 2.

[Configuration of Manufacturing System 10] FIG. 2 is a diagram showing an example of the manufacturing system 10. The manufacturing system 10 is, for example, a multi-chamber system as shown in FIG. 2, and includes a transfer chamber 11, an etching device 20, a plurality of film forming devices 21 to 23, a load lock vacuum chamber 30, and a control device 80. The etching device 20 performs an etching process on the substrate 100 under a predetermined reduced pressure atmosphere. Each of the film forming apparatuses 21 to 23 forms a predetermined film on the substrate 100 under a predetermined reduced pressure atmosphere.

The film forming apparatus 21 is an example of a first film forming apparatus, the film forming apparatus 22 is an example of a second film forming apparatus, and the film forming apparatus 23 is an example of a third film forming apparatus. Furthermore, one etching device and three film forming devices are provided in the manufacturing system 10 of this embodiment, but the number of etching devices and film forming devices is not limited to this. For example, in the manufacturing system 10, two or more etching devices can be installed, and two or less or more than four film forming devices can also be installed.

The etching device 20 and the film forming devices 21 to 23 are connected to the transfer chamber 11 via a gate valve G, respectively. In this embodiment, the planar shape of the transfer chamber 11 is a pentagon, and any one of the etching device 20 and the film forming devices 21 to 23 is connected to each of the four side surfaces of the transfer chamber 11 via a gate valve G. In addition, the load lock vacuum chamber 30 is connected to one side surface of the transfer chamber 11 via a gate valve G.

A predetermined decompression environment is maintained in the transfer chamber 11, and a transfer device 70 that transfers the substrate 100 is installed in the transfer chamber 11. The conveying device 70 has an arm 71 and a placing part 72. The substrate 100 is placed on the placing portion 72. The support arm 71 supports the mounting portion 72. Furthermore, the support arm 71 moves the substrate 100 between the etching apparatus 20, the film forming apparatuses 21 to 23, and the load lock vacuum chamber 30 by moving the placing portion 72.

The side surface of the load lock vacuum chamber 30 opposite to the side surface to which the transfer chamber 11 is connected is connected to the transfer chamber 60 via a gate valve G. A plurality of carriers 50 accommodating the substrate 100 are connected to the transfer chamber 60. A transfer device 61 is provided in the transfer chamber 60. The transfer device 61 removes the substrate 100 from the carrier 50 and transfers it to the load lock vacuum chamber 30, and removes the substrate 100 from the load lock vacuum chamber 30 and transfers it to the carrier 50.

The control device 80 has a memory, a processor, and an input and output interface. The processor reads and executes the program or formula stored in the memory, thereby controlling each part of the manufacturing system 10 through the input and output interface. The processing illustrated in FIG. 1 is realized by the control device 80 controlling each part of the manufacturing system 10.

In addition, before the processing illustrated in FIG. 1, the substrate 100 illustrated in FIG. 3 is prepared, for example. On the substrate 100, a plurality of semiconductor devices are formed by the process illustrated in FIG. 1. FIG. 3 is a cross-sectional view showing an example of the substrate 100 of the first embodiment. The prepared substrate 100 has a BLC (Bit Line Contact) 101, a BL (Bit Line) 102, an insulating film 103, a sacrificial film 104, an insulating film 105, and a sacrificial film 106. The BLC101 is connected to the working area that constitutes either the source or the drain of the transistor not shown. BL102 is installed on BLC101 and connected to BLC101. BLC101 and BL102 are covered with an insulating film 103. In this embodiment, the insulating film 103 is, for example, a SiN film.

Between the insulating film 103 and the insulating film 105, a sacrificial film 104 is provided. In the area of the sacrificial film 104, an air gap is formed by removing the sacrificial film 104 in the process described later. The sacrificial film 104 is an example of a spacer layer. In this embodiment, the sacrificial film 104 can be an oxide film such as a silicon oxide (SiO) film. In this embodiment, the insulating film 105 is, for example, a silicon nitride (SiN) film.

Between adjacent insulating films 105, a sacrificial film 106 is provided. The sacrificial film 106 is disposed on the working area of either the source electrode or the drain electrode of the transistor which is not shown in the figure. In this embodiment, the sacrificial film 106 is, for example, SOD (Spin On Dielectric), such as SiO.

Return to Figure 1 to continue the description. Hereinafter, with reference to FIGS. 4 to 7 and FIGS. 9 to 10, an example of the manufacturing process of the semiconductor device of the first embodiment will be described. FIGS. 4 to 7 and FIGS. 9 to 10 are diagrams showing an example of the manufacturing process of the semiconductor device of the first embodiment.

First, for example, the carrier 50 containing the substrate 100 shown in FIG. 3 is connected to the transfer chamber 60, and the substrate 100 is carried out from the carrier 50 and into the load lock vacuum chamber 30 by the transfer device 61 in the transfer chamber 60 . Then, the substrate 100 is transported out of the load lock vacuum chamber 30 by the transport device 70 in the transport chamber 11 and carried into the etching device 20. Then, the sacrificial film 106 is removed by the etching device 20, thereby forming a hole in the area of the substrate 100 where the SNC is formed (S10). Thereby, for example, as shown in FIG. 4, in the area of the substrate 100 where the SNC is formed, a hole 107 with a CD of ΔW1 is formed. Step S10 is an example of the hole formation process. Then, the substrate 100 is carried out from the etching apparatus 20 by the transport apparatus 70 and carried into the film forming apparatus 21.

Next, with the film forming device 21, a conductive material is embedded in the bottom of the hole 107 (S11). In this way, as shown in FIG. 5, for example, the conductive material 108 is embedded at the bottom of the hole 107. The conductive material 108 is connected to the working area of either the source electrode or the drain electrode of the transistor which is not shown in the figure. The conductive material 108 embedded in step S11 is an example of the first conductive material, such as polysilicon. The electrode formed by the conductive material 108 embedded in step S11 is an example of the second electrode. Step S11 is an example of the first embedding process.

Next, by the film forming apparatus 21, an electrode film is formed on the upper surface of the conductive material 108 (S12). Thereby, for example, as shown in FIG. 6, an electrode film 109 is laminated on the upper surface of the conductive material 108 in the hole 107. In this embodiment, the electrode film 109 is, for example, cobalt silicide. Then, the substrate 100 is carried out from the film forming apparatus 21 by the conveying device 70 and carried into the film forming apparatus 22.

Next, by the film forming device 22, a barrier film 110 is formed on the sidewall of the hole 107 and the electrode film 109 in the hole 107 (S13). Step S13 is an example of the first build-up process. Thereby, for example, as shown in FIG. 7, a barrier film 110 is laminated in the hole 107. Then, the substrate 100 is carried out from the film forming apparatus 22 by the conveying device 70 and carried into the film forming apparatus 23.

FIG. 8 is an enlarged cross-sectional view showing an example of the structure of the barrier film 110. As shown in FIG. The barrier film 110 includes a first barrier film 111 and a second barrier film 112. In this embodiment, the first barrier film 111 is, for example, titanium nitride (TiN), and the second barrier film 112 is, for example, aluminum nitride (AlN). Furthermore, the first barrier film 111 may be, for example, TiON, TiSiN, or TaN, and the second barrier film 112 may be, for example, TiAlN, WN, or WSi.

In step S13, a first barrier film 111 is laminated on the sidewall of the hole 107 and the electrode film 109 in the hole 107, for example, by ALD (Atomic Layer Deposition), and on the first barrier film 111, for example, The second barrier film 112 is laminated by ALD. In this embodiment, the thickness of the first barrier film 111 is, for example, 0.3 to 1.5 [nm], and the thickness of the second barrier film 112 is, for example, 0.5 to 1.5 [nm].

In ALD, the ALD cycle including the adsorption process, the first rinse process, the reaction process, and the second rinse process is repeated multiple times. In the adsorption process, the precursor gas is supplied to the area on the surface of the target substrate 100, whereby molecules of the precursor gas are adsorbed to the area on the surface of the target substrate 100. In the first rinsing process, an inert gas is supplied to the surface of the substrate 100, thereby removing excess molecules of the precursor gas adsorbed on the surface of the substrate 100. During the reaction process, a reactive gas is supplied to the surface of the substrate 100, thereby causing the molecules of the precursor gas adsorbed on the surface of the substrate 100 to react with the molecules of the reactive gas to form a desired area on the surface of the substrate 100 to be the target的膜。 The film. In the second rinsing process, an inert gas is supplied to the surface of the substrate 100, thereby removing molecules of the reactive gas excessively supplied to the surface of the substrate 100.

The main processing conditions in the case where TiN is laminated as the first barrier film 111 are, for example, as follows. Precursor gas: TiCl ₄ ＝50～500[sccm] Purge gas: N ₂ ＝1000～10000[sccm] Reaction gas: NH ₃ ＝300～3000[sccm] Temperature: 300～600[℃] ALD cycle time: 0.3～10[sec/cycle] Repeat times: 10～100[times]

Furthermore, as the precursor gas, other than TDMAT (tetrakis (dimethylamino) titanium) or TMEAT (tetrakis (methylethylamino) titanium), for example, other titanium-containing gases may also be used. In addition, as the reaction gas, _{other nitrogen-containing gases may be used in addition to, for example, N 2} , hydrazine, MMH (monomethylhydrazine), and the like.

The main processing conditions in the case where the laminated AlN is used as the second barrier film 112 are, for example, as follows. Precursor gas: AlCl ₃ ＝10～500[sccm] Purge gas: N ₂ ＝1000～10000[sccm] Reactive gas: NH ₃ ＝1000～10000[sccm] Temperature: 250～550[℃] ALD cycle time: 0.2～20[sec/cycle] Repeat times: 1～10[times]

In addition, as the precursor gas, in addition to TMA (trimethyl aluminum) and the like, other aluminum-containing gases may also be used. In addition, as the reaction gas, _{other nitrogen-containing gases may be used in addition to, for example, N 2} , hydrazine, MMH (monomethylhydrazine), and the like.

Next, by the film forming device 23, an initial film that becomes an electrode of the SNC is formed on the barrier film 110 (S14). In this way, for example, as shown in FIG. 9, the initial film 120 is laminated on the barrier film 110. The initial film 120 is also referred to as a nucleation film. The initial film 120 promotes the crystallization of the electrode material laminated on the initial film 120 in the subsequent manufacturing process.

In this embodiment, the initial film 120 is formed by, for example, ALD. The main processing conditions for forming the initial film 120 are, for example, as follows. Precursor gas: WF ₆ ＝10～1000[sccm] Flushing gas: N ₂ ＝1000～10000[sccm] Reaction gas: B ₂ H ₆ ＝10～1000[sccm] Temperature: 150～450[℃] ALD cycle Time: 0.2～60[sec/cycle] Number of repetitions: 1～20[times]

Furthermore, as the precursor gas, other tungsten-containing gases may be used in _{addition to, for example, WCl 6 or the like.} In addition, as the reaction gas, other boron-containing gases may be used in _{addition to, for example, BCl 3 gas.}

In this embodiment, the thickness of the initial film 120 is, for example, 0.2 to 0.3 [nm]. Therefore, in this embodiment, the total thickness of the barrier film 110 and the initial film 120 is, for example, 2.5 to 3.0 [nm].

Next, by the film forming device 23, a main film that becomes an electrode of the SNC is formed on the initial film 120 (S15). Step S15 is an example of the second embedding process. Thereby, as shown in FIG. 10, for example, the main film 121 that becomes the electrode of the SNC is embedded in the hole 107. In this embodiment, the main film 121 of the electrode is, for example, tungsten. Furthermore, the main film 121 of the electrode can also be ruthenium, copper, molybdenum, titanium, or the like. The main film 121 is an example of a second conductive material. The electrode formed by the main film 121 embedded in step S15 is an example of the first electrode.

In this embodiment, the main film 121 is embedded in the hole 107 by, for example, ALD. The main processing conditions at the time of film formation of the main film 121 are, for example, as follows. Precursor gas: WF ₆ ＝100～1000[sccm] Flushing gas: N ₂ ＝1000～10000[sccm] Reaction gas: H ₂ ＝5000～10000[sccm] Temperature: 300～600[℃] ALD cycle time: 0.3～3.0[sec/cycle] Repeat times: 100～1000[times]

Next, a bonding pad connected to the main film 121 is formed (S16). In step S16, a conductive material such as tungsten is deposited on the main film 121 by the film forming device 23. The substrate 100 on which the conductive material is laminated is carried out from the film forming apparatus 23 by the transport device 70 and carried into the load lock vacuum chamber 30. Then, the substrate 100 is transported out of the load lock vacuum chamber 30 by the transport device 61 in the transport chamber 60 and stored in the carrier 50.

Next, an air gap is formed between the BL 102 and the main film 121 that becomes the SNC (S17). In step S17, the carrier 50 is set in an etching device not shown, and the substrate 100 taken out from the carrier 50 is carried into the etching device. In addition, the sacrificial film 104 between the insulating film 103 and the insulating film 105 is removed by an etching device, and the opening of the air gap 130 is sealed. As a result, as shown in FIG. 11, for example, an air gap 130 with a CD of ΔW3 is formed between the BL 102 and the main film 121 that becomes the electrode of the SNC. FIG. 11 is a cross-sectional view showing an example of the semiconductor device of the first embodiment. Then, the manufacturing method of the semiconductor device shown in this flowchart ends. Furthermore, in FIG. 11, the illustration of the solder pad connected to the main film 121 and the sealing portion of the air gap 130 is omitted.

Here, the barrier film 110 of this embodiment includes a first barrier film 111 as a TiN film and a second barrier film 112 as an AlN film. The AlN film has higher barrier properties to metals (such as tungsten) than the TiN film. Therefore, when the desired barrier property to metal is ensured, the barrier film 110 including the AlN film can be thinner than the barrier film not including the AlN film.

In the case of using a barrier film 140 that does not include an AlN film but is composed of only a TiN film, for example, as shown in FIG. 12, the barrier film 140 must be thicker than the barrier film 110 in this embodiment. FIG. 12 is a cross-sectional view showing an example of a semiconductor device of a comparative example. In the comparative example, the total thickness of the barrier film 140 and the initial film 141 of the electrode is, for example, 4 [nm]. Therefore, in the comparative example, for example, as shown in FIG. 12, the CD of the main film 142 that becomes the SNC becomes ΔW2' which is smaller than ΔW1, for example, 8 [nm].

In the DRAM of the 14 nm generation, ΔW1 is predicted to be around 16.3 [nm]. If ΔW1 becomes approximately 16.3 [nm], ΔW2' of the comparative example becomes 8.3 [nm]. If the depth of the main film 142 is assumed to be 60 [nm], the contact resistance value of the main film 142 of the comparative example becomes 495.5 [Ω].

In contrast, the total thickness of the barrier film 110 and the initial film 120 of this embodiment is, for example, 1 to 1.5 [nm]. Therefore, for example, as shown in FIG. 11, the CD of the main film 121 that becomes the SNC becomes ΔW2 which is smaller than ΔW1, for example, 2 to 3 [nm]. If ΔW1 is assumed to be 16.3 [nm], ΔW2 becomes, for example, 13 to 14 [nm]. If the depth of the main film 142 is assumed to be 60 [nm], the contact resistance value of the main film 121 of this embodiment becomes approximately 167 [Ω]. That is, the contact resistance value of SNC can be reduced by approximately 66% compared with the comparative example. Furthermore, when titanium is used for the conductive material 108, the first barrier film 111 may not be provided. In this case, the barrier film 110 can be made thinner, so the contact resistance of the main film 121 can be further reduced.

Furthermore, in the barrier film 110 of this embodiment, the second barrier film 112 as an AlN film is laminated on the first barrier film 111 as a TiN film. Thereby, the alignment of the TiN film is eliminated, and the grain size of the initial film 120 laminated on the barrier film 110 can be increased. If the grain size of the initial film 120 becomes larger, the grain size of the main film 121 laminated on the initial film 120 also becomes larger. The second barrier film 112 is an example of an alignment control film.

FIG. 13 is a diagram showing an example of the resistance value of the electrode material with respect to the film thickness. In FIG. 13, the resistance value of the main tungsten film is shown when there is an AlN film between the TiN film and the initial tungsten film, and when there is no AlN film. It can be seen from FIG. 13 that the resistance value when there is an AlN film between the TiN film and the initial tungsten film is more than 35% lower than when there is no AlN film. It is believed that this is because the AlN film is interposed between the TiN film and the tungsten initial film, so the grain size of the tungsten initial film and the main film laminated on the AlN film becomes larger.

In this way, in the semiconductor device of the present embodiment, compared with the comparative example, the CD of the main film 121 that becomes the electrode of the SNC can be increased, and the crystal grain size of the main film 121 can be increased. Therefore, compared with the comparative example, the contact resistance of the main film 121 which becomes the electrode of SNC can be reduced. Thereby, it is possible to reduce the increase in heat generation or power consumption of the semiconductor device.

The first embodiment has been described above. As described above, the manufacturing method of the semiconductor device of this embodiment includes the hole formation process, the first embedding process, the first build-up process, and the second embedding process. In the hole formation process, a hole 107 is formed in a region separating the sacrificial film 104 and the region adjacent to the BL 102 and forming an electrode connected to the capacitor. In the first embedding process, the conductive material 108 is embedded at the bottom of the hole 107. In the first build-up process, a barrier film 110 including an alignment control film is stacked on the sidewall of the hole 107. In the second embedding process, by embedding the main film 121 in the hole 107 laminated with the barrier film 110, the electrode that becomes the SNC is formed in the BL 102. In this way, the resistance value of SNC can be reduced.

Furthermore, in the first embodiment described above, the barrier film 110 includes the first barrier film 111 and the second barrier film 112 as the alignment control film. In the first build-up process, a first barrier film 111 is laminated on the sidewall of the hole 107, and a second barrier film 112 is laminated on the first barrier film 111. Thereby, the main film 121 with a larger grain size can be formed.

Furthermore, in the first embodiment described above, the first barrier film 111 is, for example, TiN, TiON, TiSiN, TaN, or the like. Thereby, the diffusion of the metal contained in the main film 121 can be prevented.

In addition, in the first embodiment described above, the second barrier film 112 is, for example, AlN, TiAlN, WN, WSi, or the like. Thereby, the diffusion of the metal contained in the main film 121 can be prevented, and the crystal grain size of the main film 121 can be increased.

In addition, the semiconductor device of the first embodiment described above includes a conductive material 108, a barrier film 110, and a main film 121 of electrodes. The conductive material 108 is embedded in the bottom of the hole 107 formed in the area separating the air gap 130 and the adjacent area of the BL102 and for forming the main film 121 of the electrode connected to the capacitor. The barrier film 110 is laminated on the sidewall of the hole 107 on the conductive material 108 and includes an alignment control film. The main film 121 of the electrode is embedded in the hole 107, and the hole 107 is laminated with a barrier film 110 laminated on the sidewall.

Furthermore, the manufacturing system of the first embodiment described above includes an etching device 20, a film forming device 21, a film forming device 22, a film forming device 23, and a control device 80. The control device 80 performs the following processing: using the etching device 20, a hole 107 is formed in a region where the sacrificial film 104 and the BL 102 are adjacent to each other and for forming an electrode connected to the capacitor. In addition, the control device 80 performs the following processing: using the film forming device 21, the conductive material 108 is embedded in the bottom of the hole 107. In addition, the control device 80 executes the following processing: using the film forming device 22, a barrier film 110 including an alignment control film is laminated on the sidewall of the hole 107. In addition, the control device 80 performs the following process: using the film forming device 23, the main film 121 of the electrode is embedded in the hole 107 with the barrier film 110 laminated thereon, thereby forming the SNC electrode in the hole 107.

(Second embodiment) In the first embodiment described above, the barrier film 110 thinner than the comparative example is used, thereby increasing the CD of the main film 121 that becomes the SNC compared to the comparative example. In contrast, in this embodiment, a part of the increase in the CD of the SNC caused by the use of the barrier film 110 thinner than the comparative example is allocated to the CD of the spacer layer between the SNC and the BL102. Thereby, a spacer layer having a dielectric constant equal to or lower than that of the air gap of the first embodiment can be realized by a structure other than the air gap. Thereby, the process of forming the air gap is not required, the number of manufacturing processes of the semiconductor device can be reduced, and the yield of the semiconductor device can be improved.

[Method of Manufacturing Semiconductor Device] FIG. 14 is a flowchart showing an example of a method of manufacturing a semiconductor device according to the second embodiment of the present invention. The main processing illustrated in FIG. 14 is realized by, for example, the manufacturing system 10 shown in FIG. 2.

In this embodiment, before the processing illustrated in FIG. 14, for example, the substrate 100 illustrated in FIG. 15 is prepared. FIG. 15 is a cross-sectional view showing an example of the substrate 100 of the second embodiment. The prepared substrate 100 has BLC101, BL102, an insulating film 103, an insulating film 105, a sacrificial film 106, a low-k (low dielectric constant) film 150, and a low-k film 151. The BLC101 is connected to the working area that constitutes either the source or the drain of the transistor not shown. BL102 is installed on BLC101 and connected to BLC101. The insulating film 103 is provided on the BL102. Low-k films 150 are provided on both sides of BLC101, BL102 and insulating film 103. In this embodiment, the insulating film 103 is, for example, a SiN film.

The low-k film 150 is made of a material having a dielectric constant lower than that of the SiN film (for example, k=4 or less). In this embodiment, the low-k film 150 is, for example, SiCN. Furthermore, the low-k film 150 may also be SiOCN, SiOC, or the like, for example.

Between the low-k film 150 and the insulating film 105, a low-k film 151 is provided. The low-k film 151 is an example of a spacer layer. The CD of the low-k film 151 is larger than the CD of the air gap 130 of the first embodiment, which is ΔW3" (refer to FIG. 11). The low-k film 151 is made of a material with a dielectric constant lower than that of the SiN film (for example, k=4 or less) ) Configuration. In this embodiment, the low-k film 151 is, for example, SiO. In addition, the low-k film 151 may be, for example, SiOCN or SiOC. In this embodiment, the insulating film 105 is, for example, a SiN film.

Between adjacent insulating films 105, a sacrificial film 106 is provided. The sacrificial film 106 is disposed on the working area of either the source electrode or the drain electrode of the transistor which is not shown in the figure. In this embodiment, the sacrificial film 106 is, for example, SOD (Spin On Dielectric).

Return to Figure 14 to continue the description. Hereinafter, with reference to FIGS. 16 to 18, an example of the manufacturing process of the semiconductor device of the second embodiment will be described. 16 to 18 are diagrams showing an example of the manufacturing process of the semiconductor device of the second embodiment. Furthermore, in FIG. 14, the processing assigned with the same reference numerals as in FIG. 1 is the same as the processing described using FIG. 1 except for the points described below, so the repeated description will be omitted.

First, after forming the hole 107 using the etching device 20 (S10), for example, as shown in FIG. 16, the film forming device 21 is used to embed the conductive material 108 in the hole 107 (S11). Then, the substrate 100 is transported out of the film forming apparatus 21 by the transport apparatus 70, and transported into the etching apparatus 20 again.

Next, by the etching device 20, a part of the insulating film 105 is removed (S20). Thereby, for example, as shown in FIG. 17, the insulating film 105 on the sidewall of the hole 107 above the conductive material 108 is removed, and the low-k film 151 is exposed in the hole 107. Then, the substrate 100 is transported out of the etching apparatus 20 by the transporting device 70 and transported into the film forming apparatus 21 again.

Next, by the film forming device 21, a low-k film 152 is formed on the sidewall of the hole 107 (S21). The low-k film 152 is made of a material having a dielectric constant lower than that of the SiN film (for example, k=4 or less). In this embodiment, the low-k film 152 is made of SiCN, for example. Furthermore, the low-k film 152 may also be SiOCN, SiOC, SiCN, or the like, for example. The low-k film 152 is an example of a low dielectric constant insulating film. Thereby, for example, as shown in FIG. 18, a low-k film 152 is formed on the sidewall of the hole 107 above the conductive material 108. Step S21 is an example of the second build-up process.

In this embodiment, the low-k film 152 is formed by, for example, ALD. The main processing conditions for forming the low-k film 152 are, for example, as follows. Precursor gas: NH ₃ =1～10[slm] Flushing gas: N ₂ ＝50～1000[sccm] Reactive gas: TMA=10～350[sccm] Temperature: 200～500[℃] ALD cycle time: 5 ～60[sec/cycle] Repeat times: 50～500[times]

Next, the electrode film 109 is formed on the conductive material 108 in the hole 107 by the film forming device 21 (S12 ), and the substrate 100 is transferred from the film forming device 21 to the film forming device 22. Then, the barrier film 110 is formed in the hole 107 by the film forming device 22 (S13 ), and the substrate 100 is transferred from the film forming device 22 to the film forming device 23. Then, the initial film 120 of the electrode is formed in the hole 107 by the film forming device 23 (S14). Then, the main film 121 that becomes the electrode of the SNC is formed in the hole 107 (S15). Then, a conductive material is layered on the main film 121, and the conductive material is formed, thereby forming a bonding pad connected to the main film 121 (S16). Then, the manufacturing method of the semiconductor device shown in this flowchart ends. Furthermore, in this embodiment, the process of forming an air gap is not performed.

By this, for example, a semiconductor device as shown in FIG. 19 is manufactured. FIG. 19 is a cross-sectional view showing an example of the semiconductor device of the second embodiment. Furthermore, in FIG. 19, the illustration of the pads connected to the main film 121 is omitted. The CD of the main film 121 of this embodiment, that is, ΔW2" is greater than the ΔW2' of the semiconductor device of the comparative example illustrated in FIG. 12. Also, in this embodiment, since the barrier film 110 having an AlN film is used, the main film The crystal grain size of 121 becomes larger. Therefore, in this embodiment, compared with the comparative example illustrated in FIG. 12, the contact resistance of the main film 121 that becomes the electrode of the SNC can also be reduced.

Furthermore, in this embodiment, the CD of the low-k film 151, which is ΔW3", is greater than the CD of the air gap 130 of the comparative example, which is ΔW3. Therefore, in this embodiment, even in the low-k film 150 and the insulating film 105 The space (spacer layer) is filled with a material with a dielectric constant slightly larger than that of air, as the whole between the low-k film 150 and the insulating film 105, can also reduce the dielectric constant compared to the air gap 130 of the comparative example. A spacer layer with a dielectric constant equal to or lower than that of the air gap 130 can be realized by a method other than the air gap 130.

In the manufacturing method of the semiconductor device of this embodiment, the CD between BL102 and SNC is made larger than the comparative example, and a low-k film 151 with a low dielectric constant is arranged between BL102 and SNC. Thereby, a process for forming an air gap is not required, the number of manufacturing processes of the semiconductor device can be reduced, and the yield of the semiconductor device can be improved.

Furthermore, in the comparative example, the air gap 130 is formed by removing the sacrificial film 104 by wet etching. Therefore, around the sacrificial film 104, an insulating film 105 such as a SiN film that is resistant to etchant must be provided. In most cases, the dielectric constant of the insulating film 105 having resistance to etchant is higher than the dielectric constant of a low-permittivity insulating film such as SiCN.

On the other hand, in this embodiment, the low-k film 151 is not removed, so the low-k film 150 and the low-k film 152 disposed around the low-k film 151 do not need to be resistant to etchant. Therefore, a low-dielectric constant insulating film such as SiCN having a dielectric constant lower than that of a SiN film or the like can be used for the low-k film 150 and the low-k film 152 provided around the low-k film 151. Thereby, the dielectric constant of the low-k film 150, the low-k film 151, and the low-k film 152 as a whole interposed between the BL102 and the SNC can be reduced. As a result, compared with the comparative example, the parasitic capacitance between BL102 and SNC can be reduced by about 10%.

The second embodiment has been described above. As described above, the manufacturing method of the semiconductor device of the present embodiment further includes a second build-up process in which the dielectric constant of the sidewall build-up layer of the hole 107 above the conductive material 108 is lower than the low-k of the SiN film膜152。 Membrane 152. In the second embedding process, the main film 121 is embedded in the hole 107, and the low-k film 152 is laminated on the sidewall of the hole 107. In this way, the dielectric constant between BL102 and SNC can be reduced.

In addition, in the second embodiment described above, the low-k film 152 is, for example, SiCN, SiOCN, SiOC, or the like. In this way, the dielectric constant between BL102 and SNC can be reduced.

Furthermore, in the second embodiment described above, the low-k film 151 is made of a material having a lower dielectric constant than the SiN film. In this way, the dielectric constant between BL102 and SNC can be reduced.

In addition, in the second embodiment described above, the low-k film 151 is, for example, SiO, SiOCN, SiOC, or the like. In this way, the dielectric constant between BL102 and SNC can be reduced.

[other] Furthermore, the disclosed technology is not limited to the above-mentioned embodiment, and various changes can be made within the scope of the subject matter.

For example, in the second embodiment described above, a part of the increase in the CD of the SNC caused by the use of the barrier film 110 is allocated to the CD of the spacer layer between the SNC and the BL102, and the spacer layer is composed of the low-k film 151. However, the disclosed technology is not limited to this. For example, in the second embodiment, the spacer layer may also be constituted by the air gap 130. In this way, the parasitic capacitance between SNC and BL102 can be further reduced. In addition, the aspect ratio of the air gap 130 can be reduced, thereby improving the quality of the air gap 130 formed by wet etching.

Furthermore, in the second embodiment, a part of the insulating film 105 is removed in step S20, and a low-k film 152 is formed on the sidewall of the hole 107 in step S21, but the disclosed technology is not limited to this. For example, in the second embodiment, the processing of steps S20 and S21 may be omitted. Thereby, the manufacturing process of the semiconductor device can be reduced, and the output can be improved.

Furthermore, it should be considered that the embodiments disclosed this time are illustrative in all aspects and not restrictive. In fact, the above-mentioned embodiments can be implemented in various ways. In addition, the above-mentioned embodiments may be omitted, replaced, and changed in various ways without departing from the scope of the attached patent application and the spirit thereof.

10: Manufacturing system 11: Transfer room 20: Etching device 21: Film forming device 22: Film forming device 23: Film forming device 30: Loading interlock vacuum chamber 50: Vehicle 60: transfer room 61: Conveying device 70: Conveying device 71: support arm 72: Placement Department 80: control device 100: substrate 100': substrate 101: BLC 102:BL 103: Insulating film 104: Sacrificial Film 105: insulating film 106: Sacrificial Film 107: Electric Hole 108: conductive material 109: Electrode film 110: barrier film 111: 1st barrier film 112: 2nd barrier film 120: initial film 121: main film 130: air gap 140: barrier film 141: initial film 142: Main Film 150: low-k film 151: low-k film 152: low-k film G: Gate valve ΔW1:CD ΔW1":CD ΔW2:CD ΔW2':CD ΔW2":CD ΔW3:CD ΔW3":CD

FIG. 1 is a flowchart showing an example of the manufacturing method of the first embodiment of the present invention. Fig. 2 is a diagram showing an example of a manufacturing system. Fig. 3 is a cross-sectional view showing an example of the substrate of the first embodiment. 4 is a cross-sectional view showing an example of the manufacturing process of the semiconductor device of the first embodiment. 5 is a cross-sectional view showing an example of the manufacturing process of the semiconductor device of the first embodiment. 6 is a cross-sectional view showing an example of the manufacturing process of the semiconductor device of the first embodiment. FIG. 7 is a cross-sectional view showing an example of the manufacturing process of the semiconductor device of the first embodiment. Fig. 8 is an enlarged cross-sectional view showing an example of the structure of the barrier film. FIG. 9 is a cross-sectional view showing an example of the manufacturing process of the semiconductor device of the first embodiment. 10 is a cross-sectional view showing an example of the manufacturing process of the semiconductor device of the first embodiment. FIG. 11 is a cross-sectional view showing an example of the semiconductor device of the first embodiment. FIG. 12 is a cross-sectional view showing an example of a semiconductor device of a comparative example. FIG. 13 is a diagram showing an example of the resistance value of the electrode material with respect to the film thickness. Fig. 14 is a flowchart showing an example of the manufacturing method of the second embodiment of the present invention. FIG. 15 is a cross-sectional view showing an example of the substrate of the second embodiment. FIG. 16 is a cross-sectional view showing an example of the manufacturing process of the semiconductor device of the second embodiment. FIG. 17 is a cross-sectional view showing an example of the manufacturing process of the semiconductor device of the second embodiment. 18 is a cross-sectional view showing an example of the manufacturing process of the semiconductor device of the second embodiment. FIG. 19 is a cross-sectional view showing an example of the semiconductor device of the second embodiment.

Claims (10)

A method of manufacturing a semiconductor device, which includes: The hole formation process involves forming holes in the region between the spacer layer and the bit line adjacent to the area where the electrode connected to the capacitor is formed; The first embedding process involves embedding a first conductive material at the bottom of the above-mentioned electric hole; The first build-up process involves stacking a barrier film including an alignment control film on the sidewall of the above-mentioned hole; and The second embedding process involves embedding a second conductive material in the hole on which the barrier film is laminated to form the electrode in the hole. The method for manufacturing a semiconductor device according to claim 1, wherein the barrier film includes a first barrier film and a second barrier film as the alignment control film, In the above-mentioned first build-up process, The first barrier film is laminated on the side wall of the hole, and the second barrier film is laminated on the first barrier film. The method for manufacturing a semiconductor device according to claim 2, wherein the first barrier film is TiN, TiON, TiSiN, or TaN. The method for manufacturing a semiconductor device according to claim 2 or 3, wherein the second barrier film is AlN, TiAlN, WN, or WSi. The method for manufacturing a semiconductor device according to any one of claims 1 to 4, which further includes a second build-up process, wherein the second build-up process is based on the dielectric constant of the sidewall build-up of the hole above the first conductive material Low dielectric constant insulating film lower than SiN film, In the second embedding process, the second conductive material is embedded in the hole, and the low dielectric constant insulating film is laminated on the sidewall of the hole. The method for manufacturing a semiconductor device according to claim 5, wherein the low dielectric constant insulating film is SiCN, SiOCN, or SiOC. The method for manufacturing a semiconductor device according to any one of claims 1 to 6, wherein the spacer layer is made of a material having a dielectric constant lower than that of the SiN film. The method for manufacturing a semiconductor device according to any one of claims 1 to 7, wherein the spacer layer is SiO, SiOCN, or SiOC. A semiconductor device including: The second electrode is embedded in the bottom of the electric hole, and the above electric hole is formed in the area between the spacer layer and the bit line adjacent to the area where the first electrode connected to the capacitor is formed; A barrier film, which is located on the second electrode, is laminated on the sidewall of the hole, and includes an alignment control film; and The first electrode is embedded in the hole, and the barrier film is laminated on the side wall of the hole. A manufacturing system including an etching device, a first film forming device, a second film forming device, a third film forming device, and a control device, The above-mentioned control device performs the following processing: Using the above-mentioned etching device, a hole is formed in the area between the spacer layer and the bit line adjacent to the area where the electrode connected to the capacitor is formed; Using the above-mentioned first film forming device, embed a first conductive material at the bottom of the above-mentioned electric hole; Using the second film forming device described above, a barrier film including an alignment control film is laminated on the sidewall of the hole; and Using the third film forming apparatus, a second conductive material is embedded in the hole on which the barrier film is laminated, thereby forming the electrode in the hole.

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