KR20050046065A - Method of forming a metal line in semiconductor devices - Google Patents
Method of forming a metal line in semiconductor devices Download PDFInfo
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- KR20050046065A KR20050046065A KR1020030080043A KR20030080043A KR20050046065A KR 20050046065 A KR20050046065 A KR 20050046065A KR 1020030080043 A KR1020030080043 A KR 1020030080043A KR 20030080043 A KR20030080043 A KR 20030080043A KR 20050046065 A KR20050046065 A KR 20050046065A
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- tungsten film
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- 238000000034 method Methods 0.000 title claims abstract description 53
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 50
- 239000002184 metal Substances 0.000 title claims abstract description 50
- 239000004065 semiconductor Substances 0.000 title claims abstract description 14
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims abstract description 56
- 229910052721 tungsten Inorganic materials 0.000 claims abstract description 56
- 239000010937 tungsten Substances 0.000 claims abstract description 56
- 238000009792 diffusion process Methods 0.000 claims abstract description 19
- 238000005229 chemical vapour deposition Methods 0.000 claims abstract description 17
- 238000000231 atomic layer deposition Methods 0.000 claims abstract description 13
- 230000004888 barrier function Effects 0.000 claims abstract description 13
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 239000000463 material Substances 0.000 claims description 3
- 239000005300 metallic glass Substances 0.000 claims description 2
- 238000000151 deposition Methods 0.000 abstract description 4
- 239000007769 metal material Substances 0.000 description 5
- 239000007789 gas Substances 0.000 description 4
- 230000006911 nucleation Effects 0.000 description 3
- 238000010899 nucleation Methods 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 239000000047 product Substances 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 230000003746 surface roughness Effects 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 239000006227 byproduct Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000003795 desorption Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 150000002736 metal compounds Chemical class 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 150000002739 metals Chemical group 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 239000012495 reaction gas Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000001179 sorption measurement Methods 0.000 description 1
- 238000006557 surface reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
- H01L21/76876—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for deposition from the gas phase, e.g. CVD
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 반도체 소자의 금속배선 형성방법에 관한 것으로, 본 발명의 사상은 도전성 영역을 노출하는 콘택홀에 반도체 소자의 금속배선을 형성하는 방법에 있어서, 상기 콘택홀에 확산 방지막을 형성하는 단계, 상기 형성된 확산 방지막 상에 비정질인 제1 금속층을 형성하는 단계, 상기 비정질인 제1 금속층상에 제2 금속층을 형성하는 단계 및 상기 결과물 전면에 평탄화 공정을 수행하는 단계를 포함한다. 따라서 금속배선 매립 공정시 원자층 증착법으로 비정질인 제1 텅스텐막을 형성하고, 그 상부에 화학 기상 증착법으로 제2 텅스텐막을 형성함으로써, 금속배선의 비저항을 낮추게 되고, 또한, 금속배선 매립 공정시 원자층 증착법으로 비정질인 제1 텅스텐막을 형성하고, 그 상부에 화학 기상 증착법으로 제2 텅스텐막을 형성하고, 상기 결과물 전면에 평탄화 공정을 수행하는 단계를 포함]함으로써, 금속배선의 형성 공정시 후속 패턴 공정으로 인해 발생되는 브릿지를 억제하게 된다. The present invention relates to a method for forming a metal wiring of a semiconductor device, the idea of the invention is a method for forming a metal wiring of the semiconductor device in a contact hole exposing a conductive region, forming a diffusion barrier in the contact hole, Forming an amorphous first metal layer on the formed diffusion barrier layer, forming a second metal layer on the amorphous first metal layer, and performing a planarization process on the entire surface of the resultant. Therefore, by forming an amorphous first tungsten film by the atomic layer deposition method in the metal wiring embedding process and forming a second tungsten film by the chemical vapor deposition method thereon, the specific resistance of the metal wiring is lowered, and the atomic layer during the metal wiring embedding process Forming an amorphous first tungsten film by a deposition method, forming a second tungsten film by a chemical vapor deposition method thereon, and performing a planarization process on the entire surface of the resultant. It is possible to suppress the bridge that is generated.
Description
본 발명은 반도체 소자의 제조 방법에 관한 것으로, 더욱 상세하게는 반도체소자의 금속배선 형성방법에 관한 것이다. The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming metal wiring of a semiconductor device.
일반적으로 반도체 소자의 고집적화로 인해 금속 배선의 선폭 감소는 필연적이며 또한 기생 커패시턴스를 최소화하려면 금속 배선의 두께 또한 최소화된다. In general, due to the high integration of semiconductor devices, the reduction of the line width of the metal wiring is inevitable, and the thickness of the metal wiring is also minimized to minimize the parasitic capacitance.
그러나 선폭 및 크기가 점차 작아지는 콘택홀에 금속 배선이 매립되면 금속배선 자체의 비저항이 증가하게 되는 문제점이 있다. However, there is a problem in that the resistivity of the metal wiring itself increases when the metal wiring is buried in the contact hole where the line width and size gradually decrease.
따라서 금속배선 형성 공정시 상기와 같은 종횡비가 큰 콘택홀에 수행되는 금속 물질의 매립공정은 매립특성이 우수한 화학적 기상 증착법을 채택한다. Therefore, in the metallization forming process, the buried process of the metal material, which is performed in the above-mentioned high aspect ratio contact hole, employs a chemical vapor deposition method having excellent embedding characteristics.
이 화학적 기상증착법을 통한 매립 공정은, 웨이퍼 표면으로의 반응 기체의 유입 및 흡착, 표면 반응, 금속이나 금속화합물의 증착, 부산물의 탈착과정을 통해 형성된다. 이러한 각각의 단계들에 미치는 주변 환경들이 형성되는 매립막의 성질에 영향을 미친다. 특히, 원하는 금속막을 증착하기 위한 하지층의 표면 구조가 매립막의 특성에 미치는 영향은 매우 크다. The landfill process through chemical vapor deposition is formed by inflow and adsorption of reaction gas onto the wafer surface, surface reaction, deposition of metals or metal compounds, and desorption of by-products. The surrounding environments affecting each of these stages affect the properties of the landfill film formed. In particular, the effect of the surface structure of the underlying layer for depositing the desired metal film on the properties of the buried film is very large.
일반적으로, 콘택홀을 매립하는 매립막의 금속물질은 텅스텐이나 구리 등인데, 이들은 증착 전 금속물질의 확산을 방지하기 위한 확산 방지막을 증착하는 데, 상기 확산 방지막의 역할을 수행하는 막질의 결정 구조는 그 상에 증착되는 금속물질의 비저항을 증가시키는 원인이 되고, 이는 소자의 성능 저하를 유발하는 문제점이 있다. In general, the metal material of the buried film filling the contact hole is tungsten or copper, and they deposit a diffusion preventing film for preventing the diffusion of the metal material before deposition, and the crystalline structure of the film that serves as the diffusion blocking film is There is a cause of increasing the specific resistance of the metal material deposited thereon, which causes a problem of deterioration of the device performance.
상술한 문제점을 달성하기 위한 본 발명의 목적은 금속배선 자체의 비저항을 감소시켜 소자의 성능 향상을 가져오는 반도체 소자의 금속배선 형성방법을 제공함에 있다. An object of the present invention for achieving the above-described problem is to provide a method for forming a metal wiring of the semiconductor device to reduce the specific resistance of the metal wiring itself to improve the performance of the device.
상술한 목적을 달성하기 위한 본 발명의 사상은 도전성 영역을 노출하는 콘택홀에 반도체 소자의 금속배선을 형성하는 방법을 있어서, 상기 콘택홀에 확산 방지막을 형성하는 단계, 상기 형성된 확산 방지막 상에 비정질인 제1 금속층을 형성하는 단계, 상기 비정질인 제1 금속층상에 제2 금속층을 형성하는 단계 및 상기 결과물 전면에 평탄화 공정을 수행하는 단계를 포함한다. According to an aspect of the present invention for achieving the above object, a method of forming a metal wiring of a semiconductor device in a contact hole exposing a conductive region, the step of forming a diffusion barrier in the contact hole, the amorphous on the formed diffusion barrier Forming a phosphorous first metal layer, forming a second metal layer on the amorphous first metal layer, and performing a planarization process on the entire surface of the resultant.
상기 확산 방지막은 상기 제1 및 제2 금속층의 확산을 방지하는 막으로 형성하는 것이 바람직하다. Preferably, the diffusion barrier is formed of a film that prevents diffusion of the first and second metal layers.
상기 확산 방지막은 TiN막, TiW막, Ti막, Ta막, TaN막, TaW막 및 WN막 중 어느 하나인 것이 바람직하다. Preferably, the diffusion barrier is any one of a TiN film, a TiW film, a Ti film, a Ta film, a TaN film, a TaW film, and a WN film.
상기 제1 금속층은 상기 제2 금속층의 시드층으로써 비정질인 금속물질을 형성하는 것이 바람직하다. The first metal layer preferably forms an amorphous metal material as a seed layer of the second metal layer.
상기 제1 금속층은 소스 가스로써 WF6과 환원기체로써 B2H6을 사용하여 원자층 증착(ALD)공정을 통해 형성하는 텅스텐막인 것이 바람직하다.The first metal layer is preferably a tungsten film formed through atomic layer deposition (ALD) using WF 6 as a source gas and B 2 H 6 as a reducing gas.
상기 제2 금속층은 화학적 기상증착(CVD)법을 통해 형성되는 텅스텐막인 것이 바람직하다. The second metal layer is preferably a tungsten film formed through chemical vapor deposition (CVD).
이하, 첨부 도면을 참조하여 본 발명의 실시 예를 상세히 설명한다. 그러나, 본 발명의 실시예들은 여러 가지 다른 형태로 변형될 수 있지만 본 발명의 범위가 아래에서 상술하는 실시예들로 인해 한정되어지는 것으로 해석되어져서는 안 된다. 본 발명의 실시예들은 당업계에서 평균적인 지식을 가진 자에게 본 발명을 보다 완전하게 설명하기 위해 제공되어지는 것이다. 따라서, 도면에서의 막의 두께 등은 보다 명확한 설명을 강조하기 위해서 과장되어진 것이며, 도면상에서 동일한 부호로 표시된 요소는 동일한 요소를 의미한다. 또한 어떤 막이 다른 막 또는 반도체 기판의 '상'에 있다 또는 접촉하고 있다라고 기재되는 경우에, 상기 어떤 막은 상기 다른 막 또는 반도체 기판에 직접 접촉하여 존재할 수 있고, 또는 그 사이에 제 3의 막이 개재되어질 수도 있다.Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, embodiments of the present invention may be modified in many different forms, but the scope of the present invention should not be construed as being limited by the embodiments described below. Embodiments of the present invention are provided to more fully describe the present invention to those skilled in the art. Accordingly, the thickness of the film and the like in the drawings are exaggerated for clarity, and the elements denoted by the same reference numerals in the drawings mean the same elements. In addition, when a film is described as being on or in contact with another film or semiconductor substrate, the film may be in direct contact with the other film or semiconductor substrate, or a third film is interposed therebetween. It may be done.
도 1을 참조하면, 하부구조를 형성된 반도체 기판(미도시) 상에 실리콘 산화막(12 : SiO2)을 형성하고, 이 실리콘 산화막(12)을 패터닝하여 상기 하부 구조를 노출하는 콘택홀(미도시)을 형성한다. 이 콘택홀(미도시)을 포함한 결과물에 이후 형성되는 금속물질의 확산을 방지하는 막으로 확산 방지막(14)을 형성한다. 상기 확산 방지막(14)은 TiN막, TiW막, Ti막, Ta막, TaN막, TaW막들 중 어느 하나를 사용한다.Referring to FIG. 1, a contact hole for forming a silicon oxide film 12 (SiO 2 ) on a semiconductor substrate (not shown) having a lower structure and patterning the silicon oxide film 12 to expose the lower structure (not shown) ). A diffusion barrier 14 is formed on the resulting product including the contact hole (not shown) as a film to prevent diffusion of a metal material to be formed later. The diffusion barrier 14 may use any one of a TiN film, a TiW film, a Ti film, a Ta film, a TaN film, and a TaW film.
도 2를 참조하면, 상기 이 TiN막(14) 상에 원자층 증착(ALD)공정을 이용하여 제1 텅스텐막(16)을 형성한다. 이는 이후 증착되는 제2 텅스텐막(도 3의 18)의 시드층이다. Referring to FIG. 2, a first tungsten film 16 is formed on the TiN film 14 by using an atomic layer deposition (ALD) process. This is the seed layer of the second tungsten film (18 in FIG. 3) that is subsequently deposited.
상기 원자층 증착공정을 통해 형성하는 제1 텅스텐막(16)은 소스 가스로써 WF6과 환원기체로써 B2H6을 사용하여 형성하는 데, 이 제1 텅스텐막(16)은 비정질 텅스텐막이다.The first tungsten film 16 formed through the atomic layer deposition process is formed using WF 6 as a source gas and B 2 H 6 as a reducing gas. The first tungsten film 16 is an amorphous tungsten film. .
도 3을 참조하면, 시드층의 제1 텅스텐막(16)상에 화학적 기상증착(CVD)법을 이용하여 제2 텅스텐막(18)을 형성한다. Referring to FIG. 3, a second tungsten film 18 is formed on the first tungsten film 16 of the seed layer by chemical vapor deposition (CVD).
상기 비정질인 제1 텅스텐막(16)상에 형성된 제2 텅스텐막(18)의 그레인 사이즈(grain size)는 화학적 기상 증착법을 통해 형성된 즉, 다결정인 제1 텅스텐막 상에 형성된 제2 텅스텐막의 그레인 사이즈보다 작다. The grain size of the second tungsten film 18 formed on the amorphous first tungsten film 16 is formed through chemical vapor deposition, that is, the grain of the second tungsten film formed on the first polycrystalline tungsten film. Smaller than size
도 5a 및 도 5b에 도시된 TEM사진을 참조하면, 도 5a에 도시된 다결정인 제1 텅스텐막상에 증착된 제2 텅스텐막의 그레인 사이즈는 매우 균일하고 작은 크기이지만, 도 5b에 도시된 비정질인 제1 텅스텐막 상에 증착된 제2 텅스텐막의 그레인 사이즈는 도 5a에 도시된 상기 다결정인 제1 텅스텐막상에 형성된 제2 텅스텐막의 그레인 사이즈보다 불균일하고, 매우 큰 크기이다. 5A and 5B, the grain size of the second tungsten film deposited on the first polycrystalline tungsten film shown in FIG. 5A is very uniform and small in size, but the amorphous material shown in FIG. The grain size of the second tungsten film deposited on the first tungsten film is non-uniform and very large than the grain size of the second tungsten film formed on the polycrystalline first tungsten film shown in Fig. 5A.
따라서 상기와 같이 비정질인 제1 텅스텐막상에 증착된 제2 텅스텐막의 그레인 사이즈가 크기 때문에, 비정질인 제1 텅스텐막상에 증착된 제2 텅스텐막의 비저항은 다결정인 제1 텅스텐막 상에 증착된 제2 텅스텐막의 비저항보다 작게 된다. Therefore, since the grain size of the second tungsten film deposited on the amorphous first tungsten film is large, the specific resistance of the second tungsten film deposited on the amorphous first tungsten film is the second deposited on the polycrystalline first tungsten film. It becomes smaller than the specific resistance of a tungsten film.
이를 보다 상세히 설명하면, 화학적 기상증착법을 통해서만 증착된 제1 및 제2 텅스텐막(다결정인 제1 텅스텐막 상에 증착된 제2 텅스텐막)은 SiH4를 사용하는 결정핵형성단계(nucleation step)가 필수적으로 포함되어야 하기 때문에 실리콘 불순물이 많아 막의 비저항이 크게 되지만, 본 발명에서 사용한 비정질인 제1 텅스텐막 상에 화학적 기상증착법을 통해 형성된 제2 텅스텐막은 SiH4를 사용하는 결정핵 형성 단계(nucleation step)가 없기 때문에 상대적으로 막의 비저항이 낮게 된다.In more detail, the first and second tungsten films (second tungsten film deposited on the polycrystalline first tungsten film) deposited only by chemical vapor deposition are nucleation steps using SiH 4 . Since the silicon resistivity must be included to increase the specific resistance of the film is large, but the second tungsten film formed by chemical vapor deposition on the amorphous first tungsten film used in the present invention is a nucleation step (nucleation) using SiH 4 Since there is no step), the film resistivity is relatively low.
도 4를 참조하면, 상기 제2 텅스텐막이 형성된 결과물 전면에 CMP 공정과 같은 평탄화 공정을 수행하여, 금속배선의 형성공정을 완료한다. 이 평탄화 공정의 수행은 후속 패턴 공정으로 인해 브릿지(bridge)와 같은 불량을 유발할 위험을 제거해준다.Referring to FIG. 4, a planarization process such as a CMP process is performed on the entire surface of the resultant product on which the second tungsten film is formed, thereby completing the process of forming metal wiring. Performing this planarization process eliminates the risk of causing failures such as bridges due to subsequent patterning processes.
다시 말해, 표 1에 도시된 바와 같이 비정질인 제1 텅스텐막(16)상에 형성된 제2 텅스텐막(18)의 표면 거칠기는 다결정인 제1 텅스텐막 상에 형성된 제2 텅스텐막보다 높은 값을 가지게 된다. 이런 표면 거칠기를 갖은 상태의 텅스텐막을 금속배선으로 사용할 경우, 후속 패턴 공정으로 인해 브릿지(bridge)와 같은 불량을 발생시킬 위험이 있다. 따라서 상기 문제점을 해결하기 위해 제2 텅스텐막(18)에 평탄화 공정을 수행하는 것이다. In other words, as shown in Table 1, the surface roughness of the second tungsten film 18 formed on the amorphous first tungsten film 16 is higher than that of the second tungsten film formed on the polycrystalline first tungsten film. Have. If a tungsten film having such a surface roughness is used as a metal wiring, there is a risk of generating a defect such as a bridge due to a subsequent pattern process. Therefore, the planarization process is performed on the second tungsten film 18 to solve the above problem.
한편, 본 발명의 일실시 예인 비정질인 제1 텅스텐막상에 형성된 제2 텅스텐막은 종횡비가 15이상의 종횡비를 가진 콘택홀에 적합하다. On the other hand, the second tungsten film formed on the amorphous first tungsten film according to an embodiment of the present invention is suitable for contact holes having an aspect ratio of 15 or more.
본 발명에 의하면, 금속배선 매립 공정시 원자층 증착법으로 비정질인 제1 텅스텐막을 형성하고, 그 상부에 화학 기상 증착법으로 제2 텅스텐막을 형성함으로써, 금속배선의 비저항을 낮추게 된다. According to the present invention, by forming an amorphous first tungsten film by an atomic layer deposition method in a metal wiring embedding process and forming a second tungsten film by a chemical vapor deposition method thereon, the specific resistance of the metal wiring is lowered.
또한, 금속배선 매립 공정시 원자층 증착법으로 비정질인 제1 텅스텐막을 형성하고, 그 상부에 화학 기상 증착법으로 제2 텅스텐막을 형성함으로써, 금속배선의 형성 공정시 후속 패턴 공정으로 인해 발생되는 브릿지를 억제하게 된다. In addition, by forming an amorphous first tungsten film by an atomic layer deposition method and forming a second tungsten film by a chemical vapor deposition method in the metal wiring embedding process, the bridge caused by the subsequent pattern process in the formation process of the metal wiring is suppressed. Done.
이상에서 살펴본 바와 같이 본 발명에 의하면, 금속배선 매립 공정시 원자층 증착법으로 비정질인 제1 텅스텐막을 형성하고, 그 상부에 화학 기상 증착법으로 제2 텅스텐막을 형성함으로써, 금속배선의 비저항을 낮추게 되는 효과가 있다. As described above, according to the present invention, an amorphous first tungsten film is formed by an atomic layer deposition method in a metal wiring embedding process, and a second tungsten film is formed by a chemical vapor deposition method thereon, thereby lowering the specific resistance of the metal wiring. There is.
또한, 금속배선 매립 공정시 원자층 증착법으로 비정질인 제1 텅스텐막을 형성하고, 그 상부에 화학 기상 증착법으로 제2 텅스텐막을 형성함으로써, 금속배선의 형성 공정시 후속 패턴 공정으로 인해 발생되는 브릿지를 억제하게 되는 효과가 있다. 본 발명은 구체적인 실시 예에 대해서만 상세히 설명하였지만 본 발명의 기술적 사상의 범위 내에서 변형이나 변경할 수 있음은 본 발명이 속하는 분야의 당업자에게는 명백한 것이며, 그러한 변형이나 변경은 본 발명의 특허청구범위에 속한다 할 것이다.In addition, by forming an amorphous first tungsten film by an atomic layer deposition method and forming a second tungsten film by a chemical vapor deposition method in the metal wiring embedding process, the bridge caused by the subsequent pattern process in the formation process of the metal wiring is suppressed. It is effective. Although the present invention has been described in detail only with respect to specific embodiments, it is apparent to those skilled in the art that modifications or changes can be made within the scope of the technical idea of the present invention, and such modifications or changes belong to the claims of the present invention. something to do.
도 1 내지 도 4는 본 발명에 따른 반도체 소자의 금속배선 형성방법을 설명하기 위한 단면도들이고, 1 to 4 are cross-sectional views illustrating a method for forming metal wirings of a semiconductor device according to the present invention.
도 5a 및 도 5b는 본 발명에 따라 형성된 금속배선의 그레인 사이즈와 종래기술에 따라 형성된 금속배선의 그레인 사이즈를 비교한 TEM사진이다. 5A and 5B are TEM photographs comparing grain sizes of metal interconnections formed according to the present invention with grain sizes of metal interconnections formed according to the prior art.
*도면의 주요부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *
12: 절연막 14: 확산방지막12: insulating film 14: diffusion barrier film
16: 제1 텅스텐막 18: 제2 텅스텐막 16: first tungsten film 18: second tungsten film
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100648252B1 (en) * | 2004-11-22 | 2006-11-24 | 삼성전자주식회사 | Method of forming a tungsten layer and method of forming a semicondcutor device using the same |
| KR100808584B1 (en) * | 2005-09-26 | 2008-02-29 | 주식회사 하이닉스반도체 | Method for forming bit line of semiconductor device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100648252B1 (en) * | 2004-11-22 | 2006-11-24 | 삼성전자주식회사 | Method of forming a tungsten layer and method of forming a semicondcutor device using the same |
| KR100808584B1 (en) * | 2005-09-26 | 2008-02-29 | 주식회사 하이닉스반도체 | Method for forming bit line of semiconductor device |
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