TW202046324A - Semiconductor memory device being small in size and having high functionality - Google Patents

Abstract

Disclosed is a semiconductor memory device which is small in size and has high functionality. The semiconductor memory device according to an embodiment of the present invention includes a plurality of memory cell array layers which has a first surface and a second surface opposite to the first surface and does not include a substrate, in addition, the plurality of memory cell array layers includes: a plurality of memory cells three-dimensionally arranged in a memory cell array region, and a surface wiring layer that is embedded in the first surface and/or the second surface. The surface wiring layers of the memory cell array layers are provided so as to overlap one another when viewed in a direction perpendicular to the first surface, and the plurality of memory cell array layers is stacked by the surface wiring layers being connected to each other.

Description

Semiconductor memory device

The embodiment of the present invention relates to a semiconductor memory device.

The present invention proposes a semiconductor memory device with a three-dimensional structure. A laminate in which a plurality of electrode layers are laminated on a substrate and an insulating edge is formed to form a memory hole, and a charge storage film is interposed in the memory hole There is a silicon body that becomes a channel. In addition, a technology is proposed in which the control circuit of the memory cell array with the 3-dimensional structure is arranged directly below or directly above the memory cell array.

However, in this example, the memory density per unit area cannot be sufficiently increased.

The embodiment provides a small and high-performance semiconductor memory device.

According to an embodiment, a semiconductor memory device is provided, which has a plurality of memory cell array layers, the memory cell array layer has a first surface and a second surface opposite to the first surface and does not include a substrate, and includes: A plurality of memory cells, which are arranged in the memory cell array area in three dimensions; and the surface wiring layer, which is embedded in the first surface or/and the second surface; and The surface wiring layers of each of the memory cell array layers are arranged to overlap when viewed from a direction perpendicular to the first surface, and the surface wiring layers are joined to each other, thereby stacking a plurality of the memory cell array layers.

Hereinafter, the embodiment will be described with reference to the drawings. In addition, the same elements in the drawings are labeled with the same symbols.

(First Embodiment) FIG. 1 is a schematic cross-sectional view of the semiconductor memory device of the first embodiment. The semiconductor memory device of the first embodiment has the following structure: a peripheral circuit layer 100 including a control circuit for controlling data writing, erasing, and reading to the memory cell, and a first memory cell including a plurality of first memory cells arranged in three dimensions 1 The memory cell array layer 200 is joined to the build-up layer in an opposing manner and adhered. In addition, it has the following structure: the first memory cell array layer 200 and the second memory cell array layer 300 including a plurality of second memory cells arranged in a three-dimensional arrangement are joined and laminated in an opposing manner, and bonded together.

First, the first memory cell array layer 200 will be described. The first memory cell array layer 200 has a first surface (lower surface) Sa1 in FIG. 1 and a second surface (upper surface) Sa2 opposite to the first surface, and has a first memory cell array 10a with a three-dimensional structure. 2 is a schematic perspective view of the semiconductor memory device of the first embodiment, and is a schematic perspective view of the first memory cell array 10a. In addition, in FIG. 2, the illustration of a part of the insulating layer such as the inter-electrode insulating layer is omitted. In addition, Fig. 2 is up and down opposite to Fig. 1, the upper side of Fig. 2 is the first surface side, and the lower side is the second surface side.

In FIG. 2, the two directions orthogonal to each other are referred to as the X direction and the Y direction, and the direction orthogonal to the X direction and the Y direction (XY plane) and having a plurality of electrode layers WL laminated is referred to as Z Direction (stacking direction).

The first memory cell array 10a has a first layered body 12a in which a plurality of electrode layers WL and insulating layers 11 are alternately laminated one by one. In the first laminated body 12a, a plurality of first columnar portions 13a extending in the Z direction are provided. The first columnar portion 13a is provided in a cylindrical shape or an elliptical cylindrical shape, for example. The plurality of first columnar portions 13a are arranged in a zigzag grid or a square grid on the XY plane, for example. The electrode layer WL is separated into a plurality of blocks in the Y direction and extends in the X direction.

The electrode layer WL is, for example, a layer containing silicon as a main component. Furthermore, the electrode layer WL contains boron as an impurity for making the silicon layer conductive. In addition, the electrode layer WL may also include metal silicide.

The insulating layer 11 mainly includes silicon and oxygen, for example, a silicon oxide film (SiO), a silicon oxynitride film (SiON), a silicon oxide film containing carbon (SiOC), and the like.

The drain side selection gate SGD is provided on the first surface Sa1 side of the first columnar portion 13a, which is the upper part, and the source side selection gate SGS is provided on the second surface Sa2 side, which is the lower part. The drain-side select gate SGD is disposed on the uppermost electrode layer WL via the insulating edge layer 11. The source-side selection gate SGS is disposed under the lowermost electrode layer WL via the insulating edge layer 11. Here, for example, the drain side selection gate SGD and the source side selection gate SGS may be formed thicker than the one-layer electrode layer WL.

The first bit line 16a is connected to the first surface Sa1 side, that is, the upper end of the first columnar portion 13a. The first bit line 16a is provided in plural, and metal is used. The plurality of first bit lines 16a are spaced apart in the X direction and extend in the Y direction. The first bit line 16a is disposed on the drain side selection gate SGD via the insulating edge layer 11 and the interlayer insulating layer 14.

The first source line 17a is connected to the second surface Sa2 side, that is, the lower end of the first columnar portion 13a. The first source line 17a is disposed under the source-side selection gate SGS via the interlayer insulating layer 15. In addition, at the lower end of the first columnar portion 13a, and further down the first source line 17a, a first source-side wiring layer 19a is provided in the interlayer insulating layer 18. The interlayer insulating layer 18 may also be a laminated layer.

3 is a schematic cross-sectional view of the semiconductor memory device of the first embodiment, and is a schematic cross-sectional view of the vicinity of the first columnar portion. Fig. 4 is a schematic cross-sectional view showing an enlarged part of a part near the first columnar part of Fig. 3, that is, A part. 3 and 4 show cross-sections parallel to the YZ plane in FIG. 2.

As shown in FIG. 3, the first columnar portion 13a is formed in an I-shaped memory hole formed in the first laminate 12a including a plurality of electrode layers WL and a plurality of insulating layers 11. Inside the memory hole, there is a channel main body 20 as a semiconductor channel. The channel main body 20 is, for example, a silicon film. The impurity concentration of the channel body 20 is lower than the impurity concentration of the electrode layer WL.

As shown in FIG. 4, the memory cell MC is provided with a memory film 21 between the inner wall of the memory hole and the channel main body 20. The memory film 21 has, for example, a block insulating film 22, a charge storage film 23, and a tunnel insulating film 24. Between the electrode layer WL and the channel body 20, a block insulating film 22, a charge storage film 23, and a tunnel insulating film 24 are sequentially provided from the electrode layer WL side.

The channel main body 20 is provided in a cylindrical shape extending in the stacking direction of the laminated body, and the memory film 21 is arranged in a cylindrical shape extending in the laminated direction of the laminated body so as to surround the outer peripheral surface of the channel main body 20. The electrode layer WL surrounds the channel body 20 through the memory film 21. In addition, a core insulating film 25 is provided inside the channel main body 20. The core insulating film 25 is, for example, a silicon oxide film.

The block insulating film 22 is in contact with the electrode layer WL, the tunnel insulating film 24 is in contact with the channel main body 20, and a charge storage film 23 is provided between the block insulating film 22 and the tunnel insulating film 24.

The channel main body 20 functions as a channel of the memory cell MC, and the electrode layer WL functions as a control gate of the memory cell. The charge storage film 23 functions as a data memory layer that stores the charge injected from the channel main body 20. That is, at the intersection of the channel main body 20 and each electrode layer WL, a memory cell MC with a structure in which the control gate surrounds the channel is formed.

The semiconductor memory device of the first embodiment is a non-volatile semiconductor memory device that can electrically and freely erase and write data, and retain the memory content even when the power is turned off.

The memory cell MC is, for example, a charge trap type memory cell. The charge storage film 23 has a plurality of trap sites for trapping charges, such as a silicon nitride film. It can also be a floating gate type memory cell.

The tunnel insulating film 24 becomes a potential energy barrier when charges are injected into the charge storage film 23 from the channel main body 20 or when the charges stored in the charge storage film 23 diffuse to the channel main body 20. The tunnel insulating film 24 is, for example, a silicon oxide film.

Alternatively, as the tunnel insulating film, a laminated film (ONO film) having a structure in which a silicon nitride film is sandwiched between a pair of silicon oxide films may also be used. If an ONO film is used as the tunnel insulating film, compared with a single layer of silicon oxide film, the erasing operation can be performed with a lower electric field.

The block insulating film 22 prevents the charge accumulated in the charge storage film 23 from diffusing to the electrode layer WL. The block insulating film 22 has, for example, a silicon nitride film 221 provided in contact with the electrode layer WL, and a silicon oxide film 222 provided between the silicon nitride film 221 and the charge storage film 23.

By placing the silicon nitride film 221, which has a higher dielectric constant than the silicon oxide film 222, in contact with the electrode layer WL, it is possible to suppress the injection of tunnel electrons from the electrode layer WL during erasing. That is, by using a laminated film of a silicon oxide film and a silicon nitride film as the block insulating film 35, the charge blocking property can be improved.

As shown in FIGS. 2 and 3, the drain side selection transistor STD is provided on the upper portion of the first columnar portion 13a, and the source side selection transistor STS is provided on the other lower portion.

The memory cell MC, the drain-side select transistor STD, and the source-side select transistor STS are vertical transistors that flow current in the stacking direction (Z direction) of the laminate.

The drain-side selective gate SGD functions as a gate electrode (control gate) of the drain-side selective transistor STD. Between the drain side selection gate SGD and the channel main body 20, there is provided an insulating film 26 that functions as a gate insulating film of the drain side selection transistor STD (FIG. 3). The channel main body 20 of the drain side selection transistor STD arranged in the first column portion 13a is above the drain side selection gate SGD, and is connected to the bit line BL.

The source-side selective gate SGS functions as the gate electrode (control gate) of the source-side selective transistor STS. Between the source-side selection gate SGS and the channel main body 20, there is provided an insulating film 27 that functions as a gate insulating film of the source-side selection transistor STS (FIG. 3). The channel body 20 of the source-side selection transistor STS provided in the first columnar portion 13a is below the source-side selection gate SGS and is connected to the source line SL.

Further below the source line SL, a first source-side wiring layer 19 a is provided in the interlayer insulating layer 18.

The plurality of memory cells MC, drain-side selection transistors STD, and source-side selection transistors STS are connected in series through the channel main body 20 to form a memory string MS in the shape of an I. By arranging plural memory strings MS in the X direction and Y direction, the plural memory cells MC are arranged in three dimensions in the X direction, Y direction and Z direction.

FIG. 1 shows the region at the end of the first memory cell array 10a in the X direction. At the end of the first memory cell array region 28a where a plurality of memory cells MC are arranged, a step structure 29 of the electrode layer WL extending in the X direction is formed. In the step structure portion 29, the end portions of the electrode layers WL of each layer in the X direction are formed in a step shape. In the stepped structure portion 29, a plurality of contact plugs 30 connected to the electrode layers WL of each layer formed in a stepped shape are provided. The contact plug 30 penetrates the interlayer insulating layer 31 and is connected to the electrode layer WL of each stepped layer.

In addition, in the stepped structure portion 29, the select gate SG (drain-side select gate SGD, source-side select gate SGS) is connected to the contact plug 32.

The contact plug 30 connected to the electrode layer WL is connected to the character wiring layer 33. The contact plug 32 connected to the selection gate SG is connected to the selection gate wiring layer 34. The character wiring layer 33 and the selection gate wiring layer 34 are provided in the same layer.

The first memory cell array layer 200 does not include a substrate. Furthermore, on the second surface side of the first source line SL, a first source-side wiring layer 19a is further provided.

At least a part of the character wiring layer 33 and the selective gate wiring layer 34 is drawn from the vertical to the first as the word line lead-out portion 35 and the select gate line lead-out portion 36 by other wiring layers or plugs. The outer side of the first memory cell array region 28a when viewed in the direction of the plane. The character line lead-out portion 35 and the select gate line lead-out portion 36 drawn to the outside of the first memory cell array area 28a are connected to the first signal line lead electrode 37a provided on the outside of the first memory cell array area 28a.

In addition, the channel main body 20 of the first columnar portion 13a is electrically connected to the first bit line BL and the first source line SL. In addition, at least a part of the first bit line BL and the first source line SL is similarly used as the first bit line lead-out portion and the first source line lead-out portion by other wiring layers or plugs, and It is drawn out to the outside of the first memory cell array region 28a (not shown) when viewed from a direction perpendicular to the first surface. The first bit line lead-out portion and the first source line lead-out portion drawn to the outside of the first memory cell array region 28a are connected to the first signal line lead electrode 37a provided on the outside of the first memory cell array region 28a.

On the first surface Sa1 and the second surface Sa2 of the first memory cell array layer 200, a first surface wiring layer 38a and a second surface wiring layer 39a are provided. The first surface wiring layer 38a and the second surface wiring layer 39a are embedded in the first surface Sa1 and the second surface Sa2, respectively, and the surfaces are exposed from an interlayer insulating layer not shown. Here, for example, the first signal line extraction electrode 37a is electrically connected to the first surface wiring layer 38a and the second surface wiring layer 39a provided on the first surface Sa1 and the second surface Sa2 of the first memory cell array layer 200, respectively. The first signal line extraction electrode 37a, the first surface wiring layer 38a, and the second surface wiring layer 39a penetrate the first memory cell array layer 200.

In addition, a first external connection electrode 40a is provided on the outer side of the first memory cell array region 28a. That is, the first external connection electrode 40a is provided in an area outside the stepped structure portion of the memory cell array. The first external connection electrode 40a is electrically connected to the first surface wiring layer 38a and the second surface wiring layer 39a provided on the first surface Sa1 and the second surface Sa2 of the first memory cell array layer 200, respectively. The first surface wiring layer 38a and the second surface wiring layer 39a are embedded in the first surface Sa1 and the second surface Sa2, respectively, and the surfaces are exposed from an interlayer insulating layer not shown. The first external connection electrode 40 a, the first surface wiring layer 38 a, and the second surface wiring layer 39 a penetrate the first memory cell array layer 200.

The peripheral circuit layer 100 includes the circuit board 1. The circuit substrate 1 of the peripheral circuit layer 100 is, for example, a silicon substrate. A control circuit is formed on the circuit formation surface of the circuit substrate 1 of the peripheral circuit layer. As a control circuit, it is formed as an integrated circuit including a transistor. As the transistor, it has a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) structure including a gate electrode, source/drain regions, and the like. The source/drain regions of the MOSFET are connected to the circuit-side connection electrode 41 through other wiring layers or plugs. The circuit-side connection electrode 41 is electrically connected to the circuit-side wiring layer 42 provided on the circuit formation surface of the peripheral circuit layer 100. The circuit-side wiring layer 42 is embedded in the circuit formation surface, and the surface is exposed from the interlayer insulating layer (not shown).

The second memory cell array layer 300 has the same structure as the first memory cell array layer 200 shown in FIGS. 1 to 4. That is, the second memory cell array layer 300 has a third surface (lower surface) Sb1 in FIG. 1 and a fourth surface (upper surface) Sb2 opposite to the third surface, and has a second memory cell array 10b with a three-dimensional structure. . In addition, the description of the same configuration is omitted.

The second memory cell array layer 300 does not include a substrate. Furthermore, a second source-side wiring layer 19b is further provided on the fourth surface side from the second source line SL.

Similar to the first memory cell array layer 200, at least a part of the character wiring layer 33 and the selective gate wiring layer 34 is formed by other wiring layers or plugs as the word line lead-out portion 35 and the select gate line lead-out portion 36, and is led out to the outside of the second memory cell array area 28b when viewed from a direction perpendicular to the third surface. The character line lead-out portion 35 and the select gate line lead-out portion 36 drawn to the outside of the second memory cell array region 28b are connected to the second signal line lead electrode 37b provided on the outside of the second memory cell array region 28b.

In addition, the channel main body 20 of the second columnar portion 13b is electrically connected to the second bit line BL and the second source line SL. In addition, at least a part of the second bit line BL and the second source line SL is led to as a second bit line lead-out portion and a second source line lead-out portion through other wiring layers or plugs The outer side of the second memory cell array region 28b when viewed from a direction perpendicular to the third surface. The second bit line lead-out portion and the second source line lead-out portion drawn to the outside of the first memory cell array region 28b are connected to the second signal line lead electrode 37b provided on the outside of the second memory cell array region 28b. In addition, since the structure in the second memory cell array region 28b is the same as the first memory cell array layer 200, the description of the symbols is omitted.

On the third surface Sb1 and the fourth surface Sb2 of the second memory cell array layer 300, a third surface wiring layer 38b and a fourth surface wiring layer 39b are provided. The third surface wiring layer 38b and the fourth surface wiring layer 39b are embedded in the third surface Sb1 and the fourth surface Sb2, respectively, and the surfaces are exposed from the interlayer insulating layer (not shown). Here, for example, the second signal line extraction electrode 37b is electrically connected to the third surface wiring layer 38b and the fourth surface wiring layer 39b respectively provided on the third surface and the fourth surface of the second memory cell array layer 300. The second signal line extraction electrode and the third and fourth surface wiring layers penetrate the second memory cell array layer 300.

In addition, a second external connection electrode 40b is provided on the outer side of the second memory cell array region 28b. That is, the second external connection electrode 40b is provided in a region of the memory cell array that is more outside than the stepped structure portion. The second external connection electrode 40b is electrically connected to the third surface wiring layer 38b and the fourth surface wiring layer 39b provided on the third surface Sb1 and the fourth surface Sb2 of the second memory cell array layer 300, respectively. The third surface wiring layer 38b and the fourth surface wiring layer 39b are embedded in the third surface Sb1 and the fourth surface Sb2, respectively, and the surfaces are exposed from the interlayer insulating layer (not shown). The second external connection electrode 40 b, the third surface wiring layer 38 b, and the fourth surface wiring layer 39 b penetrate the second memory cell array layer 300. In the fourth surface wiring layer 39b, an external connection pad 52 is provided on the surface wiring layer electrically connected to the second external connection electrode 40b.

As shown in FIG. 1, the first surface wiring layer 38a provided on the first surface Sa1 and the circuit side wiring layer 42 provided on the circuit forming surface are pasted and joined. The first surface wiring layer 38a and the circuit side wiring layer 42 are, for example, copper or a copper alloy mainly composed of copper. An insulating film (not shown) is provided around the first surface wiring layer 38a and the circuit side wiring layer 42. The insulating film is, for example, an inorganic film, a resin film, or the like. The first memory cell array layer 200 and the peripheral circuit layer 100 are electrically connected via the first surface wiring layer 38 a and the circuit side wiring layer 42.

In addition, as shown in FIG. 1, the second surface wiring layer 39a provided on the second surface Sa2 and the third surface wiring layer 38b provided on the third surface Sb1 are pasted and joined. The second surface wiring layer 39a and the third surface wiring layer 38b are, for example, copper or a copper alloy containing copper as a main component. An insulating film (not shown) is provided around the second surface wiring layer 39a provided on the second surface and the third surface wiring layer 38b provided on the third surface Sb1. The insulating film is, for example, an inorganic film including a silicon nitride film. The first memory cell array layer and the second memory cell array layer are electrically connected via the second surface wiring layer 39a and the third surface wiring layer 38b.

In addition, when the insulating film around the wiring layer is an inorganic film, the wiring layers can be bonded to each other on the bonding surface, and bonding using hydrogen bonding between the inorganic films can be performed. Therefore, if an inorganic film is used as the insulating film, since the gap between the joint surfaces is not easily generated, it is preferable in that underfilling using a resin mold is not required.

5 is a schematic perspective view of the semiconductor memory device of the first embodiment, and is a schematic perspective view of the electrical connection state of the peripheral circuit layer, the first memory cell array layer, and the second memory cell array layer.

As shown in FIG. 5, the peripheral circuit layer 100, the first memory cell array layer 200, and the second memory cell array layer 300 are led by the first signal line lead electrode, the second signal line lead electrode, the first external connection electrode and the second 2 Externally connect electrodes (not shown) for electrical connection. Signal line lead-out electrodes are arranged outside the memory cell array regions 28a, 28b, and external connection electrodes are arranged on the outside of the memory cell array region, and the stepped structure part and the outside of the memory cell array. When viewed from a direction perpendicular to the first surface Sa1, the signal line lead-out electrodes and external connection electrodes of the memory cell array layer are respectively arranged in the overlapping area. The signal lead-out electrode is electrically connected to the surface wiring layers 39a and 39b, and the external connection electrode of the second memory cell array layer 300 which becomes the uppermost layer is electrically connected to the external connection pad 52. In addition, in FIG. 5, only a part of the electrical connection states of the first signal line extraction electrode, the second signal line extraction electrode, the first external connection electrode, and the second external connection electrode are shown, and the illustration is omitted otherwise.

Using FIGS. 6-9, the manufacturing method of the semiconductor memory device of the first embodiment will be described. 6 to 9 are related to the manufacturing method of the semiconductor memory device of the first embodiment, and are cross-sectional views of the semiconductor memory device.

As shown in FIG. 6, a control circuit including a transistor or the like is formed on the circuit substrate 1, and a peripheral circuit layer 100 having a circuit-side wiring layer 42 whose surface is exposed from an insulating film (not shown) is formed. In addition, a first insulating layer 50 is formed under the other substrate 2, such as a silicon oxide film as a buffer layer, and a first source line side wiring layer 19a and a first source line 17a are formed under the first insulating layer 50. A first selection gate SG, a plurality of electrode layers WL, and the like are formed under one source line 17a. Next, the memory string MS, the step structure portion 29, and the like are formed. Furthermore, a first surface wiring layer 38a whose surface is exposed from the first external connection electrode 40a, the first signal line extraction electrode 37a, and the insulating film (not shown) is formed to form the first memory cell array layer 200. Next, the circuit-side wiring layer 42 of the peripheral circuit layer 100 and the first surface wiring layer 38a of the first memory cell array layer 200 are laminated so as to face each other.

Next, as shown in FIG. 7, the peripheral circuit layer 100 and the first memory cell array layer 200 are laminated. At this time, the circuit-side wiring layer 42 and the first surface wiring layer 38a are joined. As the bonding method, for example, mechanical pressure is applied to bond and diffusion bonding is performed. Alternatively, inert plasma treatment is performed on the joint surface, and the joint is joined by hydrogen bonding due to the formation of OH groups on the joint surface. Alternatively, an organic adhesive or the like is used for bonding. Thereafter, the substrate 2 is removed by, for example, a chemical solution such as KOH. At this time, the insulating films around the respective wiring layers may be joined to each other.

It is believed that since the memory cell array layer does not have a substrate, it is easy to deform due to the stress applied to the memory cell array layer, causing the laminated semiconductor memory device to bend. Therefore, the second insulating layer 51 is formed. The second insulating layer 51 is a layer having stress in a direction opposite to the bending generated after removing the substrate, and is formed as a stress adjusting film. As the second insulating layer 51, for example, a silicon nitride film is formed. Thereby, the stress generated in the semiconductor memory device can be relieved, and the bending of the semiconductor memory device can be suppressed.

Next, the first insulating layer 50 and the second insulating layer 51 are removed so that the upper surfaces of the first external connection electrode 40a and the first signal line extraction electrode 37a are exposed to form grooves. As shown in FIG. 8, the second surface wiring layer 39a as a bonding metal is formed in this groove, and the upper surface of the second surface wiring layer 39a is exposed.

Next, following FIG. 8, replace the peripheral circuit layer 100 shown in FIG. 6 as the first memory cell array layer 200, and replace the first memory cell array layer 200 shown in FIG. 6 as the second memory cell array layer 300. Repeat the same steps as in Figs. 6 to 8. As shown in FIG. 9, in the fourth surface wiring layer 39b exposed on the upper surface, an external connection pad 52 is formed on the surface wiring layer electrically connected to the second external connection electrode 40b. In this way, a semiconductor memory device in which the peripheral circuit layer 100, the first memory cell array layer 200, and the second memory cell array layer 300 are laminated can be formed.

In the first embodiment, the second memory cell array layer 300 is laminated on the first memory cell array layer 200, but one or more other memory cell array layers may be further laminated on the second memory cell array layer 300. At this time, at least a part of one or more other memory cell array layers may also include a substrate. In this case, the bending of the stacked semiconductor memory device can be reduced.

In addition, the peripheral circuit layer 100 may not be laminated, and only a laminated body of the memory cell array layer may be formed.

(First modification example) 10 is a schematic cross-sectional view of a semiconductor memory device of a first modification of the first embodiment. A wiring layer 61 connecting the memory string MS1 of the first memory cell array layer 200 and the memory string MS2 of the second memory cell array layer 300 is provided. The wiring layer 61 is disposed inside the memory cell array area, and is connected to the first source-side wiring layer 19a of the first memory cell array layer 200 and the second bit line 16b of the second memory cell array layer 300. The first memory cell array layer and the second memory cell array layer are not connected via signal line lead-out electrodes arranged outside the memory cell array area.

In the first modification, the first memory cell array layer and the second memory cell array layer are connected with the wiring layer provided on the inner side of the memory cell array area in addition to the signal line lead-out electrodes provided outside the memory cell array area .

By forming in this way, the electrode area required for the connection of the memory cell array layer can be reduced, and the chip area can be reduced.

(The second modification example) 11 is a schematic cross-sectional view of a semiconductor memory device of a second modification of the first embodiment. The description of external connection electrodes is omitted.

At least a part of the character wiring layer and the selective gate wiring layer of the first memory cell array layer 200 are led out as the word line lead-out portion 35 and the select gate line lead-out portion 36 through other wiring layers or plugs. When viewed in the direction perpendicular to the first surface Sa1, it is folded back to the inner side of the first memory cell array region 28a. The character line lead-out portion 35 and the select gate line lead-out portion 36 drawn to the inner side of the first memory cell array region 28a are connected to the first signal line lead electrode 37a provided on the inner side of the first memory cell array region 28a.

In addition, at least a part of the first bit line BL and the first source line SL is also drawn out as a first bit line lead-out portion and a first source line lead-out portion through other wiring layers or plugs, When viewed from a direction perpendicular to the first surface Sa1, it turns back to the inner side of the first memory cell array region 28a (not shown). The first bit line lead-out portion and the first source line lead-out portion drawn to the inside of the first memory cell array region 28a are connected to the first signal line lead electrode 37a provided on the inner side of the first memory cell array region 28a.

In addition, the first source-side wiring layer 19a on the second surface Sa2 side is connected to the first signal line extraction electrode 37a provided inside the first memory cell array region 28a. Here, a part of the first signal line extraction electrode 37a may also be provided on the outer side of the first memory cell array region 28a.

On the first surface Sa1 and the second surface Sa2 of the first memory cell array layer 200, a first surface wiring layer 38a and a second surface wiring layer 39a are respectively provided inside the memory cell array area. The first surface wiring layer 38a and the second surface wiring layer 39a disposed inside the memory cell array area are electrically connected to the first signal line extraction electrode 37a.

In the second memory cell array layer 300, similar to the first memory cell array layer 200, at least a part of the character wiring layer and the selective gate wiring layer is formed by other wiring layers or plugs as the character line lead portion 35 and selection The gate line lead-out portion 36 is led out and folded back to the inside of the second memory cell array region 28b when viewed from the direction perpendicular to the third surface Sb1. The character line lead-out portion 35 and the select gate line lead-out portion 36 drawn to the inner side of the second memory cell array region 28b are connected to the second signal line lead electrode 37b provided on the inner side of the second memory cell array region 28b.

In addition, at least a part of the second bit line BL and the second source line SL is led out as a second bit line lead-out portion and a second source line lead-out portion through other wiring layers or plugs, and is drawn from perpendicular to When viewed in the direction of the third surface, it is folded back to the inner side of the second memory cell array region 28b (not shown). The second bit line lead-out portion and the second source line lead-out portion drawn to the inner side of the second memory cell array area 28b are connected to the second signal line lead-out electrode 37b provided on the inner side of the second memory cell array area 28b. Here, a part of the second signal line extraction electrode 37b may also be arranged outside the second memory cell array region 28b.

On the third surface Sb1 of the second memory cell array layer 300, a third surface wiring layer 38b is provided inside the memory cell array area. The third surface wiring layer 38 disposed inside the memory cell array area is electrically connected to the second signal line lead electrode 37b. Here, on the fourth surface Sb2 of the second memory cell array layer 300, a fourth surface wiring layer (not shown) may also be provided inside the memory cell array area. In this case, the fourth surface wiring layer provided inside the memory cell array area is electrically connected to the second signal line lead electrode 37b.

Therefore, the signal line lead-out electrodes of each memory cell array layer are connected to the surface wiring layer arranged inside the memory cell array area, and the surface wiring layer of each memory cell array layer can be arranged separately when viewed from a direction perpendicular to the first surface In the overlapping area. Thereby, when a plurality of memory cell array layers are laminated, the chip area can be further reduced, the wiring length can be suppressed, and the operation delay can be suppressed.

According to the second modification, at least a part of bit lines or word lines are folded back to the inside of the memory cell array area. The signal line lead-out electrodes connected via the bit line lead-out portion and the word line lead-out portion are arranged inside the memory cell array area. In addition, the signal line lead-out electrodes of each memory cell array layer are connected to the surface wiring layer arranged inside the memory cell array area, and the surface wiring layer of each memory cell array layer can be arranged separately when viewed from a direction perpendicular to the first surface In the overlapping area. Thereby, when a plurality of memory cell array layers are laminated, the chip area can be further reduced, the wiring length can be suppressed, and the operation delay can be suppressed.

According to the first embodiment, the first memory cell array layer 200 and the second memory cell array layer 300 do not have a substrate (for example, a silicon substrate). Therefore, when the first memory cell array layer 200 and the second memory cell array layer 300 are stacked and electrically connected, the TSV (Through Silicon Via) can be connected without forming a TSV. Thereby, there is no need to perform the etching step of the substrate that takes cost or processing time, or the formation of an insulating film to prevent the short circuit between the substrate and the through hole, which can reduce the cost and increase the throughput.

In addition, since the memory cell array layer and the peripheral circuit layer are formed by different wafer processes, when high-temperature heat treatment is required to form the memory cell array layer, the diffusion of impurities in the transistors of the peripheral circuit layer or the metal Adverse effects such as deterioration of the wiring layer.

In addition, the memory cell array layer is laminated so that the first surface faces the peripheral circuit layer. Lead the bit line or the word line to the first side of the memory cell array layer, and connect the bit line or the word line to the signal line lead electrode. Since the memory cell array layer is laminated with the first surface facing the peripheral circuit layer, the wiring distance of the electrode layer can be reduced and the adverse effect on the operating speed can be suppressed.

Furthermore, according to the first embodiment, a plurality of memory cell array layers are laminated on the peripheral circuit layer. By this, when the laminated body of 1 memory cell array layer is 48 layers, for example, by stacking 2 memory cell array layers, using 48-layer process technology, a 96-layer memory that is twice the 48-layer can be realized. Cell array. Therefore, the memory density can be easily increased.

Furthermore, at least a part of bit lines or word lines are led out to the outside of the memory cell array area, and signal line lead-out electrodes connected via bit line lead-out portions and word line lead-out portions, etc. are arranged in the memory cell array area Outside. In addition, on the outer side of the memory cell array area, and the area outside the step structure portion of the memory cell array, external connection electrodes are provided. When viewed from a direction perpendicular to the first surface, the signal line extraction electrodes and external connection electrodes of each memory cell array layer are respectively arranged in the overlapping area. Thereby, when a plurality of memory cell array layers are laminated, the wiring length can be suppressed, and the operation delay can be suppressed.

Alternatively, at least a part of bit lines or word lines are folded back to the inside of the memory cell array area. The signal line lead-out electrodes connected via the bit line lead-out portion and the word line lead-out portion are arranged inside the memory cell array area. In addition, the signal line lead-out electrode of each memory cell array layer is connected to the surface wiring layer arranged inside the memory cell array area, and the surface wiring layer of each memory cell array layer is arranged in the direction perpendicular to the first surface. Overlapping area. Thereby, when a plurality of memory cell array layers are laminated, the chip area can be further reduced, the wiring length can be suppressed, and the operation delay can be suppressed.

In addition, the external connection electrode and the surface wiring layer connected to the external connection electrode penetrate at least the upper and lower layers (here, the first memory cell array layer) sandwiched by the memory cell array layer or/and the peripheral circuit layer Set up. In addition, the signal line extraction electrode and the surface wiring layer connected to the signal line extraction electrode at least penetrate through the upper and lower layers sandwiched by the memory cell array layer or/and the peripheral circuit layer (here, the first memory cell array layer) The way to set. Therefore, when a plurality of memory cell array layers are stacked, the wiring length can be further suppressed, the operation delay can be further suppressed, and the reliability can be improved.

Furthermore, the external connection electrode can be arranged without connecting to the memory cell, and external signals can be input to the peripheral circuit layer from the external connection pad without passing through the memory cell. This can further suppress adverse effects such as operation delay. In addition, since the signal line leading electrode is electrically connected to each memory cell array layer even in a path that is not connected to the memory cell, the signal line of each layer is not connected through the memory cell. This can further suppress adverse effects such as operation delay.

In addition, the memory cell array layer does not have a substrate, and there is no need to form TSV and other silicon through electrodes. Instead of providing a substrate, a source-side wiring layer is provided on the second surface side (fourth surface side) of the memory cell array layer. Thereby, the stacked memory cell array layers can be arbitrarily connected, and the wiring area can be increased without increasing the chip area.

Furthermore, the first source-side wiring layer can be used as the first source lead-out portion of the first source line SL. The second source-side wiring layer can be used as the second source line lead-out portion of the second source line SL. In this way, in the memory cell array having the I-shaped columnar portion, the source side wiring layer is provided on the second surface side (fourth surface side) of the source line, which can effectively suppress the source The wiring length from wire to signal wire lead electrode.

In addition, the signal line extraction electrode and the surface wiring layer of the second memory cell array layer can also be formed to penetrate the second memory cell array layer in the same manner as the first memory cell array layer. In this case, the device structure of the first memory cell array layer and the second memory cell array layer can be shared, and the characteristics such as stress generated by the memory cell array layer can be uniform. In addition, it is better in that the manufacturing process of the first memory cell array layer and the second memory cell array layer can be shared, and the memory cell array layer can be manufactured efficiently.

In addition, in the first memory cell array layer or the second memory cell array layer, the bit line or the word line is drawn to the first surface side or the third surface side, and the bit line or the word line is connected to the signal line Lead out the electrode. The first memory cell array layer is laminated so that the first side faces the peripheral circuit layer, and the second memory cell array layer is laminated so that the third side faces the first memory cell array layer. That is, the first memory cell array layer and the second memory cell array layer lead out the signal lines in the same direction, and the first memory cell array layer and the second memory cell array layer are stacked in such a way that the orientation of the second memory cell array layer is the same. In this way, since the bit line or the word line is drawn to the side where the peripheral circuit layer is provided (the lower side in FIG. 1) and stacked on the peripheral circuit layer, the wiring distance of the electrode layer can be reduced, and the interaction can be suppressed The adverse effect of speed.

In addition, assuming that the first memory cell array layer and the second memory cell array layer are stacked in different directions, for example, a memory cell array layer must be placed on a tape. After the substrate is removed from the tape, Laminate in such a way that the surface after removing the substrate faces the peripheral circuit or another memory cell array layer. If the first memory cell array layer and the second memory cell array layer are laminated with the same orientation, there is no need to use a tape or the like. That is, it can be formed by laminating the memory cell array layer formed on the substrate directly on the peripheral circuit layer with the substrate surface as the top, and removing the substrate. Thereby, the memory cell array layer and the second memory cell array layer are laminated with the same orientation, which is also preferable in that they can be easily formed without using a tape or the like.

(Second Embodiment) Next, the semiconductor memory device of the second embodiment will be described. In addition, the basic configuration is the same as that of the first embodiment, so the description of the matters explained in the first embodiment is omitted.

12 is a schematic cross-sectional view of the semiconductor memory device of the second embodiment. In FIG. 12, for the semiconductor memory device of FIG. 1, a memory cell array layer is further laminated, and a peripheral circuit layer 100, a first memory cell array layer 200, and a second memory cell array layer are sequentially arranged from the bottom. 300. The third memory cell array layer 400.

Here, as shown in FIG. 12, the laminated second memory cell array layer 300 is between the third surface wiring layer 38b provided on the third surface Sb1 and the fourth surface wiring layer 39b provided on the fourth surface Sb2 , There is a wiring layer 71 connected to the memory string MS3. That is, the second memory cell array layer 300 is connected to the upper and lower memory cell array layers via the wiring layer 71 via the memory string MS3.

Fig. 13 is a circuit diagram of the semiconductor memory device of the second embodiment. In FIG. 13, a part of the circuit of the memory string MS3 connected to the wiring layer 71 is shown. There are plural memory cells, some of which are omitted. A drain-side selective transistor STD and a source-side selective transistor STS are provided on the plurality of memory cells, and the memory has an array layer ID arranged on each memory cell array layer. The circuit of the memory string MS3 functions as a part of the selection circuit for selecting the array layer of the array layer.

FIG. 14 is a block diagram showing the system configuration of the semiconductor memory device of the second embodiment. In FIG. 14, the structure of a system including a semiconductor memory device including an array layer selection circuit provided in the memory string MS3 connected to the wiring layer 71 is shown.

At each memory cell array layer, input address lines and array layer selection signal lines as signal lines. In the memory cell array layer, the array layer selects the signal line and the memory array layer ID to determine whether to select the memory cell array layer, and input address lines to the memory cell array.

By forming in this way, instead of using each signal line to individually select the memory cell array, the transistor and memory cell in the memory string MS3 can be used to select the memory cell array layer, even if it is a semiconductor with a plurality of stacked memory cell array layers. The memory device can also greatly reduce the number of wiring.

Moreover, in this case, for each of the memory area or the memory block of the second memory cell array layer, the wiring layer 71 can also be used to connect to the upper and lower memory cell array layers. By forming in this way, each transistor and each memory cell in each memory string MS can be used to select a memory area or a memory block, even if it is a semiconductor memory device with a plurality of stacked memory cell array layers. Significantly reduce the number of wiring.

In the above, while referring to the drawings, the embodiment has been described. However, the present invention is not limited to this.

In the present invention, an example including a circuit board is described, but a case where only the memory cell array layer is laminated is also included in the scope of the present invention.

Those skilled in the art who have made various design changes regarding the structure of the memory cell array constituting the present invention are also included in the scope of the present invention as long as they do not depart from the gist of the present invention.

Furthermore, according to yet another aspect, a semiconductor memory device is provided, which is characterized by having a 3-dimensional memory cell array of other configurations.

Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and changes can be made without departing from the spirit of the invention. These embodiments or their changes are included in the scope or spirit of the invention, and are included in the invention described in the patent application and its equivalent scope.

1: Circuit board 2: substrate 10a: The first memory cell array 10b: 2nd memory cell array 11: Insulation layer 12a: Layer 1 13a: The first columnar part 13b: The second columnar part 14: Interlayer insulating film 15: Interlayer insulating film 16a: 1st bit line 16b: 2nd bit line 17a: 1st source line 18: Interlayer insulating film 19a: The first source-side wiring layer 19b: 2nd source side wiring layer 20: Channel body 21: Memory film 22: Block insulation film 23: charge accumulation film 24: Tunnel insulation film 25: Core insulation film 26: insulating film 27: Insulating film 28a: The first memory cell array area 28b: 2nd memory cell array area 29: Step structure 30: contact plug 31: Interlayer insulation layer 32: contact plug 33: Character wiring layer 34: Select the gate wiring layer 35: Character line lead-out part 36: Select the gate lead 37a: Leading electrode of the first signal line 37b: 2nd signal wire lead electrode 38a: The first surface wiring layer 38b: 3rd surface wiring layer 39a: Second surface wiring layer 39b: 4th surface wiring layer 40a: The first external connection electrode 40b: 2nd external connection electrode 41: Circuit side connection electrode 42: Circuit side wiring layer 50: The first insulating layer 51: 2nd insulating layer 52: External connection pad 61: Wiring layer 71: Wiring layer 100: Peripheral circuit layer 200: The first memory cell array layer 221: silicon nitride film 222: Silicon oxide film 300: 2nd memory cell array layer 400: 3rd memory cell array layer A: Part BL: bit line MC: memory cell MS: memory string MS1: memory string MS2: memory string MS3: memory string Sa1: side 1 Sa2: Side 2 Sb1: Side 3 Sb2: Side 4 SG: select gate SGD: Select the gate on the drain side SGS: Source side select gate SL: source line STD: Select the transistor on the drain side STS: Source-side select transistor WL: Electrode layer X: direction Y: direction Z: direction

FIG. 1 is a schematic cross-sectional view showing the semiconductor memory device of the first embodiment. FIG. 2 is a schematic perspective view showing the semiconductor memory device of the first embodiment. 3 is a schematic cross-sectional view showing the semiconductor memory device of the first embodiment. 4 is an enlarged schematic cross-sectional view of a part of the semiconductor memory device of the first embodiment. FIG. 5 is a schematic perspective view showing the semiconductor memory device of the first embodiment. 6 is a schematic cross-sectional view showing the manufacturing method of the semiconductor memory device of the first embodiment. 7 is a schematic cross-sectional view showing the manufacturing method of the semiconductor memory device of the first embodiment. FIG. 8 is a schematic cross-sectional view showing the manufacturing method of the semiconductor memory device of the first embodiment. 9 is a schematic cross-sectional view showing the manufacturing method of the semiconductor memory device of the first embodiment. 10 is a schematic cross-sectional view of a semiconductor memory device of a first modification of the first embodiment. 11 is a schematic cross-sectional view of a semiconductor memory device of a second modification of the first embodiment. FIG. 12 is a schematic cross-sectional view showing the semiconductor memory device of the second embodiment. Fig. 13 is a circuit diagram of the semiconductor memory device of the second embodiment. FIG. 14 is a block diagram showing the system configuration of the semiconductor memory device of the second embodiment.

1: Circuit board

10a: The first memory cell array

10b: 2nd memory cell array

19a: The first source-side wiring layer

19b: 2nd source side wiring layer

28a: The first memory cell array area

28b: 2nd memory cell array area

29: Step structure

30: contact plug

31: Interlayer insulation layer

32: contact plug

33: Character wiring layer

34: Select the gate wiring layer

35: Character line lead-out part

36: Select the gate lead

37a: Leading electrode of the first signal line

37b: 2nd signal wire lead electrode

38a: The first surface wiring layer

38b: 3rd surface wiring layer

39a: Second surface wiring layer

39b: 4th surface wiring layer

40a: The first external connection electrode

40b: 2nd external connection electrode

41: Circuit side connection electrode

42: Circuit side wiring layer

52: External connection pad

100: Peripheral circuit layer

200: The first memory cell array layer

300: 2nd memory cell array layer

BL: bit line

Sa1: side 1

Sa2: Side 2

Sb1: Side 3

Sb2: Side 4

SG: select gate

SL: source line

WL: Electrode layer

X: direction

Z: direction

Claims (8)

A semiconductor memory device comprising: Substrate The transistor is arranged on the above-mentioned substrate; The peripheral circuit layer has a first bonding metal disposed on the bonding surface facing the memory cell array layer; and A memory cell array layer, which is attached to the above-mentioned peripheral circuit layer; and The aforementioned memory cell array layer includes: Laminated body, which is an electrode layer and an insulating layer alternately laminated in the first direction in plural layers; A columnar portion, which extends in the first direction within the laminated body, and a memory cell is formed in a portion intersecting with the electrode layer; A first wiring layer, which is provided between the bonding surface and the laminate; A plug that connects one of the plurality of electrode layers and the first wiring layer and extends in the first direction; and The second bonding metal is provided on the first bonding metal and is electrically connected to the first wiring layer; and The second bonding metal overlaps with the laminate when viewed from the first direction. The semiconductor memory device of claim 1, wherein the first bonding metal and the second bonding metal are directly bonded. The semiconductor memory device of claim 1, wherein the memory cell array layer has a first surface connected to the bonding surface and a second surface opposite to the first surface, and does not include a substrate; and The aforementioned semiconductor memory device further includes: A second wiring layer, which is provided between the second surface and the laminate; A third bonding metal, which is provided on the second surface, overlaps the laminate when viewed from the first direction, and is electrically connected to the second wiring layer; and The signal line extraction electrode is electrically connected to the first wiring layer and the second wiring layer, and extends in the first direction. The semiconductor memory device of claim 3, wherein a bit line is electrically connected to the first surface side of the columnar portion, and a source line is electrically connected to the second surface side of the columnar portion. The source line is further provided with the second wiring layer on the second surface side. Such as the semiconductor memory device of claim 3 or 4, which further has at least one other memory cell array layer of the same type as the above-mentioned memory cell array layer laminated in a manner opposed to the above-mentioned memory cell array layer, and has two or more layers The plural memory cell array layers. The semiconductor memory device of claim 5, wherein at least one memory cell array layer of the plurality of memory cell array layers is provided with a memory string as part of the array layer selection circuit, and the memory string has a circuit for selecting the memory cell array layer The memory cell of the crystal and memory array layer ID. The semiconductor memory device of claim 6, wherein the plurality of memory cell array layers are at least three layers of memory cell array layers, and a part of the array layer selection circuit is arranged in the plurality of memory cell array layers by other memory cells A memory cell array layer sandwiched by the array layer. The semiconductor memory device of claim 6, wherein a part of the array layer selection circuit is disposed in each memory area or memory block of the at least one memory cell array layer.

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