TW202044587A - Semiconductor device - Google Patents

Abstract

This invention provides a semiconductor device which comprises an active layer, a first semiconductor layer, a first strain-release structure positioned between the active layer and the first semiconductor layer, and an intermediate layer positioned between the first strain-release structure and the active layer. The strain-release structure comprises plural first sub-layers and plural second sub-layers alternately stacked. The band gap of the second sub-layer is smaller than the band gap of the first sub-layer. The intermediate layer comprises a first portion connected to the first strain-release layer and a second portion connected to the active layer, wherein the second portion and the second sub-layer each comprises an indium composition and the indium composition of the second portion is smaller than that of the second sub-layer.

Description

Semiconductor components

The present invention relates to a semiconductor device, especially to a semiconductor device with an intermediate layer.

III-V compound semiconductors have been widely developed and used in various electronic components, such as high electron-mobility transistors (HEMT), high-efficiency photovoltaic devices (photovoltaic devices), and light-emitting diodes ( light-emitting diode; LED).

Taking light-emitting diodes as an example, light-emitting diodes have been regarded as one of the best solutions to replace traditional light sources. In order to further achieve energy-saving and carbon-saving effects, brightness enhancement has always been a long-term research topic in the field . The brightness improvement of light-emitting diodes is mainly divided into two parts. One is the improvement of Internal Quantum Efficiency (IQE), which is mainly through the improvement of the epitaxial film structure to increase the efficiency of electron-hole bonding; the other is The improvement of Light Extraction Efficiency (LEE) mainly focuses on enabling the light emitted from the active layer to effectively penetrate to the outside of the device and reducing the absorption of light by the internal structure of the light-emitting diode.

The present invention is to improve the quality of the epitaxial thin film structure of III-V compound semiconductor devices, thereby improving the performance of semiconductor devices, such as increasing the internal quantum efficiency of light-emitting diodes.

The present invention provides a semiconductor device, which includes an active layer, a first semiconductor layer, a first stress buffer structure, located between the active layer and the first semiconductor layer, an intermediate layer located in the first stress buffer structure and Between the active layers, wherein the first stress buffer structure includes a plurality of first sublayers and a plurality of second sublayers overlapping each other, and the energy gap of the second sublayer is smaller than the energy gap of the first sublayer, The intermediate layer includes a first portion adjacent to the first stress buffer structure and a second portion adjacent to the active layer, the second portion and the second sublayer each include an indium content, and the second portion has an indium content less than the first The indium content of the two sublayers. In another embodiment of the present invention, the semiconductor device further includes a second stress buffer structure located between the second part and the active layer, wherein the second stress buffer structure includes a plurality of third sublayers and A plurality of fourth sublayers overlap each other, and the energy gap of the fourth sublayer is smaller than the energy gap of the third sublayer.

Figure 1 shows a first embodiment of a semiconductor device according to the present invention. The semiconductor device 1 includes a substrate 10, a first semiconductor layer 20 formed on the substrate 10, and a first stress buffer structure 31 formed on the first semiconductor layer 20 , An intermediate layer 40 is formed on the first stress buffer structure 20, an active layer 50 is formed on the intermediate layer 40, a second semiconductor layer 60 is formed on the active layer 50, and a first electrode 71 is electrically conductive It is connected to the first semiconductor layer 20 and a second electrode 72 is electrically connected to the second semiconductor layer 60. In an embodiment of the present invention, the first semiconductor layer 20 includes a first region and a second region, the first stress buffer layer 31 is formed on the first region, and the first electrode 71 is formed on the The second area is electrically connected to the first semiconductor layer 20; wherein, the first stress buffer structure 31, the intermediate layer 40, the active layer 50, and the first electrode 71 are not provided between the second area and the first electrode 71 The second semiconductor layer 60.

In one embodiment of the present invention, the substrate 10, the first semiconductor layer 20, the first stress buffer structure 31, the intermediate layer 40, the active layer 50 and the second semiconductor layer 60 all comprise a single crystal epitaxial structure. Each epitaxial structure is preferably formed by metal organic vapor deposition (MOCVD), and the material composition of each epitaxial structure can be changed by changing the reactants passed into the reactor when the epitaxial structure is formed The flow rate and/or reactor temperature can be adjusted. The difference between the lattice constant of the substrate 10 and the lattice constant of the first semiconductor layer 20 is not less than 1% of the lattice constant of the substrate 10, wherein the material of the substrate 10 includes sapphire, for example. The first semiconductor layer 20 includes a III-V compound having a first conductivity type, such as n-type gallium nitride (GaN) and an n-type dopant (for example, silicon) and an n-type doping concentration between Between 1*10 ¹⁸ ~5*10 ¹⁸ cm ^-3 . The second semiconductor layer 60 includes a group III-V compound having a second conductivity type, for example, p-type GaN with a p-type dopant (for example, magnesium) and a p-type dopant concentration of 1*10 ¹⁹ ~5*10 ²⁰ cm ^-3 , where the second conductivity type is opposite to the first conductivity type. When the semiconductor element 1 is a light emitting diode (LED), the active layer 50 includes, for example, III-V compounds and a multiple quantum well (Multiple Quantum Wells; MQW) structure, wherein the multiple quantum well structure includes a plurality of barrier layers ( The barrier layer 501 and a plurality of well layers 502 are stacked alternately, and emit visible light or invisible light when driven, and the number of overlapped pairs is between 3-15 pairs. The material of the well layer 501 has an energy band gap corresponding to the wavelength of the emitted light and is smaller than the energy gap of the barrier layer 501. The well layer 502 includes, for example, unintentionally doped In _x Ga _1–xN ( 0.05≤x≤0.25) and has a thickness between 1~5 nm. The barrier layer 501 includes, for example, doped or unintentionally doped GaN and/or Al _x Ga _1-x N (0.01≤x≤0.1 ) And has a thickness between 5-15 nm.

In an embodiment of the present invention, the first stress buffer structure 31 includes, for example, a plurality of first sub-layers 311 and a plurality of second sub-layers 312 alternately stacked to form a superlattice structure, wherein the number of overlapping pairs Between 3~10 pairs (pairs); among them, the second sub-layer 312 closest to the intermediate layer 40 is directly connected to the intermediate layer 40; among them, the material of the second sub-layer 312 includes unintentionally doped III-V compounds , For example, In _x Ga _1-x N (0.01 ≤ x ≤ 0.03); the material of the first sub-layer 311 includes a first conductivity type III-V compound, such as n-type GaN or n-type In _x Ga _{1- x} N (0.001≤x≤0.01) and has an n-type dopant (for example, silicon) and an n-type dopant concentration between 10 ^{1 7} cm ^-3 and 10 ¹⁸ cm ^-3 . Among them, the first The sub-layer 311 does not contain indium or contains an indium content less than that of the second sub-layer 312. The first sub-layer 311 has a thickness between 10-50 nm; the second sub-layer 312 has a thickness between 0.5-3 nm; the first stress buffer structure 31 has a thickness between 50-500 nm.

In one embodiment of the present invention, the intermediate layer 40 includes a first portion 401 adjacent to the first stress buffer structure 31 and a second portion 402 adjacent to the active layer 50; the first portion 401 does not contain indium or contains an indium content less than the first portion The indium content, for example, includes GaN or In _x Ga _1-x N (0 <x ≤0.01); the second part 402 is directly connected to the first part 401, and its material includes, for example, In _x Ga _1-x N (0.001≤ x ≤ 0.02) and has an indium content greater than that of the first portion 401. In one embodiment of the present invention, the indium content of the second portion 402 is less than the indium content of the second sub-layer 312 to reduce piezoelectric strain generated between the first stress buffer structure 31 and the active layer 50. The intermediate layer 40 has a thickness of less than 100 nm; preferably between 30 nm and 90 nm; wherein, the first portion 401 has a thickness between 10 nm and 50 nm, and the second portion 402 has a thickness between 0.5 nm and 15 nm. Wherein, the ratio of the thickness of the second portion 402 to the thickness of the intermediate layer 40 is between 0.1 and 0.5. In an embodiment of the present invention, the indium content of the second portion 402 is less than the indium content of the second sublayer 312, and the thickness of the second portion 402 is greater than or equal to the thickness of the second sublayer 312 to further reduce the first stress buffer structure The compressive stress generated between 31 and the active layer 50. The first portion 401 and second portion 402 each having an n-type dopant (such as silicon) and an n-type doping concentration between 10 ^{1 8} cm ^-3 and 10 ¹⁹ cm ^-3 range. Preferably, the n-type doping concentration of the second part 402 is greater than the n-type doping concentration of the first part 401. In an embodiment of the present invention, the thickness of the intermediate layer 40 is smaller than the thickness of the first stress buffer structure 31.

Figure 2 shows the second embodiment of the semiconductor device in accordance with the present invention. The semiconductor device 2 includes a substrate 10, a first semiconductor layer 20 formed on the substrate 10, and a first stress buffer structure 31 formed on the first semiconductor layer 20 , An intermediate layer 40 is formed on the first stress buffer structure 20, a second stress buffer structure 32 is formed on the intermediate layer 40, an active layer 50 is formed on the second stress buffer structure 32, and a second The semiconductor layer 60 is formed on the active layer 50, a first electrode 71 is electrically connected to the first semiconductor layer 20, and a second electrode 72 is electrically connected to the second semiconductor layer 60. In one embodiment of the present invention, the first semiconductor layer 20 includes a first region and a second region, the first stress buffer layer 31 is formed on the first region; the first electrode 71 is formed on the The second region is electrically connected to the first semiconductor layer 20; wherein, there is no first stress buffer structure 31, intermediate layer 40, and second stress buffer structure between the second region and the first electrode 71 32. The active layer 50 and the second semiconductor layer 60. The difference between the second embodiment and the first embodiment is that the semiconductor device 2 includes not only the entire structure of the semiconductor device 1, but also a second stress buffer structure 32 formed between the intermediate layer 40 and the active layer 50, where the second The stress buffer structure 32 includes a single crystal epitaxial structure, and the second stress buffer structure 32 includes, for example, a plurality of third sub-layers 321 and a plurality of fourth sub-layers 322 stacked alternately to form a superlattice structure, wherein the number of overlapped logs Between 3~10 pairs (pairs). In one embodiment of the present invention, the fourth sublayer 321 closest to the active layer 50 is directly connected to one of the barrier layers 502 of the active layer 50; the third sublayer 321 closest to the intermediate layer 40 and the second Part 402 is directly connected. The indium content of the fourth sublayer 322 of the second stress buffer structure 32 is greater than the indium content of the second sublayer 322 of the first stress buffer structure 31, wherein the third sublayer 321 does not contain indium or contains an indium content less than the fourth The indium content of the sub-layer 322; the material of the third sub-layer 321 includes, for example, GaN or In _x Ga _1-x N (0< x ≤ 0.02), and the material of the fourth sub-layer 322 includes, for example, In _x Ga _1-x N ( 0.03≤x≤0.1), wherein the indium content of the fourth sublayer 322 is greater than the indium content of the second sublayer 312. Wherein, the third sub-layer 321 has an n-type dopant (for example, silicon) and an n-type doping concentration is between 10 ^{1 7} cm ^-3 and 10 ¹⁸ cm ^-3 . The n-type doping concentration of the second portion 402 of the intermediate layer is greater than the n-type doping concentration of the third sub-layer 321 to reduce the compressive stress generated between the first stress buffer structure 31 and the active layer 50. Preferably, the n-type doping concentration of the second portion 402 is greater than the n-type doping concentration of the first portion 401 and the n-type doping concentration of the second portion 402 is greater than the n-type doping concentration of the third sublayer 321 to further reduce The compressive stress generated between the first stress buffer structure 31 and the active layer 50. The third sub-layer 321 has a thickness between 5-10 nm; the fourth sub-layer 322 has a thickness between 0.5-3 nm; and the second stress buffer structure 32 has a thickness between 30-80 nm. In one embodiment of the present invention, the thickness of the intermediate layer 40 is equal to or greater than the thickness of the second stress buffer structure 32, and the thickness of the intermediate layer 40 is smaller than the thickness of the first stress buffer structure 31. The description of the rest of the structure of this embodiment is the same as that of the first embodiment, that is, the structures with the same reference numerals in Fig. 2 and Fig. 1 represent the same structures, and have been described in detail in the first embodiment, and will not be repeated here.

The invention can effectively reduce the compressive stress of the semiconductor element, reduce the forward voltage and improve the luminous efficiency. The embodiments listed in the present invention are only used to illustrate the present invention, but not to limit the scope of the present invention. Any obvious modification or change made by anyone to the present invention does not depart from the spirit and scope of the present invention.

1, 2: Semiconductor components 10: substrate 20: The first semiconductor layer 31: The first stress buffer structure 311: first sublayer 312: second sublayer 32: The second stress buffer structure 321: third sublayer 322: fourth sublayer 40: middle layer 401: Part One 402: Part Two 50: active layer 501: Barrier Layer 502: Well Layer 60: second semiconductor layer 71: first electrode 72: second electrode

FIG. 1 is a schematic diagram showing the first embodiment of the semiconductor device according to the present invention.

FIG. 2 is a schematic diagram showing the second embodiment of the semiconductor device according to the present invention.

1: Semiconductor components

10: substrate

20: The first semiconductor layer

31: The first stress buffer structure

311: first sublayer

312: second sublayer

40: middle layer

401: Part One

402: Part Two

50: active layer

501: Barrier Layer

502: Well Layer

60: second semiconductor layer

71: first electrode

72: second electrode

Claims (10)

A semiconductor component, which includes: An active layer A first semiconductor layer; A first stress buffer structure is located between the active layer and the first semiconductor layer. The first stress buffer structure includes a plurality of first sublayers and a plurality of second sublayers overlapping each other. The energy gap is smaller than the energy gap of the first sublayer; An intermediate layer is located between the first stress buffer structure and the active layer, wherein the intermediate layer includes a first part adjacent to the first stress buffer structure and a second part adjacent to the active layer, wherein the second part and The second sublayers each include an indium content and the indium content of the second part is less than the indium content of the second sublayer. The semiconductor device according to claim 1, wherein the ratio of the thickness of the second part to the thickness of the intermediate layer is between 0.1 and 0.5. The semiconductor device according to claim 1, wherein the thickness of the second part is greater than or equal to the thickness of the second sub-layer. The semiconductor device according to claim 1, wherein the first part and/or the first sublayer does not contain indium. The semiconductor device described in claim 1 further includes a second stress buffer structure located between the second part and the active layer, wherein the second stress buffer structure includes a plurality of third sublayers and a plurality of The fourth sublayers overlap each other, and the energy gap of the fourth sublayer is smaller than the energy gap of the third sublayer. The semiconductor device according to claim 5, wherein the first part, the second part, the first sub-layer and the third sub-layer each include an n-type dopant and an n-type doping concentration . The semiconductor device according to claim 6, wherein the n-type doping concentration of the second part is greater than the n-type doping concentration of the third sub-layer. The semiconductor device according to claim 6, wherein the n-type doping concentration of the second part is greater than the n-type doping concentration of the first part. The semiconductor device according to item 5 of the scope of patent application, wherein the first stress buffer structure and/or the second stress buffer structure comprise a superlattice structure. The semiconductor device according to claim 1, wherein the thickness of the intermediate layer is less than the thickness of the first stress buffer structure.

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