TW202032262A - Method of manufacturing semiconductor device and system for manufacturing semiconductor device - Google Patents

Abstract

A method (of manufacturing a semiconductor device) includes, for a layout diagram stored on a non-transitory computer-readable medium, generating the layout diagram including: selecting a candidate pattern in the layout diagram, the candidate pattern being a first conductive pattern in the M_2nd level (first M_2nd pattern) or a first conductive pattern in the M_1st level (first M_1st pattern); determining that the candidate pattern satisfies one or more criteria; and changing a size of the candidate pattern thereby revising the layout diagram.

Description

Method for generating layout drawing to improve wiring resources and its system

An integrated circuit ("IC") includes one or more semiconductor components. One way to represent semiconductor devices is through a plan view called a layout plan. Generate layout diagrams in the context of design rules. A set of design rules restricts the placement of corresponding patterns in the layout, for example, geographic/spatial restrictions, connection restrictions, or the like. Often the set of design rules includes a subset of design rules related to the spacing and other interactions between patterns in adjacent or adjacent cells, where patterns represent conductors in a metalized layer.

Generally, a set of design rules is specifically used for process technology nodes, by which process technology nodes will manufacture semiconductor devices based on layout drawings. The set of design rules compensates for the variability of the corresponding process technology nodes. This compensation increases the possibility that the actual semiconductor device generated by the layout drawing will be an acceptable counterpart of the virtual device on which the layout drawing is based.

100‧‧‧Semiconductor components

101‧‧‧Circuit Macro

102‧‧‧Column

104‧‧‧Unit area

200A‧‧‧Layout

200B‧‧‧Layout

200C‧‧‧Layout

200D‧‧‧Layout

200E‧‧‧Layout

200F‧‧‧Layout

202‧‧‧Column

203N‧‧‧Subline

203P‧‧‧Subline

Unit 204(1)(A)‧‧‧

Unit 204(1)(B)‧‧‧

Unit 204(2)(C)‧‧‧

Unit 204(2)(D)‧‧‧

Unit 204(3)(E)‧‧‧

Unit 204(3)(F)‧‧‧

208N‧‧‧Active area pattern

208P‧‧‧Main area pattern

210(1)‧‧‧MD pattern

210(2)‧‧‧MD pattern

210(3)‧‧‧MD pattern

210(4)‧‧‧MD pattern

210(5)‧‧‧MD pattern

210(6)‧‧‧MD pattern

210(7)‧‧‧MD pattern

210(8)‧‧‧MD pattern

210(9)‧‧‧MD pattern

210(10)‧‧‧MD pattern

210(11)‧‧‧MD pattern

210(12)‧‧‧MD pattern

210(13)‧‧‧MD pattern

210(14)‧‧‧MD pattern

210(15)‧‧‧MD pattern

210(16)‧‧‧MD pattern

210(17)‧‧‧MD pattern

210(18)‧‧‧MD pattern

210(19)‧‧‧MD pattern

210(20)‧‧‧MD pattern

212(1)‧‧‧Gate pattern

212(2)‧‧‧Gate pattern

212(3)‧‧‧Gate pattern

212(4)‧‧‧Gate pattern

212(5)‧‧‧Gate pattern

212(6)‧‧‧Gate pattern

214(1)‧‧‧Gate pattern

214(2)‧‧‧Gate pattern

214(3)‧‧‧Gate pattern

214(4)‧‧‧Gate pattern

214(5)‧‧‧Gate pattern

214(6)‧‧‧Gate pattern

214(7)‧‧‧Gate pattern

214(8)‧‧‧Gate pattern

214(9)‧‧‧Gate pattern

214(10)‧‧‧Gate pattern

214(11)‧‧‧Gate pattern

214(12)‧‧‧Gate pattern

216(1)‧‧‧VGD pattern

216(2)‧‧‧VGD pattern

216(3)‧‧‧VGD pattern

216(4)‧‧‧VGD pattern

216(5)‧‧‧VGD pattern

216(6)‧‧‧VGD pattern

216(7)‧‧‧VGD pattern

216(8)‧‧‧VGD pattern

216(9)‧‧‧VGD pattern

216(10)‧‧‧VGD pattern

216(11)‧‧‧VGD pattern

216(12)‧‧‧VGD pattern

216(13)‧‧‧VGD pattern

216(14)‧‧‧VGD pattern

216(15)‧‧‧VGD pattern

216(16)‧‧‧VGD pattern

216(17)‧‧‧VGD pattern

216(18)‧‧‧VGD pattern

216(19)‧‧‧VGD pattern

216(20)‧‧‧VGD pattern

216(21)‧‧‧VGD pattern

216(22)‧‧‧VGD pattern

216(23)‧‧‧VGD pattern

218(1)‧‧‧M0 pattern

218(2)‧‧‧M0 pattern

218(3)‧‧‧M0 pattern

218(4)‧‧‧M0 pattern

218(5)‧‧‧M0 pattern

218(6)‧‧‧M0 pattern

218(7)‧‧‧M0 pattern

218(8)‧‧‧M0 pattern

218(9)‧‧‧M0 pattern

218(10)‧‧‧M0 pattern

218(11)‧‧‧M0 pattern

218(12)‧‧‧M0 pattern

218(12)'‧‧‧Dotted line shape

218(13)‧‧‧M0 pattern

218(14)‧‧‧M0 pattern

218(14)'‧‧‧Dotted line shape

218(15)‧‧‧M0 pattern

218(16)‧‧‧M0 pattern

218(17)‧‧‧M0 pattern

218(18)‧‧‧M0 pattern

218(19)‧‧‧M0 pattern

218(20)‧‧‧M0 pattern

218(20)'‧‧‧M0 pattern

218(21)‧‧‧M0 pattern

220(1)‧‧‧VIA0 pattern

220(1)'‧‧‧dotted line shape

220(2)‧‧‧VIA0 pattern

220(3)‧‧‧VIA0 pattern

220(3)'‧‧‧dotted line shape

220(4)‧‧‧VIA0 pattern

220(4)'‧‧‧dotted line shape

220(5)‧‧‧VIA0 pattern

222(1)‧‧‧M1 pattern

222(2)‧‧‧M1 pattern

222(3)‧‧‧M1 pattern

222(4)‧‧‧M1 pattern

230‧‧‧Side border

232‧‧‧Gap

300A‧‧‧Layout

300B‧‧‧Layout

300C‧‧‧Layout

300D‧‧‧Layout

300E‧‧‧Layout

300F‧‧‧Layout

300G‧‧‧Layout

300H‧‧‧Layout

Unit 304(1)(A)‧‧‧

Unit 304(1)(B)‧‧‧

Unit 304(2)(C)‧‧‧

Unit 304(2)(D)‧‧‧

312(1)‧‧‧Gate pattern

312(2)‧‧‧Gate pattern

314(1)‧‧‧Gate pattern

314(2)‧‧‧Gate pattern

316(1)‧‧‧VGD pattern

318(1)‧‧‧VGD pattern

318(1)(A)‧‧‧M0 pattern

318(2)‧‧‧M0 pattern

318(2)(C)‧‧‧M0 pattern

318(2)(D)‧‧‧M0 pattern

318(3)(E)‧‧‧M0 pattern

318(3)(F)‧‧‧M0 pattern

318(4)(G)‧‧‧M0 pattern

318(4)(H)‧‧‧M0 pattern

320(1)‧‧‧VIA0 pattern

336(1)‧‧‧OH/Width

336(2)‧‧‧OH/Width

336(3)‧‧‧OH/Width

336(4)‧‧‧OH/Width

338(1)‧‧‧Part Three

338(1)'‧‧‧Dotted line shape

338(2)‧‧‧Part Five

338(2)'‧‧‧Dotted line shape

338(3)'‧‧‧Dotted line shape

338(4)'‧‧‧Dotted line shape

400A‧‧‧Cross Section

400B‧‧‧Cross Section

400C‧‧‧Cross Section

400D‧‧‧Cross Section

410(2)‧‧‧MD structure

410(3)‧‧‧MD structure

412(1)‧‧‧Gate structure

412(2)‧‧‧Gate structure

416(2)‧‧‧VGD structure

416(3)‧‧‧VGD structure

418(2)‧‧‧Conductive M0 section

418(4)‧‧‧Conductive M0 section

418(5)‧‧‧VGD structure

420(1)‧‧‧VIA0 pattern

420(1)'‧‧‧Dotted line shape

420(2)‧‧‧VIA0 structure

422(1)‧‧‧Conductive M1 section

422(1)'‧‧‧Dotted line shape

422(2)‧‧‧M1 section

422(2)'‧‧‧Dotted line shape

422(3)‧‧‧M1 section

450‧‧‧ILD

452‧‧‧Transistor layer

454‧‧‧M0 floor

456‧‧‧V0 floor

458‧‧‧M1 floor

460‧‧‧Interlayer Dielectric Layer (ILD)

462‧‧‧ILD

464‧‧‧ILD

466‧‧‧ILD

468‧‧‧ILD

500‧‧‧Method

502‧‧‧Block

504‧‧‧Block

602‧‧‧Block

604‧‧‧Block

606‧‧‧Block

610‧‧‧Cube

612‧‧‧Block

620‧‧‧Cube

622‧‧‧Cube

630‧‧‧Block

632‧‧‧Block

640‧‧‧Block

642‧‧‧Block

650‧‧‧Block

652‧‧‧Block

660‧‧‧Block

662‧‧‧Cube

670‧‧‧Block

672‧‧‧Block

674‧‧‧Block

676‧‧‧Block

678‧‧‧Cube

680‧‧‧Block

682‧‧‧Cube

700‧‧‧Electronic Design Automation (EDA) System

702‧‧‧hardware processor

704‧‧‧Non-temporary computer-readable storage media

706‧‧‧computer code

707‧‧‧Library

708‧‧‧Bus

710‧‧‧I/O interface

712‧‧‧Network Interface

714‧‧‧Internet

742‧‧‧User Interface (UI)

800‧‧‧Integrated Circuit (IC) Manufacturing System

820‧‧‧Design Room

822‧‧‧IC design layout

830‧‧‧Masked Room

832‧‧‧Data preparation

844‧‧‧Mask manufacturing

845‧‧‧Mask

850‧‧‧IC manufacturer/manufacturer ("Fab")

852‧‧‧Wafer Manufacturing

853‧‧‧Semiconductor Wafer

860‧‧‧IC components

When read in conjunction with the accompanying drawings, the aspect of the embodiments of the present disclosure can be best understood from the following detailed description. It should be noted that according to industry standards Quasi-practical, various features are not drawn to scale. In fact, for clarity of discussion, the size of various features can be increased or decreased arbitrarily.

Figure 1 is a block diagram according to some embodiments.

2A to 2F are corresponding layout diagrams 200A to 200F according to some embodiments.

3A to 3H are corresponding layout diagrams 300A to 300H according to some embodiments.

4A to 4D are corresponding cross-sectional views 400A to 400D according to some embodiments.

Figure 5 is a flowchart of a method according to some embodiments.

6A to 6E are corresponding flowcharts of corresponding methods according to some embodiments.

Figure 7 is a block diagram of an electronic design automation (EDA) system according to some embodiments.

FIG. 8 is a block diagram of an integrated circuit (IC) manufacturing system and its associated IC manufacturing process according to some embodiments.

The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components, values, operations, materials, arrangements, or the like are described below to simplify the embodiments of the present disclosure. Of course, these are only examples and are not intended to be limiting. Other components, values, operations, materials, arrangements, or the like are expected. For example, the first feature is formed on or on the second feature in the following description It may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not directly contact Examples. In addition, the embodiments of the present disclosure may repeat element symbols and/or letters in various examples. This repetition is for the purpose of simplification and clarity, and by itself does not represent the relationship between the various embodiments and/or configurations discussed.

In addition, for the sake of simplicity of description, spatially relative terms such as "below", "below", "lower", "above", "upper" and similar terms can be used in this article. To describe the relationship between one element or feature and another (other) element or feature as illustrated in the figures. In addition to the orientations depicted in the figures, these spatially relative terms are intended to cover different orientations of elements in use or operation. The device can be oriented in other ways (rotated by 90 degrees or in other orientations), and the spatial relative descriptors used in this text can also be interpreted accordingly.

For some embodiments, generating the layout plan includes: selecting candidate patterns in the layout plan, for example, M1 pattern or M0 pattern; determining whether the candidate pattern meets one or more criteria; and changing the size of the candidate pattern to thereby revise the layout Figure, thereby improving the M0 wiring resources. In some embodiments, the context for generating the layout diagram is the first design rule (design rule 1), design rule 2, design rule 3, or design rule 4. In some embodiments where the context is design rule 3, the size of the candidate pattern is changed by reducing the size of the candidate pattern. In some embodiments where the context is design rule 1 or design rule 2, the size of the candidate pattern is changed by removing the candidate pattern from the layout small. In some embodiments where the context is design rule 4, the size of the candidate pattern is changed by increasing the size of the candidate pattern.

FIG. 1 is a block diagram of a semiconductor device 100 according to some embodiments.

In FIG. 1, the semiconductor device 100 includes (among other things) a circuit macro (hereinafter referred to as a macro) 101. In some embodiments, the macro 101 is a logical macro. In some embodiments, the macro 101 is an SRAM macro. In some embodiments, the macro 101 is a macro other than a logic macro or an SRAM macro. The macro 101 includes (among other things) one or more unit regions 104 arranged in a row 102. In some embodiments, each cell area 104 is implemented based on a layout generated by one or more of the design rules disclosed herein, and thus each cell area 104 has improved M0 wiring resources.

2A to 2B are corresponding layout diagrams 200A to 200B according to some embodiments.

The layout diagram 200A represents an initial layout diagram, and the layout diagram 200B represents a corresponding layout diagram generated by one or more methods of the embodiments disclosed herein according to some embodiments.

Figures 2A to 2B assume an orthogonal XYZ coordinate system, where the X axis, Y axis, and Z axis represent the corresponding first, second, and third directions. In some embodiments, the first, second, and third directions correspond to an orthogonal coordinate system different from the XYZ coordinate system.

In Figure 2A, floor plan 200A includes cell 204(1)(A). Unit 204(1)(A) represents the semi-conductor based on layout drawing 200A The cell area in the body component. The cells 204(1)(A) are arranged in a row 202 which extends substantially in the first direction (extends horizontally). Although not shown for simplicity of description, in some embodiments, column 202 includes additional instances of cells, for example, cell 204(1)(A) and/or other cells. Column 202 includes sub-columns 203N and 203P.

The layout 200A further includes: active area patterns 208P and 208N; MD patterns 210(1), 210(2), 210(3), 210(4), 210(5), 210(6), 210(7), 210(8), 210(9), 210(10) and 210(11); gate patterns 212(1), 212(2), 212(3), 212(4), 212(5), 214( 1), 214(2), 214(3) and 214(4); VGD patterns 216(1), 216(2), 216(3), 216(4), 216(5), 216(6), 216(7), 216(8), 216(9), 216(10), 216(11) and 216(12); M0 pattern 218(1), 218(2), 218(3), 218(4 ), 218(5), 218(6), 218(7), 218(8) and 218(9); VIA0 patterns 220(1), 220(2), 220(3), 220(4) and 220 (5); and M1 patterns 222(1), 222(2), 222(3) and 222(4). In some embodiments, the unit 204(1)(A) includes: active area patterns 208P and 208N; MD patterns 210(1) to 210(11); gate patterns 212(1) to 214(4); VGD patterns 216(1) to 216(12); M0 patterns 218(2) to 218(8); parts of M0 pattern 218(1) and 218(9); VIA0 patterns 220(1) to 220(5); and M1 Patterns 222(1) to 222(4).

In the example of Figure 2A, it is assumed that: M0 patterns 218(1) and 218(9) are power grid (PG) patterns, and these power grid (PG) patterns represent the power grids of semiconductor devices manufactured based on the layout plan 200A Corresponding guide And M0 patterns 218(2) to 218(8) are wiring patterns, and these wiring patterns represent non-PG conductors of semiconductor elements manufactured based on the layout plan 200A. In some embodiments, the PG pattern 218(1) is designated to provide the first system reference voltage, and the PG pattern 218(9) is designated to provide the second system reference voltage. In Figure 2A, the PG pattern 218(1) is designated to provide VDD, and the PG pattern 218(9) is designated to provide VSS. In some embodiments, PG pattern 218(1) is designated to provide VSS, and PG pattern 218(9) is designated to provide VDD. In some embodiments, the PG patterns 218(1) and 218(9) are designated to provide corresponding voltages other than VDD and VSS, or VSS and VDD.

Active area patterns 208P and 208N, MD patterns 210(1) to 210(11), gate patterns 212(1) to 212(5) and 214(1) to 214(4), and VGD patterns 216(1) to 216 (2) Included in the transistor level of the layout plan 200A, which corresponds to the transistor layer of the semiconductor device based on the layout plan 200A. The M0 patterns 218(1) to 218(9) are included in the metallization level M0 in the layout diagram 200A, and this metalization level M0 corresponds to the metalization layer M0 of the semiconductor device based on the layout diagram 200A. The VIA0 patterns 220(1) to 210(5) are included in the interconnection level V0 in the layout 200A, and this interconnection level V0 corresponds to the interconnection layer V0 of the semiconductor element based on the layout 200A. The M1 patterns 222(1) to 222(4) are included in the M1 metallization level, which corresponds to the metallization layer M1 of the semiconductor device based on the layout diagram 200A.

MD patterns 210(1) to 210(11) and gate patterns 212(1) to 212(5) and 214(1) to 214(4) are located in the active area pattern Above the corresponding parts of 208P and 208N. In some embodiments, the active area patterns 208P and 208N are located on the substrate pattern (not shown). The VGD patterns 216(1) to 216(12) are located on the corresponding portions of the MD patterns 210(1) to 210(7) and 210(11) and the gate patterns 212(1) to 212(5). The M0 patterns 218(1) to 218(9) are located on the corresponding VGD patterns 216(1) to 216(12). The VIA0 patterns 220(1) to 220(5) are located on the corresponding M0 patterns 218(2) to 218(5) and 218(7). The M1 patterns 222(1) to 222(4) are located on the corresponding VIA0 patterns 220(1) to 220(5).

The layout diagram 200A assumes a corresponding semiconductor technology process generation (process technology node), and the semiconductor technology process generation includes various design rules for generating the layout diagram. The layout drawing 200A further assumes that the design rules follow a numbering convention, in which the first level of metallization (M_1st) and the corresponding first level (V_1st) of the interconnect structure are referred to as M0 and V0, respectively. The levels M0 and V0 of the layout drawing 200A correspond to the metallization layer M0 and the interconnection structure layer V0 in the semiconductor device based on the layout drawing 200A. In some embodiments, the numbering convention assumes that the M_1st level and the V_1st level are called M1 and V1, respectively.

The active area patterns 208P and 208N and the M0 patterns 218(1) to 218(9) have corresponding long axes that extend substantially along the X axis (extend horizontally). MD patterns 210(1) to 210(11), gate patterns 212(1) to 212(5) and 214(1) to 214(4), and M1 patterns 222(1) to 222(4) have substantially upper edges The corresponding long axis of the Y-axis extension (extending vertically).

In Figure 2A, the active area patterns 208P and 208N represent corresponding PMOS and NMOS fins in the semiconductor device based on the layout diagram 200A sheet. Therefore, the active area patterns 208P and 208N are designated for the corresponding PMOS finFET and NMOS finFET configurations, and are referred to as the corresponding fin patterns 208P and 208N. In some embodiments, the fin patterns 208P and 208N are designated for PMOS and NMOS configurations, respectively. Although not shown for simplicity of description, in some embodiments, each of the sub-rows 203N and 203P includes two or more fin patterns correspondingly designated for PMOS finFET and NMOS finFET configurations . In some embodiments, active area patterns 208P and 208N are designated for planar transistor configurations, and thus represent corresponding active areas in the cell area based on cell 204(1)(A). In some embodiments, active area patterns 208P and 208N are designated for nanowire configurations. In some embodiments, active area patterns 208P and 208N are designated for nanosheet configurations. In some embodiments, the active area patterns 208P and 208N are designated for a Gate-All-Around (GAA) configuration. In some embodiments in which the active area is referred to as oxide-dimensioned (OD) area, the active area patterns 208P and 208N are referred to as corresponding OD patterns 208P and 208N.

In the layout plan 200A, the MD patterns 210(1) to 210(11) represent corresponding MD conductive structures in the transistor layer of the semiconductor device based on the layout plan 200A. The gate patterns 212(1) to 212(5) and 214(1) to 214(4) represent corresponding gate structures in the transistor layer of the semiconductor device based on the layout diagram 200A. The VGD patterns 216(1) to 216(12) represent corresponding VG or VD structures in the transistor layer of the semiconductor device based on the layout diagram 200A. The VG structure (see Figure 4B) electrically couples the gate structure to the corresponding M0 Conductive section. The VD structure (see FIG. 4A) electrically couples the drain/source structure to the corresponding M0 conductive section. The M0 patterns 218(1) to 218(9) represent corresponding conductive sections in the metallization layer M0 of the semiconductor device based on the layout diagram 200A. The VIA0 patterns 220(1) to 220(5) represent corresponding interconnection structures (for example, vias) in the interconnection layer V0 of the semiconductor device based on the layout diagram 200A. M1 patterns 222(1) to 222(4) represent corresponding conductive sections in the metallization layer M1 of the semiconductor device based on the layout diagram 200A.

In Figure 2A, the gate patterns 212(1) to 212(5) are included in the cell 204(1)(A). With respect to the X axis, the gate patterns 214(1) to 212(4) are included in the cell 204(1)(A). With respect to the Y axis, the gate patterns 214(1) and 214(3) are substantially collinear, and the gate patterns 214(2) and 214(4) are substantially collinear. In some embodiments (not shown in the figure), the gate patterns 214(1) and 214(3) are merged and covered by a cut pattern, which (in fact) results in corresponding to the gate patterns 214(1) and 214 (3) Two discrete gate patterns. In some embodiments (not shown in the figure), the gate patterns 214(2) and 214(4) are merged and covered by a cut pattern, which (in fact) results in corresponding to the gate patterns 214(2) and 214 (4) Two discrete gate patterns.

Regarding the layout 200A, in some embodiments, the gate patterns 212(1) to 212(5) are active gate patterns. In some embodiments, the gate patterns 214(1) to 214(4) are correspondingly designated as active or dummy gate patterns. In some embodiments, depending on whether the corresponding active area patterns 208P and 208N are substantially continuous or substantially discontinuous at the side boundary of the cell 204(1)(A) relative to the X axis, the gate pattern 212(1) To 212(5) and 214(1) To 214(4) are correspondingly designated as active or dummy gate patterns. In some embodiments, where the active area pattern is substantially continuous at the side boundary of the cell 204(1)(A), this configuration is referred to as a continuous oxide diffusion (CNOD) configuration. In some embodiments where there is a CND configuration, the area of the active area pattern covering the side boundary of the cell is designated for doping, which results in a corresponding filled area in the semiconductor device. In some embodiments, when the active area pattern is substantially discontinuous at the side boundary of the cell 204(1)(A), this configuration is referred to as continuous poly over diffusion edge (CPODE). ) Configuration. In some embodiments where there is a CPODE configuration, an insulator pattern (not shown in the figure) is placed on an area indicating that the active area pattern is disconnected at the side boundary of the cell. In some embodiments, the active gate pattern is designated to receive signals regarding the function of the circuit represented by cell 204(1)(A). In some embodiments, with respect to the X axis, the dummy gate pattern represents a dummy gate structure, and this dummy gate structure helps provide a cell region corresponding to cell 204(1)(A) and adjacent (eg, adjacent) cells Isolation between regions (not shown in the figure). In some embodiments, the dummy gate structure is used for floating, so the dummy gate pattern is designated as floating accordingly, for example, in the case of a CPODE configuration. In some embodiments, with respect to the X axis, the dummy gate structure is used to receive a voltage that inhibits conduction in the underside of the corresponding fin, for example, inhibits the inversion layer in the underside of the corresponding fin, so the dummy The gate pattern is correspondingly designated to receive the conduction suppression voltage.

With respect to the X axis, the gate patterns 212(1) to 212(5) and 214(1) to 214(4) are separated by a certain distance (uniform distance). In some In the embodiment, the uniform distance represents a contacted poly pitch (CPP) corresponding to the generation of the semiconductor technology process. For example, the gate patterns 214(1) and 212(1) are separated by a CPP. Therefore, with respect to the X axis, the unit 204(1) has a width of 6 CPP.

Element 204(1)(A) represents a circuit. In some embodiments, unit 204(1)(A) represents a circuit that provides a function. In some embodiments, the unit 204(1)(A) represents a circuit that provides a logic function, and is therefore referred to as a logic unit. In some embodiments, unit 204(1)(A) represents a logical function AND, for example, a four-input AND (AND4). In some embodiments, at least one of the units 204(1) to 204(2) represents a circuit that provides functions other than logic functions.

In the example of Figure 2A, the cell 204(1)(A) has input marks A1, A2, A3, and A4, and an output mark Z. These marks indicate that the semiconductor device corresponding to the cell 204(1)(A) The corresponding input signals A1, A2, A3 and A4 and output signal Z of the unit area. The input mark A1 is graphically coupled to the gate via a diagrammatic path including gate pattern 212(1), VGD pattern 216(2), M0 pattern 218(4), VIA0 pattern 220(1), and M1 pattern 222(1) Pole pattern 212(1). The input mark A2 is graphically coupled to the gate via a diagrammatic path including gate pattern 212(2), VGD pattern 216(9), M0 pattern 218(6), VIA0 pattern 220(4), and M1 pattern 222(2) Pole pattern 212(2). The input mark A3 is graphically coupled to the gate pattern 212(3) via a diagrammatic path including the gate pattern 212(3), the VGD pattern 216(4), and the M0 pattern 218(5). The input mark A4 passes through the diagrammatic path including the gate pattern 212(4), the VGD pattern 216(10) and the M0 pattern 218(7) to It is graphically coupled to the gate pattern 212(4). The output mark Z is graphically coupled to the MD pattern via a diagrammatic path including MD pattern 210(6), VGD pattern 216(7), M0 pattern 218(3), VIAO pattern 220(3), and M1 pattern 222(4) 210(6).

Recall that the layout diagram 200A represents an initial layout diagram, and also recall that the layout diagram 200B represents a corresponding layout diagram generated by one or more methods of the embodiments disclosed herein according to some embodiments. More specifically, the cell 204(1)(B) of the floor plan 200B indicates that the method including the first design rule (Design Rule 1) (discussed below) has been applied to the floor plan 200A according to some embodiments. An example of the cell area corresponding to the cell 204(1)(B) is the cell area 104 in Figure 1.

The floor plan 200B is similar to the floor plan 200A. Figure 2B follows a numbering convention similar to that of Figure 2A. For the sake of brevity, the discussion will focus more on the difference between Figure 2B and Figure 2A than on the similarities.

In Figure 2B, compared with Figure 2A, some patterns have been removed. Specifically, in Figure 2B, the VIA0 patterns 220(1), 220(4), and 220(3) of Figure 2A have been removed, as shown by the corresponding dashed shapes 220(1)', 220(4) 'And 220(3)'. In addition, in Figure 2B, the M1 patterns 222(1), 222(2), and 222(4) in Figure 2A have been removed, as shown by the corresponding dashed shapes 222(1)', 222(2)' and 222(4)' indicates.

In some embodiments, the design rule 1 is as follows: if the unique VIA0 pattern is covered by a given M1 pattern, then the given M1 pattern is removed. More specific and In other words, the given M1 pattern is a part of the graphical path, and this graphical path includes the given M1 pattern, the unique VIA0 pattern, and the corresponding underlying M0 pattern.

In some embodiments, design rule 1 is as follows: for the first M1 pattern designated as the pinhole pattern, if the first VIA0 pattern is the only VIA0 pattern covered by the first M1 pattern, remove the first M1 pattern And instead, the corresponding first M0 pattern is designated as the nail hole pattern.

In some embodiments, the designation as a pinhole pattern should be understood as follows: For the first conductive pattern in the first metallization level M_1st corresponding to the overlying first interconnection level V_1st, the first conductive pattern is designated as The pinhole pattern indicates that for the corresponding first via pattern in the level V_1st, there are at least first and second allowable overlying positions. At this first via pattern, the second metallization level At least the corresponding second and third conductive patterns may be positioned to cover the first via pattern. For example, for the first M0 pattern and the corresponding overlying first VIA0 pattern, if the first VIA0 pattern has multiple positions (at these positions, the corresponding M1 pattern can be positioned to cover the first VIA0 pattern) , The first M0 pattern is designated as the pinhole pattern. For example, for the first M1 pattern and the corresponding overlying first VIA1 pattern, if the first VIA1 pattern has multiple positions (at these positions, the corresponding M2 pattern can be positioned to cover the first VIA1 pattern) , The first M1 pattern is designated as the pinhole pattern. In some embodiments, the relationship of the given M0/M1 pattern with respect to the overlying pattern is analyzed to determine whether to assign the given M0/M1 as the pinhole pattern. In some embodiments, the state designated as a pinhole pattern is a property associated with a given M0/M1 pattern, so that checking the attributes of the given M1 pattern reveals whether the given M1 pattern is a pinhole pattern.

In FIG. 2A, M1 patterns 222(1), 222(2), and 222(4) and M0 patterns 218(5) and 218(7) are designated as pinhole patterns. Thus, regarding the M1 pattern 222(1), there are multiple allowable overlying positions corresponding to the via pattern VIA1(1) (not shown in the figure). At these positions, the corresponding M2 pattern (not shown in the figure) can be It is positioned to cover the via pattern VIA1(1). Regarding the M1 pattern 222(2), the corresponding via hole pattern VIA1(2) (not shown) has multiple allowable overlying positions. At these positions, the corresponding M2 pattern (not shown) can be positioned A pattern of covering vias VIA1(2) is formed. Regarding the M1 pattern 222(4), there are a plurality of allowable overlying positions corresponding to the via pattern VIA1(3) (not shown), and these positions can be positioned to cover the via pattern VIA1(3).

In the layout 200A, among the M1 patterns designated as pinhole patterns, each of the M1 patterns 222(1), 222(2), and 222(4) covers only one VIA0 pattern (that is, the corresponding VIA0 patterns 220(1), 220(4) and 220(3)). Therefore, design rule 1 is applied to each of the M1 patterns 222(1), 222(2), and 222(4).

Figure 2B shows the result of applying Design Rule 1 to Figure 2A. The unit 204(1)(B) of the layout 200B is the result of applying the method including the design rule 1 to the layout 200A, and more specifically, it is applied to the M1 patterns 222(1), 222(2) and 222( 4). The results of applying Design Rule 1 to Figure 2A include: VIA0 patterns 220(1), 220(4) and 220(3) and M1 patterns 222(1), 222(2) and 222 have been removed from Figure 2B (4), such as the corresponding dashed shapes 220(1)', 220(4)', 220(3)', 222(1)', 222(2)' and 222(4)'; and M0 patterns 218(4), 218(6), 218(5), 218(7) and 218(3) have been designated as nail hole patterns.

In Figure 2B, the designation of the M0 pattern 218(4) as the pinhole pattern indicates that there are multiple allowable overlying positions corresponding to the via pattern 220(1)" (not shown in the figure). At these positions, The corresponding M1 pattern (for example, 220(1)") (not shown) can be positioned to cover the via pattern 220(1)". In Figure 2B, the M0 pattern 218(6) is designated as the nail hole pattern It indicates that the corresponding via pattern 220(4)" (not shown in the figure) has multiple allowable overlying positions. At these positions, the corresponding M1 pattern (for example, 222(2)") (not shown in the figure) ) Can be positioned to cover the via pattern 220(4)". In Figure 2B, the designation of M0 pattern 218(5) as the pinhole pattern indicates that the corresponding via pattern VIA(4) (not shown) has multiple allowable overlying positions. At these positions, corresponding The M1 pattern (not shown) can be positioned to cover the via pattern VIA(4). In Figure 2B, the designation of M0 pattern 218(7) as the pinhole pattern indicates that the corresponding via pattern VIA(5) (not shown) has multiple allowable overlying positions. In these positions, corresponding The M1 pattern (not shown) can be positioned to cover the via pattern VIA(5). In Figure 2B, the designation of the M0 pattern 218(3) as the pinhole pattern indicates that there are multiple allowable overlying positions corresponding to the via pattern 220(3)" (not shown in the figure). At these positions, The corresponding M1 pattern (for example, 222(4)") (not shown) can be positioned to cover the via pattern 220(4)".

3%)至(

4%)。 By removing M1 patterns 222(1), 222(2), and 222(4) and VIA0 patterns 220(1), 220(4), and 220(3), compared with the layout diagram 200A, the layout diagram 200B is Not congested. By removing the M1 patterns 222(1), 222(2), and 222(4) and VIA0 patterns 220(1), 220(4), and 220(3), compared with the layout diagram 200A, the layout diagram 200B has Improved M1 wiring resources. In some embodiments, because the floor plan 200B has fewer M1 patterns than the floor plan 200A, the floor plan 200B is regarded as having improved wiring resources relative to the floor plan 200A. In some embodiments, reduced congestion in level M1 results in reduced congestion in level M2. In some embodiments, congestion is reduced in level M2 (

3%) to (

4%).

2C to 2D are corresponding layout diagrams 200C to 200D according to some embodiments.

The layout diagram 200C represents an initial layout diagram, and the layout diagram 200D represents a corresponding layout diagram generated by one or more methods of the embodiments disclosed herein according to some embodiments. More specifically, the cell 204(2)(D) of the floor plan 200D indicates that the method including the second design rule (Design Rule 2) (discussed below) has been applied to the floor plan 200C according to some embodiments. An example of the cell area corresponding to the cell 204(2)(D) is the cell area 104 in Figure 1.

The layout drawings 200C to 200D are similar to the corresponding layout drawings 200A to 200B of FIG. 2A to FIG. 2B. Figures 2C to 2D follow a numbering convention similar to that of Figures 2A to 2B. Although corresponding, some parts are still different. To help identify corresponding parts that still have differences, the numbering convention uses parentheses. For example, the pattern 218(10) in Figure 2C and the pattern 218(1) in Figure 2B are both M0 patterns, where the similarities are reflected in the common root 218(_), and the differences are reflected in parentheses _(10) And _(1). For the sake of brevity, the discussion will focus more on the differences between FIGS. 2C to 2D and FIGS. 2A to 2B than the similarities.

In Figure 2C, the floor plan 200C includes the cell 204(2)(C). The layout diagram 200C further includes: MD patterns 210(10), 210(11), 210(12), 210(13), 210(14) and 210(15); gate patterns 212(6), 214(5) , 214(6), 214(7) and 214(8); VGD patterns 216(3), 216(14), 216(15) and 216(16); and M0 patterns 218(10), 218(11) , 218(12), 218(13), 218(14) and 218(15). For simplicity of description, (except for other patterns), the fin pattern and the M1 pattern are omitted from FIGS. 2C to 2D. In some embodiments, the cell 204(2)(C) includes: MD patterns 210(10) to 210(15); gate patterns 212(6) and 214(5) to 214(8); VGD pattern 216( 13) to 216(16); M0 patterns 218(11) to 218(14); and parts 218(10) and 218(15) of M0 patterns.

In some embodiments, the units 204(2)(C) and 204(2)(D) corresponding to the 2C and 2D images are inverting units representing corresponding inverting circuits.

In Figure 2D, compared with Figure 2C, some patterns have been removed. Specifically, the M0 patterns 218(12) and 218(14) in the 2C image have been removed in the 2D image, as shown in the corresponding dotted line shapes 218(12)' and 218(14)' in the 2D image Indicated.

In some embodiments, design rule 2 is as follows: if a given M0 pattern does not cover one or more VGD contact patterns and if a given M0 pattern is not covered by one or more V0 contact patterns, remove the given M0 pattern. More specifically In other words, a given M0 pattern is not a part of a graphical path including a given M0 pattern and one or more VGD patterns, and a given M0 pattern is not a part of a graphical path including a given M0 pattern and one or more VIA0 patterns.

In Figure 2C, the M0 pattern 218(12) does not cover one or more VGD contact patterns, and the M0 pattern 218(12) is not covered by one or more V0 contact patterns. Therefore, Design Rule 2 applies to the M0 pattern 218(12). Similarly, in Figure 2C, the M0 pattern 218 (14) does not cover one or more VGD contact patterns, and the M0 pattern 218 (14) is also not covered by one or more V0 contact patterns. Therefore, Design Rule 2 applies to the M0 pattern 218 (14).

Figure 2D shows the result of applying Design Rule 2 to Figure 2C. The unit 204(2)(D) of the layout 200D is the result of applying the method including the design rule 2 to the layout 200C, and more specifically, it is applied to the M0 patterns 218(12) and 218(14). The results of applying Design Rule 2 to Figure 2C include: M0 pattern 218(12) has been removed from Figure 2D, as indicated by the corresponding dashed shape 218(12)' in Figure 2D; and Figure 2D has been removed from Figure 2D. The figure removes the M0 pattern 218(14), as indicated by the corresponding dashed shape 218(14)' in the 2D figure.

With the M0 patterns 218(12) and 218(4) removed, the layout 200D is less congested compared to the layout 200C. By removing the M0 patterns 218(12) and 218(4), compared with the floor plan 200C, the floor plan 200D has improved M0 wiring resources. In some embodiments, because the floor plan 200D has fewer M0 patterns than the floor plan 200C, the floor plan 200D is regarded as having improved M0 wiring resources relative to the floor plan 200C.

2E to 2F are corresponding layout diagrams 200E to 200F according to some embodiments.

The layout diagram 200E represents an initial layout diagram, and the layout diagram 200F represents a corresponding layout diagram generated by one or more methods disclosed herein according to some embodiments. More specifically, the unit 204(3)(F) of the floor plan 200F indicates that the method including the third design rule (design rule 3) (discussed below) has been applied to the floor plan 200E according to some embodiments. An example of the cell area corresponding to the cell 204(3)(F) is the cell area 104 in Figure 1.

The layout drawings 200E to 200F are similar to the corresponding layout drawings 200A to 200D of FIG. 2A to FIG. 2D. Figures 2E to 2F follow a numbering convention similar to that of Figures 2A to 2D. Although corresponding, some parts are still different. To help identify corresponding parts that still have differences, the numbering convention uses parentheses. For example, the pattern 218(16) in Figure 2E and the pattern 218(10) in Figure 2D are both M0 patterns, where the similarities are reflected in the common root 218(_), and the differences are reflected in parentheses _(16) and _(10). For the sake of brevity, the discussion will focus more on the differences between Figures 2E to 2F and Figures 2A to 2D than the similarities.

In Figure 2E, the floor plan 200E includes the unit 204(3)(E). The layout diagram 200E further includes: MD patterns 210(17), 210(18), 210(19), 210(20) and 210(21); gate patterns 212(7), 212(8), 214(9) , 214(10), 214(11) and 214(12); VGD patterns 216(17), 216(18), 216(19), 216(20), 216(21), 216(22) and 216( 23); and M0 pattern 218(16), 218(17), 218(18), 218(19), 218(20) and 218(21). For simplicity of description, (except for other patterns), the fin pattern, VIA0 pattern, and M1 pattern are omitted from FIGS. 2C to 2D. In some embodiments, the unit 204(3)(E) includes: MD patterns 210(17) to 210(21); gate patterns 212(7) to 212(8) and 214(9) to 214(12) ; VGD patterns 216(17) to 216(23); M0 patterns 218(17) to 218(20); and parts 218(16) and 218(21) of M0 patterns.

Element 204(3)(E) represents a circuit. In some embodiments, element 204(3)(E) represents a circuit that provides a function. In some embodiments, unit 204(3)(E) represents a circuit that provides a logic function, and is therefore referred to as a logic unit. In some embodiments, cell 204(3)(E) represents a logical function NAND, for example, two-input NAND (NAND2).

CPP，且因此緊鄰之MD圖案彼此相距一個軌道。在一些實施例中，軌道間距(PT)為PT

½CPP，且因此緊鄰之MD圖案彼此相距兩個軌道。在一些實施例中，相對於X軸，每一MD圖案(例如，MD圖案210(1))之寬度為WMD

CPP。 In the layout diagram 200E, with respect to the X axis, MD patterns 210(17) to 210(21) are arranged according to a grid of virtual tracks substantially parallel to the Y axis. In some embodiments, with respect to the X axis, the pitch of tracks (PT) is PT

CPP, and therefore the adjacent MD patterns are one track away from each other. In some embodiments, the track pitch (PT) is PT

½ CPP, and therefore the adjacent MD patterns are two tracks away from each other. In some embodiments, with respect to the X axis, the width of each MD pattern (eg, MD pattern 210(1)) is WMD

CPP.

CPP之一些實施例中，對應MD圖案210(15)及210(18)之長軸大體上與第一軌道共線，MD圖案210(16)及210(19)之長 軸大體上與第二軌道共線，且對應MD圖案210(17)及210(19)之長軸大體上與第三(且最後)軌道共線。 Relative to the X axis, where the track pitch (PT) is PT

In some embodiments of CPP, the long axes of corresponding MD patterns 210(15) and 210(18) are substantially collinear with the first track, and the long axes of MD patterns 210(16) and 210(19) are substantially aligned with the second track. The tracks are collinear, and the long axes of the corresponding MD patterns 210(17) and 210(19) are substantially collinear with the third (and last) track.

CPP之一些實施例中，軌道界定MD行(MD-column)。如此，MD圖案210(15)及210(18)位於第一MD行中，MD圖案210(16)及210(19)位於第二MD行中，且MD圖案210(17)及210(19)位於第三(且最後)MD行中。 Relative to the X axis, where the track pitch (PT) is PT

In some embodiments of CPP, the track defines MD-column. Thus, MD patterns 210(15) and 210(18) are located in the first MD row, MD patterns 210(16) and 210(19) are located in the second MD row, and MD patterns 210(17) and 210(19) Located in the third (and last) MD row.

In Figure 2E, M0 patterns 218(17) to 218(20) are in cell 204(3)(E). With respect to the X axis, one end of each of the M0 patterns 218(17) and 218(20) is positioned close to the side boundary 230 of the cell 204(3)(E).

(1/6)CPP。 In some embodiments, with respect to the X axis, in order to help provide that the first unit area corresponding to the unit 204(3)(E) is adjacent (for example, adjacent to) the first unit area located on the right side of the side boundary 230 of the first unit area The isolation between the two cell regions (not shown) provides a gap 232 between the right end of each of the M0 patterns 218(17) and 218(20) and the side boundary 230 of the cell 204(3)(E). In some embodiments, the length of the gap 232 is L232, where L232

(1/6) CPP.

CPP。 In the layout diagram 200E, with respect to the X-axis, the M0 patterns 218(18), 218(19), and 218(20) each have a width substantially equal to the minimum width Lmin of the level M0. With respect to the typical manufacturing tolerance of the generation of semiconductor technology processes that produce semiconductor devices, the minimum width Lmin represents the minimum length of the conductive section in the layer M0 in the semiconductor device. The minimum width Lmin is less than CPP, and Lmin<CPP. In some embodiments, Lmin is based on the distance between cut M0 (CM0) patterns (not shown). In some embodiments, Lmin

CPP.

1.5CPP。 In some embodiments, design rule 3 is as follows: if the given MD pattern is located in the first MD row or the last MD row of the unit, and if the given MD pattern is covered by the corresponding VGD pattern, and if the corresponding M0 of the corresponding VGD pattern is covered If the pattern is not a PG pattern, the width of the corresponding M0 pattern (relative to the X axis) is set to be at least L2, where CPP<L2. In some embodiments, L2

1.5CPP.

In Figure 2E, MD patterns 210(15) and 210(18) are located in the first MD row, and MD patterns 210(17) and 210(20) are located in the last MD row. Each of the MD patterns 210(15), 210(17), 210(18), and 210(20) is VD patterned (that is, corresponding to VD patterns 216(17), 216(18), 216(23) ) And 216(22)) coverage.

In the layout 200E, the MD pattern 210 (20) is covered by the M0 pattern 218 (20), which is not a PG pattern. Therefore, design rule 3 is applied to the MD pattern 210 (20).

Figure 2F shows the result of applying Design Rule 3 to Figure 2E. The cell 204(3)(F) of the floor plan 200F is the result of applying the method including the design rule 3 to the floor plan 200E, and more specifically, to the M0 pattern 218(20). The result of applying design rule 3 to Figure 2E includes changing the M0 pattern 218(20) in Figure 2E to the M0 pattern 218(20)' in Figure 2F. In Figure 2F, the increase in the width of the M0 pattern 218(20)' by ΔW, ΔW is shown as the symbol 234. In some embodiments, with respect to the X-axis, L2 represents the CM0 pattern corresponding to the generation of the semiconductor technology process (not shown in the figure) The minimum separation distance between. By increasing the width of the M0 pattern 218(20)' enough to be designated as a pinhole pattern, compared with the layout plan 200E, the layout plan 200F has improved M0 wiring resources. In some embodiments, because the given M0 pattern is designated as the pinhole pattern, and because the layout plan 200F has an additional M0 pattern that can be designated as the pinhole pattern in comparison with the layout plan 200E, the layout plan 200F is regarded as Compared with the floor plan 200E, it has improved M0 wiring resources.

3A to 3H are corresponding layout diagrams 300A to 300H according to some embodiments.

Layout drawings 300A, 300C, 300E, and 300G represent initial layout drawings, and layout drawings 300B, 300D, 300F, and 300H represent corresponding layout drawings generated by one or more methods disclosed herein according to some embodiments (post method (post) -method) layout diagram). For example, the layout diagram 300A represents an initial layout diagram, and the layout diagram 300B represents a corresponding post-method layout diagram generated by one or more methods of the embodiments disclosed herein according to some embodiments. More specifically, the cell 304(1)(B) of the floor plan 300B indicates that the method including the fourth design rule (design rule 4) (discussed below) has been applied to the floor plan 300A of FIG. 3A according to some embodiments. An example of the cell area corresponding to the cells 304(1)(B), 304(2)(D), 304(3)(F), and 304(4)(H) is the cell area 104 in FIG. 1.

The layout drawings 300A to 300H are similar to the corresponding layout drawings 200A to 200F of FIG. 2A to FIG. 2F. Figures 3A to 3H follow a numbering convention similar to that of Figures 2A to 2F. Although corresponding, some parts are still different. Figures 2A to 2F use 2 serial numbers, and Figures 3A to 3H use 3 serial numbers. To help identify corresponding parts that still have differences, the numbering convention uses parentheses. For example, the pattern 318(1)(A) in Figure 3A and the pattern 218(11) in Figure 2C are both M0 patterns, and the similarities are reflected in the common root_18(_), and The difference is reflected in the serial numbers 3_(_)(_) and 2_(_) and brackets _(1)(_) and _(11). To help reflect the difference between the corresponding initial layout diagram and the post-method layout diagram, some components include a second bracket. For example, the pattern 318(1)(A) in Figure 3A and the pattern 318(1)(B) in Figure 3B are both M0 patterns, and the difference is reflected in the second bracket _(_)(A) And _(_)(B). For the sake of brevity, the discussion will focus more on the differences between FIGS. 3A to 3H and FIGS. 2A to 2F than the similarities.

In Figure 3A, the floor plan 300A includes part of cell 304(1)(A). The layout diagram 300A further includes: gate patterns 312(1), 312(2), 314(1) and 314(2); VGD pattern 316(1); M0 pattern 318(1)(A); and VIA0 pattern 320 (1). For simplicity of description, (except for other patterns), the fin pattern, MD pattern, and M1 pattern are omitted from Fig. 2C to Fig. 2D. In some embodiments, the cell 304(1)(A) includes: gate patterns 312(1) to 312(2) and 314(1) to 314(2); VGD pattern 316(1); and M0 pattern 318 (1)(A).

In the layout 300A, the VGD pattern 316(1) is covered by the M0 pattern 318(1)(A), and the M0 pattern 318(1)(A) is covered by the VIAO pattern 320(1). Relative to the horizontal direction, the first part of the M0 pattern 318(1)(A) extends to the right of the VIA0 pattern 320(1) by a width 336(2).

0.2CPP)

WOH

(

0.3CPP)。在一些實施例中，相對於產生半導體元件之半導體技術製程世代的典型製造容限，若半導體中之M0區段的最小高度Hmin(相對於Y軸)為(

20nm)<Hmin，則WOH

0.2CPP。在一些實施例中，若對應半導體技術製程世代之最小高度Hmin為(

9nm)

Hmin

(

20nm)，則WOH

0.3CPP。在一些實施例中，在M0圖案突出於對應VIA0圖案且M0圖案之突出部分的寬度為大致OH 336(_)的情況下，則將突出部分稱作短節部分。 The first part of the M0 pattern 318(1)(A) protrudes from the right side of the VIAO pattern 320(1) by a width 336(2), and therefore the width 336(2) is called an overhang (OH) 336(2). In some embodiments, OH 336(_) (for example, OH 336(1), OH 336(2), or the like) represents the smallest protrusion in a semiconductor device that can be generated within typical manufacturing tolerances of the corresponding semiconductor technology process generation. The width WHO (relative to the X axis), for example, the corresponding first conductive section in the layer M0 protrudes from the first VIA0 structure, where the first VIA0 structure is represented by the VIA0 pattern 320(1), and the first conductive section in the layer M0 The section is represented by the M0 pattern 318(1)(A). In some embodiments, (

0.2CPP)

WOH

(

0.3CPP). In some embodiments, relative to the typical manufacturing tolerance of the generation of semiconductor technology processes that produce semiconductor devices, if the minimum height Hmin (relative to the Y axis) of the M0 section in the semiconductor is (

20nm)<Hmin, then WOH

0.2CPP. In some embodiments, if the minimum height Hmin corresponding to the semiconductor technology process generation is (

9nm)

Hmin

(

20nm), then WOH

0.3CPP. In some embodiments, when the M0 pattern protrudes from the corresponding VIA0 pattern and the width of the protruding part of the M0 pattern is approximately OH 336 (_), the protruding part is referred to as a short section.

Relative to the horizontal direction, the second part of the M0 pattern 318(1)(A) extends to the left of the VGD pattern 316(1) to a width 336(1), and the third part 338 of the M0 pattern 318(1)(A) (1) Extend to the left of the second part of M0 pattern 318(1)(A).

In some embodiments, design rule 4 is as follows: with respect to the X axis, if a given M0 pattern covers a given VGD pattern or is given a VIA0 pattern Cover, the first and second wing parts (within the current range) of a given M0 pattern are reduced to the corresponding first and second sub-section parts, where (A) the first wing part extends to the leftmost interposer The left side of the hole pattern (which is a VG pattern or VIA0 pattern) is greater than OH 336(_), and (B) the second wing portion extends to the right of the rightmost via pattern (which is a VG pattern or VIA0 pattern). Greater than the amount of OH 336(_), (C) the first short section extends to the left of the leftmost via pattern (which is a VG pattern or VIAO pattern) and has a width substantially equal to OH 336(_), and (D) The second short section extends to the right of the rightmost via pattern (which is a VG pattern or a VIAO pattern) and has a width substantially equal to OH 336(_). In some embodiments, reducing the wing portion of a given M0 pattern to a short section is called a trimming wing portion.

In Figure 3A, with respect to the protrusion of the M0 pattern 318(1)(A), the leftmost via pattern is the VGD pattern 316(1). The first wing part of the M0 pattern 318(1)(A) corresponds to the combination of the third part 338(1) of the M0 pattern 318(1)(A) and the second part of the M0 pattern 318(1)(A), This second part extends to the left of the VGD pattern 316(1) by a width 336(1).

The first wing portion extends to the left of the VGD pattern 316(1) by an amount greater than OH 336(2). Therefore, Design Rule 4 is applicable to the first wing portion of the M0 pattern 318(1)(A). Specifically, the amount of the first wing portion of the M0 pattern 318(1)(A) extending beyond the OH 336(2) is equal to the width of the third portion 338(1) of the M0 pattern 318(1)(A).

In the layout diagram 300A, with respect to the protrusion of the M0 pattern 318(1)(A), the rightmost via pattern is the VIA0 pattern 320(1). The second wing part of M0 pattern 318(1)(A) corresponds to the second wing part of M0 pattern 318(1)(A) section. The second wing portion of the M0 pattern 318(1)(A) extends to the right of the VIA0 pattern 320(1), but does not reach an amount greater than OH 336(2). Therefore, Design Rule 4 does not apply to the second wing portion of the M0 pattern 318(1)(A).

Figure 3B shows the result of applying design rule 4 to Figure 3A. Unit 304(1)(B) of layout 300B is the result of applying the method including design rule 4 to layout 300A, and more specifically, it is applied to the first wing portion of M0 pattern 318(1)(A) . The results of applying design rule 4 to Figure 3A include: the narrower (relative to the X axis) pattern 318(1)(B) of M0 has replaced the wider pattern 318(1)(A). M0 pattern 318(1)(B) is narrower than M0 pattern 318(1)(A) because the third part 338(1) of M0 pattern 318(1)(A) has been removed from Figure 3A, as shown by The corresponding dotted line shape 338(1)' in Figure 3B is indicated.

With the third part 338(1) of the M0 pattern 338(1)(A) removed, the layout 300B is less congested compared with the layout 300A. By removing the third part 338(1) of the M0 pattern 338(1)(A), the layout plan 300B has improved M0 wiring resources compared with the layout plan 300A. In some embodiments, because the M0 pattern 318(1)(B) of the layout plan 300B is narrower than the M0 pattern 318(1)(A) of the layout plan 300A, the layout plan 300B is regarded as relative to the layout plan 300A. With improved M0 wiring resources.

Regarding Figure 3C and Figure 3D, it should be remembered that cell 304(2)(D) of layout 300D indicates that the method including design rule 4 has been applied to layout 300C of Figure 3C according to some embodiments.

In the layout diagram 300C, with respect to the protrusion of the M0 pattern 318(2)(C), the leftmost via pattern is VIA0 pattern 316(1), making the M0 pattern The first wing part of case 318(2)(C) is the same as the first wing part of M0 pattern 318(1)(A). Therefore, Design Rule 4 is applicable to the first wing part of the M0 pattern 318(2)(C).

In the layout drawing 300C, with respect to the protrusion of the M0 pattern 318(2)(C), the rightmost via pattern is the VGD pattern 316(1). Regarding the M0 pattern 318(2)(C), the fourth part of the M0 pattern 318(2)(C) extends to the right of the VGD pattern 316(1) to the width 336(3), and the M0 pattern 318(2)(C) The fifth part 338(2) of) extends to the right of the fourth part of the M0 pattern 318(2)(C). The second wing portion of the M0 pattern 318(2)(C) corresponds to the combination of the fifth portion 338(2) of the M0 pattern 318(2)(C) and the fourth portion of the M0 pattern 318(2)(C). The second wing portion extends to the right of the VGD pattern 316(1) by an amount greater than OH 336(3). Therefore, design rule 4 is applicable to the second wing portion of the M0 pattern 318(2)(C). Specifically, the second wing portion of the M0 pattern 318(2)(C) extends beyond the OH 336(3) by an amount equal to the width of the fifth portion 338(2) of the M0 pattern 318(2)(C).

Figure 3D shows the result of applying design rule 4 to Figure 3C. The cell 304(2)(D) of the layout 300D is the result of applying the method including the design rule 4 to the layout 300C, and more specifically, it is applied to the first and the first and the first of the M0 pattern 318(2)(C) The second wing part. The results of applying Design Rule 4 to Figure 3C include: the narrower (relative to the X axis) M0 pattern 318(2)(D) has replaced the wider M0 pattern 318(2)(C). M0 pattern 318(2)(D) is narrower than M0 pattern 318(1)(C) because the third part 338(1) and fifth part of M0 pattern 318(2)(C) have been removed from Figure 3C Part 338(2), as shown in the corresponding dashed shapes 338(1)' and 338(2)' in the 3D figure Indicated. In some embodiments, because the M0 pattern 318(2)(D) of the layout plan 300D is narrower than the M0 pattern 318(2)(C) of the layout plan 300C, the layout plan 300D is regarded as relative to the layout plan 300C. With improved M0 wiring resources.

Figure 3F shows the result of applying design rule 4 to Figure 3E. The unit 304(3)(F) of the layout drawing 300F is the result of applying the method including the design rule 4 to the layout drawing 300E, and more specifically, the first wing part of the M0 pattern 318(3)(E) . The results of applying design rule 4 to Figure 3E include that the narrower (relative to the X axis) pattern 318(3)(F) of M0 has replaced the wider pattern 318(3)(E) of M0. The M0 pattern 318(3)(F) is narrower than the M0 pattern 318(3)(E) because the part 338(3) of the M0 pattern 318(3)(E) has been removed from the 3E figure, as shown in the 3F The corresponding dashed shape 338(3)' in the figure indicates. In some embodiments, because the M0 pattern 318(3)(F) of the layout plan 300F is narrower than the M0 pattern 318(3)(E) of the layout plan 300E, the layout plan 300F is regarded as relative to the layout plan 300E. With improved M0 wiring resources.

Figure 3H shows the result of applying Design Rule 4 to Figure 3G. The cell 304(4)(H) of the layout drawing 300H is the result of applying the method including the design rule 4 to the layout drawing 300G, and more specifically, it is applied to the first and the first and the first of the M0 pattern 318(4)(G) The second wing part. The result of applying design rule 4 to the 3G image includes that the narrower (relative to the X axis) M0 pattern 318(4)(H) has replaced the wider M0 pattern 318(4)(G). M0 pattern 318(4)(H) is narrower than M0 pattern 318(4)(G) because part 338(3) and part 338(4) of M0 pattern 318(4)(G) have been removed from the 3G image. ), as by The corresponding dashed shapes 338(3)' and 338(4)' in the 3H figure are indicated. In some embodiments, because the M0 pattern 318(4)(H) of the layout plan 300H is narrower than the M0 pattern 318(4)(G) of the layout plan 300G, the layout plan 300H is regarded as relative to the layout plan 300G With improved M0 wiring resources.

4A to 4C are corresponding cross-sectional views 400A to 400C of corresponding parts of corresponding semiconductor devices according to some embodiments.

More specifically, the cross-sectional views 400A to 400B show corresponding parts of the semiconductor device based on the layout plan 200A of FIG. 2A. The cross-sectional views 400C to 400D show corresponding portions of the semiconductor device based on the layout diagram 200 of FIG. 2B. The portions corresponding to the cross-sectional views 400C to 400D and the semiconductor device including these portions are corresponding examples of the cell region 104 and the semiconductor device 100 in FIG. 1.

Figures 4A to 4C assume an orthogonal XYZ coordinate system, where the X-axis, Y-axis, and Z-axis represent the corresponding first, second, and third directions. In some embodiments, the first, second, and third directions correspond to an orthogonal coordinate system different from the XYZ coordinate system.

The cross-sectional views 400A to 400D follow a numbering convention similar to that of FIGS. 2A to 2F. Figures 2A to 2F use 2 sequence numbering, and Figures 4A to 4D use 4 sequence numbering. For example, the fin 408P in Figure 4A corresponds to the fin pattern 208P in Figure 2A.

In Figure 4A, the portion corresponding to the cross-sectional view 400A includes the transistor layer 452; the M0 metallization layer on the transistor layer 452; the V0 layer 456 on the M0 layer 454; and the V0 layer 456 458 on the M1 floor.

Transistor layer 452 includes: fin 408P; interlayer dielectric (ILD) 460 in the sublayer corresponding to fin 408P; MD structure 410(2) on fin 408P; gate on fin 408P Structure 412(2); ILD 462 in the sublayer corresponding to MD structure 410(2) and gate structure 412(2); VGD structure 416(3) on MD structure 410(2); and ILD 464 in the sub-layer of VGD structure 416(3). The M0 layer 454 includes a conductive M0 section 418(2) (which covers the VGD structure 416(3)) and an ILD 466. The V0 layer 456 includes the VIAO structure 420(2) (which is on the M0 section 418(2)) and the ILD 468. The M1 layer 458 includes M1 sections 422(2) and 422(3) (the latter is overlaid on V0 420(2)) and an ILD 450.

The long axis of the fin 408P extends in a direction substantially parallel to the X axis. The long axes of the MD structure 410(2) and the gate structure 412(2) extend in the Y direction (not shown in FIG. 4A). With respect to the Z axis, the MD structure 410(2) and the gate structure 412(2) are arranged on the fin 408P.

The VGD structure (for example, VGD structure 416(3)) is a contact structure, which electrically couples the overlying conductive section (for example, M0 section 418(2)) in the layer M0 and the underlying MD structure (for example, MD structure) 410(2)) or underlying gate structure. In some embodiments, VGD is an abbreviation for the phrase via gate or via drain/source.

In FIG. 4B, regarding the portion corresponding to the cross-sectional view 400B, the transistor layer 452 includes: an interlayer dielectric layer (ILD) 460 in the sublayer corresponding to the fin 408P (not shown in FIG. 4B); and a gate Pole structures 412(1) and 412(2); ILD 462; VGD structure 416(3) on gate structure 412(1); and ILD 464. M0 layer 454 includes conductive M0 section 418(4) (It is overlaid on VGD structure 416(3)) and 418(5) and ILD 466. The V0 layer 456 includes the VIAO structure 420(1) (which is on the M0 section 418(4)) and the ILD 468. The M1 layer 458 includes conductive M1 sections 422(1) (which are on the VIAO structure 420(1)), 422(2) and 422(3), and ILD 450.

In Figure 4C, compared with Figure 4A, some structures have been removed. Specifically, in Figure 4C, the M1 pattern 422(2) of Figure 4A has been removed, as indicated by the corresponding dashed shape 422(2)'.

In Figure 4D, compared with Figure 4B, some structures have been removed. In particular, the VIAO pattern 420(1) of Figure 4B has been removed in Figure 4D, as indicated by the corresponding dashed shape 420(1)'. Furthermore, in Figure 4D, the M1 patterns 422(1) and 422(2) of Figure 4B have been removed, as indicated by the corresponding dashed shapes 422(1)' and 422(2)'.

FIG. 5 is a flowchart of a method 500 of manufacturing a semiconductor device according to some embodiments.

Examples of semiconductor devices that can be manufactured according to the method 500 include the semiconductor device 100 of FIG. 1.

In Figure 5, the method 500 includes blocks 502 to 504. At block 504, a layout diagram is generated that includes (among other things) improved placement of M0 wiring resources. Examples of semiconductor devices including cell regions with improved M0 wiring resources (which correspond to the layout generated by the method 500) include the semiconductor device 100 in FIG. Block 502 is discussed in more detail below with reference to FIG. 6A. From block 502, the flow proceeds to block 504.

At block 504, based on the layout, perform at least one of the following: (A) perform one or more photolithographic exposures; or (B) manufacture a Or multiple semiconductor masks; or (C) manufacturing one or more components in the layer of semiconductor components. See the description in Figure 8 below.

FIG. 6A is a flowchart of a method of generating a layout diagram according to some embodiments.

More specifically, according to one or more embodiments, the method of FIG. 6A shows block 502 of FIG. 5 in more detail.

Examples of layout diagrams that can be generated according to the method of FIG. 6A include layout diagrams of the embodiments disclosed herein, or the like. In some embodiments, the layout diagram and its corresponding version are stored on a non-transitory computer-readable medium, for example, stored as layout diagram(s) 708 in the computer-readable medium 704 in Figure 7 (discussed below). According to some embodiments, for example, an EDA system 700 (Figure 7, discussed below) may be used to implement the method of Figure 6A. Examples of semiconductor devices that can be manufactured based on the layout drawing generated according to the method of FIG. 6A include the semiconductor device 100 of FIG. 1, and semiconductors based on layout drawings 200B, 200D, 200F, 300B, 300D, 300F, 300G or the like element.

In FIG. 6A, block 502 includes blocks 602 to 606. At block 602, a candidate pattern is selected, and the candidate pattern is the first conductive pattern in the M_2nd level or the M_1st level of the layout. In some embodiments, the M_2nd level is the M1 level, and the M_1st level is the M0 level. Examples of patterns in the M_2nd level include the M1 patterns 222(1), 222(2), and 222(4) in the M1 level of FIG. 2A, or the like. Examples of patterns in the M_1st level include M0 patterns 218(12) and 218(14) in the M0 level of Figure 2C, M0 patterns 218(20) and 3A in the M0 level of Figure 2F. The M0 pattern 318(1)(A) in the M0 level of the figure, the M0 pattern 318(2)(C) in the M0 level of the 3C figure, the M0 pattern 318(3)(E) in the M0 level of the 3E figure ), the M0 pattern 318(4)(G) in the M0 level of the 3G picture, or the like. From block 602, the flow proceeds to block 604.

At block 604, it is determined that the candidate pattern satisfies one or more criteria. Examples of criteria are criteria corresponding to design rules 1, 2, 3, or 4, or the like. From block 604, the flow proceeds to block 606.

At block 606, the size of the candidate pattern is changed. In some embodiments, the size of the candidate pattern is changed by decreasing, for example, as shown in 3B, 3D, 3F, 3H, or the like. In some embodiments, the size of the candidate pattern is changed by removing the candidate pattern from the layout, for example, as shown in Figure 2B, Figure 2D, or the like. In some embodiments, the size of the candidate pattern is changed by increasing, for example, as shown in Figure 2F or the like.

FIG. 6B is a flowchart of a method of generating a layout diagram according to some embodiments.

More specifically, according to one or more embodiments, the method in FIG. 6B correspondingly shows blocks 604 and 606 in FIG. 6A in more detail. The context of Figure 6B is Design Rule 1.

An example of the layout diagram that can be generated according to the method of FIG. 6B is layout diagram 200B, or the like. Examples of semiconductor devices that can be manufactured based on the layout plan generated according to the method of FIG. 6B include the semiconductor device 100 of FIG. 1, the semiconductor device based on the layout plan 200B, or the like.

In FIG. 6B, block 604 includes blocks 620 to 622. In blocks 620 to 622, the candidate pattern is the first M_2nd pattern. At block 620, it is determined that the first M_2nd pattern is designated as the pinhole pattern. Examples of M_2nd patterns designated as pinhole patterns include M1 patterns 222(1), 222(2), and 222(4).

In some embodiments, the relationship of the given M1 pattern with respect to the overlying pattern is analyzed to determine whether to assign the given M1 as the pinhole pattern. In some embodiments, the state designated as a pinhole pattern is a property associated with a given M1 pattern, so that checking the attributes of the given M1 pattern reveals whether the given M1 pattern is a pinhole pattern. From block 620, the process proceeds to block 622.

At block 622, it is determined that the first via pattern (first VIA_1st pattern) in the first interconnect level is the only VIA_1st pattern covered by the first M_2nd pattern. Continuing as an example of the M1 pattern 222(1) of the nail hole pattern, the VIA0 pattern 222(1) is the only VIA0 pattern covered by the M1 pattern 222(2). From block 622, the flow leaves block 604 and proceeds to block 606.

In FIG. 6B, block 606 includes block 610. At block 610, at least the size of the candidate pattern is reduced. Block 610 includes block 612. At block 612, the candidate pattern is removed from the layout. An example of removing candidate patterns is removing the M1 pattern 222(1) from Figure 2B, as indicated by the corresponding dashed shape 222(1)' in Figure 2B. In some embodiments, the corresponding via pattern is also removed, for example, VIAO pattern 220(1), as indicated by the corresponding dashed shape 222(1)' in Figure 2B.

In some embodiments, after the candidate patterns have been removed, the method further includes alternatively specifying the corresponding underlying first pattern (first M_1st pattern) in the first level as the pinhole pattern. An example of alternatively specifying the M_1st pattern as the pinhole pattern is to specify the M0 pattern 218(4) of Figure 2B as the pinhole pattern after removing the corresponding M1 pattern 222(1).

FIG. 6C is a flowchart of a method of generating a layout diagram according to some embodiments.

More specifically, according to one or more embodiments, the method of FIG. 6C correspondingly shows blocks 604 and 606 of FIG. 6A in more detail. The context of Figure 6C is Design Rule 2.

An example of a layout diagram that can be generated according to the method of FIG. 6C is layout diagram 200D, or the like. Examples of semiconductor devices that can be manufactured based on the layout plan generated according to the method of FIG. 6C include the semiconductor device 100 of FIG. 1, the semiconductor device based on the layout plan 200D, or the like.

In FIG. 6C, block 604 includes blocks 630 to 632. In blocks 630 to 632, the candidate pattern is the first M_1st pattern. At block 630, it is determined that the first M_1st pattern does not cover at least the first via pattern (first VIA_1st pattern) in the VIA_1st level. Examples of the M_1st pattern that does not cover at least the first VIA_1st pattern include the M0 patterns 218(12) and 218(14) of Figure 2C, or the like. From block 630, the process proceeds to block 632.

At block 632, it is determined that the first M_1st pattern is not covered by at least the first VIA_2nd pattern. Examples of the M_1st pattern not covered by at least the first VIA_1st pattern include the M0 patterns 218(12) and 218(14) of Figure 2C, or the like.

In FIG. 6C, block 606 includes block 640. At block 640, at least the size of the candidate pattern is reduced. Block 640 includes block 642. At block 642, the candidate pattern is removed from the layout. An example of removing candidate patterns is removing the M0 pattern 218(12) from the 2C figure, as indicated by the corresponding dashed shape 218(12)' in the 2D figure.

FIG. 6D is a flowchart of a method for generating a layout diagram according to some embodiments.

More specifically, according to one or more embodiments, the method in FIG. 6D correspondingly shows blocks 604 and 606 in FIG. 6A in more detail. The context of Figure 6D is Design Rule 4.

Examples of layout diagrams that can be generated according to the method of Figure 6D are layout diagrams 300B, 300D, 300F, 300H, or the like. Examples of semiconductor devices that can be manufactured based on the layout plan generated according to the method of FIG. 6D include the semiconductor device 100 of FIG. 1, semiconductor devices based on the layout plans 300B, 300D, 300F, 300H, or the like.

In Figure 6D, block 604 includes blocks 650 to 652. In blocks 650 to 652, the candidate pattern is the first M_1st pattern. As shown in Figure 6D, the process proceeds to block 650 or block 652. At block 650, it is determined that the first M_1st pattern covers at least the first via pattern (first VIA_1st pattern) in the VIA_1st level. Examples of M_1st patterns covering at least the first VIA_1st pattern include M0 patterns 318(1)(A), 318(2)(C), 318(3) corresponding to the 3A, 3C, 3E, and 3G patterns. )(E) and 318(4)(G), or the like.

At block 652, it is determined that the first M_1st pattern is covered by at least the first via pattern (first VIA_2nd pattern) in the VIA_2nd level. Examples of the M_1st pattern covered by at least the first VIA_2nd pattern include M0 patterns 318(1)(A) and 318(3)(E) corresponding to the 3A and 3E figures, or the like.

In FIG. 6D, block 606 includes block 660. At block 660, at least the size of the candidate pattern is reduced. Block 660 includes block 662. At block 662, the size of the wing portion of the candidate pattern is trimmed to result in a smaller subsection portion. Examples of wing parts and corresponding wing parts are as follows. An example of the wing portion is the first wing portion of M0 pattern 318(1)(A), which corresponds to the third portion 338(1) and M0 pattern 318(1)(A) of M0 pattern 318(1)(A) The combination of the second part, the second part extends to the left of the VGD pattern 316(1) to the width 336(1) in Figure 3A. An example of the corresponding short section is the second part of the M0 pattern 318(1)(B), which extends to the left of the VGD pattern 316(1) by the width 336(1) in Figure 3B.

FIG. 6E is a flowchart of a method of generating a layout diagram according to some embodiments.

More specifically, according to one or more embodiments, the method of FIG. 6E correspondingly shows blocks 604 and 606 of FIG. 6A in more detail. The context of Figure 6E is Design Rule 3.

An example of the layout diagram that can be generated according to the method of FIG. 6E is layout diagram 200F, or the like. Examples of semiconductor devices that can be manufactured based on the layout plan generated according to the method of FIG. 6E include the semiconductor device 100 of FIG. 1, the semiconductor device based on the layout plan 200F, or the like.

In FIG. 6F, block 604 includes blocks 670 to 676. In blocks 670 to 676, the candidate pattern is the first M_1st pattern. In block 670, it is determined that the first MD pattern is located in the first or last MD row. Examples of the MD patterns located in the first MD row include MD patterns 210(15) and 210(18) in Figure 2E, or the like. Examples of the MD patterns located in the last MD row include MD patterns 210(17) and 210(20) in Figure 2E, or the like. From block 670, the process proceeds to block 672.

At block 672, it is determined that the first MD pattern is covered by the first via pattern (first VIA_1st pattern) (here, the first VGD pattern) in the VIA_1st level. Examples of the MD pattern covered by the first VIA_1st pattern include the MD patterns 210(15), 210(17), 210(18), 210(20) of Figure 2E, or the like. From block 672, the flow proceeds to block 674.

At block 674, it is determined that the first VIA_1st pattern is also covered by the first M_1st pattern. Examples of VIA_1st patterns that are also covered by the first M_1st pattern include VIA0 patterns 216(17), 216(18), 216(23), and 216(22) in Figure 2E, or the like. From block 674, the flow proceeds to block 676.

At block 676, it is determined that the first M_1st pattern is also not a PG pattern. An example of the first M_1st pattern that is not a PG pattern is the M0 pattern 218 (20) of Figure 2E, or the like. From block 676, the process proceeds to block 678.

At block 678, it is determined that the length of the M_1st pattern is less than the first reference distance. An example of the first reference distance is L2 (see Figures 2E to 2F).

In Figure 6E, block 606 includes block 680. At block 680, the size of the candidate pattern is increased. Block 680 includes block 682. At block 682, the size of the candidate pattern is increased to at least substantially equal to the first reference distance. An example of increasing the size of the candidate pattern is that the size of the M0 pattern 218(20)' of the 2F figure has been increased by the amount ΔW, as shown by the symbol 234 in the figure 2F.

FIG. 7 is a block diagram of an electronic design automation (EDA) system 700 according to some embodiments.

In some embodiments, the EDA system 700 includes an automatic placement and routing (APR) system. According to some embodiments, for example, the EDA system 700 may be used to implement the method described herein for generating a PG floor plan according to one or more embodiments.

In some embodiments, the EDA system is a general-purpose computing device. The general-purpose computing device includes a hardware processor 702 and a non-transitory computer-readable storage medium (also referred to as memory, storage medium, or the like) 704. The storage medium 704 (among other things) is encoded with (ie, stores) computer program code, that is, a set of executable instructions 706. The execution of the instruction 706 by the hardware processor 702 represents (at least partly) an EDA tool that implements a part or all of the method according to the embodiment, for example, the method described herein according to one or more embodiments (hereinafter , Is the process and/or method).

The processor 702 is electrically coupled to the computer-readable storage medium 704 via the bus 708. The processor 702 is also electrically coupled to the I/O interface 710 via the bus 708. The network interface 712 is also electrically connected to the processor 702 via the bus 708. The network interface 712 is connected to the network 714 so that the processor 702 and the computer The readable storage medium 704 can be connected to external components via a network 714. The processor 702 is used to execute the computer program code 706 encoded in the computer-readable storage medium 704 so that the system 700 can be used to execute part or all of the processes and/or methods. In one or more embodiments, the processor 702 is a central processing unit (CPU), a multi-processor, a distributed processing system, an application-specific integrated circuit (ASIC), and/or an appropriate processing unit.

In one or more embodiments, the computer-readable storage medium 704 is an electronic, magnetic, optical, electromagnetic, infrared, and/or semiconductor system (or device or device). For example, the computer-readable storage medium 704 includes semiconductor or solid-state memory, magnetic tape, removable computer disk, random access memory (RAM), read-only memory (ROM), rigid disk and/or Disc. In one or more embodiments of using optical discs, the computer-readable storage medium 704 includes compact disc-read-only memory (CD-ROM), compact disc-read/write (CD-R/W) and/or digital Video Disc (DVD).

In one or more embodiments, the computer-readable storage medium 704 stores computer program codes (instructions) 706 that are used to make the system 700 (where this execution means (at least in part) an EDA tool) can be used to execute the process And/or part or all of the method. In one or more embodiments, the computer-readable storage medium 704 also stores information that facilitates the execution of part or all of the process and/or method. In one or more embodiments, the computer-readable storage medium 704 stores a library 707 of standard cells (ie, a standard cell library), and the library 707 includes the standard cells as disclosed herein and one or the like disclosed herein. Multiple layout drawings 708.

The EDA system 700 includes an I/O interface 710. The I/O interface 710 is coupled to an external circuit system. In one or more embodiments, the I/O interface 710 includes a keyboard, a keypad, a mouse, a trackball, a touch pad, a touch screen, and/or a cursor direction key for conveying information and commands to Processor 702.

The EDA system 700 also includes a network interface 712 coupled to the processor 702. The network interface 712 allows the system 700 to communicate with a network 714 connected to one or more other computer systems. The network interface 712 includes a wireless network interface, such as Bluetooth, WIFI, WIMAX, GPRS or WCDMA; or a wired network interface, such as ETHERNET, USB or IEEE-1364. In one or more embodiments, two or more systems 700 are used to implement part or all of the process and/or method.

The system 700 is used to receive information through the I/O interface 710. The information received via the I/O interface 710 includes one or more of commands, data, design rules, a library of standard units, and/or other parameters for processing by the processor 702. The information is transmitted to the processor 702 via the bus 708. The EDA system 700 is used to receive information related to the UI through the I/O interface 710. The information is stored in the computer-readable medium 704 as a user interface (UI) 742.

In some embodiments, part or all of the processes and/or methods are implemented as independent software applications for execution by a processor. In some embodiments, part or all of the processes and/or methods are implemented as a software application that is part of an additional software application. In some embodiments, part or all of the processes and/or methods are implemented as plug-ins of software applications. In some embodiments, at least one of the process and/or method is implemented as a software application that is part of the EDA tool formula. In some embodiments, part or all of the processes and/or methods are implemented as software applications running on the EDA system 700. In some embodiments, VIRTUOSO® or another suitable layout generation tool, such as VIRTUOSO® available from CADENCE DESIGN SYSTEMS CO., LTD., is used to generate a layout including standard cells.

In some embodiments, the process is implemented as a function of a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, external/removable and/or internal/embedded storage or memory units, for example, optical disks (such as DVD), magnetic disks ( One or more of such as hard disk), semiconductor memory (such as ROM, RAM, memory card) and the like.

FIG. 8 is a block diagram of an integrated circuit (IC) manufacturing system 800 and its associated IC manufacturing process according to some embodiments. In some embodiments, the manufacturing system 800 is used to manufacture (A) one or more semiconductor masks or (B) at least one component in a layer of a semiconductor integrated circuit based on the layout drawing.

In Figure 8, the IC manufacturing system 800 includes entities that interact with each other in the design, development, and manufacturing cycles and/or services related to the manufacturing of IC components 860, such as design room 820, mask room 830, and IC manufacturer/ Manufacturer ("Fab") 850. The entities in the system 800 are connected through a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an intranet and the Internet. The communication network includes wired and/or wireless communication channels. Each entity interacts with one or more of the other entities and provides services to one or more of the other entities and/or receives services from one or more of the other entities. In some implementation In an example, two or more of the design room 820, the mask room 830, and the IC fab 850 are owned by a single larger company. In some embodiments, two or more of the design room 820, the mask room 830, and the IC fab 850 coexist in a common facility and use common resources.

The design office (or design team) 820 generates an IC design layout 822. The IC design layout 822 includes various geometric patterns designed for the IC component 860. The geometric pattern corresponds to the pattern of the metal, oxide, or semiconductor layer constituting the various components of the IC device 860 to be manufactured. Various layers are combined to form various IC features. For example, a part of the IC design layout 822 includes various IC features to be formed in a semiconductor substrate (such as a silicon wafer), such as active regions, gate electrodes, source and drain electrodes, and metal lines for interconnection between layers Or vias, and openings for bonding pads; and various material layers placed on the semiconductor substrate. The design room 820 implements appropriate design procedures to form an IC design layout 822. The design procedure includes one or more of logic design, physical design, or placement and routing. The IC design layout 822 is presented in one or more data files with information of geometric patterns. For example, the IC design layout 822 can be expressed in GDSII file format or DFII file format.

The mask room 830 includes data preparation 832 and mask manufacturing 844. The mask room 830 uses the IC design layout 822 to manufacture one or more masks 845, and the one or more masks 845 are used to manufacture various layers of the IC element 860 according to the IC design layout 822. The mask room 830 performs mask data preparation 832, in which the IC design layout 822 is converted into a representative data file ("RDF"). The mask data preparation 832 provides RDF to the mask manufacturing 844. The mask manufacturing 844 includes a mask direct writing machine. The mask direct writer converts RDF to Change to the image on the substrate, such as a mask (main mask) 845 or a semiconductor wafer 853. The mask data preparation 832 manipulates the design layout 822 to meet the specific characteristics of the mask direct writer and/or the requirements of the IC fab 850. In FIG. 8, the mask data preparation 832 and the mask manufacturing 844 are shown as separate components. In some embodiments, mask data preparation 832 and mask manufacturing 844 may be collectively referred to as mask data preparation.

In some embodiments, the mask data preparation 832 includes optical proximity correction (OPC), which uses lithography enhancement technology to compensate for image errors, such as images that may be caused by diffraction, interference, other process effects, and the like error. OPC adjusts IC design layout 822. In some embodiments, the mask data preparation 832 includes other resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution assist features, phase shift masks, other suitable techniques, and the like or combinations thereof. In some embodiments, inverse lithography (ILT) is also used, which treats OPC as an inverse imaging problem.

In some embodiments, the mask data preparation 832 includes a mask rule checker (MRC), which checks the IC design layout 822 that has undergone processing in OPC. This OPC has a set of mask generation rules. These masks The generation rules contain certain geometric and/or connectivity restrictions to ensure sufficient margin to allow for the variability of the semiconductor manufacturing process, and the like. In some embodiments, MRC modifies the IC design layout 822 to compensate for limitations during mask manufacturing 844, which can offset part of the modifications performed by OPC to comply with the mask generation rules.

In some embodiments, the mask data preparation 832 includes lithography process inspection (LPC), the simulation of which will be implemented by the IC fab 850 to manufacture IC elements 860 processing. The LPC simulates this process based on the IC design layout 822 to generate simulated manufactured components, such as IC components 860. The processing parameters in the LPC simulation may include parameters associated with various processes of the IC manufacturing cycle, parameters associated with tools used to manufacture ICs, and/or other aspects of the manufacturing process. LPC takes into account various factors, such as spatial image contrast, depth of focus ("DOF"), mask error enhancement factor ("MEEF"), other appropriate factors, and the like or combinations thereof. In some embodiments, after the LPC has produced the analog-manufactured device, if the shape of the analog device is not close enough to meet the design rules, the OPC and/or MRC are repeated to further refine the IC design layout 822.

It should be understood that the above description of mask data preparation 832 has been simplified for clarity purposes. In some embodiments, the data preparation 832 includes additional features such as logic operations (LOP) to modify the IC design layout 822 according to manufacturing rules. In addition, the process applied to the IC design layout 822 during the data preparation 832 can be performed in a variety of different orders.

After the mask data is prepared 832 and during mask manufacturing 844, the mask 845 and the group of the mask 845 are manufactured based on the modified IC design layout 822. In some embodiments, mask manufacturing 844 includes performing one or more lithographic exposures based on the IC design layout 822. In some embodiments, a mechanism using an electron beam (e-beam) or multiple electron beams forms a pattern on the mask (mask or main mask) based on the modified IC design layout 822. The mask 845 can be formed in various techniques. In some embodiments, the mask 845 is formed using a binary technique. In some embodiments, the mask pattern includes opaque areas and transparent areas. Used to expose the image sensitive material layer that has been coated on the wafer (example For example, a radiation beam of photoresist (such as an ultraviolet (UV) beam) is blocked by the opaque area and passes through the transparent area. In one example, the binary mask version of the mask 845 includes a transparent substrate (for example, fused silica) and an opaque material (for example, chromium) coated in the opaque area of the binary mask. In another example, the mask 845 is formed using phase transfer technology. In the phase transfer mask (PSM) version of the mask 845, various features in the pattern formed on the phase transfer mask are arranged to have appropriate phase differences in order to enhance the resolution and image quality. In various examples, the phase shift mask may be an attenuated PSM or an alternating PSM. The mask(s) produced by mask manufacturing 844 are used in a variety of manufacturing processes. For example, the mask(s) is used in the ion implantation process of forming various doped regions in the semiconductor wafer 853, used in the etching process of forming various etching regions in the semiconductor wafer 853, and/ Or used in other appropriate manufacturing processes.

The IC fab 850 includes wafer fabrication 852. IC fab 850 is an IC manufacturing company that includes one or more manufacturing facilities for manufacturing a variety of different IC products. In some embodiments, the IC fab 850 is a semiconductor foundry. For example, there may be a manufacturing facility (front-end manufacturing (FEOL) manufacturing) for the front-end manufacturing of multiple IC products, and a second manufacturing facility can provide back-end manufacturing (front-end manufacturing) for interconnection and packaging of IC products. (BEOL) manufacturing), and the third manufacturing facility can provide other services for foundry companies.

The IC fab 850 uses the mask(s) 845 manufactured by the mask chamber 830 to manufacture IC components 860. Therefore, the IC fab 850 at least indirectly uses the IC design layout 822 to manufacture IC components 860. In some embodiments, the semiconductor wafer 853 is manufactured by the IC fab 850 using the mask(s) 845 to form the IC component 860. In some embodiments, IC manufacturing includes at least One or more lithographic exposures are performed based on the IC design layout 822 indirectly. The semiconductor wafer 853 includes a silicon substrate or other suitable substrates on which a material layer is formed. The semiconductor wafer 853 further includes one or more of various doped regions, dielectric features, multi-level interconnects, and the like (formed in subsequent manufacturing steps).

Details on the integrated circuit (IC) manufacturing system (for example, the system 800 in Figure 8) and the IC manufacturing process associated with it can be found in (for example) US Patent No. 9,256,709 issued on February 9, 2016, 2015 It can be found in the U.S. Pending Authorization Publication No. 20150278429 published on October 1, 2014, the U.S. Pending Authorization Publication No. 0140040838 published on February 6, 2014, and U.S. Patent No. 7,260,442 issued on August 21, 2007. These The entire contents of each of the cases are hereby incorporated by reference.

In an embodiment, a method (for manufacturing a semiconductor device) includes (for a layout plan stored on a non-transitory computer-readable medium, the semiconductor device is based on the layout plan, and the layout plan includes a first and an overlying second metal Level (corresponding to M_1st and M_2nd levels) and the first interconnection level (VIA_1st level) therebetween, corresponding to the first and overlying second metallization layers in the semiconductor device and the first interconnection layer in between), resulting in a layout Figure, including the following steps. Select the candidate pattern in the layout plan. The candidate pattern is the first conductive pattern in the M_2nd level (first M_2nd pattern) or the first conductive pattern in the M_1st level (first M_1st pattern); it is determined that the candidate patterns satisfy one or more Criteria; and at least reduce the size of the candidate pattern, thereby revising the layout. In an embodiment, the layout diagram includes the first and overlying second metallization levels (corresponding to the M_1st and M_2nd levels) and the first interconnection level therebetween (VIA_1st level), corresponding to the first and overlying second metallization layers in the semiconductor device and the first interconnection layer therebetween; and the candidate pattern is the first M_2nd pattern; determining that the candidate pattern satisfies one or more criteria includes: Decide that the first M_2nd pattern is designated as the pinhole pattern; Decide that the first via pattern (first VIA_1st pattern) in the first interconnection level is the only VIA_1st pattern covered by the first M_2nd pattern; and at least reduce The size of the candidate pattern includes removing the first M_2nd pattern from the layout. In an embodiment, generating the layout map further includes: alternatively specifying the corresponding underlying first pattern (first M_1st pattern) in the first level as the pinhole pattern. In the embodiment, the first M_1st pattern is designated as the pinhole pattern, because the first VIA_1st pattern in the VIA_1st interconnection level has at least the first and second allowable overlying positions. At these positions, at least one of the M_2nd levels is The corresponding first M_2nd pattern and second M_2nd pattern can be positioned to cover the first VIA_1st pattern; or the first M_2nd pattern is designated as the pinhole pattern because the corresponding first via in the second interconnection level (VIA_2nd level) The pattern (first VIA_2nd pattern) has at least first and second allowable overlying positions. At these positions, at least the corresponding first and second conductive patterns (first and second) in the third metallization level (M_3rd) The second M_3rd pattern) can be positioned to cover the first VIA_2nd pattern. In an embodiment, the layout diagram further includes a second interconnection level (VIA_2nd level), this second interconnection level (VIA_2nd level) overlying the first M_1st level and corresponding to the second interconnection level, this second interconnection level The first metallization layer in the overlying semiconductor device; and the candidate pattern is the first M_1st pattern; determining that the candidate pattern satisfies one or more criteria includes: a first sub-method, the first sub-method includes determining that the first M_1st pattern does not cover At least the first via pattern (first VIA_1st pattern) in the VIA_1st level; and determining that the first M_1st pattern is not covered by at least the first via pattern (first VIA_2nd pattern) in the VIA_2nd level; or the second sub-method , The second sub-method includes, relative to the first direction, determining that the first M_1st pattern covers at least the first via pattern (first VIA_1st pattern) in the VIA_1st level; or relative to the first direction, determining that the first M_1st pattern is At least the first via pattern (the first VIA_2nd pattern) in the VIA_2nd level covers; in the context of the first sub-method, at least reducing the size of the candidate pattern includes removing the first M_1st pattern from the layout; and in the second In the context of the sub-method, reducing at least the size of the candidate pattern includes trimming the first wing portion of the first M_1st pattern to result in a smaller first sub-section portion; and where there is a first VIA_1st pattern or a At least one of a VIA_2nd pattern, so that the first wing portion is located between the first end of the first M_1st pattern and the first VIA_1st pattern or the first VIA_2nd pattern, and there is no corresponding underlay or overlying the first wing portion Other VIA_1st or VIA_2nd patterns. In an embodiment, the layout diagram further includes a transistor level, which corresponds to the transistor layer in the semiconductor device, and there is no metallization level between the M_1st level and the transistor layer. In an embodiment, the method further includes: based on the layout drawing, performing at least one of the following: (A) performing one or more photolithographic exposures; (B) manufacturing one or more semiconductor masks; or (C) Manufacturing at least one component in the layer of the semiconductor integrated circuit.

In an embodiment, a system (for manufacturing semiconductor components) includes at least one processor and at least one memory, and the at least one The memory includes computer code for one or more programs; at least one memory, computer code, and at least one processor are used to execute the system (for a layout plan stored on a non-transitory computer-readable medium, The semiconductor device is based on a layout diagram, which includes the first and overlying second metallization levels (corresponding to the M_1st and M_2nd levels) and the first interconnection level (VIA_1st level) in between, corresponding to the first and upper levels in the semiconductor device Covering the second metallization layer and the first interconnection layer therebetween) to generate a layout diagram includes the following steps. Select the candidate pattern in the layout; the candidate pattern is the first conductive pattern in the M_2nd level (the first M_2nd pattern) or the first conductive pattern in the M_1st level (the first M_1st pattern); it is determined that the candidate pattern satisfies one or more criteria , And changing the size of the candidate pattern to revise the layout; and the layout further includes a transistor level, which corresponds to the transistor layer in the semiconductor device, and there is no metal between the M_1st level and the transistor layer化 level. In an embodiment, the layout diagram includes the first and overlying second metallization levels (corresponding to the M_1st and M_2nd levels) and the first interconnection level (VIA_1st level) therebetween, corresponding to the first and overlying second metallization levels in the semiconductor device. Two metallization layers and the first interconnection layer therebetween; and the candidate pattern is the first M_2nd pattern; determining that the candidate pattern satisfies one or more criteria includes: deciding that the first M_2nd pattern is designated as a pinhole pattern; deciding to be at the first level The first via pattern (first VIA_1st pattern) is the only VIA_1st pattern covered by the first M_2nd pattern; changing the size of the candidate pattern includes removing the first M_2nd pattern from the layout; and generating the layout further includes replacing Ground designates the corresponding underlying first pattern (first M_1st pattern) in the first level as the pinhole pattern. In an embodiment, specify the first M_2nd pattern As a pinhole pattern, because the first VIA_1st pattern in the VIA_1st interconnect level has at least first and second allowable overlying positions, at these positions at least the corresponding first M_2nd pattern and the second M_2nd pattern in the M_2nd level It can be positioned to cover the first VIA_1st pattern; or specify the first M_2nd pattern as the pinhole pattern, because the corresponding first via pattern (first VIA_2nd pattern) in the second interconnect level (VIA_2nd level) has at least the first And the second allowable overlying positions. At these positions, at least the corresponding first and second conductive patterns (first and second M_3rd patterns) in the third metallization level (M_3rd) can be positioned to cover the first A VIA_2nd pattern. In an embodiment, the layout diagram further includes a second interconnection level (VIA_2nd level), this second interconnection level (VIA_2nd level) overlying the first M_1st level and corresponding to the second interconnection level, this second interconnection level The first metallization layer in the overlying semiconductor device; and the candidate pattern is the first M_1st pattern; determining that the candidate pattern meets one or more criteria includes: a first sub-method, the first sub-method includes determining that the first M_1st pattern does not cover At least the first via pattern (first VIA_1st pattern) in the VIA_1st level; and determining that the first M_1st pattern is not covered by at least the first via pattern (first VIA_2nd pattern) in the VIA_2nd level; or the second sub-method , The second sub-method includes, relative to the first direction, determining that the first M_1st pattern covers at least the first via pattern in the VIA_1st level (the first VIA_1st pattern) or the first M_1st pattern is covered by at least the first in the VIA_2nd level Layer hole pattern (first VIA_2nd pattern) coverage; in the context of the first sub-method, changing the size of the candidate pattern includes removing the first M_1st pattern from the layout; and in the context of the second sub-method, changing the candidate pattern Size includes trimming first The first wing portion of the M_1st pattern results in a correspondingly smaller first sub-section portion; and where there is at least one of the first VIA_1st pattern or the first VIA_2nd pattern relative to the first direction, so that the first wing portion It is located between the first end of the first M_1st pattern and the first VIA_1st pattern or the first VIA_2nd pattern, and there is no other VIA_1st or VIA_2nd pattern corresponding to the ground or overlying the first wing portion. In an embodiment, the layout diagram further includes a transistor level, which corresponds to the transistor layer in the semiconductor device, and there is no metallization level between the M_1st level and the transistor layer. In an embodiment, the system further includes at least one of the following: a mask facility for manufacturing one or more semiconductor masks based on the layout; or a manufacturing facility for manufacturing based on The layout plan manufactures at least one component in the layer of the semiconductor integrated circuit. In an embodiment, as an aspect included in the manufacture of one or more semiconductor masks, the mask facility is further used to perform one or more lithographic exposures based on the layout; or as a layer included in the semiconductor integrated circuit During the manufacturing of at least one component in the manufacturing facility, the manufacturing facility is further used to perform one or more lithographic exposures based on the layout.

1.5CPP。在實施例中，此方法進一步包括：基於佈局圖，進行如下各者中之至少一者：(A)進行一或多次光微影曝光；(B)製造一或多個半導 體遮罩；或(C)製造半導體積體電路之層中的至少一個部件。 In an embodiment, a method (for manufacturing a semiconductor device) includes (for a layout plan stored on a non-transitory computer-readable medium, the semiconductor device is based on the layout plan, and the layout plan includes a first and an overlying second metal Level (corresponding to the M_1st and M_2nd levels) and the first interconnection level (VIA_1st level) therebetween, corresponding to the first and overlying second metallization layers in the semiconductor device and the first interconnection layer between them) , Including: selecting the candidate pattern in the layout map, the candidate pattern being the first conductive pattern in the M_1st level (the first M_1st pattern); determining that the candidate pattern satisfies one or more criteria; and increasing the size of the candidate pattern to modify Layout. In an embodiment, the layout diagram further includes a transistor level, which corresponds to the transistor layer in the semiconductor device; the cells of the layout diagram are organized into MD rows, and these MD rows extend in the first direction; A second direction that is substantially perpendicular to the first direction. For the first and last rows in the MD row located close to the first and second boundaries of the cell, determining that the candidate pattern satisfies one or more criteria includes: determining the transistor level The first metal to drain/source (MD) pattern is located in the first or last MD row; it is determined that the first MD pattern is covered by the first gate-drain/source (VGD) via pattern; it is determined The first VGD pattern is covered by the first conductive pattern (first M_1st pattern) in the M_1st level; and determining that the length of the first M_1st pattern is less than the first reference distance; increasing the size of the candidate pattern includes: relative to the second direction, The length of the first M_1st pattern is increased to at least substantially equal to the first reference distance, and the first MD pattern and the first VGD pattern represent corresponding MD and VGD structures in the transistor layer of the semiconductor device. In an embodiment, the first reference distance is greater than the second reference distance; and the second reference distance represents the minimum length of the conductive section in the layer M0 relative to the typical manufacturing tolerance of the generation of semiconductor technology processes that produce semiconductor devices. In the embodiment, the first reference distance is represented by L2; and L2 is greater than a contact polysilicon pitch (CPP) corresponding to the generation of the semiconductor technology process of the semiconductor device. In an embodiment, the layout diagram further includes a transistor level, which corresponds to the transistor layer in the semiconductor device; there is no metallization level between the M_1st level and the transistor layer; and L2

1.5CPP. In an embodiment, the method further includes: based on the layout drawing, performing at least one of the following: (A) performing one or more photolithographic exposures; (B) manufacturing one or more semiconductor masks; or (C) Manufacturing at least one component in the layer of the semiconductor integrated circuit.

The foregoing summarizes the features of several embodiments, so that those familiar with the art can better understand the aspects of the embodiments of the present disclosure. Those familiar with the art should understand that they can easily use the embodiments of the present disclosure as a basis for designing or modifying other processes and structures for achieving the same purpose and/or achieving the same advantages of the embodiments described herein. Those who are familiar with the art should also realize that these equivalent structures do not depart from the spirit and scope of the embodiments of the present disclosure, and they can be implemented in this article without departing from the spirit and scope of the embodiments of the present disclosure. Various changes, substitutions and replacements.

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Claims (20)

A method of manufacturing semiconductor components, including: For a layout plan stored on a non-transitory computer-readable medium, a semiconductor device is based on the layout plan. The layout plan includes a plurality of first and overlying second metallization levels (corresponding to one M_1st and one M_2nd). Level) and a first interconnection level (a VIA_1st level) therebetween, the layout diagram corresponds to a plurality of first and overlying second metallization layers in the semiconductor device and a first interconnection layer in between, Generate the layout diagram, including: Selecting a candidate pattern in the layout diagram, the candidate pattern being a first conductive pattern in the M_2nd level (first M_2nd pattern) or a first conductive pattern in the M_1st level (first M_1st pattern); Determine that the candidate pattern satisfies one or more criteria; and At least one of the candidate patterns is reduced in size, thereby revising the layout. The method described in claim 1, wherein: The layout diagram includes a first and an overlying second metallization level (corresponding to M_1st and M_2nd levels) and a first interconnection level (VIA_1st level) therebetween, corresponding to the first and overlying second metal in the semiconductor device And a first interconnection layer therebetween; and The candidate pattern is the first M_2nd pattern; The steps for determining that the candidate pattern meets one or more criteria include: Decide that the first M_2nd pattern is designated as a pinhole pattern; Determine a first via pattern (first VIA_1st pattern) in the first interconnection level to be a unique VIA_1st pattern covered by the first M_2nd pattern; and The step of reducing at least one size of the candidate pattern includes: removing the first M_2nd pattern from the layout drawing. The method according to claim 2, wherein the step of generating the layout diagram further comprises: Instead, a corresponding one of the underlying first pattern (first M_1st pattern) in the first level is designated as a pinhole pattern. The method described in claim 2, wherein: The first M_1st pattern is designated as a pinhole pattern, because the first VIA_1st pattern in the VIA_1st interconnection level has at least first and second allowable overlying positions. At these positions, at least one of the M_2nd levels The corresponding first M_2nd pattern and a second M_2nd pattern can be positioned to cover the first VIA_1st pattern; or The first M_2nd pattern is designated as a pinhole pattern, because a corresponding first via pattern (first VIA_2nd pattern) in a second interconnect level (VIA_2nd level) has at least first and second allowable overlying Locations, at these locations, the corresponding first and second conductive patterns (first and second M_3rd patterns) in at least one third metallization level (M_3rd) can be positioned to cover the first VIA_2nd pattern. The method described in claim 1, wherein: The layout diagram further includes a second interconnection level (VIA_2nd level), the second interconnection level (VIA_2nd level) overlying the first M_1st The level corresponds to a second interconnection layer, the second interconnection layer overlying the first metallization layer in the semiconductor device, and The candidate pattern is the first M_1st pattern; The steps for determining that the candidate pattern meets one or more criteria include: A first sub-method, including: Determine that the first M_1st pattern does not cover at least one of the first via patterns (first VIA_1st pattern) in the VIA_1st level; and Determine that the first M_1st pattern is not covered by at least one of the first via patterns (first VIA_2nd pattern) in the VIA_2nd level; or A second sub-method, including: With respect to a first direction, determine that the first M_1st pattern covers at least one of the first via patterns in the VIA_1st level (the first VIA_1st pattern); or With respect to a first direction, it is determined that the M_1st pattern is covered by at least one of the first via patterns (first VIA_2nd patterns) in the VIA_2nd level; In the context of one of the first sub-methods, at least the step of reducing the size of the candidate pattern includes: Remove the first M_1st pattern from the layout diagram; and In the context of one of the second sub-methods, at least the step of reducing the size of the candidate pattern includes: Trimming a first wing portion of the first M_1st pattern to result in a smaller first short section; and Wherein relative to the first direction, there is at least one of the first VIA_1st pattern or the first VIA_2nd pattern, so that the first wing portion is located at a first end of the first M_1st pattern and the first VIA_1st pattern Or between the first VIA_2nd patterns, and there is no other VIA_1st or VIA_2nd pattern corresponding to the ground or overlying the first wing part. The method described in claim 1, wherein: The layout diagram further includes a transistor level corresponding to one of the transistor layers in the semiconductor device; and There is no metallization level between the M_1st level and the transistor layer. The method described in claim 1, further comprising: Based on the layout drawing, perform at least one of the following: (A) Perform one or more photolithographic exposures; (B) Manufacturing one or more semiconductor masks; or (C) Manufacturing at least one component in a layer of a semiconductor integrated circuit. A system for manufacturing semiconductor components, including: At least one processor; and At least one memory, which includes computer code for one or more programs; The at least one memory, the computer program code, and the at least one processor are used to enable the system to execute: For a layout plan stored on a non-transitory computer-readable medium, the semiconductor device is based on the layout plan. The layout plan includes a plurality of first and overlying second metallization levels (corresponding to a M_1st And a M_2nd level) and a first interconnection level (a VIA_1st level) therebetween. The layout diagram corresponds to the plurality of first and overlying second metallization layers in the semiconductor device and a first interconnection layer in between , Generate the layout diagram, including: Selecting a candidate pattern in the layout diagram, the candidate pattern being a first conductive pattern in the M_2nd level (first M_2nd pattern) or a first conductive pattern in the M_1st level (first M_1st pattern); Determine that the candidate pattern satisfies one or more criteria; and Changing the size of one of the candidate patterns, thereby revising the layout; and among them: The layout diagram further includes a transistor level corresponding to one of the transistor layers in the semiconductor device; and There is no metallization level between the M_1st level and the transistor layer. The system described in claim 8, wherein: The layout diagram includes a plurality of first and overlying second metallization levels (corresponding to a plurality of M_1st and M_2nd levels) and a first interconnection level (VIA_1st level) therebetween, corresponding to the plurality of first and overlying levels in the semiconductor device The second metallization layer and a first interconnection layer therebetween; and The candidate pattern is the first M_2nd pattern; The steps for determining that the candidate pattern meets one or more criteria include: Decide that the first M_2nd pattern is designated as a pinhole pattern; Deciding that a first via pattern (first VIA_1st pattern) in the first level is a unique VIA_1st pattern covered by the first M_2nd pattern; The steps of changing the size of one of the candidate patterns include: Remove the first M_2nd pattern from the layout diagram; and The steps of generating the layout diagram further include: Instead, a corresponding one of the underlying first pattern (first M_1st pattern) in the first level is designated as a pinhole pattern. The system described in claim 9, wherein: The first M_2nd pattern is designated as a pinhole pattern, because the first VIA_1st pattern in the VIA_1st interconnect level has at least first and second allowable overlying positions, at which positions at least the corresponding ones in the M_2nd level The first M_2nd pattern and a second M_2nd pattern of may be positioned to cover the first VIA_1st pattern; or The first M_2nd pattern is designated as a pinhole pattern, because one of a second interconnection level (VIA_2nd level) corresponds to the first via pattern (first VIA_2nd pattern) with at least the first and second allowable overlays Locations, at these locations, the corresponding first and second conductive patterns (first and second M_3rd patterns) in at least one third metallization level (M_3rd) can be positioned to cover the first VIA_2nd pattern. The system described in claim 8, wherein: The layout diagram further includes a second interconnection level (VIA_2nd level), and the second interconnection level (VIA_2nd level) overlies the first M_1st Level and corresponding to a second interconnection layer, the second interconnection layer overlying the first metallization layer in the semiconductor device, and The candidate pattern is the first M_1st pattern; The steps for determining that the candidate pattern meets one or more criteria include: A first sub-method, including: Determine that the first M_1st pattern does not cover at least one of the first via patterns (first VIA_1st pattern) in the VIA_1st level; and Determine that the first M_1st pattern is not covered by at least one of the first via patterns (first VIA_2nd pattern) in the VIA_2nd level; or A second sub-method, including: With respect to a first direction, it is determined that the first M_1st pattern covers at least one of the first via patterns in the VIA_1st level (the first VIA_1st pattern) or the first is at least one of the first via patterns ( The first VIA_2nd pattern) cover; In the context of one of the first sub-methods, the step of changing the size of one of the candidate patterns includes: Remove the first M_1st pattern from the layout diagram; and In the context of one of the second sub-methods, the step of changing the size of one of the candidate patterns includes: Trimming a first wing portion of the first M_1st pattern to result in a correspondingly smaller first short section; and Wherein relative to the first direction, there is at least one of the first VIA_1st pattern or the first VIA_2nd pattern, so that the The first wing portion is located between a first end of the first M_1st pattern and the first VIA_1st pattern or the first VIA_2nd pattern, and there is no corresponding VIA_1st or VIA_2nd pattern overlying the first wing portion. The system described in claim 8, wherein: The layout diagram further includes a transistor level corresponding to one of the transistor layers in the semiconductor device; and There is no metallization level between the M_1st level and the transistor layer. The system according to claim 8, further comprising at least one of the following: A mask facility for manufacturing one or more semiconductor masks based on the layout plan; or A manufacturing facility for manufacturing at least one component of a semiconductor integrated circuit layer based on the layout drawing. The system described in claim 13, wherein: As an aspect included in the manufacturing of the one or more semiconductor masks, the mask facility is further used to perform one or more lithographic exposures based on the layout; or As an aspect in the manufacture of the at least one component included in the layer of the semiconductor integrated circuit, the manufacturing facility is further configured to perform one or more lithographic exposures based on the layout. A method of manufacturing semiconductor components, including: For a layout plan stored on a non-transitory computer-readable medium, the semiconductor device is based on the layout plan. The layout plan includes a plurality of first and overlying second metallization levels (corresponding to an M_1st and an M_2nd). Floor Level) and a first interconnection level (a VIA_1st level) therebetween, the layout diagram corresponds to a plurality of first and overlying second metallization layers in the semiconductor device and a first interconnection layer in between, Generate the layout diagram, including: Selecting a candidate pattern in the layout diagram, and the candidate pattern is a first conductive pattern (first M_1st pattern) in the M_1st level; Determine that the candidate pattern satisfies one or more criteria; and Increase the size of one of the candidate patterns to revise the layout. The method according to claim 15, wherein: The layout diagram further includes a transistor level corresponding to a transistor layer in the semiconductor device; A unit of the layout diagram is organized into a plurality of MD rows, and the MD rows extend in a first direction; With respect to a second direction substantially perpendicular to the first direction, for the first and last rows of the MD rows located close to the first and second boundaries of the cell, it is determined that the candidate pattern satisfies one or more The steps of this criterion include: Determining that one of the first metal to drain/source (MD) patterns in the transistor level is located in the first or last MD row; Determine that the first MD pattern is covered by a first gate-drain/source (VGD) via pattern; Determine that the first VGD pattern is covered by one of the first conductive patterns (first M_1st pattern) in the M_1st level; and Determining that a length of the first M_1st pattern is less than a first reference distance; The steps of increasing the size of one of the candidate patterns include: Relative to the second direction, increasing a length of the first M_1st pattern to be at least substantially equal to the first reference distance; and The first MD pattern and the first VGD pattern represent corresponding MD and VGD structures in the transistor layer of the semiconductor device. The method according to claim 15, wherein: The first reference distance is greater than a second reference distance; and The second reference distance represents a minimum length of a conductive section in the layer M0 relative to the typical manufacturing tolerance of the generation of the semiconductor technology process that produced the semiconductor device. The method according to claim 15, wherein: The first reference distance is represented by L2; and L2 is greater than a contact polysilicon pitch (CPP) corresponding to a semiconductor technology process generation of the semiconductor device. The method described in claim 18, wherein: The layout diagram further includes a transistor level corresponding to a transistor layer in the semiconductor device; There is no metallization level between the M_1st level and the transistor layer; and L2

1.5CPP. The method according to claim 15, further comprising: Based on the layout drawing, perform at least one of the following: (A) Perform one or more photolithographic exposures; (B) Manufacturing one or more semiconductor masks; or (C) Manufacturing at least one component in a layer of a semiconductor integrated circuit.

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