CN110991139A

CN110991139A - Method and system for manufacturing semiconductor device

Info

Publication number: CN110991139A
Application number: CN201910931515.6A
Authority: CN
Inventors: 彭士玮; 曾健庭; 林威呈; 杨登杰
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 2018-09-28
Filing date: 2019-09-29
Publication date: 2020-04-10
Anticipated expiration: 2039-09-29
Also published as: CN110991139B; TW202032262A; TWI770425B

Abstract

The method (of manufacturing a semiconductor device) includes, for a layout stored on a non-transitory computer readable medium, generating the layout including: selecting a candidate pattern in the layout, the candidate pattern being a first conductive pattern in an M _2nd level (a first M _2nd pattern) or a first conductive pattern in an M _1st level (a first M _1st pattern); determining that the candidate pattern satisfies one or more criteria; and changing the size of the candidate pattern to modify the layout. Embodiments of the present invention also relate to methods of manufacturing semiconductor devices and systems for manufacturing semiconductor devices.

Description

Method and system for manufacturing semiconductor device

Technical Field

Embodiments of the invention relate to methods and systems for fabricating semiconductor devices.

Background

An integrated circuit ("IC") includes one or more semiconductor devices. One way to represent a semiconductor device is to have a plan view called a layout. The layout is generated in the context of design rules. A set of design rules impose constraints on the placement of the respective patterns in the layout, e.g., geographic/spatial constraints, connection constraints, etc. Typically, a set of design rules includes a subset of design rules related to spacing and other interactions between patterns in adjacent or contiguous cells, where the patterns represent conductors in a metallization layer.

Typically, a set of design rules is specific to a process technology node by which a semiconductor device is to be manufactured based on a layout diagram. The design rule set compensates for variability of the corresponding process technology node. Such compensation increases the likelihood that the actual semiconductor device produced by the layout will be an acceptable counterpart of the virtual device upon which the layout is based.

Disclosure of Invention

An embodiment of the present invention provides a method of manufacturing a semiconductor device, the method including: for a layout stored on a non-transitory computer readable medium, the semiconductor device generating the layout based on the layout including first and second metallization levels corresponding to first and second upper metallization layers in the semiconductor device and a first interconnect layer therebetween (respective M _1st and M _2nd levels) and a first interconnect level therebetween (VIA _1st level), the generating the layout comprising: selecting a candidate pattern in the layout, the candidate pattern being a first conductive pattern in an M _2nd level (a first M _2nd pattern) or a first conductive pattern in an M _1st level (a first M _1st pattern); determining that the candidate pattern satisfies one or more criteria; and reducing at least the size of the candidate pattern, thereby modifying the layout.

Another embodiment of the present invention provides a system for manufacturing a semiconductor device, the system including: at least one processor; and at least one memory including computer program code for one or more programs; wherein the at least one memory, the computer program code, and the at least one processor are configured to cause a system to perform: for a layout stored on a non-transitory computer readable medium, the semiconductor device generating the layout based on the layout including first and second metallization levels corresponding to first and second upper metallization layers in the semiconductor device and a first interconnect layer therebetween (respective M _1st and M _2nd levels) and a first interconnect level therebetween (VIA _1st level), the generating the layout comprising: selecting a candidate pattern in the layout, the candidate pattern being a first conductive pattern in the second metallization level (first M _2nd pattern) or a first conductive pattern in the first metallization level (first M _1st pattern); determining that the candidate pattern satisfies one or more criteria; and changing the size of the candidate pattern, thereby modifying the layout; and wherein: the layout further includes transistor levels corresponding to transistor layers in the semiconductor device; and no metallization level is present between the first metallization level and the transistor layer.

Yet another embodiment of the present invention provides a method of manufacturing a semiconductor device, the method including: for a layout stored on a non-transitory computer readable medium, the semiconductor device generating the layout based on the layout including first and second metallization levels corresponding to first and second upper metallization layers in the semiconductor device and a first interconnect layer therebetween (respective M _1st and M _2nd levels) and a first interconnect level therebetween (VIA _1st level), the generating the layout comprising: selecting a candidate pattern in the layout, the candidate pattern being a first conductive pattern (first M _1st pattern) in the first metallization level; determining that the candidate pattern satisfies one or more criteria; and increasing the size of the candidate pattern, thereby modifying the layout.

Drawings

Various aspects of the invention are best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that, in accordance with standard practice in the industry, various components are not drawn to scale. In fact, the dimensions of the various elements may be arbitrarily increased or decreased for clarity of discussion.

Fig. 1 is a block diagram in accordance with some embodiments.

Fig. 2A-2F are respective layout diagrams 200A-200F according to some embodiments.

Fig. 3A-3H are respective layout diagrams 300A-300H according to some embodiments.

Fig. 4A-4D are respective cross-sectional views 400A-400D according to some embodiments.

Fig. 5 is a flow diagram of a method according to some embodiments.

Fig. 6A-6E are respective flow diagrams of respective methods according to some embodiments.

Fig. 7 is a block diagram of an Electronic Design Automation (EDA) system in accordance with some embodiments.

Fig. 8 is a block diagram of an Integrated Circuit (IC) manufacturing system and IC manufacturing flow associated therewith, in accordance with some embodiments.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components, values, operations, materials, arrangements, etc. are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to limit the invention. Other components, values, operations, materials, arrangements, etc. are contemplated. For example, in the following description, forming a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Further, the present invention may repeat reference numerals and/or characters in the various embodiments. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Also, spatially relative terms, such as "below …," "below …," "lower," "above …," "upper," and the like, may be used herein for ease of description to describe one element or component's relationship to another element (or other) component as illustrated. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

For some embodiments, generating the layout comprises: selecting a candidate pattern in the layout, such as an M1 pattern or an M0 pattern; determining that the candidate pattern satisfies one or more criteria; and changing the size of the candidate pattern to modify the layout improves the M0 routing resource. In some embodiments, the context used to generate the layout is a first design rule (design rule 1), design rule 2, design rule 3, or design rule 4. In some embodiments where the context is design rule 3, the size of the candidate pattern is changed by reducing the size of the candidate pattern. In some embodiments where the context is design rule 1 or design rule 2, the size of the candidate pattern is changed by removing the candidate pattern from the layout. In some embodiments where the context is design rule 4, the size of the candidate pattern is changed by increasing the size of the candidate pattern.

Fig. 1 is a block diagram of a semiconductor device 100 according to some embodiments.

In fig. 1, a semiconductor device 100 includes, inter alia, a circuit macro (hereinafter referred to as macro) 101. In some embodiments, macro 101 is a logical macro. In some embodiments, macro 101 is an SRAM macro. In some embodiments, macro 101 is a macro other than a logical macro or an SRAM macro. The macro 101 includes one or more cell regions 104 arranged in a row 102. In some embodiments, each cell region 104 is implemented based on a layout generated by one or more of the design rules disclosed herein, thus having improved M0 routing resources.

Fig. 2A-2B are respective layout diagrams 200A-200B according to some embodiments.

According to some embodiments, map 200A represents an initial map and map 200B represents a corresponding map generated by one or more methods disclosed herein.

Fig. 2A to 2B assume an orthogonal XYZ coordinate system, in which the X, Y and Z axes represent respective first, second and third directions. In some embodiments, the first, second, and third directions correspond to an orthogonal coordinate system different from the XYZ coordinate system.

In fig. 2A, the layout diagram 200A includes the cells 204(1) (a). The cell 204(1) (a) represents a cell region in the semiconductor device based on the layout diagram 200A. The cells 204(1) (a) are arranged in rows 202, the rows 202 extending substantially in a first direction (extending horizontally). Although not shown for simplicity of illustration, in some embodiments, row 202 includes additional instances of cells, e.g., cell 204(1) (a) and/or other cells. Row 202 includes subrows 203N and 203P.

The layout 200A further includes: active region patterns 208P and 208N; MD patterns 210(1), (210 (2), (210 (3), (210 (4)), 210(5), (210 (6), (210 (7), (210 (8)), 210(9), (210 (10)), and 210 (11); gate patterns 212(1), 212(2), 212(3), 212(4), 212(5), 214(1), 214(2), 214(3) and 214 (4); VGD pattern 216(1), 216(2), 216(3), 216(4), 216(5), 216(6), 216(7), 216(8), 216(9), 216(10), 216(11), and 216 (12); m0 patterns 218(1), 218(2), 218(3), 218(4), 218(5), 218(6), 218(7), 218(8) and 218 (9); VIA0 pattern 220(1), 220(2), 220(3), 220(4), and 220 (5); and M1 patterns 222(1), 222(2), 222(3), and 222 (4). In some embodiments, unit 204(1) (a) comprises:

active region patterns

208P and 208N; MD pattern 210(1) -210 (11); gate patterns 212(1) -214 (4); VGD pattern 216(1) -216 (12); m0 pattern 218(2) -218 (8); portions of M0 patterns 218(1) and 218 (9); VIA0 patterns 220(1) -220 (5); and M1 patterns 222(1) -222 (4).

In the example of fig. 2A, assume that: m0 patterns 218(1) and 218(9) are grid (PG) patterns representing respective conductors in the grid of the semiconductor device fabricated based on layout 200A; and M0 patterns 218(2) -218(8) are wiring patterns representing non-PG conductors of the semiconductor device manufactured based on layout 200A. In some embodiments, PG pattern 218(1) is designated to provide a first system reference voltage and PG pattern 218(9) is designated to provide a second system reference voltage. In FIG. 2A, PG pattern 218(1) is designated for VDD and PG pattern 218(9) is designated for VSS. In some embodiments, PG pattern 218(1) is designated for providing VSS and PG pattern 218(9) is designated for providing VDD. In some embodiments, PG patterns 218(1) and 218(9) are designated to provide respective voltages other than VDD and VSS or VSS and VDD, respectively.

Active region patterns

208P and 208N, MD patterns 210(1) -210(11), gate patterns 212(1) -212(5) and 214(1) -214(4), and VGD patterns 216(1) -216(12) are included in the transistor level of layout 200A, which corresponds to the transistor layers of the semiconductor device based on layout 200A. M0 patterns 218(1) -218(9) are included in metallization level M0 in layout 200A, which is based on metallization layer M0 of the semiconductor device of layout 200A, respectively. VIA0 patterns 220(1) -220(5) are included in interconnect level V0 in layout 200A, which corresponds to interconnect level V0 of the semiconductor device based on layout 200A. M1 patterns 222(1) -222(4) are included in the M1 metallization level, which corresponds to metallization layer M1 of the semiconductor device based on layout diagram 200A.

The MD patterns 210(1) -210(11) and the gate patterns 212(1) -212(5) and 214(1) -214(4) are located above the respective portions of the

active region patterns

208P and 208N. In some embodiments, the

active area patterns

208P and 208N are located above a substrate pattern (not shown). The VGD patterns 216(1) -216(12) are located above the respective portions of the MD patterns 210(1) -210(7) and 210(11) and the gate patterns 212(1) -212 (5). The M0 patterns 218(1) -218(9) are located above the corresponding VGD patterns 216(1) -216 (12). VIA0 patterns 220(1) -220(5) are located above the corresponding M0 patterns 218(2) -218(5) and 218 (7). The M1 patterns 222(1) -222(4) are located above the corresponding VIA0 patterns 220(1) -220 (5).

The layout diagram 200A assumes that the corresponding semiconductor process technology node includes various design rules for generating the layout diagram. Layout diagram 200A further assumes that the design rules follow a numbering convention in which the first metallization level (M _1st) and the corresponding first interconnect structure level (V _1st) are referred to as M0 and V0, respectively. Levels M0 and V0 of layout 200A represent metallization layer M0 and interconnect structure layer V0, respectively, in a semiconductor device based on layout 200A. In some embodiments, the numbering convention assumes that the M _1st level and the V _1st level are referred to as M1 and V1, respectively.

The

active area patterns

208P and 208N and the M0 patterns 218(1) -218(9) have respective major axes that extend substantially along the X-axis (extend horizontally). The MD patterns 210(1) -210(11), the gate patterns 212(1) -212(5) and 214(1) -214(4), and the M1 and M1 patterns 222(1) -222(4) have respective long axes extending substantially along the Y axis (extending vertically).

In fig. 2A,

active area patterns

208P and 208N represent respective NMOS and NMOS fins in the semiconductor device based on layout diagram 200A. Accordingly, the

active area patterns

208P and 208N are designated for respective NMOS finFET and nmosffet configurations and are referred to as

respective fin patterns

208P and 208N. In some embodiments, the

fin patterns

208P and 208N are designated for NMOS and NMOS configurations, respectively. Although not shown for simplicity of illustration, in some embodiments, each of the sub-rows 203N and 203P includes two or more fin patterns designated for NMOS finFET and NMOS finFET configurations, respectively. In some embodiments,

active area patterns

208P and 208N are designated for planar transistor configurations, thus representing respective active areas in the cell area based on cell 204(1) (a). In some embodiments,

active area patterns

208P and 208N are designated for nanowire configurations. In some embodiments,

active area patterns

208P and 208N are specified for a nanosheet configuration. In some embodiments,

active area patterns

208P and 208N are designated for a Gate All Around (GAA) configuration. In some embodiments in which the active area is referred to as an Oxide Dimension (OD) area, the

active area patterns

208P and 208N are referred to as

respective OD patterns

208P and 208N.

In layout 200A, MD patterns 210(1) -210(11) represent the corresponding MD conductive structures in the transistor layers of the semiconductor device based on layout 200A. Gate patterns 212(1) -212(5) and 214(1) -214(4) represent respective gate structures in the transistor layers of the semiconductor device based on layout 200A. VGD patterns 216(1) -216(12) represent the corresponding VG or VD structures in the transistor layers of the semiconductor device based on layout 200A. The VG structures (see fig. 4B) electrically couple the gate structures to respective M0 conductive segments. The VD structure (see fig. 4A) electrically couples the drain/source structure to the corresponding M0 conductive segment. M0 patterns 218(1) -218(9) represent respective conductive segments in metallization layer M0 of the semiconductor device based on layout 200A. VIA0 patterns 220(1) -220(5) represent corresponding interconnect structures, e.g., VIAs, in interconnect layer V0 of the semiconductor device based on layout 200A. M1 patterns 222(1) -222(4) represent respective conductive segments in metallization layer M1 of the semiconductor device based on layout 200A.

In fig. 2A, the gate patterns 212(1) -212(5) are included in the cells 204(1) (a). With respect to the X axis, the gate patterns 214(1) -214(4) are included in the cells 204(1) (a). With respect to the Y-axis, gate patterns 214(1) and 214(3) are substantially collinear, and gate patterns 214(2) and 214(4) are substantially collinear. In some embodiments (not shown), the gate patterns 214(1) and 214(3) are merged and covered with a cut pattern that (in effect) produces two discrete gate patterns corresponding to the gate patterns 214(1) and 214 (3). In some embodiments (not shown), the gate patterns 214(2) and 214(4) are merged and covered with a cut pattern that (in effect) produces two discrete gate patterns corresponding to the gate patterns 214(2) and 214 (4).

With respect to the layout diagram 200A, in some embodiments, the gate patterns 212(1) -212(5) are active gate patterns. In some embodiments, the gate patterns 214(1) -214(4) are designated as active or dummy gate patterns, respectively. In some embodiments, the gate patterns 212(1) -212(5) and 214(1) -214(4) are designated as active or dummy gate patterns, respectively, based on whether the respective

active area patterns

208P and 208N are substantially continuous or substantially discontinuous at the side boundaries of the cell 204(1) (a) relative to the X-axis. In some embodiments, where the active area pattern is substantially continuous at the side boundaries of cells 204(1), (a), this configuration is referred to as a continuous oxide diffusion (CNOD) configuration. In some embodiments where a CNOD configuration is present, regions of the active area pattern that overlap the side boundaries of the cells are designated for doping, which results in a fill region in the corresponding semiconductor device. In some embodiments, where the active area pattern is substantially discontinuous at the side boundaries of the cells 204(1) (a), this configuration is referred to as a continuous multi-diffusion edge (CPODE) configuration. In some embodiments where a CPODE configuration is present, an insulator pattern (not shown) is disposed over the area representing the active area pattern discontinuity at the side boundary of the cell. In some embodiments, the active gate pattern is designated to receive signals related to the function of the circuit represented by the unit 204(1) (a). In some embodiments, the dummy gate pattern represents a dummy gate structure with respect to the X-axis that helps provide isolation between the cell region of the respective cell 204(1) (a) and an adjacent (e.g., contiguous) cell region (not shown). In some embodiments, the dummy gate structure is configured to float, and thus the dummy gate pattern is designated to float accordingly, e.g., in the case of a CPODE configuration. In some embodiments, the dummy gate structures are configured to receive a voltage that inhibits conduction in the underlying portion of the respective fin, e.g., inhibits the inversion layer of the underlying portion of the respective fin, relative to the X-axis, and therefore the dummy gate patterns are accordingly designated to receive the turn-on inhibit voltage.

The gate patterns 212(1) -212(5) and 214(1) -214(4) are spaced apart by a uniform distance with respect to the X-axis. In some embodiments, the uniform distance represents one Contact Polysilicon Pitch (CPP) of the respective semiconductor process technology node, e.g., gate patterns 214(1) and 212(1) are separated by one CPP. Thus, relative to the X-axis, cell 204(1) has a width of 6 CPP.

The unit 204(1) (a) represents a circuit. In some embodiments, element 204(1) (a) represents circuitry that provides functionality. In some embodiments, cell 204(1) (a) represents circuitry that provides logic functions, and is therefore referred to as a logic cell. In some embodiments, cell 204(1) (a) represents a logic function AND, for example, a four-input AND (AND 4). In some embodiments, at least one of the units 204(1) -204(2) represents circuitry that provides functionality other than logic functionality.

In the example of fig. 2A, cell 204(1) (a) has input tags a1, a2, A3, and a4, and output tag Z, which represent respective input signals a1, a2, A3, and a4, and output signal Z of a cell region in the semiconductor device corresponding to cell 204(1) (a). Input tag a1 is diagrammatically coupled to gate pattern 212(1) by schematic paths including gate pattern 212(1), VGD pattern 216(2), M0 pattern 218(4), VIA0 pattern 220(1), and M1 pattern 222 (1). Input tag a2 is graphically coupled to gate pattern 212(2) by schematic paths including gate pattern 212(2), VGD pattern 216(9), M0 pattern 218(6), VIA0 pattern 220(4), and M1 pattern 222 (2). Input tag a3 is graphically coupled to gate pattern 212(3) by a schematic path that includes gate pattern 212(3), VGD pattern 216(4), and M0 pattern 218 (5). Input tag a4 is graphically coupled to gate pattern 212(4) by a schematic path that includes gate pattern 212(4), VGD pattern 216(10), and M0 pattern 218 (7). Output label Z is graphically coupled to MD pattern 210(6) by a schematic path that includes MD pattern 210(6), VGD pattern 216(7), M0 pattern 218(3), VIA0 pattern 220(3), and M1 pattern 222 (4).

Recall that layout 200A represents an initial layout and that, according to some embodiments, layout 200B represents a corresponding layout generated by one or more methods disclosed herein. More specifically, according to some embodiments, cell 204(1) (B) of layout 200B indicates that a method including a first design rule (design rule 1) (discussed below) has been applied to layout 200A. An example of a cell region of the respective cell 204(1) (B) is the cell region 104 of fig. 1.

Layout 200B is similar to layout 200A. Fig. 2B follows a similar numbering convention as that of fig. 2A. For the sake of brevity, the discussion will focus more on the differences between fig. 2B and fig. 2A rather than on the similarities.

In fig. 2B, some of the pattern has been removed as compared to fig. 2A. In particular, VIA0 patterns 220(1), (220), (4), and 220(3) in fig. 2A have been removed in fig. 2B, as shown by the respective dashed line shapes 220(1), (220), (4), and 220 (3). In addition, the M1 patterns 222(1), (222), (2), and 222(4) in fig. 2A have been removed in fig. 2B, as shown by the respective dashed line shapes 222(1), (222), (2), and 222 (4).

In some embodiments, design rule 1 is as follows: if the unique VIA0 pattern overlaps the given M1 pattern, the given M1 pattern is removed. More specifically, a given M1 pattern is part of a schematic path that includes a given M1 pattern, a unique VIA0 pattern, and a corresponding underlying M0 pattern.

In some embodiments, design rule 1 is as follows: for the first M1 pattern designated as the lead pattern, if the first VIA0 pattern is the only VIA0 pattern that overlaps the first M1 pattern, the first M1 pattern is removed and instead the corresponding underlying first M0 pattern is designated as the lead pattern.

In some embodiments, the designation as pin pattern should be understood as follows: for a first conductive pattern in a first metallization level M _1st, which has a respective underlying first interconnect level V _1st, the designation of the first conductive pattern as a pin pattern indicates that there are at least first and second allowed upper locations for a respective first via pattern in level V _1st, where at least respective second and third conductive patterns in a second metallization level can be correspondingly positioned to overlap the first via pattern. For example, for the first M0 pattern and the corresponding first VIA0 pattern above, if there are multiple locations for the first V1a0 pattern at which the corresponding M1 pattern can be positioned to overlap the first V1a0 pattern, the first M0 pattern is designated as a lead pattern. For example, for the first M1 pattern and the corresponding first VIA1 pattern, if there are multiple locations for the first V1a1 pattern at which the corresponding M2 pattern can be positioned to overlap the first V1a1 pattern, the first M1 pattern is designated as a lead pattern. In some embodiments, the relationship of a given M0/M1 pattern relative to the above patterns is analyzed to determine whether a given M0/M1 is to be designated as a pin pattern. In some embodiments, the state designated as a pin pattern is an attribute associated with a given M0/M1 pattern, such that checking the attribute of a given M1 pattern reveals whether the given M1 pattern is a pin pattern.

In fig. 2A, the M1 patterns 222(1), 222(2), and 222(4) and the M0 patterns 218(5) and 218(7) are designated as pin patterns. As such, with respect to the M1 pattern 222(1), there are a plurality of allowable upper positions for the respective VIA patterns VIA1(1) (not shown) at which the respective M2 patterns (not shown) can be positioned to overlap the VIA patterns V1a1 (1). With respect to the M1 pattern 222(2), there are a plurality of allowable upper positions for the respective VIA patterns VIA1(2) (not shown) where the respective M2 patterns (not shown) can be positioned to overlap the VIA patterns V1a1 (2). Regarding the M1 pattern 222(4), there are a plurality of allowable upper positions for the respective VIA patterns VIA1(3) (not shown), which may be positioned to overlap the VIA patterns V1a1 (3).

In layout 200A, of the M1 patterns designated as the pin pattern, each of the M1 patterns 222(1), 222(2), and 222(4) overlaps only one VIA0 pattern, the VIA0 pattern being the corresponding VIA0 patterns 220(1), 220(4), and 220 (3). Thus, design rule 1 applies to each of M1 patterns 222(1), 222(2), and 222 (4).

The result of applying design rule 1 to FIG. 2A is shown in FIG. 2B. Cell 204(1) (B) of layout 200B is the result of applying a method including design rule 1 to layout 200A, and more particularly to M1 patterns 222(1), 222(2), and 222 (4). The results of applying design rule 1 to FIG. 2A include: VIA0 patterns 220(1), 220(4) and 220(3) and M1 patterns 222(1), 222(2) and 222(4) have been removed from fig. 2B, as shown by the respective dashed line shapes 220(1), 220(4), 220(3), 222(1), 222(2), and 222 (4); and the M0 patterns 218(4), 218(6), 218(5), 218(7), and 218(3) have been designated as pin patterns.

In fig. 2B, designating the M0 pattern 218(4) as a pin pattern indicates that there are multiple permissible upper locations for the respective via patterns 220(1) (not shown) at which the respective M1 patterns, e.g., 222(1) (not shown), may be positioned to overlap the via patterns 220 (1). In fig. 2B, designating the M0 pattern 218(6) as a pin pattern indicates that there are multiple permissible upper locations for the respective via patterns 220(4) (not shown) at which the respective M1 patterns, e.g., 222(2) (not shown), may be positioned to overlap the via patterns 220 (4). In fig. 2B, designating the M0 pattern 218(5) as a lead pattern indicates that there are multiple allowable upper locations for the respective VIA patterns VIA (4) (not shown) where the respective M1 patterns (not shown) may be positioned to overlap the VIA patterns VIA (4). In fig. 2B, designating the M0 pattern 218(7) as a lead pattern indicates that there are multiple allowable upper locations for the respective VIA patterns VIA (5) (not shown) where the respective M1 patterns (not shown) may be positioned to overlap the VIA patterns VIA (5). In fig. 2B, designating the M0 pattern 218(3) as a pin pattern indicates that there are multiple allowed upper locations for the respective via patterns 220(3) (not shown) where the respective M1 patterns, e.g., 222(4) (not shown), may be positioned to overlap the via patterns 220 (4).

By removing M1 patterns 222(1), 222(2), and 222(4) and VIA0 patterns 220(1), 220(4), and 220(3), layout 200B is less congested compared to layout 200A. By removing M1 patterns 222(1), 222(2), and 222(4) and VIA0 patterns 220(1), 220(4), and 220(3), layout 200B has improved M1 routing resources compared to layout 200A. In some embodiments, because layout 200B has fewer M1 patterns than layout 200A, layout 200B is considered to have improved routing resources relative to layout 200A. In some embodiments, the reduced congestion in tier M1 causes reduced congestion in tier M2. In some embodiments, congestion in tier M2 is reduced (≈ 3%) - (≈ 4%).

Fig. 2C-2D are respective layouts 200C-200D according to some embodiments.

Layout 200C represents an initial layout, and layout 200D represents a corresponding layout generated by one or more methods disclosed herein, according to some embodiments. More specifically, cell 204(2) (D) of layout diagram 200D represents that a method including a second design rule (design rule 2) (discussed below) to layout diagram 200C has been applied according to some embodiments. An example of a cell region of the respective cell 204(2) (D) is the cell region 104 of fig. 1.

The layouts 200C-200D are similar to the corresponding layouts 200A-200B of FIGS. 2A-2B. Fig. 2C-2D follow a similar numbering convention as fig. 2A-2B. Although corresponding, some components may differ. To help identify corresponding, but still different, components, the numbering convention uses parentheses. For example, pattern 218(10) in fig. 2C and pattern 218(1) in fig. 2B are both M0 patterns, with similarity reflected in common root 218(_), and differences reflected in brackets _ (10) and _ (1). For the sake of brevity, the discussion will focus more on the differences between fig. 2C-2D and fig. 2A-2B rather than the similarities.

In fig. 2C, layout 200C includes cells 204(2) (C). The layout 200A further includes: MD patterns 210(10), 210(11), 210(12), 210(13), 210(14), and 210 (15); gate patterns 212(6), 214(5), 214(6), 214(7), and 214 (8); VGD patterns 216(13), 216(14), 216(15), and 216 (16); and M0 patterns 218(10), 218(11), 218(12), 218(13), 218(14) and 218 (15). The fin pattern and the M1 pattern are omitted in fig. 2C to 2D for simplicity of explanation. In some embodiments, unit 204(2) (C) comprises: MD pattern 210(10) -210 (15); gate patterns 212(6) and 214(5) -214 (8); VGD pattern 216(13) -216 (16); m0 pattern 218(11) -218 (14); and portions of M0 patterns 218(10) and 218 (15).

In some embodiments, cells 204(2), (C) and 204(2) (D) of respective fig. 2C and 2D are inverter cells representing respective inverter circuits.

In fig. 2D, some of the pattern has been removed compared to fig. 2C. In particular, the M0 patterns 218(12) and 218(14) in fig. 2C have been removed in fig. 2D, as shown by the respective dashed line shapes 218(12) 'and 218 (14)' in fig. 2D.

In some embodiments, design rule 2 is as follows: if the given M0 pattern does not overlap with one or more VGD contact patterns, and if the given M0 pattern does not overlap with one or more V0 contact patterns, the given M0 pattern is removed. More specifically, the given M0 pattern is not part of a schematic path that includes the given M0 pattern and one or more VGD patterns, nor is the given M0 pattern part of a schematic path that includes the given M0 pattern and one or more VIA0 patterns.

In fig. 2C, the M0 pattern 218(12) does not overlap with one or more VGD contact patterns, and the M0 pattern 218(12) also does not overlap with one or more V0 contact patterns. Thus, design rule 2 applies to M0 pattern 218 (12). Similarly, in fig. 2C, the M0 pattern 218(14) does not overlap with one or more VGD contact patterns, and the M0 pattern 218(14) also does not overlap with one or more V0 contact patterns. Thus, design rule 2 applies to M0 pattern 218 (14).

The result of applying design rule 2 to fig. 2C is shown in fig. 2D. Cell 204(2) (D) of layout diagram 200D is the result of applying the method including design rule 2 to layout diagram 200C, and more particularly to M0 patterns 218(12) and 218 (14). The results of applying design rule 1 to FIG. 2C include: the M0 patterns 218(12) and 218(14) have been removed from fig. 2D, as shown by the corresponding dashed line shape 218 (12)' in fig. 2D; and the M0 and M0 patterns 218(14) have been removed from fig. 2D, as shown by the corresponding dashed shapes 218 (14)' in fig. 2D.

By removing M0 patterns 218(12) and 218(14), layout 200D is less congested compared to layout 200C. By removing M0 patterns 218(12) and 218(14), layout 200D has improved M0 routing resources compared to layout 200C. In some embodiments, because layout 200D has fewer M0 patterns than layout 200C, layout 200D is considered to have improved M0 routing resources relative to layout 200C.

Fig. 2E-2F are respective layout diagrams 200E-200F according to some embodiments.

Layout diagram 200E represents an initial layout diagram, and layout diagram 200F represents a corresponding layout diagram generated by one or more methods disclosed herein, according to some embodiments. More specifically, element 204(3) (F) of layout diagram 200F represents that a method including a third design rule (design rule 3) (discussed below) has been applied to layout diagram 200E according to some embodiments. An example of a cell region corresponding to cell 204(3) (F) is cell region 104 of fig. 1.

The layouts 200E-200F are similar to the layouts 200A-200D of the corresponding FIGS. 2A-2D. Fig. 2E-2F follow a similar numbering convention as fig. 2A-2D. Although corresponding, some components may differ. To help identify corresponding, but still different, components, the numbering convention uses parenthetical numbers. For example, pattern 218(16) in fig. 2E and pattern 218(10) in fig. 2D are both M0 patterns, with similarity reflected in common root 218(_), and differences reflected in parenthesis (16) and (10). For the sake of brevity, the discussion will focus more on the differences between fig. 2A-2F and fig. 2A-2D rather than the similarities.

In fig. 2E, layout diagram 200E includes cells 204(3) (E). The layout diagram 200E further includes: MD patterns 210(17), 210(18), 210(19), 210(20), and 210 (21); gate patterns 212(7), 212(8), 214(9), 214(10), 214(11), and 214 (12); VGD patterns 216(17), 216(18), 216(19), 216(2), 216(21), 216(22), and 216 (23); and M0 patterns 218(16), 218(17), 218(18), 218(19), 218(20), and 218 (21). For simplicity of explanation, the fin pattern, VIA0 pattern and M1 pattern are omitted in fig. 2C to 2D. In some embodiments, unit 204(2) (C) comprises: MD pattern 210(17) -210 (21); gate patterns 212(7) -212(8) and 214(9) -214 (12); VGD pattern 216(17) -216 (23); m0 pattern 218(17) -218 (20); and portions of M0 patterns 218(16) and 218 (21).

The unit 204(3) (E) represents a circuit. In some embodiments, element 204(3) (E) represents circuitry that provides functionality. In some embodiments, units 204(3) (E) represent circuitry that provides logic functions, and are therefore referred to as logic units accordingly. In some embodiments, cells 204(3) (E) represent a logical function NAND, such as a two-input NAND (NAND 2).

In layout 200E, with respect to the X-axis, MD patterns 210(17) -210(21) are arranged according to a grid of imaginary tracks that are substantially parallel to the Y-axis. In some embodiments, the Pitch (PT) of the tracks is PT ≈ CPP with respect to the X-axis, and thus the immediately adjacent MD patterns are one track away from each other. In some embodiments, the Pitch (PT) of the tracks is PT ≈¹/₂The CPP, and thus the immediately adjacent MD pattern, are two tracks that are distant from each other. In some embodiments, the width of each MD pattern, e.g., MD pattern 210(1), is WMD ≈ with respect to the X-axis¹/₃CPP。

With respect to the X-axis, in some embodiments where track Pitch (PT) is PT ≈ CPP, the long axes of respective MD patterns 210(15) and 210(18) are substantially collinear with the first track, the long axes of MD patterns 210(16) and 210(19) are substantially collinear with the second track, and the long axes of respective MD patterns 210(17) and 210(19) are substantially collinear with the third (and last) track.

With respect to the X-axis, in some embodiments where track Pitch (PT) is PT ≈ CPP, the tracks define MD columns. Since the MD patterns 210(15) and 210(18) are located in the first MD column, the MD patterns 210(16) and 210(19) are located in the second MD column, and the MD patterns 210(17) and 210(19) are located in the third (and last) MD column.

In fig. 2E, M0 patterns 218(17) -218(20) are internal to cells 204(3) (E). With respect to the X-axis, one end of each of the M0 patterns 218(17) and 218(20) is located proximal to the side boundary 230 of cell 204(3) (E).

In some embodiments, to help provide isolation between a first cell region corresponding to cell 204(3) (E) and an adjacent (e.g., contiguous) second cell region (not shown) disposed to the right of the side boundary 230 of the first cell region, a gap 232 is provided between the right end of each of the M0 patterns 218(17) and 218(20) and the side boundary 230 of cell 204(3) (E), relative to the X-axis. In some embodiments, the length L232 of gap 232 is L232 ≈ 1/6 CPP.

In the layout diagram 200E, the widths of the M0 patterns 218(18), 218(19), and 218(20) are substantially equal to the minimum width Lmin of the level M0, with respect to the X-axis. The minimum width Lmin represents the minimum length of the conductive segments in layer M0 in the semiconductor device, relative to typical manufacturing tolerances of the semiconductor process technology node from which the semiconductor device is produced. The minimum width Lmin is less than CPP, Lmin < CPP. In some embodiments, Lmin is based on the pitch (not shown) of the cut M0(CM0) pattern. In some embodiments, Lmin ≈ 2/3 CPP.

In some embodiments, design rule 3 is as follows: if a given MD pattern is located in the first or last MD column of cells, and if the given MD pattern overlaps with a corresponding VGD pattern, if the corresponding M0 pattern overlapping with the corresponding VGD pattern is not a PG pattern, the width (relative to the X-axis) of the corresponding M0 pattern is set to at least L2, where CPP < L2. In some embodiments, L2 ≈ 1.5 CPP.

In fig. 2E, MD patterns 210(15) and 210(18) are in the first MD column, and MD patterns 210(17) and 210(20) are in the last MD column. Each of the MD patterns 210(15), 210(17), 210(18), and 210(20) overlaps with a VD pattern, i.e., the respective VD patterns 216(17), 216(18), 216(23), and 216 (22).

In layout 200E, MD pattern 210(20) overlaps with M0 pattern 218(20), which is not a PG pattern. Therefore, design rule 3 applies to MD pattern 210 (20).

The result of applying design rule 3 to FIG. 2E is shown in FIG. 2F. Cell 204(3) (F) of layout 200F is the result of applying the method including design rule 3 to layout 200E, and more particularly to M0 pattern 218 (20). The result of applying design rule 3 to fig. 2E includes changing the M0 pattern 218(20) of fig. 2E to the M0 pattern 218 (20)' in fig. 2F. The increase in width aw of the M0 pattern 218 (20)' is shown in fig. 2F as reference numeral 234. In some embodiments, L2 represents the minimum separation distance between CM0 patterns (not shown) of corresponding semiconductor process technology nodes, relative to the X-axis. By increasing the width of the M0 pattern 218 (20)' enough to be designated as a pin pattern, layout 200F has improved M0 routing resources compared to layout 200E. In some embodiments, because designating a given M0 pattern as a pin pattern improves routability, and because floorplan 200F has one additional M0 pattern that can be designated as a pin pattern as compared to floorplan 200E, floorplan 200F is considered to have an improved M0 routing resource relative to floorplan 200E.

Layouts

300A, 300C, 300E, and 300G represent initial layouts, and according to some embodiments,

layouts

300B, 200D, 300F, and 300H represent corresponding layouts (post-process layouts) generated by one or more of the methods disclosed herein. For example, layout 300A represents an initial layout and layout 300B represents a corresponding post-method layout resulting from one or more methods disclosed herein, according to some embodiments. More specifically, element 304(1) (B) of layout diagram 300B represents that a method including a fourth design rule (design rule 4) (discussed below) has been applied to layout diagram 300A of fig. 3A, according to some embodiments. Examples of cell regions corresponding to cells 304(1), (B), 304(2), (D), 304(3), (F), and 304(4) (H) are cell region 104 of fig. 1.

The layouts 300A-300H are similar to the layouts 200A-200F of the corresponding FIGS. 2A-2F. Fig. 3A-3H follow a similar numbering convention as fig. 2A-2F. Although corresponding, some components may differ. While fig. 2A-2F use 2-series numbers, fig. 3A-3H use 3-series numbers. To help identify corresponding, but still different, components, the numbering convention uses parenthetical numbers. For example, pattern 318(1) (A) in FIG. 3A and pattern 218(11) in FIG. 2C are both M0 patterns, with similarity reflected in the common root _18 _, and differences reflected in the numbers 3_ (_) and 2_ (l), and in the brackets _ (1) (_) and (11). To help reflect differences between the corresponding initial and post-process layouts, some elements include a second parenthesis. For example, pattern 318(1) (a) in fig. 3A and pattern 318(1) (B) in fig. 3B are both M0 patterns, with the difference reflected in the second brackets _ (a) and _ (B). For the sake of brevity, the discussion will focus more on the differences between fig. 3A-3H and fig. 2A-2F rather than the similarities.

In fig. 3A, layout diagram 300A includes portions of cells 304(1) (a). The layout 300A further includes: gate patterns 312(1), 312(2), 314(1), and 314 (2); VGD pattern and 316 (1); m0 pattern 318(1) (a); and VIA0 pattern 320 (1). The fin pattern, MD pattern, and M1 pattern are omitted in fig. 2C to 2D for simplicity of explanation. In some embodiments, unit 304(1) (a) comprises: gate patterns 312(1) -312(2) and 314(1) -314 (2); VGD pattern 316 (1); and M0 pattern 318(1) (a).

In the layout diagram 300A, the VGD pattern 316(1) overlaps with the M0 pattern 318(1) (a), and the M0 pattern 318(1) (a) overlaps with the VIA0 pattern 320 (1). With respect to the layer direction, the first portion of the M0 pattern 318(1) (a) extends to the right width 336(2) of the VIA0 pattern 320 (1).

The first portion of the M0 pattern 318(1) (a) overhangs the right width 336(2) of the VIA0 pattern 320(1), and thus the width 336(2) is referred to as Overhang (OH)336 (2). In some embodiments, OH336 (), e.g., OH336 (1), OH336(2), etc., represent the minimum width (relative to the X-axis) WOH of overhang in a semiconductor device that can be produced within typical manufacturing tolerances by a corresponding semiconductor process technology node, e.g., overhang of the first VIA0 structure of a corresponding first conductive segment in layer M0, where the first VIA0 structure is represented by VIA0 pattern 320(1) and the first conductive segment in layer M0 is represented by M0 pattern 318(1) (a). In some embodiments, (≈ 0.2CPP) ≦ WOH ≦ 0.3 CPP. In some embodiments, relative to typical manufacturing tolerances of a semiconductor process technology node from which a semiconductor device is produced, WOH ≈ 0.2CPP if the minimum height Hmin (relative to the Y-axis) of the M0 segment in the semiconductor is (≈ 20nm) < Hmin. In some embodiments, WOH ≈ 0.3CPP if the minimum height Hmin of the corresponding semiconductor process technology node is (≈ 9nm) ≦ Hmin ≦ 20 nm. In some embodiments, where the M0 pattern overhangs the corresponding VIA0 pattern and the overhang portion of the M0 pattern is about OH336 (), the overhang portion is referred to as a stub portion.

With respect to the horizontal direction, the second portion of the M0 pattern 318(1) (a) extends to the left width 336(1) of the VGD pattern 316(1), and the third portion 338(1) of the M0 pattern 318(1) (a) extends to the left of the second portion of the M0 pattern 318(1) (a).

In some embodiments, design rule 4 is as follows: with respect to the X-axis, if a given M0 pattern overlaps a given VGD pattern or overlaps a given VIA0 pattern, the first and second wing portions of the given M0 pattern are (to the present extent) reduced to respective first and second stub portions, where (a) the first wing portion extends to the left of the leftmost VIA pattern (whether VG pattern or VIA0 pattern) by an amount greater than OH336 (), (B) the second wing portion extends to the right of the rightmost VIA pattern (whether VG pattern or VIA0 pattern) by an amount greater than OH336 (), (C) the first stub portion extends to the left of the leftmost VIA pattern (whether VG pattern or VIA0 pattern) and has a width substantially equal to OH336 (), and (D) the second stub portion extends to the right of the rightmost VIA pattern (either VG pattern or a0 pattern), and has a width substantially equal to OH336 (_). In some embodiments, reducing the wing portion of a given M0 pattern to the stub portion is referred to as trimming the wing portion.

In fig. 3A, the leftmost via pattern is the VGD pattern 316(1) with respect to the overhang of the M0 pattern 318(1) (a). The first wing portion of the M0 pattern 318(1) (a) corresponds to the combination of the third portion 338(1) of the M0 pattern 318(1) (a) and the second portion of the M0 pattern 318(1) (a), the second portion of the M0 pattern 318(1) (a) extending to the left width 336(1) of the VGD pattern 316 (1).

The first wing portion extends to the left of VGD pattern 316(1) by an amount greater than OH336 (2). Thus, design rule 4 applies to the first wing portion of M0 pattern 318(1) (a). In particular, the first wing portion of M0 pattern 318(1) (a) extends beyond OH336(2) by an amount equal to the width of third portion 338(1) of M0 pattern 318(1) (a).

In layout diagram 300A, the rightmost VIA pattern is VIA0 pattern 320(1), relative to the overhang of M0 pattern 318(1) (a). The second wing portion of the M0 pattern 318(1) (a) corresponds to the second portion of the M0 pattern 318(1) (a). The second wing portion of the M0 pattern 318(1) (a) extends to the right of the VIA0 pattern 320(1), but does not extend by more than the amount of OH336 (2). Thus, design rule 4 does not apply to the second wing portion of M0 pattern 318(1) (a).

The result of applying design rule 4 to FIG. 3A is shown in FIG. 3B. Cell 304(1) (B) of layout 300B is the result of applying a method including design rule 4 to layout 300A, and more specifically, to the first wing portion of M0 pattern 318(1) (a). The results of having applied design rule 4 to FIG. 3A include: the narrower (relative to the X-axis) M0 pattern 318(1) (B) has replaced the wider M0 pattern 318(1) (a). The M0 pattern 318(1) (B) is narrower than the M0 pattern 318(1) (a) because the third portion 338(1) of the M0 pattern 318(1) (a) has been removed from fig. 3A, as shown by the corresponding dashed line shape 338 (1)' in fig. 3B.

By removing the third portion 338(1) of the M0 pattern 318(1) (a), the layout 300B is less congested compared to the layout 300A. By removing third portion 338(1) of M0 pattern 318(1) (a), layout 300B has improved M0 routing resources compared to layout 300A. In some embodiments, because the M0 pattern 318(1) (B) of layout 300B is narrower than the M0 pattern 318(1) (a) of layout 300A, layout 300B is considered to have improved M0 routing resources relative to layout 300A.

With respect to fig. 3C and 3D, it should be recalled that, according to some embodiments, element 304(2) (D) of layout 300D represents that the method including design rule 4 has been applied to layout 300C of fig. 3C.

In layout diagram 300C, the leftmost VIA pattern is VIA0 pattern 316(1) relative to the overhang of M0 pattern 318(2) (C), such that the first wing portion of M0 pattern 318(2) (C) is the same as the first wing portion of M0 pattern 318(1) (a). Thus, design rule 4 applies to the first wing portion of M0 pattern 318(2) (C).

In the layout diagram 300C, the rightmost via pattern is the VGD pattern 316(1) with respect to the overhang of the M0 pattern 318(2) (C). Regarding the M0 pattern 318(2) (C), the fourth portion of the M0 pattern 318(2) (C) extends to the right width 336(3) of the VGD pattern 316(1), and the fifth portion 338(2) of the M0 pattern 318(2) (C) extends to the right of the fourth portion of the M0 pattern 318(2) (C). The second wing portion of the M0 pattern 318(2) (C) corresponds to the combination of the fifth portion 338(2) of the M0 pattern 318(2) (C) and the fourth portion of the M0 pattern 318(2) (C). The second wing portion extends to the right side of VGD pattern 316(1) by an amount greater than OH336 (3). Thus, design rule 4 applies to the second wing portion of M0 pattern 318(2) (C). In particular, the second wing of the M0 pattern 318(2) (C) extends beyond OH336 (3) by an amount equal to the width of the fifth portion 338(2) of the M0 pattern 318(2) (C).

The result of applying design rule 4 to FIG. 3C is shown in FIG. 3D. Cell 304(2) (D) of layout diagram 300D is the result of applying a method including design rule 4 to layout diagram 300D, and more specifically to the first and second wing portions of M0 pattern 318(2) (C). The results of having applied design rule 4 to FIG. 3C include: the narrower (relative to the X-axis) M0 pattern 318(2) (D) has replaced the wider M0 pattern 318(2) (C). The M0 pattern 318(2) (D) is narrower than the M0 pattern 318(2) (C) because the third portion 338(1) and fifth portion 338(2) of the M0 pattern 318(2) (C) have been removed from fig. 3C, as shown by the respective dashed shapes 338(1) 'and 338 (2)' in fig. 3D. In some embodiments, because M0 pattern 318(2) (D) of layout 300D is narrower than M0 pattern 318(2) (C) of layout 300C, layout 300D is considered to have improved M0 routing resources relative to layout 300C.

The result of applying design rule 4 to FIG. 3E is shown in FIG. 3F. Cell 304(3) (F) of layout 300F is the result of applying the method including design rule 4 to layout 300E, and more specifically, to the first wing portion of M0 pattern 318(3) (E). The results of applying design rule 4 to FIG. 3E include: the narrower (relative to the X-axis) M0 pattern 318(3) (F) has replaced the wider M0 pattern 318(3) (E). The M0 pattern 318(3) (F) is narrower than the M0 pattern 318(3) (E) because the portion 338(3) of the M0 pattern 318(3) (E) has been removed from fig. 3E, as shown by the corresponding dashed shape 338 (3)' in fig. 3F. In some embodiments, because M0 pattern 318(3) (F) of layout 300F is narrower than M0 pattern 318(3) (E) of layout 300E, layout 300F is considered to have improved M0 routing resources relative to layout 300E.

The result of applying design rule 4 to fig. 3G is shown in fig. 3H. Cell 304(4) (H) of layout diagram 300H is the result of applying a method including design rule 4 to layout diagram 300G, and more particularly to the first and second wing portions of M0 pattern 318(4) (G). The results of applying design rule 4 to FIG. 3G include: the narrower (relative to the X-axis) M0 pattern 318(4) (H) has replaced the wider M0 pattern 318(4) (G). The M0 pattern 318(4) (H) is narrower than the M0 pattern 318(4) (G) because the portion 338(3) and the portion 338(4) of the M0 pattern 318(4) (G) have been removed from fig. 3G, as shown by the corresponding dashed line shapes 338(3) 'and 338 (4)' in fig. 3H. In some embodiments, because M0 pattern 318(4) (H) of layout 300H is narrower than M0 pattern 318(4) (G) of layout 300G, layout 300H is considered to have improved M0 routing resources relative to layout 300G.

Fig. 4A-4C are respective cross-sectional views 400A-400C of respective portions of respective semiconductor devices according to some embodiments.

More specifically, cross-sectional views 400A-400B illustrate corresponding portions of a semiconductor device based on layout diagram 200A of FIG. 2A. Cross-sectional views 400C-400D illustrate corresponding portions of a semiconductor device based on layout diagram 200 of fig. 2B. Portions of the respective cross-sectional views 400C-400D and the semiconductor device including the same are respective examples of the cell region 104 and the semiconductor device 100 of fig. 1.

Fig. 4A to 4C assume an orthogonal XYZ coordinate system, in which the X, Y and Z axes represent respective first, second and third directions. In some embodiments, the first, second, and third directions correspond to an orthogonal coordinate system different from the XYZ coordinate system.

The cross-sectional views 400A-400D follow a similar numbering convention as fig. 2A-2F. While fig. 2A-2F use 2-series numbers, fig. 4A-4D use 4-series numbers. For example, fin 408N of fig. 4A corresponds to fin pattern 208N of fig. 2A.

In fig. 4A, a portion corresponding to cross-sectional view 400A includes transistor layer 452, M0 metallization layer located above transistor layer 452; a V0 layer 456 located over the M0 layer 454; an M1 layer 458 above the V0 layer 456.

The transistor layer 452 includes: a fin 408N; an interlayer dielectric (ILD)460 in a sublayer corresponding to fin 408N; MD structure 410(2) on fin 408N; a gate structure 412(2) on fin 408N; ILD 462 in sub-layers corresponding to MD structure 410(2) and gate structure 412 (2); a VGD structure 416(3) on the MD structure 410 (2); and ILD 464 in a sublayer corresponding to VGD structure 416 (3). The M0 layer 454 includes a conductive M0 segment 418(2) overlying the VGD structure 416(3), and an ILD 466. The V0 layer 456 includes VIA0 structures 420(2) and ILD468 over the M0 segment 418 (2). The M1 layer 458 includes conductive M1 segments 422(2) and 422(3), which are overlappingly located on V0420 (2), and ILD 450.

The long axis of the fin 408N extends in a direction substantially parallel to the X-axis. The long axes of the MD structures 410(2) and the gate structures 412(2) extend in the Y-direction (not shown in fig. 4A). With respect to the Z-axis, MD structures 410(2) and gate structures 412(2) are disposed on fin 408N.

VGD structures, such as VGD structure 410(2), are contact structures that electrically couple the upper overlapping conductive segment (e.g., M0 segment 418(2)) in layer M0, and the lower overlapping MD structure, such as MD structure 410(2), or the lower overlapping gate structure. In some embodiments, VGD is an acronym for the phrase via-gate or via-source/drain.

In fig. 4B, with respect to the portion corresponding to cross-sectional view 400B, transistor layer 452 includes: an interlayer dielectric (ILD)460 in a sublayer corresponding to fin 408N (not shown in fig. 4B); gate structures 412(1) and 412 (2); ILD 462; VGD structure 416(2) on gate structure 412 (1); and ILD 464. The M0 layer 454 includes conductive M0 segments 418(4) (which are overlappingly located on VGD structures 416 (2)) and 418(5), and ILD 466. The V0 layer 456 includes VIA0 structure 420(1) and ILD468 over the M0 segment 418 (4). The M1 layer 458 includes conductive M1 segments 422(1) (which overlies VIA0 structure 420 (1)), 422(2), and 422(3), and ILD 450.

In fig. 4C, some structures have been removed as compared to fig. 4A. Specifically, the M1 pattern 422(2) in fig. 4A has been removed in fig. 4C, as shown by the corresponding dashed line shape 422 (2)'.

In fig. 4D, some structures have been removed as compared to fig. 4B. Specifically, VIA0 pattern 420(1) in fig. 4B has been removed in fig. 4D, as shown by the corresponding dashed line shape 420 (1)'. Also, the M1 patterns 422(1) and 222(2) in fig. 4A have been removed in fig. 4D, as shown by the respective dashed line shapes 422(1) 'and 422 (2)'.

Fig. 5 is a flow chart of a method 500 of fabricating a semiconductor device according to some embodiments.

Examples of semiconductor devices that may be fabricated according to method 500 include semiconductor device 100 of fig. 1.

In FIG. 5, the method 500 includes blocks 502-504. At block 502, a floorplan is generated that also includes an arrangement of refinement M0 routing resources. Examples of semiconductor devices that include cell regions with improved M0 routing resources corresponding to the layout map generated by method 500 include semiconductor device 100 of fig. 1. Block 502 is discussed in more detail below with reference to fig. 6A. From block 502, flow proceeds to block 504.

At block 504, based on the layout, (a) at least one of one or more lithographic exposures is performed or (B) one or more semiconductor masks are fabricated or (C) one or more components in a layer of a semiconductor device are fabricated. See discussion of fig. 8 below.

Fig. 6A is a flow diagram of a method of generating a layout diagram according to some embodiments.

More specifically, the method of fig. 6A illustrates block 502 of fig. 5 in greater detail, in accordance with one or more embodiments.

Examples of layouts that may be generated according to the method of FIG. 6A include the layouts disclosed herein, and the like. In some embodiments, the layout and its corresponding version are stored on a non-transitory computer readable medium, e.g., in computer readable medium 704 of fig. 7 (discussed below) as layout 708. According to some embodiments, the method of fig. 6A may be implemented, for example, using EDA system 700 (fig. 7, discussed below). Examples of semiconductor devices that may be fabricated based on the layout generated according to the method of fig. 6A include the semiconductor device 100 of fig. 1, as well as semiconductor devices based on the

layouts

200B, 200D, 200F, 300B, 300D, 300F, 300G, and so forth.

In FIG. 6A, block 502 includes block 602 and block 606. At block 602, a candidate pattern is selected, which is the first conductive pattern in the M _2nd level or the M _1st level of the layout. In some embodiments, the M _2nd level is the M0 level, and the M _1st level is the M0 level. Examples of patterns in the M _2nd level include the M1 patterns 222(1), 222(2), and 222(4) in the M1 level of fig. 2A, and so on. Examples of patterns in the M _1st level include M0 patterns 218(12) and 218(14) in the M0 level of fig. 2C, M0 pattern 218(20) in the M0 level of fig. 2F, M0 pattern 318(1) in the M0 level of fig. 3A, M0 pattern 318(2) in the M0 level of fig. 3C (C), M0 pattern 318(3) in the M0 level of fig. 3E (E), M0 pattern 318(4) in the M0 level of fig. 3G (G), and the like. From block 602, flow proceeds to block 604.

At block 604, it is determined that the candidate pattern satisfies one or more criteria. Examples of criteria are the criteria of the

respective design rule

1, 2, 3 or 4, etc. From block 604, flow proceeds to block 606.

At block 606, the size of the candidate pattern is changed. In some embodiments, the size of the candidate pattern is changed by decreasing, for example, as shown in fig. 3B, 3D, 3F, or 3H. In some embodiments, the size of the candidate pattern is changed by removing the candidate pattern from the layout, such as fig. 2B, 2D, etc. In some embodiments, the size of the candidate pattern is changed by increasing, such as fig. 2F or the like.

FIG. 6B is a flow diagram of a method of generating a map, according to some embodiments.

More specifically, the method of fig. 6B illustrates

blocks

604 and 606 of fig. 6A, respectively, in greater detail in accordance with one or more embodiments. The context of FIG. 6B is design rule 1.

An example of a layout that may be generated according to the method of FIG. 6B is layout 200B, and so forth. Examples of semiconductor devices that may be manufactured based on the layout generated according to the method of fig. 6B include the semiconductor device 100 of fig. 1, a semiconductor device based on the layout 200B, and so on.

In FIG. 6B, block 604 includes

blocks

610 and 612. In blocks 610-612, the candidate pattern is the first M _2nd pattern. At block 610, it is determined that the first M _2nd pattern is designated as a pin pattern. Examples of M _2nd patterns designated as pin patterns include M1 patterns 222(1), 222(2), and 222 (4).

In some embodiments, the relationship of a given M1 pattern relative to the patterns above is analyzed to determine whether a given M1 will be designated as a pin pattern. In some embodiments, the state designated as a pin pattern is an attribute associated with the given M1 pattern, such that checking the attribute of the given M1 pattern reveals whether the given M1 pattern is a pin pattern. From block 610, flow proceeds to block 612.

At block 612, it is determined that the first VIA pattern in the first level of interconnection (the first VIA _1st pattern) is the only VIA _1st pattern that overlaps the first M _2nd pattern. Continuing with the example of M1 pattern 222(1) as a lead pattern, VIA0 pattern 222(1) is the only VIA0 pattern that overlaps with M1 pattern 222 (2). From block 612, flow exits block 604 and enters block 606.

In fig. 6B, block 606 includes block 620. At block 620, the size of at least the candidate pattern is reduced. Block 620 includes block 622. At block 622, the candidate pattern is removed from the map. An example of removing a candidate pattern is removing M1 pattern 222(1) from fig. 2B, as shown by the corresponding dashed shape 222 (1)' in fig. 2B. In some embodiments, the corresponding VIA pattern is also removed, e.g., VIA0 pattern 220(1) as shown by the corresponding dashed shape 220 (1)' in fig. 2B.

In some embodiments, after removing the candidate pattern, the method further comprises designating a respective underlying first pattern (first M _1st pattern) in the first level as a pin pattern. An example of replacing the M _1st pattern as the lead pattern is to designate the M0 pattern 218(4) of fig. 2B as the lead pattern after removing the corresponding M1 pattern 222 (1).

Fig. 6C is a flow diagram of a method of generating a layout diagram according to some embodiments.

More specifically, the method of fig. 6C illustrates

blocks

604 and 606 of fig. 6A, respectively, in greater detail, in accordance with one or more embodiments. The context of fig. 6C is design rule 2.

An example of a map that may be generated according to the method of FIG. 6C is map 200D, or the like. Examples of semiconductor devices that may be manufactured based on the layout generated according to the method of fig. 6C include semiconductor device 100 of fig. 1, a semiconductor device based on layout 200D, and so forth.

In FIG. 6C, block 604 includes

blocks

630 and 632. In blocks 630-632, the candidate pattern is the first M _1st pattern. At block 630, it is determined that the first M _1st pattern does not overlap at least a first VIA pattern (first VIA _1st pattern) in the VIA _1st level. Examples of M _1st patterns that do not overlap with at least the first VIA _1st pattern include M0 patterns 218(12) and 218(14) of fig. 2C, and so on. From block 630, flow proceeds to block 632.

At block 632, it is determined that the first M _1st pattern does not overlap with at least the first VIA _2nd pattern. Examples of M _1st patterns that do not at least overlap with the first VIA _1st pattern include M0 patterns 218(12) and 218(14) of fig. 2C, and so on.

In fig. 6C, block 606 includes block 640. At block 640, the size of at least the candidate pattern is reduced. Block 640 includes block 642. At block 642, the candidate pattern is removed from the map. An example of removing a candidate pattern is removing M0 pattern 218(12) from fig. 2C, as shown by the corresponding dashed shape 218 (12)' in fig. 2D.

Fig. 6D is a flow diagram of a method of generating a map, according to some embodiments.

More specifically, the methods of fig. 6C and 6D, respectively, illustrate

blocks

604 and 606 of fig. 6A in greater detail, according to one or more embodiments. The context of fig. 6C is design rule 4.

An example of a map that may be generated according to the method of FIG. 6D is map 200F, or the like. Examples of semiconductor devices that may be manufactured based on the layout generated according to the method of fig. 6D include the semiconductor device 100 of fig. 1, a semiconductor device based on the layout 200F, and so on.

In fig. 6D, block 604 includes block 650 and block 652. In blocks 650-652, the candidate pattern is the first M _1st pattern. As shown in fig. 6D, flow proceeds to block 650 or block 652. At block 650, it is determined that the first M _1st pattern overlaps at least the first VIA pattern in the VIA _1st level (the first VIA _1st pattern). Examples of M _1st patterns that overlap with at least the first VIA _1st pattern include M0 patterns 318(1) (a), 318(2) (C), 318(3) (E), 318(4) (G), etc. of fig. 3A, 3C, 3E, and 3G, respectively.

At block 652, it is determined that the first M _1st pattern overlaps at least a first VIA pattern (a first VIA _2nd pattern) in the VIA _2nd level. Examples of M _1st patterns that overlap by at least the first VIA _2nd pattern include M0 patterns 318(1) (a) and 318(3) (E) and 318(4) (G), etc., of respective fig. 3A and 3E.

In fig. 6D, block 606 includes block 660. At block 660, the size of at least the candidate pattern is reduced. Block 660 includes block 662. At block 662, the dimensions of the wing portions of the candidate pattern are trimmed to produce smaller stub portions. Examples of wing portions and corresponding wing portions are as follows. An example of a wing portion is the first wing portion of the M0 pattern 318(1) (a), which corresponds to the combination of the third portion 338(1) of the M0 pattern 318(1) (a) and the second portion of the M0 pattern 318(1) (a), which in fig. 3A extends to the left width 336(1) of the VGD pattern 316(1) of the second portion of the M0 pattern 318(1) (a). An example of a corresponding stub portion is a second portion of the M0 pattern 318(1) (B), which in fig. 3B extends to the left width 336(1) of the VGD pattern 316 (1).

Fig. 6E is a flow diagram of a method of generating a layout diagram according to some embodiments.

More specifically, in accordance with one or more embodiments, the method of fig. 6E illustrates

blocks

604 and 606 of fig. 6A, respectively, in greater detail. The context of fig. 6E is design rule 3.

An example of a map that may be generated according to the method of FIG. 6E is map 200F, or the like. Examples of semiconductor devices that may be manufactured based on the layout generated according to the method of fig. 6E include semiconductor device 100 of fig. 1, a semiconductor device based on layout 200F, and so forth.

In FIG. 6E, block 604 includes

blocks

670 and 676. In blocks 670-676, the candidate pattern is the first M _1st pattern. At block 670, it is determined that the first MD pattern is located in the first or last MD column. Examples of MD patterns located in the first MD column include MD patterns 210(15) and 210(18) of fig. 2E, and so on. Examples of MD patterns in the last MD column include MD patterns 210(17) and 210(20) of fig. 2E, and so on. From block 670, flow proceeds to block 672.

At block 672, it is determined that the first MD pattern overlaps the first VIA pattern in the VIA _1st level (the first VIA _1st pattern). Examples of MD patterns that overlap with the first VIA _1st pattern include MD patterns 210(15), 210(17), 210(18), 210(20), etc. of fig. 2E. From block 672, flow proceeds to block 674.

At block 674, it is determined that the first VIA _1st pattern also overlaps the first M _1st pattern. Examples of the first VIA _1st pattern also overlapping the first M _1st pattern include VIA0 patterns 216(17), 216(18), 216(23), 216(22), and so on, of fig. 2E. From block 674, flow proceeds to block 676.

At block 676, it is determined that the first M _1st pattern is also not a PG pattern. Examples of the first M _1st pattern that is not a PG pattern are M0 pattern 218(20) of FIG. 2E, and so forth. From block 676, flow proceeds to block 678.

At block 678, it is determined that the length of the M _1st pattern is less than the first reference distance. An example of the first reference distance is L2 (see fig. 2E to 2F).

In fig. 6E, block 606 includes block 680. At block 680, the size of the candidate pattern is increased. Block 680 includes block 682. At block 682, the size of the candidate pattern is increased to be at least substantially equal to the first reference distance. An example of a candidate pattern of increased size is the M0 pattern 218 (20)' of fig. 2F that has been increased in size by an amount aw, as indicated by reference numeral 234 in fig. 2F.

Fig. 7 is a block diagram of an Electronic Design Automation (EDA) system 700 according to some embodiments.

In some embodiments, the EDA system 700 includes an Automated Place and Route (APR) system. According to some embodiments, the methods of generating PG layouts described herein, for example, using EDA systems 700, may be implemented in accordance with one or more embodiments.

In some embodiments, the EDA system 700 is a general purpose computing device that includes a hardware processor 702 and a non-transitory computer-readable storage medium 704. The storage medium 704 or the like is encoded with, i.e., stores, computer program code 706, i.e., a set of executable instructions. The hardware processor 702 executing the instructions 706 represents (at least in part) an EDA tool that implements part or all of a method according to an embodiment, such as the methods described herein (hereinafter, referred to as processes and/or methods) according to one or more embodiments.

The processor 702 is electrically coupled to the computer-readable storage medium 704 via a bus 708. The processor 702 is also electrically coupled to the I/O interface 710 via bus 7 line 08. A network interface 712 is also electrically connected to the processor 702 via the bus 708. The network interface 712 is connected to a network 714, so that the processor 702 and the computer-readable storage medium 704 can be connected to external elements via the network 714. The processor 702 is configured to execute computer program code 706 encoded in a computer-readable storage medium 704 to make the system 700 available to perform some or all of the mentioned processes and/or methods. In one or more embodiments, processor 702 is a Central Processing Unit (CPU), multiprocessor, distributed processing system, Application Specific Integrated Circuit (ASIC), and/or suitable processing unit.

In one or more embodiments, the computer-readable storage medium 704 is an electronic, magnetic, optical, electromagnetic, infrared, and/or semiconductor system (or apparatus or device). The computer-readable storage medium 704 includes, for example, a semiconductor or solid state memory, magnetic tape, a removable computer diskette, a Random Access Memory (RAM), a read-only memory (ROM), a rigid magnetic disk and/or an optical disk. In one or more embodiments using optical disks, the computer-readable storage medium 704 includes a compact disk-read only memory (CD-ROM), a compact disk-read/write (CD-R/W), and/or a Digital Video Disk (DVD).

In one or more embodiments, the storage medium 704 stores computer program code (instructions) 706 configured to make the system 700 (where such execution represents (at least in part) an EDA tool) available to implement some or all of the mentioned processes and/or methods. In one or more embodiments, the storage medium 704 also stores information that facilitates implementing some or all of the referenced processes and/or methods. In one or more embodiments, the storage medium 704 stores a standard cell library 707 including such standard cells as disclosed herein and one or more layout maps 708 such as disclosed herein.

The EDA system 700 includes an I/O interface 710. I/O interface 710 couples to external circuitry. In one or more embodiments, the I/O interface 710 includes a keyboard, keypad, mouse, trackball, trackpad, touch screen, and/or cursor direction keys for communicating information and commands to the processor 702.

The EDA system 700 also includes a network interface 712 coupled to the processor 702. Network interface 712 allows system 700 to communicate with a network 714, where one or more other computer systems are connected to network 714. Network interface 712 includes a wireless network interface, such as BLUETOOTH, WIFI, WIMAX, GPRS, or WCDMA; or a wired network interface such as ETHERNET, USB, or IEEE-1364. In one or more embodiments, some or all of the mentioned processes and/or methods are implemented in two or more systems 700.

System 700 is configured to receive information via I/O interface 710. Information received via I/O interface 710 may include one or more of instructions, data, design rules, libraries of standard cells, and/or other parameters for processing by processor 702. Information is transferred to the processor 702 via the bus 708. The EDA system 700 is configured to receive information related to a UI through the I/O interface 710. This information is stored in the computer-readable medium 704 as a User Interface (UI) 742.

In some embodiments, some or all of the mentioned processes and/or methods are implemented as stand-alone software applications for execution by a processor. In some embodiments, some or all of the referenced processes and/or methods are implemented as software applications as part of an add-on software application. In some embodiments, parts of or methods of the processes and/or methods mentionedAll implemented as plug-ins to the software application. In some embodiments, at least one of the mentioned processes and/or methods is implemented as a software application that is part of an EDA tool. In some embodiments, some or all of the referenced processes and/or methods are implemented as software applications used by the EDA system 700. In some embodiments, a user is used such as available

A tool (from CADENCE DESIGN SYSTEMS, Inc) or other suitable layout generation tool generates a layout that includes standard cells.

In some embodiments, the process is implemented as a function of a program stored in a non-transitory computer-readable recording medium. Examples of the non-transitory computer-readable recording medium include, but are not limited to, external/removable and/or internal/built-in memories or memory units, for example, one or more of an optical disk (such as a DVD), a magnetic disk (such as a hard disk), a semiconductor memory (such as a ROM, a RAM, a memory card), and the like.

Fig. 8 is a block diagram of an Integrated Circuit (IC) manufacturing system 800 and its associated IC manufacturing flow, according to some embodiments. In some embodiments, at least one of (a) one or more semiconductor masks or (B) at least one component in a layer of a semiconductor integrated circuit is fabricated using the fabrication system 800 based on a layout map.

In fig. 8, IC manufacturing system 800 includes entities that interact with each other during design, development, and manufacturing cycles, such as design room 820, mask room 830, and IC manufacturer/manufacturer ("fab") 850 and/or services related to manufacturing IC devices 860. The entities in system 800 are connected by a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an intranet and the internet. The communication network includes wired and/or wireless communication channels. Each entity interacts with and provides services to and/or receives services from one or more other entities. In some embodiments, two or more of the design chamber 820, the mask chamber 830, and the IC fab 850 are owned by a single larger company. In some embodiments, two or more of the design chamber 820, the mask chamber 830, and the IC fab 850 coexist in a common facility and use common resources.

A design room (or design team) 820 generates an IC design layout 822. IC design layout 822 includes various geometric patterns designed for IC device 860. The geometric pattern corresponds to the pattern of the metal, oxide or semiconductor layers that make up the various components of the IC device 860 to be fabricated. The various layers combine to form various IC components. For example, portions of IC design layout 822 include various IC components formed in a semiconductor substrate (such as a silicon wafer), such as active regions, gate electrodes, sources and drains, metal lines or vias for inter-level interconnects, and openings for bond pads; and various material layers disposed on the semiconductor substrate. The design room 820 implements the appropriate design procedures to form the IC design layout 822. The design program includes one or more of a logical design, a physical design, or a place and route. The IC design layout 822 is presented in one or more data files with information of geometric patterns. For example, the IC design layout 822 may be represented in a GDSII file format or a DFII file format.

Mask chamber 830 includes data preparation 832 and mask fabrication 844. Mask chamber 830 uses IC design layout 822 to fabricate one or more masks 845 for fabricating the various layers of IC device 860 according to IC design layout 822. The mask chamber 830 performs mask data preparation 832 in which the IC design layout 822 is converted to a representative data file ("RDF"). The mask data preparation 832 provides the RDF to the mask manufacturer 844. Mask making 844 includes a mask writer. The mask writer converts the RDF into an image on a substrate, such as mask (reticle) 845 or semiconductor wafer 853. Mask data preparation 832 manipulates design layout 822 to conform to the specific characteristics of a mask writer and/or the requirements of IC fab 850. In fig. 8, mask data preparation 832 and mask fabrication 844 are shown as separate elements. In some embodiments, mask data preparation 832 and mask fabrication 844 may be collectively referred to as mask data preparation.

In some embodiments, mask data preparation 832 includes Optical Proximity Correction (OPC), which uses lithographic enhancement techniques to compensate for image errors such as may be caused by diffraction, interference, other process effects, and the like. The OPC adjusts the IC design layout 822. In some embodiments, the mask data preparation 832 includes further Resolution Enhancement Techniques (RET), such as off-axis illumination, sub-resolution assist features, phase shifting masks, other suitable techniques, or the like or combinations thereof. In some embodiments, Inverse Lithography (ILT) is also used, which treats OPC as an inverse imaging problem.

In some embodiments, the mask data preparation 832 includes a Mask Rule Checker (MRC) that checks the IC design layout 822 that has undergone the process in OPC with a set of mask creation rules that include specific geometric and/or connection constraints to ensure sufficient margin to account for variability in the semiconductor manufacturing process, etc. In some embodiments, the MRC modifies the IC design layout 822 to compensate for constraints during mask manufacturing 844, which may undo part of the modification of the OPC implementation to meet mask creation rules.

In some embodiments, mask data preparation 832 includes a Lithography Process Check (LPC) that simulates the processing to be performed by IC fab 850 to fabricate IC device 860. The LPC models the process based on the IC design layout 822 to create a simulated fabricated device such as IC device 860. The process parameters in the LPC simulation may include parameters associated with individual processes of the IC fabrication cycle, parameters associated with the tool used to fabricate the IC, and/or other aspects of the fabrication process. LPC takes into account various factors such as aerial image contrast, depth of focus ("DOF"), mask error enhancement factor ("MEEF"), other suitable factors, and the like, or combinations thereof. In some embodiments, after creating a simulated fabricated device by LPC, if the shapes of the simulated devices are not close enough to meet the design rules, OPC and/or MRC will be repeated to further refine the IC design layout 822.

It should be appreciated that the above description of mask data preparation 832 has been simplified for the sake of brevity. In some embodiments, data preparation 832 includes additional features such as Logic Operations (LOPs) to modify IC design layout 822 according to manufacturing rules. Further, the processes applied to the IC design layout 822 during the data preparation 832 may be performed in a variety of different orders.

After mask data preparation 832 and during mask fabrication 844, mask 845 or mask set 845 is fabricated based on modified IC design layout 822. In some embodiments, mask fabrication 844 includes performing one or more lithographic exposures based on the IC design layout 822. In some embodiments, an e-beam or multiple e-beam mechanism is used to pattern on mask (photomask or reticle) 845 based on modified IC design layout 822. Various techniques may be employed to form mask 845. In some embodiments, mask 845 is formed using a binary technique. In some embodiments, the mask pattern includes opaque regions and transparent regions. A radiation beam, such as an Ultraviolet (UV) beam, used to expose a layer of image sensitive material (e.g., photoresist) that has been coated on the wafer is blocked by the opaque regions and passes through the transparent regions. In one example, the binary mask version of mask 845 includes a transparent substrate (e.g., quartz glass) and an opaque material (e.g., chrome) coated in opaque regions of the binary mask. In another example, mask 845 is formed using a phase-shift technique. In a Phase Shift Mask (PSM) version of mask 845, various features in the pattern formed on the phase shift mask are configured to have appropriate phase differences to improve resolution and imaging quality. In various examples, the phase shift mask may be an attenuated PSM or an alternating PSM. The resulting mask is used in various processes by mask making 844. Such masks may be used, for example, in ion implantation processes to form various doped regions in semiconductor wafer 853, in etching processes to form various etched regions in semiconductor wafer 853, and/or in other suitable processes.

IC fab 850 includes wafer fabrication 852. IC fab 850 is an IC fabrication facility that includes one or more fabrication facilities for fabricating a variety of different IC products. In some embodiments, IC fab 850 is a semiconductor foundry. For example, there may be a manufacturing facility for front end of line (FEOL) manufacturing of a plurality of IC products, while a second manufacturing facility may provide back end of line (BEOL) manufacturing for interconnection and packaging of IC products, and a third manufacturing facility may provide other services for a foundry.

IC fab 850 uses mask (or masks) 845, produced by mask chamber 830, to fabricate IC device 860. Thus, IC foundry 850 uses, at least indirectly, IC design layout 822 to fabricate IC device 860. In some embodiments, semiconductor wafer 853 is fabricated by IC fab 850 using mask (or masks) 845 to form IC device 860. In some embodiments, IC fabrication includes performing one or more lithographic exposures based at least indirectly on the IC design layout 822. Semiconductor wafer 853 comprises a silicon substrate or other suitable substrate having a layer of material formed thereon. The semiconductor wafer 853 also includes one or more of various doped regions, dielectric features, multilayer interconnects, etc. (formed in subsequent fabrication steps).

For example, details regarding Integrated Circuit (IC) manufacturing systems (e.g., system 800 of fig. 8) and their associated IC manufacturing flows are found in the following patents: united states patent number 9,256,709 issued on 9/2/2016, united states patent number 20150278429 issued on 1/10/2015, united states patent number 20140040838 issued on 6/2/2014, and united states patent number 7,260,442 issued on 21/8/2007, each of which is incorporated herein by reference in its entirety.

In an embodiment, a method (of manufacturing a semiconductor device) includes generating a layout (for a layout stored on a non-transitory computer readable medium, the semiconductor device based on the layout including a first metallization level corresponding to a first metallization layer and an overlying second metallization layer in the semiconductor device and a first interconnect layer therebetween and an overlying second metallization level (respective M _1st and M _2nd levels) and a first interconnect level therebetween (VIA _1st level)) comprising: selecting a candidate pattern in the layout, the candidate pattern being a first conductive pattern in an M _2nd level (first M _2nd pattern) or a first conductive pattern in an M _1st level (first M _1st pattern); determining that the candidate pattern satisfies one or more criteria; and at least reducing the size of the candidate pattern to thereby modify the layout. In an embodiment, the layout comprises a first metallization level and an upper second metallization level (respective M _1st and M _2nd levels) corresponding to a first metallization layer and an upper second metallization layer in the semiconductor device and a first interconnect level between them (VIA _1st level); and the candidate pattern is the first M _2nd pattern; determining that the candidate pattern satisfies one or more criteria includes: determining that the first M _2nd pattern is designated as a pin pattern; determining that a first VIA pattern (a first VIA _1st pattern) in a first interconnect level is the only VIA _1st pattern that overlaps the first M _2nd pattern; and reducing at least the size of the candidate pattern comprises: the first M _2nd pattern is removed from the layout. In an embodiment, generating the layout further comprises: the respective lower first pattern (first M _1st pattern) in the first level is designated as a lead pattern. In an embodiment, the first M _1st pattern is designated as a pin pattern because there are at least first and second allowed upper locations for the first VIA _1st pattern in the first VIA _1st interconnect level where at least the first M _2nd pattern and the second M _2nd pattern in the M _2nd level can be correspondingly positioned to overlap the first VIA _1st pattern; or the M _2nd pattern is designated as a lead pattern, because there are at least first and second allowed upper locations for the respective first VIA pattern (first VIA _2nd pattern) in the second interconnect level (VIA _2nd level), where at least the respective first and second conductive patterns (first and second M _3rd patterns) in the third metallization level (M _3rd) can be positioned to overlap the first VIA _2nd pattern. In an embodiment, the layout further includes a second interconnect level (VIA _2nd level) located above the first M _1st level and corresponding to a second interconnect layer located above the first interconnect layer in the semiconductor device, and the candidate pattern is a first M _1st pattern; determining that the candidate pattern satisfies one or more criteria includes: a first sub-method, comprising: determining that the first M _1st pattern does not overlap with at least a first VIA pattern (first VIA _1st pattern) in the VIA _1st level; and determining that the first M _1st pattern does not overlap with at least a first VIA pattern (a first VIA _2nd pattern) in the VIA _2nd level; or the second sub-method comprises: determining that the first M _1st pattern overlaps with at least a first VIA pattern (a first VIA _1st pattern) in a VIA _1st level with respect to a first direction; or determining that the first M _1st pattern overlaps with at least a first VIA pattern (a first VIA _2nd pattern) in the VIA _2nd level with respect to the first direction; in the context of the first sub-method, reducing at least the size of the candidate pattern comprises: removing the M _1st pattern from the layout; and in the context of a second sub-method, reducing at least the size of the candidate pattern comprises: trimming the first wing portion of the first M _1st pattern to produce a smaller first stub portion; and wherein, with respect to the first direction, at least one of the first VIA _1st pattern or the first VIA _2nd pattern is present such that the first wing portion is located between the first end of the first M _1st pattern and the first VIA _1st pattern or the first VIA _2nd pattern, and there is no other VIA _1st or VIA _2nd pattern that overlaps with or above the first wing portion, respectively. In an embodiment, the layout diagram further includes a transistor level corresponding to a transistor layer in the semiconductor device; and there is no metallization level between the M _1st level and the transistor layer. In an embodiment, the method further comprises: based on the layout: (A) performing one or more lithographic exposures; (B) fabricating one or more semiconductor masks; or (C) fabricating at least one component in a layer of the semiconductor integrated circuit.

In an embodiment, a system (for manufacturing a semiconductor device) comprises at least one processor and at least one memory including computer program code for one or more programs, the at least one memory, the computer program code, and the at least one processor configured to cause the system to perform (for a layout stored on a non-transitory computer readable medium, the semiconductor device is based on a layout comprising a first metallization level corresponding to a first metallization layer and an upper second metallization layer in the semiconductor device and a first interconnect layer therebetween and an upper second metallization level (respective M _1st and M _2nd levels) and a first interconnect level therebetween (VIA _1st level)) generating the layout comprising: selecting a candidate pattern in the layout, the candidate pattern being a first conductive pattern in an M _2nd level (a first M _2nd pattern) or a first conductive pattern in an M _1st level (a first M _1st pattern); and determining that the candidate pattern satisfies one or more criteria; and changing the size of the candidate pattern, thereby modifying the layout; and wherein the layout diagram further includes transistor layers corresponding to transistor levels in the semiconductor device; and there is no metallization level between the M _1st level and the transistor layer. In an embodiment, the layout comprises a first metallization level and an upper second metallization level (respective M _1st and M _2nd levels) corresponding to a first metallization layer and an upper second metallization layer in the semiconductor device and a first interconnect level between them (VIA _1st level); and the candidate pattern is an M _2nd pattern; determining that the candidate pattern satisfies one or more criteria includes: determining that the M _2nd pattern is designated as a pin pattern; determining that a first VIA pattern (first VIA _1st pattern) in a first level is the only VIA _1st pattern that overlaps the first M _2nd pattern; changing the size of the candidate pattern includes: removing the first M _2nd pattern from the layout; and generating the layout further comprises: the corresponding lower first pattern (first M _1st pattern) in the first hierarchy is designated as a lead pattern. In an embodiment, the M _2nd pattern is specified as a pin pattern because there are at least first and second allowed upper locations for the first VIA _1st pattern in the VIA _1st interconnect level where at least the first M _2nd pattern and the second M _2nd pattern in the M _2nd level can be positioned accordingly to overlap the first VIA _1st pattern; or the M _2nd pattern is designated as a lead pattern, because there are at least first and second allowed upper locations for the respective first VIA pattern (first VIA _2nd pattern) in the second interconnect level (VIA _2nd level), where at least the first and second conductive patterns (first and second M _3rd patterns) in the third metallization level (M _3rd) are correspondingly positioned to overlap the first VIA _2nd pattern. In an embodiment, the layout further comprises a second interconnect level (VIA _2nd level) located above the first M _1st level and corresponding to a second interconnect layer in the semiconductor device located above the first metallization layer, and the candidate pattern is an M _1st pattern; determining that the candidate pattern satisfies one or more criteria includes: a first sub-method, comprising: determining that the first M _1st pattern does not overlap with at least a first VIA pattern (first VIA _1st pattern) in the VIA _1st level; and determining that the first M _1st pattern does not overlap with at least a first VIA pattern (a first VIA _2nd pattern) in the VIA _2nd level; or a second sub-method, comprising: determining that the first M _1st pattern overlaps at least the first VIA pattern in the VIA _1st level (first VIA _1st pattern) or the first M _1st pattern overlaps at least the first VIA pattern in the VIA _2nd level (first VIA _2nd pattern), with respect to the first direction; in the context of the first sub-method, varying the size of the candidate pattern comprises: removing the M _1st pattern from the layout; in the context of the second sub-method, varying the size of the candidate pattern comprises: trimming the first wing portions of the first M _1st pattern to produce correspondingly smaller first stub portions; and wherein, with respect to the first direction, there is at least one of the first VIA _1st pattern or the first VIA _2nd pattern such that the first wing portion is between the first end of the first M _1st pattern and the first VIA _1st pattern or the first VIA _2nd pattern, there being no other VIA _1st or VIA _2nd pattern that overlaps up or down with the first wing portion, respectively. In an embodiment, the layout diagram further includes a transistor level corresponding to a transistor layer in the semiconductor device; and there is no metallization level between the M _1st layer and the transistor layer. In an embodiment, the system further comprises: at least one of: a masking device configured to manufacture one or more semiconductor masks based on the layout; alternatively, a manufacturing apparatus is configured to manufacture at least one component in a layer of a semiconductor integrated circuit based on a layout. In an embodiment, the mask apparatus is further configured to, as an aspect involved in the manufacture of the one or more semiconductor masks, perform one or more lithographic exposures based on the layout map; alternatively, the manufacturing apparatus is further configured to include an aspect in the manufacture of at least one component in a layer of the semiconductor integrated circuit to perform one or more lithographic exposures based on the layout.

In an embodiment, a method (of manufacturing a semiconductor device) includes generating a layout (for a layout stored on a non-transitory computer readable medium, the semiconductor device based on the layout including a first metallization level corresponding to a first metallization layer and an overlying second metallization layer in the semiconductor device and a first interconnect layer therebetween and an overlying second metallization level (respective M _1st and M _2nd levels) and a first interconnect level therebetween (VIA _1st level)) comprising: selecting a candidate pattern in the layout, the candidate pattern being a first conductive pattern (first M _1st pattern) in the M _1st level; determining that the candidate pattern satisfies one or more criteria; and increasing the size of the candidate pattern to modify the layout. In an embodiment, the layout diagram further includes a transistor level corresponding to a transistor layer in the semiconductor device; the cells of the layout are organized into MD columns, the MD columns extending along a first direction; determining that the candidate pattern satisfies the one or more criteria for first and last MD columns located near first and second boundaries of the cell relative to a second direction substantially perpendicular to the first direction comprises: determining that a first metal-drain/source (MD) pattern in a transistor level is located in a first or last MD column; determining that the first MD pattern overlaps with a first gate-drain/source (VGD) via pattern; determining that the first VGD pattern overlaps the first conductive pattern (first M _1st pattern) in the M _1st level; and determining that the length of the first M _1st pattern is less than a first reference distance; increasing the size of the candidate pattern includes: increasing a length of the first M _1st pattern to be at least substantially equal to the first reference distance with respect to the second direction; and wherein the first MD pattern and the first VGD pattern represent respective MD and VGD structures in a transistor layer of the semiconductor device. In an embodiment, the first reference distance is greater than the second reference distance; and the second reference distance represents a minimum length of the conductive segments in layer M0 relative to typical manufacturing tolerances of a semiconductor process technology node from which the semiconductor device is produced. In an embodiment, the first reference distance is represented by L2; and L2 is greater than one Contact Polysilicon Pitch (CPP) for the semiconductor process technology node of the corresponding semiconductor device. In an embodiment, the layout diagram further includes a transistor level corresponding to a transistor layer in the semiconductor device; there is no metallization level between the M _1st level and the transistor layer; and L2 ≈ 1.5 CPP. In an embodiment, the method further comprises: based on the layout, (a) performing one or more lithographic exposures; (B) fabricating one or more semiconductor masks; or (C) fabricating at least one component in a layer of the semiconductor integrated circuit.

The foregoing has outlined features of several embodiments so that those skilled in the art may better understand the aspects of the present invention. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims

1. A method of manufacturing a semiconductor device, the method comprising:

for a layout stored on a non-transitory computer readable medium, the semiconductor device is based on the layout, the layout comprising first and second metallization levels corresponding to first and second upper metallization layers in the semiconductor device and a first interconnect layer therebetween (respective M _1st and M _2nd levels) and a first interconnect level therebetween (VIA _1st level),

generating the layout comprises:

selecting a candidate pattern in the layout, the candidate pattern being a first conductive pattern in an M _2nd level (a first M _2nd pattern) or a first conductive pattern in an M _1st level (a first M _1st pattern);

determining that the candidate pattern satisfies one or more criteria; and

at least reducing the size of the candidate pattern, thereby modifying the layout.

2. The method of claim 1, wherein:

the layout comprises first and second metallization levels corresponding to first and second overlying metallization layers in the semiconductor device and a first interconnect layer therebetween (respective M _1st and M _2nd levels) and a first interconnect level therebetween (VIA _1st level); and

the candidate pattern is a first M _2nd pattern;

determining that the candidate pattern satisfies one or more criteria comprises:

determining that the first M _2nd pattern is designated as a pin pattern;

determining that a first VIA pattern (first VIA _1st pattern) in the first interconnect level is the only VIA _1st pattern that overlaps a first M _2nd pattern; and

reducing at least the size of the candidate pattern comprises:

removing the first M _2nd pattern from the map.

3. The method of claim 2, wherein generating the map further comprises:

the respective lower first pattern (first M _1st pattern) in the first metallization level is designated as a lead pattern.

4. The method of claim 2, wherein:

the first M _1st pattern is designated as a pin pattern because there are at least first and second allowed upper locations for a first VIA _1st pattern in the first interconnect level, at least the first M _2nd pattern and a second M _2nd pattern in the M _2nd level are correspondingly positioned to overlap the first VIA _1st pattern at the at least first and second allowed upper locations for the first VIA _1st pattern in the first interconnect level; or designating the first M _2nd pattern as a lead pattern, in that there are at least first and second allowed upper locations for the respective first VIA pattern (first VIA _2nd pattern) in the second interconnect level (VIA _2nd level), at least the respective first and second conductive patterns (first and second M _3rd patterns) in the third metallization level (M _3rd) are positioned to overlap the first VIA _2nd pattern at the at least first and second allowed upper locations for the respective first VIA pattern (first VIA _2nd pattern) in the second interconnect level (VIA _2nd level).

5. The method of claim 1, wherein

The layout further includes a second interconnect level (VIA _2nd level) located above the first M _1st level and corresponding to a second interconnect layer above the first metallization layer in the semiconductor device, and

the candidate pattern is a first M _1st pattern;

the first sub-method comprises the following steps:

determining that the first M _1st pattern does not overlap at least a first VIA pattern (first VIA _1st pattern) in the VIA _1st level; and

determining that the first M _1st pattern does not overlap at least a first VIA pattern (a first VIA _2nd pattern) in the VIA _2nd level; or

The second sub-method comprises:

determining that the first M _1st pattern overlaps at least a first VIA pattern (first VIA _1st pattern) in the VIA _1st level with respect to a first direction; or

Determining that the first M _1st pattern overlaps with at least a first VIA pattern (a first VIA _2nd pattern) in the VIA _2nd level with respect to a first direction;

in the context of the first sub-method, reducing at least the size of the candidate pattern comprises:

removing the first M _1st pattern from the map; and

in the context of the second sub-method, reducing at least the size of the candidate pattern comprises:

trimming a first wing portion of the first M _1st pattern to produce a smaller first stub portion; and

wherein, with respect to the first direction, at least one of the first VIA _1st pattern or the first VIA _2nd pattern is present such that the first wing part is located between the first end of the first M _1st pattern and the first VIA _1st pattern or the first VIA _2nd pattern, and there is no other VIA _1st or VIA _2nd pattern that overlaps or overlaps below the first wing part.

6. The method of claim 1, wherein:

the layout further includes transistor levels corresponding to transistor layers in the semiconductor device; and

there is no metallization level between the M _1st level and the transistor layer.

7. The method of claim 1, further comprising:

based on the layout, at least one of:

(A) performing one or more lithographic exposures;

(B) fabricating one or more semiconductor masks; or

(C) At least one component in a layer of a semiconductor integrated circuit is fabricated.

8. A system for fabricating a semiconductor device, the system comprising:

at least one processor; and

at least one memory including computer program code for one or more programs;

wherein the at least one memory, the computer program code, and the at least one processor are configured to cause a system to perform:

generating the layout comprises:

selecting a candidate pattern in the layout, the candidate pattern being a first conductive pattern in the second metallization level (first M _2nd pattern) or a first conductive pattern in the first metallization level (first M _1st pattern);

determining that the candidate pattern satisfies one or more criteria; and

changing the size of the candidate pattern, thereby modifying the layout; and

wherein:

there is no metallization level between the first metallization level and the transistor layer.

9. The system of claim 8, wherein:

the candidate pattern is a first M _2nd pattern;

determining that the first M _2nd pattern is designated as a pin pattern;

determining that a first VIA pattern (a first VIA _1st pattern) in the first interconnect level is the only VIA _1st pattern that overlaps the first M _2nd pattern;

changing the size of the candidate pattern includes:

removing the first M _2nd pattern from the map; and

generating the layout further comprises:

the respective underlying first pattern (first M _1st pattern) in the first metallization level is designated as a pin pattern.

10. A method of manufacturing a semiconductor device, the method comprising:

for a layout stored on a non-transitory computer readable medium, the semiconductor device is based on the layout, the layout comprising a first metallization level and an upper second metallization level corresponding to a first metallization layer and an upper second metallization layer in the semiconductor device and a first interconnect layer therebetween (respective M _1st and M _2nd levels) and a first interconnect level therebetween (VIA _1st level),

generating the layout comprises:

selecting a candidate pattern in the layout, the candidate pattern being a first conductive pattern (first M _1st pattern) in the first metallization level;

determining that the candidate pattern satisfies one or more criteria; and

increasing the size of the candidate pattern, thereby modifying the layout.