TW202030593A - Electronic device and device wake-up method - Google Patents

Abstract

A device wake-up method suitable for an electronic device is provided. The method includes starting to perform a wake-up operation, loading an optimized frequency value, and substituting a preset frequency value of a counter by the optimized frequency value; starting to continuously accumulate a waiting count value having an initial value according to the optimized frequency value; in response to determining that the accumulated waiting count value is equal to a target count value, respectively performing a read test operation to one or more test physical addresses in a rewritable non-volatile memory module; and, in response to determining that all the one or more test physical addresses pass the corresponding read test operations, loading a plurality of initial information corresponding to the rewritable non-volatile memory module, so as to complete the wake-up operation.

Description

Electronic device and device wake-up method

The present invention relates to an electronic device, and more particularly to an electronic device and a device wake-up method.

With the evolution of technology, more and more electronic devices will use Rewritable Non-volatile Memory (NVM) as a storage unit to store data used by the electronic device. At present, the common NVM on the market is Flash Memory. When the flash memory is shipped from the factory, a wake-up time (also known as power-up to operation time) (such as 10.17 microseconds (µs)) is set. The controller of the electronic device needs to restore the electronic device from a deep standby power state (such as hibernation or sleep mode) to a state where the flash memory can be accessed normally. The length of time it takes is less than the specified wake-up time To avoid errors. In addition, the operation of restoring the electronic device from a deep standby power state (eg, hibernation) to a state where the flash memory can be normally accessed is also called a wake-up operation.

It should be noted that while waiting for the completion of the wake-up operation (ie, wake-up time), the controller still consumes power continuously. That is to say, if the electronic device often needs to be awakened from sleep or sleep, the number and frequency of the wake-up operations will increase, resulting in the power of the electronic device being wasted in the wake-up time of each wake-up operation. In particular, electronic devices that use batteries as power sources are more difficult to tolerate waste of power.

Based on this, how to reduce the wake-up time so as to improve the convenience of electronic devices and improve the efficiency of the wake-up operation is the goal of development by those in the art.

The present invention provides an electronic device and a device wake-up method, which can reduce the time for the electronic device to be awakened, so as to reduce the power consumption required for the electronic device to be awakened, thereby improving the use time and efficiency of the electronic device.

An embodiment of the present invention provides an electronic device. The electronic device includes a rewritable non-volatile memory module and a controller. The rewritable non-volatile memory module is used for storing data. The controller includes a processor and a counter. The processor is coupled to the rewritable non-volatile memory module. The counter is coupled to the processor and used to receive an instruction from the processor to accumulate a count value. The processor is used to start a wake-up operation, load an optimized frequency value, and replace the preset frequency value of the counter with the optimized frequency value. The processor is further configured to instruct the counter to start continuously accumulating a waiting count value with an initial value according to the optimized frequency value, wherein in response to determining that the accumulated waiting count value is equal to a target count value, The processor is further configured to perform a read test operation on one or more test physical addresses in the rewritable non-volatile memory module. The processor is further configured to determine whether the one or more test entity addresses all pass the corresponding read test operation, wherein the response is to determine whether the one or more test entity addresses all pass the corresponding For the read test operation, the processor is further used to load a plurality of initialization information corresponding to the rewritable non-volatile memory module to complete the wake-up operation.

Another embodiment of the present invention provides an electronic device. The electronic device includes a rewritable non-volatile memory module and a controller. The rewritable non-volatile memory module is used for storing data. The controller includes a processor and a counter. The processor is coupled to the rewritable non-volatile memory module. The counter is coupled to the processor and used to receive an instruction from the processor to accumulate a count value. The processor is used to start a wake-up operation, load an optimized frequency value and an optimized target count value, replace a preset frequency value of a counter with the optimized frequency value, and use the The optimized target count value replaces the preset target count value of the counter, wherein the optimized target count value is obtained through another wake-up operation completed before the wake-up operation is performed. The processor is further configured to instruct the counter to start continuously accumulating a waiting count value having an initial value according to the optimized frequency value, wherein the waiting count value is determined to be equal to the optimized count value. For the target count value, the processor is further used to load a plurality of initialization information corresponding to the rewritable non-volatile memory module to complete the wake-up operation.

An embodiment of the present invention provides a device wake-up method suitable for an electronic device. The electronic device includes a rewritable non-volatile memory module, a processor and a counter. The method includes: starting to perform a wake-up operation, loading an optimized frequency value, and replacing the preset frequency value of the counter with the optimized frequency value; starting to continuously accumulate a frequency value according to the optimized frequency value The waiting count value of the initial value; in response to determining that the accumulated waiting count value is equal to a target count value, one or more test entity addresses in the rewritable non-volatile memory module are respectively executed Read test operation; determine whether the one or more test entity addresses all pass the corresponding read test operation; and respond to the determination that the one or more test entity addresses all pass the corresponding read In the test operation, a plurality of initialization information corresponding to the rewritable non-volatile memory module is loaded to complete the wake-up operation.

Another embodiment of the present invention provides a device wake-up method suitable for an electronic device. The electronic device includes a rewritable non-volatile memory module, a processor and a counter. The method includes: starting to perform a wake-up operation, loading an optimized frequency value and an optimized target count value, replacing a preset frequency value of a counter with the optimized frequency value, and using the The optimized target count value replaces the preset target count value of the counter, wherein the optimized target count value is obtained through another wake-up operation completed before the wake-up operation is performed; according to the The optimized frequency value starts to accumulate a waiting count value with an initial value; in response to determining that the accumulated waiting count value is equal to the optimized target count value, the processor is further used to load the corresponding A plurality of initialization information of the duplicate non-volatile memory module is used to complete the wake-up operation.

Based on the above, the electronic device and device wake-up method provided by the embodiments of the present invention can use the optimized frequency value to replace the preset frequency value of the counter when performing the wake-up operation, or use the optimized target The count value replaces the preset target count value of the counter, so as to shorten the count time of the counter and can omit the read test operation, thereby shortening the time consumed to complete the wake-up operation. In this way, since the time consumed to complete the wake-up operation is reduced, the power consumption of the electronic device during the wake-up phase can be greatly reduced, thereby improving the battery life of the electronic device. In addition, since the time taken to complete the wake-up operation is reduced, the speed at which the electronic device is awakened is increased, thereby increasing the speed of the electronic device from the standby stage to the normal use stage, and improving the overall operating efficiency of the electronic device.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

The electronic device and device wake-up method provided in an embodiment of the present invention can effectively reduce the wake-up time. In addition to allowing the wake-up time to meet the specifications of the rewritable non-volatile memory (eg, flash memory, Flash) of the electronic device, it can also reduce the power consumption of the electronic device. Hereinafter, it will be explained using FIG. 1.

FIG. 1 is a schematic diagram illustrating a plurality of non-volatile memory signals according to an embodiment of the invention. 1, it is assumed that the controller of the electronic device uses a power supply VDD and a plurality of signals PORb, DPSTB, and CEb to manage a plurality of power states and corresponding operation states of the electronic device. The power supply VDD can also be referred to as a non-volatile memory power supply, which provides power to the internal and peripheral circuits of the Flash; the signal PORb can also be referred to as a Power on Reset signal. This signal PORb can be used at startup or as a power supply VDD When insufficient, the non-volatile memory will be reset; the signal DPSTB can also be referred to as a deep standby (Deep Standby) signal; the signal CEb can also be referred to as a non-volatile memory chip enable signal.

More specifically, the controller of the electronic device controls the voltages of the multiple signals to be high or low corresponding to different power states, thereby changing the electronic device to different power states. For example, in this embodiment, when the signal DPSTB changes from a low level to a high level, it means that the electronic device is about to enter a deep standby power state, and the controller will start to perform a sleep operation or sleep operation; when the signal DPSTB changes from a high level When changing to a low level, it indicates that the electronic device wants to leave the deep standby power state, and the controller will start to perform the wake-up operation (such as time point T1), so that the electronic device will be awakened and enter the normal operating power state (such as time point T2) .

In different power states, each hardware component in the electronic device will be turned on or off correspondingly (the power consumption of each hardware component in the electronic device can be adjusted individually) to make the total power consumption of the electronic device The amount corresponds to the current power state. For example, in this embodiment, if the electronic device is currently in the deep standby power state, only the hardware components (such as one of the processor, detector, and output device) of the electronic device corresponding to the deep standby power state Many of them are provided with power (to detect whether to wake up the entire electronic device), and the hardware components of other parts of the electronic device can be turned off (not provided with power). For another example, in the normal operating power state, all the hardware components of the electronic device are turned on (all are supplied with power).

As shown in FIG. 1, when the wake-up operation is completed (such as time point T2), the electronic device enters a normal operating power state, and the controller of the electronic device can normally access the rewritable non-volatile memory of the electronic device Perform general read (Read), write (Write) or erase (Erase) operations (these operations are also called access operations). In this embodiment, the period during which the read operation, the write operation or the erase operation is performed can also be referred to as the memory operating time T _MOP . In addition, the interval between the operating time T _MOP of the two memories can be referred to as the standby time T _STB .

In addition, the period from the time point T1 to the time point T2 can also be referred to as the wake-up time T _WUP . It should be noted that during the wake-up time T _WUP , the controller cannot perform the access operation corresponding to the normal operating power state to the rewritable non-volatile memory. Therefore, if the wake-up time T _WUP can be reduced, the faster the controller can perform the access operation corresponding to the normal operating power state to the rewritable non-volatile memory, so that the electronic device can enter the Normal operation power state. In other words, if the electronic device enters the normal operating power state faster by shortening the wake-up time T _WUP , the overall operating efficiency of the electronic device can be improved (because it only takes a short time to complete the wake-up operation And began to operate normally). In addition, since the controller of the electronic device cannot perform various operations corresponding to the normal operating power state when the wake-up operation is performed, the controller of the electronic device still consumes power continuously. Therefore, if the wake-up time T _WUP is optimized to allow the electronic device to enter the normal operating power state sooner, the power wasted in the wake-up time T _WUP of the electronic device can also be reduced, thereby improving the overall electronic device Battery life.

FIG. 2 is a block diagram of an electronic device according to an embodiment of the invention. 2, in this embodiment, in this embodiment, the electronic device 10 includes a controller 110, a rewritable non-volatile memory module 120, and a battery 130. The controller 110 is coupled to the rewritable non-volatile memory module 120 and the battery 130. The electronic device 10 is, for example, an electronic device such as an electronic toy, a wearable device, a mobile device, a notebook computer, a tablet computer, a mobile phone, etc., which can enter a deep standby power state. The present invention is not limited to the type of the electronic device 10 .

In this embodiment, the controller 110 is used to manage the overall interaction and operation of the various components of the electronic device 10. The controller 110 includes a processor 111, a memory interface control circuit (Memory Interface Control Circuit) 112 and a counter 113. The processor 111 is coupled to the memory interface control circuit 112 and the counter 113.

The processor 111 is, for example, a core or multi-core central processing unit (CPU), a microprocessor (micro-processor) or other programmable processing unit (Programmable processor), a digital signal processor (Digital Signal Processor, DSP), programmable controller, application specific integrated circuit (Application Specific Integrated Circuits, ASIC), programmable logic device (Programmable Logic Device, PLD) or other similar devices.

The processor 111 is connected to the rewritable non-volatile memory module 120 via the memory interface control circuit 112 to access or manage the rewritable non-volatile memory module 120.

The counter 113 is used for counting. In this embodiment, the counter 113 is, for example, a high-speed internal HIRC (Internal High Speed RC) or other forms of counters. More specifically, when the counter 113 starts to perform a counting operation, the counter 113 may continuously accumulate a count value with an initial value (eg, 0) according to a frequency until the accumulated count value is equal to the target count value . The frequency can be a preset frequency value (for example, 25 MHz) or an optimized frequency value (for example, 50 MHz). The optimized frequency value is greater than the preset frequency value. For example, suppose the frequency is 25 megahertz (25 MHz) and the target count value is 500. The counter 113 may accumulate the count value by 1 every 0.00000004 seconds (1/25000000) until the count value is equal to the target count value. A total of 0.00002 seconds has passed since the count value was accumulated from 0 (the initial value) to 500 (the target count value) (ie, 500*0.00000004=0.00002).

The optimized frequency value and the target count value can be recorded in the always-on storage unit. The always-on storage unit is used to indicate a storage circuit that receives power and operates in any power state. The always-on storage unit is, for example, a special storage area separately partitioned in the rewritable non-volatile memory module 120. The special storage area provided to the special storage area will be kept, and the special storage area only stores Used to manage the information/data of the electronic device 10. In other words, the always-on storage unit can be used to record information used in all power states, so that the information/data stored in the always-on storage unit can be accessed when the electronic device 10 is in any power state. For example, when the electronic device 10 is in a deep standby power state, the information/data stored in the always-on storage unit can be accessed, but the information/data not stored in the always-on storage unit cannot be accessed. The information/data stored in the always-on storage unit also includes an optimized target count value.

The rewritable non-volatile memory module 120 is used to store data. The rewritable non-volatile memory module 120 is, for example, a flash memory (Flash Memory).

The battery 130 is used to provide power to the electronic device 10. The processor 111 can manage the power provided by the battery 130 to other hardware components of the electronic device 10.

Fig. 3 is a flowchart of a device wake-up method according to an embodiment of the invention. Referring to FIG. 3, in step S31, the processor 111 starts to perform a wake-up operation, loads an optimized frequency value, and replaces the preset frequency value of the counter with the optimized frequency value. Specifically, after the electronic device 10 enters the deep standby power state, the processor 111 may respond to determining that a specific event occurs and perform a wake-up operation to change the power state of the electronic device 10 from the deep standby power state to the normal operating power status. The specific event is, for example, a button (or other type of input unit) of the electronic device is triggered (eg, pressed or rotated), a detector (eg, a vibration sensor) detects that the electronic device 10 is moved, etc. Events, received messages from other electronic devices. The present invention is not limited to the specific event. In other words, any event that allows the processor 111 to determine that a wake-up operation needs to be performed can be referred to as the specific event.

When the processor 111 starts to perform the wake-up operation, the processor 111 first loads the optimized frequency value from the always-on storage unit, and replaces the preset frequency value of the counter 113 with the optimized frequency value . Next, in step S32, the counter 113 starts to continuously accumulate the waiting count value having the initial value according to the optimized frequency value. Specifically, after loading the optimized frequency value, the counter 113 will start to perform a counting operation corresponding to the target count value according to the optimized frequency value. After starting the counting operation, independent of other hardware components of the electronic device 10, the counter 113 will continue to accumulate the count value (also known as the waiting count value) according to the optimized frequency value, until it stops. The counting operation.

Next, in step S33, the counter 113 determines whether the accumulated waiting count value is equal to the target count value. In response to determining that the accumulated waiting count value is equal to the target count value (step S33àYes), step S34 is executed; in response to determining that the accumulated waiting count value is not equal to the target count value (step S33àNo) , Continue to perform step S33. In one embodiment, in response to determining that the accumulated waiting count value is equal to the target count value, the counter 113 will complete the counting operation and stop continuously accumulating the waiting count value.

In step S34, the processor 111 is configured to perform a read test operation on one or more test physical addresses in the rewritable non-volatile memory module 120, respectively. Specifically, in this embodiment, the rewritable non-volatile memory module 120 is formed by, for example, one or more flash memory dies (Die). The one or more test physical addresses are, for example, a physical address in one or more flash memory dies (for example, the address of a physical page or a physical sector). The one or more test entity addresses are written into (known) default test data in advance. The present invention is not limited to the bit value of the preset test data.

That is, in step S35, the processor 111 determines whether the one or more test entity addresses pass the corresponding read test operation. Specifically, the processor 111 may perform a read test operation on each of the one or more test entity addresses to determine whether the read data is equal to the preset test data to determine the corresponding one. Or multiple test entity addresses can be read normally. If the data read from a test entity address is equal to the preset test data, the processor 111 determines that the corresponding test entity address passes the corresponding Read the test operation.

In response to determining that the one or more test entity addresses all pass the corresponding read test operation (step S35àYes), step S36 is executed; in response to determining that the one or more test entity addresses do not all pass the corresponding For the read test operation (step S35à No), step S35 is executed.

That is, if the one or more test physical addresses all pass the corresponding read test operation, the processor 111 can determine that one or more flash memory die can be read normally , And it is determined that the rewritable non-volatile memory module 120 can be accessed normally. Conversely, if the one or more test entity addresses all pass the corresponding read test operation, the processor is further configured to detect that the one or more test entity addresses fail the corresponding read test operation. Take the test entity address of the test operation to perform the read test operation again, and perform the step of determining whether the one or more test entity addresses all pass the corresponding read test operation (ie, step S35) .

In step S36, the processor 111 loads a plurality of initialization information corresponding to the rewritable non-volatile memory module 120 to complete the wake-up operation. More specifically, the plurality of initialization information may be stored in the always-on storage unit in advance. The plurality of initialization information is, for example, information for initializing the rewritable non-volatile memory module 120, such as the initial setting value or calibration value of the internal low dropout linear regulator (LDO) and the internal high-speed RC oscillator (HIRC) . The present invention is not limited to the types of the plurality of initialization information. After loading a plurality of initialization information corresponding to the rewritable non-volatile memory module 120, the processor 111 determines that the executed wake-up operation has been completed. At this time, the processor 111 can switch the electronic device to a normal operating power state, and start to perform a memory access operation corresponding to the normal operating power state.

It is worth mentioning that in the embodiment of FIG. 3, when the waiting count value accumulated by the counter 113 is equal to the target count value, the processor 111 will wait until all one or more test entity addresses After passing the corresponding read test operation, it is determined that the wake-up operation has been completed. However, in another embodiment, the processor 111 may not perform a read test operation corresponding to one or more test entity addresses. The following description is made using FIG. 4.

FIG. 4 is a flowchart of another device wake-up method according to another embodiment of the present invention. 4, in step S41, the processor 111 starts to perform a wake-up operation, loads an optimized frequency value and an optimized target count value, and replaces a counter 113 with the optimized frequency value A preset frequency value of, and the optimized target count value replaces the preset target count value of the counter 113. Specifically, the difference between step S41 and step S31 is that, in S41, the processor 111 further loads an optimized target count value, and uses the optimized target counter. The numerical value replaces the original target count value of the counter 113. In this embodiment, the optimized target count value (for example, 400) is less than the target count value.

Next, in step S42, the counter 113 starts to continuously accumulate a waiting count value having an initial value according to the optimized frequency value. Step S42 is the same as step S32, and the details will not be repeated.

In step S43, the counter 113 determines whether the accumulated waiting count value is equal to the optimized target count value. That is, different from step S33, the counter 113 judges whether the accumulated waiting count value is equal to the optimized target count value, rather than judging whether the accumulated waiting count value is equal to the target count value. .

In response to determining that the accumulated waiting count value is equal to the optimized target count value (Yes in step S43à), step S44 is executed; in response to determining that the accumulated waiting count value is not equal to the optimized target count value Value (step S43→No), proceed to step S43. In one embodiment, in response to determining that the accumulated waiting count value is equal to the optimized target count value, the counter 113 will complete the counting operation and stop continuously accumulating the waiting count value.

In step S44, the processor 111 loads a plurality of initialization information corresponding to the rewritable non-volatile memory module 120 to complete the wake-up operation. Step S44 is the same as step S36, and the details will not be repeated here. That is to say, in the embodiment of FIG. 4, when the counter 113 stops counting, the processor 111 will not perform all the tests on one or more test physical addresses in the rewritable non-volatile memory module. The read test operation, but directly loads a plurality of initialization information corresponding to the rewritable non-volatile memory module 120 to complete the wake-up operation.

In this way, in the embodiment of FIG. 4, the time consuming of the wake-up operation (ie, the wake-up time) can be further shortened because there is no need to perform the one or more read test operations. In addition, in the embodiment of FIG. 4, since the electronic device 10 does not need to perform the one or more read test operations, the electronic device 10 can further avoid power consumption on the one or more read test operations. In other words, theoretically, the device wake-up method provided by the embodiment of FIG. 4 can be faster and more power-saving than the device wake-up method provided by the embodiment of FIG. 3.

However, it should be noted that the optimized target count value is obtained through another wake-up operation completed before the wake-up operation is executed. The following description will be made using FIG. 5.

FIG. 5 is a flowchart of another device wake-up method according to another embodiment of the present invention. 5, the device wake-up method corresponding to the another wake-up operation includes steps S51, S52, S53, S54, S55, and S56. Among them, compared with the device wake-up method of the embodiment of FIG. 3, step S51 is the same as step S31; step S52 is the same as step S32; step S53 is the same as step S34; step S54 is the same as step S35; and step S56 is the same as step S36. Based on this, the details of the above steps S51, S52, S53, S54, and S56 will not be repeated. The following describes only the differences between the device wake-up method of the embodiment of FIG. 5 and the device wake-up method of the embodiment of FIG. 3.

Specifically, after step S52 is executed, the processor 111 will not determine whether the accumulated waiting count value is equal to the target count value, but the processor 111 will directly respond to the rewritable non-volatile memory. The one or more test entity addresses in the module execute the read test operation respectively, and determine whether the one or more test entity addresses all pass the corresponding read test operation (S54). In response to determining that the one or more test entity addresses all pass the corresponding read test operation (step S54àYes), proceed to step S55; in response to determining that the one or more test entity addresses all pass the corresponding The read test operation (step S54→No), proceed to step S54.

In step S55, the counter 113 stops accumulating the waiting count value, and the processor 111 stores the accumulated waiting count value as the optimized target count value. The optimized target count value is stored in the always-on storage unit. In other words, in order to accurately obtain the optimized target count value, the processor 111 performs the other wake-up operation, and uses the one or more test entity addresses to pass the corresponding read test. The timing of the operation is to use the accumulated waiting count value as the optimized target count value. In other words, the processor 111 can know that after the wake-up operation is started and the waiting count value is accumulated from 0 to the optimized target count value, the rewritable non-volatile memory model The group 120 can enter the normally accessed state (because the one or more test entity addresses can all pass the read test operation after the time has passed).

In an embodiment, for example, when the electronic device 10 performs a wake-up operation for the first time, the processor 111 may execute the device wake-up method provided in the embodiment of FIG. 5 to obtain the optimized target plan. Numerical value.

In summary, the electronic device and device wake-up method provided by the embodiments of the present invention can use the optimized frequency value instead of the preset frequency value of the counter when performing the wake-up operation, or use the optimized frequency value. The target count value is changed to replace the preset target count value of the counter, so as to shorten the counting time of the counter and even omit the read test operation, thereby shortening the time consumed to complete the wake-up operation. In this way, since the time consumed to complete the wake-up operation is reduced, the power consumption of the electronic device during the wake-up phase can be greatly reduced, thereby improving the battery life of the electronic device. In addition, since the time taken to complete the wake-up operation is reduced, the speed at which the electronic device is awakened is increased, thereby increasing the speed of the electronic device from the standby stage to the normal use stage, and improving the overall operating efficiency of the electronic device.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be determined by the scope of the attached patent application.

T _RHR , T _WUP , T _MOP , T _STB : time T1, T2, T3: time point 10: electronic device 110: controller 120: rewritable non-volatile memory module 130: battery 111: processor 112: Memory interface control circuit 113: counters S31, S32, S33, S34, S35, S36: device wake-up method process steps S41, S42, S43, S44: device wake-up method process steps S51, S52, S53, S54, S55, S56: Process steps of device wake-up method

FIG. 1 is a schematic diagram of multiple signals drawn according to an embodiment of the invention. FIG. 2 is a block diagram of an electronic device according to an embodiment of the invention. Fig. 3 is a flowchart of a device wake-up method according to an embodiment of the invention. FIG. 4 is a flowchart of another device wake-up method according to another embodiment of the present invention. FIG. 5 is a flowchart of another device wake-up method according to another embodiment of the present invention.

S31, S32, S33, S34, S35, S36: process steps of the device wake-up method

Claims (10)

An electronic device including: A rewritable non-volatile memory module for storing data; and A controller, the controller includes: A processor coupled to the rewritable non-volatile memory module; A counter, coupled to the processor, for receiving an instruction from the processor to accumulate a count value, The processor is used to start a wake-up operation, load an optimized frequency value, and replace the preset frequency value of the counter with the optimized frequency value, The processor is further configured to instruct the counter to start continuously accumulating a waiting count value having an initial value according to the optimized frequency value, Wherein in response to determining that the accumulated waiting count value is equal to a target count value, the processor is further configured to execute respectively on one or more test entity addresses in the rewritable non-volatile memory module One read test operation, The processor is further used to determine whether the one or more test entity addresses pass the corresponding read test operation, Wherein in response to determining that the one or more test entity addresses have passed the corresponding read test operation, the processor is further used to load a plurality of initialization information corresponding to the rewritable non-volatile memory module To complete the wake-up operation. The electronic device according to the first item of the scope of patent application, wherein it is reflected in the determination that the one or more test entity addresses have not passed the corresponding read test operation, The processor is further configured to perform the corresponding read test operation again on the test entity addresses that have not passed the corresponding read test operation among the one or more test entity addresses, and perform the corresponding read test operation again. It is determined whether the one or more test entity addresses pass the corresponding steps of the read test operation. The electronic device according to claim 1, wherein in response to determining that the accumulated waiting count value is equal to the target count value, the processor is further configured to instruct the counter to stop continuously accumulating the waiting count Numerical value. An electronic device including: A rewritable non-volatile memory module for storing data; and A controller, the controller includes: A processor coupled to the rewritable non-volatile memory module; A counter, coupled to the processor, for receiving an instruction from the processor to accumulate a count value, The processor is used to start a wake-up operation, load an optimized frequency value and an optimized target count value, replace a preset frequency value of the counter with the optimized frequency value, and use The optimized target count value replaces a preset target count value of the counter, wherein the optimized target count value is obtained through another wake-up operation completed before the wake-up operation is performed, The processor is further configured to instruct the counter to start continuously accumulating a waiting count value having an initial value according to the optimized frequency value, Wherein in response to determining that the accumulated waiting count value is equal to the optimized target count value, the processor is further used to load a plurality of initialization information corresponding to the rewritable non-volatile memory module to complete The wake-up operation. In the electronic device described in item 4 of the scope of patent application, in the another wake-up operation, The processor starts to perform the another wake-up operation, loads the optimized frequency value, and replaces the preset frequency value of the counter with the optimized frequency value, Wherein the processor instructs the counter to start continuously accumulating the waiting count value having the initial value according to the optimized frequency value, The processor performs a read test operation on one or more test physical addresses in the rewritable non-volatile memory module, respectively, Wherein the processor determines whether the one or more test entity addresses pass the corresponding read test operation, Wherein in response to determining that the one or more test entity addresses have passed the corresponding read test operation, the processor stops accumulating the waiting count value, and stores the accumulated waiting count value as the Optimize the target count value, The processor loads a plurality of initialization information corresponding to the rewritable non-volatile memory module to complete the another wake-up operation. A device wake-up method is suitable for an electronic device, wherein the electronic device includes a rewritable non-volatile memory module, a processor, and a counter. The method includes: Start to perform a wake-up operation and load an optimized frequency value; Start to continuously accumulate a waiting count value with an initial value according to the optimized frequency value; In response to determining that the accumulated waiting count value is equal to a target count value, perform a read test operation on one or more test entity addresses in the rewritable non-volatile memory module; Determine whether the one or more test entity addresses pass the corresponding read test operation; and In response to determining that the one or more test entity addresses have passed the corresponding read test operation, a plurality of initialization information corresponding to the rewritable non-volatile memory module is loaded to complete the wake-up operation. The device wake-up method as described in item 6 of the scope of patent application, wherein it is reflected in the determination that the one or more test entity addresses have not passed the corresponding read test operation, The processor is further configured to perform the corresponding read test operation again on the test entity addresses that have not passed the corresponding read test operation among the one or more test entity addresses, and perform the corresponding read test operation again. It is determined whether the one or more test entity addresses pass the corresponding steps of the read test operation. The device wake-up method according to item 6 of the scope of patent application, wherein in response to determining that the accumulated waiting count value is equal to the target count value, the continuous accumulation of the waiting count value is stopped. A device wake-up method is suitable for an electronic device, wherein the electronic device includes a rewritable non-volatile memory module, a processor, and a counter. The method includes: Start performing a wake-up operation, load an optimized frequency value and an optimized target count value, wherein the optimized target count value is determined by another wake-up operation completed before the wake-up operation is performed obtain; Start to continuously accumulate a waiting count value with an initial value according to the optimized frequency value; In response to determining that the accumulated waiting count value is equal to the optimized target count value, the processor is further used to load a plurality of initialization information corresponding to the rewritable non-volatile memory module to complete all The wake-up operation. According to the device wake-up method described in the scope of patent application, the other wake-up operation includes: Start to execute the another wake-up operation, and load the optimized frequency value; Start to continuously accumulate the waiting count value with the initial value according to the optimized frequency value; Perform a read test operation on one or more test physical addresses in the rewritable non-volatile memory module; Determining whether the one or more test entity addresses pass the corresponding read test operation; In response to determining that the one or more test entity addresses have passed the corresponding read test operation, stop accumulating the waiting count value, and storing the accumulated waiting count value as the optimized target counter Value; and Load a plurality of initialization information corresponding to the rewritable non-volatile memory module to complete the another wake-up operation.

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