JP2007042221A - Method of controlling writing to nonvolatile storage circuit, and semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method etc. capable of writing and the like to a nonvolatile storage circuit even when power voltage is smaller than a prescribed threshold. <P>SOLUTION: A single chip microcomputer 1 is provided with: a power control part 2, a power voltage detection part 3, an oscillation part 4, a CPU core part 5, a ROM 6, a RAM 7, a nonvolatile storage part 8 and a peripheral part 9. The CPU core part 5 instructs the power voltage detection part 3 to detect power voltage, sets a first period as a writing period when the power voltage is not smaller than the prescribed threshold, and sets a second period longer than the first period as the writing period when the power voltage is smaller than the prescribed threshold. Thereafter, the CPU core part 5 makes an EEPROM controller 13 write data in the set writing period. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a method for controlling writing to a nonvolatile memory circuit in a semiconductor integrated circuit having a writable nonvolatile memory circuit. Furthermore, the present invention relates to such a semiconductor integrated circuit.

  Conventionally, a semiconductor integrated circuit incorporating an EEPROM (electrically erasable programmable read only memory) has been used.

  The EEPROM can operate at a relatively low voltage when data is not written, but requires a high voltage when data is written. Therefore, generally, an EEPROM has a built-in booster circuit for boosting a power supply voltage when writing data. When writing data to the EEPROM, a large current flows through the booster circuit.

  When a semiconductor integrated circuit is operated with power supplied from a battery, it operates normally when data is not written to the EEPROM, but cannot operate normally when data is written to the EEPROM. May cause loss of data. This is because, since the internal impedance of the battery is large, if a large current flows through the booster circuit when writing data to the EEPROM, the output voltage of the battery, that is, the power supply voltage supplied to the semiconductor integrated circuit is lowered.

  As a related technique, Patent Document 1 listed below includes a power source that generates a first output for a programming voltage and a second output for a read voltage, and is connected to the first output and the second output, and the programming voltage or A reference power supply that supplies a reference voltage in response to the read voltage, and is driven by the reference voltage. A first signal that generates a first signal in response to the read voltage when the read voltage falls below a first predetermined voltage threshold A voltage detector, driven by a reference voltage, and when the programming voltage falls below a second predetermined voltage or when the first signal is generated, the second signal in response to the programming voltage and the first signal Coupled to a second voltage detector, a power source, a first voltage detector and a second voltage detector to generate data and programs A memory comprising circuitry for storing instructions and controlling access to the memory in response to the first or second signal, and coupled to the power supply and the memory, for accessing the data and program instructions in the memory and accessing the data and A processing system is provided that includes a processing unit for processing program instructions.

  According to this processing system, it is possible to prevent an unexpected erase or programming operation in which the first or second preparation signal is generated in the nonvolatile memory device.

  However, in this processing system, the programming operation to the nonvolatile memory device cannot be performed when the first or second preparing signal is generated.

JP-T-9-503880 (first page, FIG. 1)

  Therefore, in view of the above points, the present invention provides a method for controlling writing to a nonvolatile memory circuit that can perform writing to the nonvolatile memory circuit even when the power supply voltage is smaller than a predetermined threshold value. This is the first purpose. The second object of the present invention is to provide such a semiconductor integrated circuit.

  In order to solve the above problems, a write control method to a nonvolatile memory circuit according to a first aspect of the present invention is a method for writing to a nonvolatile memory circuit in a semiconductor integrated circuit having a writable nonvolatile memory circuit. A step (a) of detecting a power supply voltage, and when the power supply voltage detected in step (a) is equal to or greater than a predetermined threshold value, a predetermined first time is stored in a nonvolatile manner. Non-volatile storage of a predetermined second time longer than the first time when the power supply voltage detected in step (b) and the step (a) is smaller than a predetermined threshold value. Step (c) set as a write time to the circuit and a write operation of desired data to a desired area of the nonvolatile memory circuit are performed at the write time set in step (b) or step (c). Comprising a step (d).

  In this non-volatile memory circuit write control method, when the power supply voltage detected in step (a) is smaller than a predetermined threshold, the second data is written to a desired area of the non-volatile memory circuit. A step (e) for notifying the outside of what is to be done in the time period may be further provided.

  Further, step (b) and / or step (c) sets a write time to the nonvolatile memory circuit by writing a desired count value in a timer circuit for counting time by counting clock signals. Alternatively, it may be a step of setting the write time to the nonvolatile memory circuit by instructing the frequency of the clock signal to the clock signal generating circuit that generates the clock signal.

  A method for controlling writing to a nonvolatile memory circuit according to a second aspect of the present invention is a method for controlling writing to a nonvolatile memory circuit in a semiconductor integrated circuit including a writable nonvolatile memory circuit. (A) performing a dummy data write operation to a dummy area in the nonvolatile memory circuit, or operating a circuit having a load equivalent to the load in the write operation to the nonvolatile memory circuit; ) Detecting the power supply voltage in step (b), and when the power supply voltage detected in step (b) is equal to or higher than a predetermined threshold value, writing operation of desired data to a desired area of the nonvolatile memory circuit (C).

  In this method of controlling writing to the nonvolatile memory circuit, the circuit may be a booster circuit for supplying a voltage necessary for writing to the nonvolatile memory circuit.

  In addition, when the power supply voltage detected in step (b) is smaller than a predetermined threshold value, a step of notifying the outside that the operation of writing the desired data to the desired area of the nonvolatile memory circuit has not been performed ( d) may be further provided.

  A method for controlling writing to a nonvolatile memory circuit according to a third aspect of the present invention is a method for controlling writing to a nonvolatile memory circuit in a semiconductor integrated circuit having a writable nonvolatile memory circuit. (A) performing a dummy data write operation to a dummy area in the nonvolatile memory circuit, or operating a circuit having a load equivalent to the load in the write operation to the nonvolatile memory circuit; ) In step (b) for detecting the power supply voltage and the power supply voltage detected in step (b) is equal to or higher than a predetermined threshold value, the predetermined first time is set as the write time to the nonvolatile memory circuit. When the power supply voltage detected in step (c) and step (b) is smaller than a predetermined threshold value, a predetermined second time longer than the first time is set to the nonvolatile memory circuit. A step (d) of setting as a write time to the memory, and a step of performing a write operation of desired data in a desired area of the nonvolatile memory circuit at the write time set in step (c) or step (d) (E).

  In this non-volatile memory circuit write control method, when the power supply voltage detected in step (b) is smaller than a predetermined threshold, the second data is written to a desired area of the non-volatile memory circuit. A step (f) of notifying the outside of what is to be done in the time period may be further provided.

  Also, step (c) and / or step (d) sets a write time to the nonvolatile memory circuit by writing a desired count value in a timer circuit for counting time by counting clock signals. Alternatively, it may be a step of setting the write time to the nonvolatile memory circuit by instructing the frequency of the clock signal to the clock signal generating circuit that generates the clock signal.

  The semiconductor integrated circuit according to the first aspect of the present invention is a semiconductor integrated circuit including a writable nonvolatile memory circuit, detects a power supply voltage, and the detected power supply voltage is equal to or higher than a predetermined threshold value. In some cases, a predetermined first time is set as a writing time to the nonvolatile memory circuit, and when the detected power supply voltage is smaller than a predetermined threshold, a predetermined second time longer than the first time is set. The write time to the nonvolatile memory circuit is set, and a write operation of desired data to a desired area of the nonvolatile memory circuit is performed with the set write time.

  A semiconductor integrated circuit according to a second aspect of the present invention is a semiconductor integrated circuit including a writable nonvolatile memory circuit, and performs a dummy data write operation to a dummy area in the nonvolatile memory circuit. Alternatively, when a circuit having a load equivalent to the load in the write operation to the nonvolatile memory circuit is operated and a power supply voltage is detected, and the detected power supply voltage is equal to or higher than a predetermined threshold value, nonvolatile storage of desired data A write operation to a desired area of the circuit is performed.

  A semiconductor integrated circuit according to a third aspect of the present invention is a semiconductor integrated circuit including a writable nonvolatile memory circuit, and performs a dummy data write operation to a dummy area in the nonvolatile memory circuit. Alternatively, when a circuit having a load equivalent to the load in the write operation to the nonvolatile memory circuit is operated and a power supply voltage is detected, and the detected power supply voltage is equal to or higher than a predetermined threshold, a predetermined first time is set. When the detected power supply voltage is smaller than a predetermined threshold, a predetermined second time longer than the first time is set as the write time to the nonvolatile memory circuit. Then, a write operation of desired data to a desired area of the nonvolatile memory circuit is performed in a set write time.

  The best mode for carrying out the present invention will be described below with reference to the drawings. In addition, the same referential mark is attached | subjected to the same component and description is abbreviate | omitted.

  FIG. 1 is a diagram showing an outline of a single-chip microcomputer as an embodiment of the present invention. In this embodiment, the present invention is applied to a single chip microcomputer.

  As shown in FIG. 1, this single-chip microcomputer 1 includes a power control unit 2, a power supply voltage detection unit 3, an oscillation unit 4, a CPU (central processing unit) core unit 5, and a ROM (read only memory). 6, a random access memory (RAM) 7, a nonvolatile storage unit 8, and a peripheral unit 9.

  The CPU core unit 2 executes a program stored in the ROM 6 while using the RAM 7 as a work area, thereby controlling each unit in the single chip computer 1 and realizing a desired process.

The power control unit 2 is supplied with a potential (here, V _DD and V _SS ) from the outside (for example, an AC adapter, a battery, etc.), and supplies a power supply voltage to each unit in the single chip computer 1. The power control unit 2 may supply different power supply voltages to each part in the single chip computer 1 or may supply a single power supply voltage to each part in the single chip computer 1.

  The power supply voltage detection unit 3 is supplied from the outside to the power control unit 2 and / or from the power control unit 2 to each unit in the single chip computer 1 under the control of the CPU core unit 5. Detection is performed.

  The oscillation unit 4 supplies a clock signal to each unit in the single chip computer 1 under the control of the CPU core unit 5. The oscillation unit 4 may supply clock signals having different frequencies to each unit in the single chip computer 1 or may supply a clock signal having a single frequency to each unit in the single chip computer 1. good.

  The nonvolatile storage unit 8 includes an EEPROM (electrically erasable programmable read only memory) 11, a timer 12, and an EEPROM controller 13.

  The EEPROM 11 is a writable (including rewriting) nonvolatile memory. As described above, the EEPROM can operate at a relatively low voltage at times other than data writing, but requires a high voltage at the time of data writing. Therefore, generally, an EEPROM has a built-in booster circuit for boosting a power supply voltage when writing data. Following this, also in the present embodiment, the EEPROM 11 includes a booster circuit for boosting the voltage supplied from the power control unit 2.

  The timer 12 measures time by counting the clock signal supplied from the oscillation unit 4 under the control of the CPU core unit 5. The timer 12 has a register (hereinafter referred to as “setting value register”) for writing a setting value indicating the number of clock signals to be counted, and the CPU core unit 5 writes a desired value to the setting value register. As a result, the time measured by the timer 12 can be set to a desired time.

  The EEPROM controller 13 writes data to the EEPROM 11 and reads data from the EEPROM 11 under the control of the CPU core unit 5.

  The peripheral unit 9 includes various peripheral circuits such as a serial communication controller and transmits / receives data to / from the outside.

  Next, the first operation of the single chip microcomputer 1 when data is written to the EEPROM 11 will be described. FIG. 2 is a flowchart showing processing of the CPU core unit 5 when data is written to the EEPROM 11.

  First, the CPU core unit 5 instructs the power supply voltage detection unit 3 to detect the power supply voltage (step S11). Then, the CPU core unit 5 checks whether or not the power supply voltage is greater than or equal to a predetermined threshold value. If the power supply voltage is greater than or equal to the predetermined threshold value, the CPU core unit 5 moves the process to step S13, and the power supply voltage is greater than the predetermined threshold value. If not, the process proceeds to step S14 (step S12).

  As described above, generally, an EEPROM incorporates a booster circuit for generating a high voltage when data is written. If the power supply voltage is smaller than a predetermined threshold, the output voltage of the booster circuit does not reach the predetermined voltage, and data writing may not be performed normally. However, even when the power supply voltage is smaller than the threshold value, data writing can be normally performed by increasing the writing time.

  Therefore, when the power supply voltage is equal to or higher than the predetermined threshold, the CPU core unit 5 sets a standard first time as the writing time (step S13).

  On the other hand, if the power supply voltage is not equal to or higher than the predetermined threshold, the CPU core unit 5 sets a second time longer than the first time as the writing time (step S14). As described above, the write time can be set by writing a desired value in the set value register in the timer 12. In addition, as the second time, for example, a time about 10 times the first time may be set.

  Then, the CPU core unit 5 notifies the external circuit that data writing to the EEPROM 11 is performed in the second time (step S15). As a result, the external circuit can detect that data writing may not be performed normally.

  Thereafter, the CPU core unit 5 causes the EEPROM controller 13 to write data in the write time set in step S13 or step S14 (step S16).

FIG. 3 is a timing chart during the data write operation in step S16.
At time _{t 1} is a falling edge of the clock signal, CPU core unit 5 (in this case, a high level) activates the chip select signal for selecting the EEPROM11 as well as to the write address to the EEPROM controller 13 Output.

At time _{t 2} is the next rising edge of the clock signal, the CPU core unit 5, and outputs the write data to the EEPROM controller 13. At this time, the timer 12 loads the set value in the set value register into a clock counter down counter (hereinafter referred to as “clock counter”).

At time t _3, which is the next falling edge of the clock signal, the timer 12 activates the write start signal by half a clock period (in this case, a high level) to. EEPROM controller 13 receives the falling edge of the write start signal at time t ₄ is a next rising edge of the clock signal, activates the write busy signal (in this case, a high level) as well as to starts data write .

Thereafter, the timer 12 counts down the clock count counter. When the value of the clock count counter becomes “0” at time t ₅ , at time t ₆ , which is the next rising edge of the clock signal, the timer 12 activates the write end signal for a half clock period (here, high level). To. EEPROM controller 13 receives the falling edge of the write end signal at time t ₇ is the next falling edge of the clock signal, and terminates the data writing, at time t _8, which is the next rising edge of the clock signal, The write busy signal is made inactive (here, low level).

In FIG. 3, the period from time t _{4 to} t ₇ is the writing time to the EEPROM 11. As described above, this time can be changed by changing the setting value in the setting value register of the timer 12.

  As described above, according to the first operation of the single-chip microcomputer 1, when the power supply voltage is smaller than the predetermined threshold, the second time longer than the first time is set as the writing time. Data writing can be performed.

  Here, the CPU core unit 5 changes the write time to the EEPROM 11 by changing the set value in the set value register of the timer 12, but the source supplied from the oscillation unit 4 to the timer 12 The time for writing to the EEPROM 11 may be changed by instructing the oscillator 4 to change the frequency of the oscillation clock signal.

  Next, the second operation of the single chip microcomputer 1 when data is written to the EEPROM 11 will be described.

  FIG. 4 is a flowchart showing processing of the CPU core unit 5 when data is written to the EEPROM 11.

  In the first operation described above (see FIG. 2), the power supply voltage is detected (see step S11 in FIG. 2). However, during a time other than the write operation of the EEPROM 11 (when the booster circuit in the EEPROM 11 is not in operation), even when the power supply voltage is equal to or higher than a predetermined threshold, the write operation of the EEPROM 11 (during the operation of the booster circuit in the EEPROM 11). In this case, the current consumption may increase and the power supply voltage may decrease. In particular, when the single-chip microcomputer 1 is supplied with power from the battery, the internal impedance of the battery is large, so that the power supply voltage is likely to decrease when the current consumption increases.

  Therefore, the CPU core unit 5 instructs the EEPROM controller 13 to perform a dummy write operation (step S21). At the same time, the CPU core unit 5 instructs the power supply voltage detection unit 3 to detect the power supply voltage supplied from the power control unit 2 to the EEPROM 11 (step S22). Here, the dummy write operation is an operation of writing dummy data to a dummy address in the EEPROM 11. When the booster circuit in the EEPROM 11 has a function capable of performing a boost operation without writing data, the booster circuit in the EEPROM 11 may be operated. Further, a circuit having a load equivalent to that of the booster circuit in the EEPROM 11 may be operated.

FIG. 5 is a timing chart in steps S21 and S22.
At time _{t 11} is a falling edge of the clock signal, CPU core unit 5, the active (in this case, a high level) the chip select signal for selecting the EEPROM11 as well as to, EEPROM controller dummy write address 13 is output.

At time t ₁₂ , which is the next rising edge of the clock signal, the CPU core unit 5 outputs dummy write data to the EEPROM controller 13. At this time, the timer 12 loads the set value in the set value register to the clock count counter.

At time t ₁₃ is the next falling edge of the clock signal, the timer 12 activates the write start signal by half a clock period (in this case, a high level) to. EEPROM controller 13 receives the falling edge of the write start signal at time t ₁₄ which is the next rising edge of the clock signal, a write busy signal active (in this case, a high level) as well as in, to operate the booster circuit Then, writing of dummy data is started.
Thereafter, the timer 12 starts to count down the clock count counter.

At time t _15, which is the next rising edge of the clock signal, CPU core unit 5, a power supply voltage detecting unit 3 actuating signals active (in this case, a high level), the power supply voltage detecting unit detects the power supply voltage 3 to do. Thereafter, CPU core unit 5, at time t ₁₆ is the next falling edge of the next clock signal (here, low level) power supply voltage detecting unit 3 actuating signals inactive to.

When the value of the clock count counter becomes “0” at time t ₁₇ , at time t ₁₈ , which is the next rising edge of the clock signal, the timer 12 is active for a half-clock period (here, high level). To. EEPROM controller 13 receives the falling edge of the write end signal at time t ₁₉ is the next falling edge of the clock signal, and terminates the writing of the dummy data, the time t ₂₀ which is the next rising edge of the clock signal , The write busy signal is made inactive (here, low level).

In FIG. 5, a period from time t _{14 to} t _{19 is} a time for writing dummy data to the EEPROM 11. This time can be changed by changing the set value in the set value register of the timer 12.

  Referring to FIG. 4 again, the CPU core unit 5 checks whether or not the power supply voltage is equal to or higher than a predetermined threshold value. If the power supply voltage is equal to or higher than the predetermined threshold value, the process proceeds to step S24, If the voltage is not equal to or greater than the predetermined threshold, the process proceeds to step S25 (step S23).

  When the power supply voltage is equal to or higher than the predetermined threshold, the CPU core unit 5 causes the EEPROM controller 13 to write data (data that is not dummy data) (step S24). The timing chart during the data write operation in step S23 is the same as that in FIG.

  On the other hand, if the power supply voltage is not equal to or higher than the predetermined threshold, the CPU core unit 5 notifies the external circuit that data has not been written (step S25). Thereby, the external circuit can detect that data writing has not been performed.

  As described above, according to the second operation of the single-chip microcomputer 1, data writing is not performed when the power supply voltage while writing dummy data to the EEPROM 11 is smaller than a predetermined threshold. can do.

  Next, the third operation of the single chip microcomputer 1 when data is written to the EEPROM 11 will be described.

  FIG. 6 is a flowchart showing processing of the CPU core unit 5 when data is written to the EEPROM 11.

  First, the CPU core unit 5 instructs the EEPROM controller 13 to perform a dummy write operation (step S31). At the same time, the CPU core unit 5 instructs the power supply voltage detection unit 3 to detect the power supply voltage supplied from the power control unit 2 to the EEPROM 11 (step S32).

  Next, the CPU core unit 5 checks whether or not the power supply voltage is equal to or higher than a predetermined threshold value. If the power supply voltage is equal to or higher than the predetermined threshold value, the process proceeds to step S34, where the power supply voltage is equal to or higher than the predetermined threshold value. If not, the process moves to step S35 (step S33).

  If the power supply voltage is equal to or higher than the predetermined threshold, the CPU core unit 5 sets a standard first time as the writing time (step S34).

  On the other hand, when the power supply voltage is not equal to or higher than the predetermined threshold, the CPU core unit 5 sets a second time longer than the first time as the writing time (step S35). Then, the CPU core unit 5 notifies the external circuit that data writing to the EEPROM 11 is performed in the second time (step S36). As a result, the external circuit can detect that data writing may not be performed normally.

  Thereafter, the CPU core unit 5 causes the EEPROM controller 13 to write data in the write time set in step S34 or step S35 (step S37). The timing chart during the data write operation in step S37 is the same as that in FIG.

  As described above, according to the third operation of the single-chip microcomputer 1, when the power supply voltage while writing dummy data to the EEPROM 11 is smaller than the predetermined threshold, the first time is used as the writing time. Data writing can be performed by setting a longer second time.

  INDUSTRIAL APPLICABILITY The present invention can be used for a method for controlling writing to a nonvolatile memory circuit in a semiconductor integrated circuit including a writable nonvolatile memory circuit. Furthermore, the present invention is applicable to such a semiconductor integrated circuit.

1 is a diagram showing a single chip microcomputer as an embodiment of the present invention. 3 is a flowchart showing the operation of the CPU core unit 5 of FIG. 2 is a timing chart of the single chip microcomputer 1 of FIG. 1. 3 is a flowchart showing the operation of the CPU core unit 5 of FIG. 2 is a timing chart of the single chip microcomputer 1 of FIG. 1. 3 is a flowchart showing the operation of the CPU core unit 5 of FIG.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 Single chip microcomputer, 2 Power control part, 3 Power supply voltage detection part, 4 Oscillation part, 5 CPU core part, 6 ROM, 7 RAM, 8 Nonvolatile memory part, 9 Peripheral part, 11 EEPROM, 12 Timer, 13 EEPROM controller

Claims (12)

In a semiconductor integrated circuit comprising a writable nonvolatile memory circuit, a method for controlling writing to the nonvolatile memory circuit,
Detecting a power supply voltage (a);
A step (b) of setting a predetermined first time as a write time to the nonvolatile memory circuit when the power supply voltage detected in step (a) is not less than a predetermined threshold;
A step of setting a predetermined second time longer than the first time as a writing time to the nonvolatile memory circuit when the power supply voltage detected in step (a) is smaller than a predetermined threshold value; When,
A step (d) of performing a write operation of desired data in a desired region of the nonvolatile memory circuit in the write time set in step (b) or step (c);
A method for controlling writing into a nonvolatile memory circuit.   When the power supply voltage detected in step (a) is smaller than a predetermined threshold value, the outside is notified that writing of desired data to a desired area of the nonvolatile memory circuit is performed in the second time. The method for controlling writing to the nonvolatile memory circuit according to claim 1, further comprising step (e).   Step (b) and / or Step (c) sets a write time to the non-volatile memory circuit by writing a desired count value in a timer circuit for counting time by counting clock signals, 3. The nonvolatile memory circuit according to claim 1, wherein the write time to the nonvolatile memory circuit is set by instructing a frequency of the clock signal to a clock signal generating circuit that generates the clock signal. Write control method. In a semiconductor integrated circuit comprising a writable nonvolatile memory circuit, a method for controlling writing to the nonvolatile memory circuit,
Performing a dummy data write operation to a dummy area in the nonvolatile memory circuit, or operating a circuit having a load equivalent to the load in the nonvolatile memory circuit write operation;
Detecting a power supply voltage in step (a) (b);
(C) performing a write operation of desired data to a desired region of the nonvolatile memory circuit when the power supply voltage detected in step (b) is equal to or higher than a predetermined threshold;
A method for controlling writing into a nonvolatile memory circuit.   5. The method for controlling writing into the nonvolatile memory circuit according to claim 4, wherein the circuit is a booster circuit for supplying a voltage necessary for writing in the nonvolatile memory circuit.   A step of notifying the outside that a write operation of desired data to a desired region of the nonvolatile memory circuit has not been performed when the power supply voltage detected in step (b) is smaller than a predetermined threshold value (d) 6. The method for controlling writing into the nonvolatile memory circuit according to claim 4, further comprising: In a semiconductor integrated circuit comprising a writable nonvolatile memory circuit, a method for controlling writing to the nonvolatile memory circuit,
Performing a dummy data write operation to a dummy area in the nonvolatile memory circuit, or operating a circuit having a load equivalent to the load in the nonvolatile memory circuit write operation;
Detecting a power supply voltage in step (a) (b);
A step (c) of setting a predetermined first time as a write time to the nonvolatile memory circuit when the power supply voltage detected in step (b) is equal to or higher than a predetermined threshold;
A step of setting a predetermined second time longer than the first time as a write time to the nonvolatile memory circuit when the power supply voltage detected in step (b) is smaller than a predetermined threshold value (d) When,
A step (e) of performing a write operation of desired data in a desired region of the nonvolatile memory circuit in the write time set in step (c) or step (d);
A method for controlling writing into a nonvolatile memory circuit.   When the power supply voltage detected in step (b) is smaller than a predetermined threshold value, the outside is notified that writing of desired data to a desired area of the nonvolatile memory circuit is performed in the second time. The method for controlling writing into the nonvolatile memory circuit according to claim 7, further comprising step (f).   Step (c) and / or Step (d) sets a write time to the non-volatile memory circuit by writing a desired count value in a timer circuit for counting time by counting clock signals, 9. The nonvolatile memory circuit according to claim 7 or 8, wherein a write time to the nonvolatile memory circuit is set by instructing a frequency of the clock signal to a clock signal generation circuit that generates the clock signal. Write control method. A semiconductor integrated circuit comprising a writable nonvolatile memory circuit,
A power supply voltage is detected, and when the detected power supply voltage is equal to or greater than a predetermined threshold, a predetermined first time is set as a write time to the nonvolatile memory circuit, and the detected power supply voltage is set to a predetermined threshold When the time is smaller, a predetermined second time longer than the first time is set as a write time to the nonvolatile memory circuit, and a write operation of desired data to a desired region of the nonvolatile memory circuit is performed. A semiconductor integrated circuit that performs at a set write time. A semiconductor integrated circuit comprising a writable nonvolatile memory circuit,
A dummy data write operation to a dummy area in the nonvolatile memory circuit is performed or a circuit having a load equivalent to a load in the write operation to the nonvolatile memory circuit is operated and a power supply voltage is detected and detected. A semiconductor integrated circuit that performs a write operation of desired data to a desired region of the nonvolatile memory circuit when a power supply voltage is equal to or higher than a predetermined threshold. A semiconductor integrated circuit comprising a writable nonvolatile memory circuit,
A dummy data write operation to a dummy area in the nonvolatile memory circuit is performed or a circuit having a load equivalent to a load in the write operation to the nonvolatile memory circuit is operated and a power supply voltage is detected and detected. When the power supply voltage is equal to or higher than a predetermined threshold, a predetermined first time is set as a write time to the nonvolatile memory circuit, and when the detected power supply voltage is smaller than the predetermined threshold, the first A semiconductor that sets a predetermined second time longer than the time as a write time to the nonvolatile memory circuit and performs a write operation of desired data to a desired region of the nonvolatile memory circuit with the set write time Integrated circuit.

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