TW202018768A - Device substrate and manufacturing mehod thereof - Google Patents

Abstract

A device substrate and a manufacturing method thereof. The device substrate includes a substrate and a patterned layer. The patterned layer is disposed on the substrate. The patterned layer includes a first area defined by a first photo mask and a second area defined by a second photo mask. The first area includes a first alignment mark. The second area includes a second alignment mark. The first alignment mark and the second alignment mark are adjacent to a boundary of the first area and the second area.

Description

Element substrate and manufacturing method thereof

The present invention relates to an element substrate, and in particular to an element substrate including a patterned layer and a method of manufacturing the same.

As technology advances, the size of display panels also increases year by year. Currently, many film layers in the display panel are formed by a lithography etching process, and in the lithography etching process, a mask is used to define the shape of the film layer. When the size of the display panel exceeds the maximum exposure size of a single mask, multiple masks will be used to complete the exposure process of each yellow light lithography. For example, the shape of one part of the film layer is defined by the first mask, and then the shape of the other part of the film layer is defined by the second mask. However, when using photomask stitching to perform the shadow etching process, the relative positions between different photomasks are difficult to align, which may easily cause the problem of uneven brightness (mura) of the manufactured display panel, and may even correspond to the photomask Lines appear at the splice.

The invention provides a component substrate, which can improve the accuracy of photomask splicing.

The invention provides a method for manufacturing a component substrate, which can improve the accuracy of photomask splicing.

At least one embodiment of the present invention provides an element substrate including a substrate and a patterned layer. The patterned layer is located on the substrate. The patterned layer includes a first area defined by the first mask and a second area defined by the second mask. The first area includes a first alignment mark. The second area includes a second alignment mark. The first alignment mark and the second alignment mark are adjacent to the boundary between the first area and the second area.

At least one embodiment of the present invention provides an element substrate including a substrate and a patterned layer. The patterned layer is located on the substrate. The patterned layer includes a first area, a second area, a third area, and a fourth area. The first area includes a plurality of first alignment marks. The second area includes a plurality of second alignment marks. The third area includes a plurality of third alignment marks. The fourth area includes a plurality of fourth alignment marks. One of the first alignment marks and one of the second alignment marks are adjacent to the junction of the first area and the second area. The other first alignment mark and one of the third alignment marks are adjacent to the junction of the first area and the third area. The other second alignment mark and one of the fourth alignment marks are adjacent to the junction of the second area and the fourth area. The other third alignment mark and the other fourth alignment mark are adjacent to the junction of the third zone and the fourth zone.

At least one embodiment of the present invention provides a method for manufacturing an element substrate, including: providing a substrate; forming a film layer on the substrate; forming a patterned photoresist layer on the film layer; and patterning with the patterned photoresist layer as a mask Film layer to form a patterned layer. The method for forming the patterned photoresist layer includes: forming a photoresist layer on the film layer; a first photoresist area is defined by the first photomask on the photoresist layer; and a second photoresist layer is defined by the second photomask Photoresist area. The first photoresist region includes a plurality of first alignment photoresists. The second photoresist region includes a plurality of second alignment photoresists. One of the first photoresist and one of the second photoresist are adjacent to the junction of the first photoresist region and the second photoresist region.

In order to make the above-mentioned features and advantages of the present invention more obvious and understandable, the embodiments are specifically described below in conjunction with the accompanying drawings for detailed description as follows.

1A to 1H are schematic top views of a manufacturing process of an element substrate 10 according to an embodiment of the invention.

Please refer to FIG. 1A to provide a substrate 100. In some embodiments, the substrate 100 includes a display area AA and a peripheral area BA located on at least one side of the display area AA. In this embodiment, the surrounding area BA surrounds the display area AA as an example, but the invention is not limited thereto. In other embodiments, the peripheral area BA may only be located on one side, two sides, or three sides of the display area AA. In this embodiment, the rectangular substrate 100 is taken as an example, but the invention is not limited thereto. In other embodiments, the shape of the substrate 100 is a triangle, a pentagon, a circle, an ellipse, or other non-rectangular shapes.

Although in this embodiment, the substrate 100 is used as an example in a display device, the invention is not limited to this. In other embodiments, the substrate 100 may also be used in other electronic devices. In other words, the substrate 100 does not necessarily include the display area AA.

Please refer to FIG. 1B, a film layer 110 is formed on the substrate 100. In some embodiments, other components (not shown) may also be included between the substrate 100 and the film layer 110, but the invention is not limited thereto. The film layer 110 is, for example, a conductive material or an insulating material.

1C to 1G are methods for forming a patterned photoresist layer 120' on the film layer 110.

Please refer to FIG. 1C first to form a photoresist layer 120 on the film layer 110. In some embodiments, the method of forming the photoresist layer 120 includes coating, printing, or other suitable methods. The photoresist layer 120 covers, for example, the display area AA and the peripheral area BA.

1D, the first photoresist region R1 is defined by the first photomask M1 on the photoresist layer 120. The first photoresist region R1 includes a plurality of first alignment photoresists K1. In some embodiments, for example, the first photomask M1 is used as a mask to expose part of the photoresist layer 120 to define a first photoresist region R1. In this step, the first photoresist region R1 may not be first developed and baked, but the invention is not limited thereto.

1E, a second photoresist region R2 is defined by the second photomask M2 in the photoresist layer 120, and the second photoresist region R2 is adjacent to the first photoresist region R1. The second photoresist region R2 includes a plurality of second alignment photoresists K2. One of the first photoresist K1 and one of the second photoresist K2 are adjacent to the junction of the first photoresist region R1 and the second photoresist region R2. In some embodiments, for example, the second photomask M2 is used as a mask to expose part of the photoresist layer 120 to define a second photoresist region R2. In this step, the development and baking process of the second photoresist region R2 may not be performed first, but the invention is not limited thereto.

1F, a third photoresist region R3 is defined by the third photomask M3 on the photoresist layer 120, and the third photoresist region R3 is adjacent to the first photoresist region R1. The third photoresist region R3 includes a plurality of third alignment photoresists K3. The other first photoresist K1 and the third photoresist K3 are adjacent to the junction of the first photoresist region R1 and the third photoresist region R3. In some embodiments, for example, the third photoresist layer M3 is used as a mask to expose part of the photoresist layer 120 to define a third photoresist region R3. In this step, the development and baking process of the third photoresist region R3 may not be performed first, but the invention is not limited thereto.

Next, referring to FIG. 1G, a fourth photoresist region R4 is defined by the fourth photomask M4 in the photoresist layer 120, and the fourth photoresist region R4 is adjacent to the second photoresist region R2 and the third photoresist region R3. The fourth photoresist region R4 includes a plurality of fourth alignment photoresists K4. One of the second second photoresist K2 and one of the fourth photoresist K4 are adjacent to the junction of the second photoresist region R2 and the fourth photoresist region R4, and the other third photoresist K3 and the other fourth alignment photoresist K4 are adjacent to the junction of the third photoresist region R3 and the fourth photoresist region R4.

In some embodiments, after performing the exposure process on the photoresist layer 120 with the first photomask M1, the second photomask M2, the third photomask M3, and the fourth photomask M4, a development process is performed on the photoresist layer 120 to A patterned photoresist layer 120' including a first photoresist region R1, a second photoresist region R2, a third photoresist region R3, and a fourth photoresist region R4 is defined. In some embodiments, the patterned photoresist layer 120' is subjected to a baking process after the development process, but the invention is not limited thereto.

In this embodiment, at least part of the first alignment photoresist K1, the second alignment photoresist K2, the third alignment photoresist K3, and the fourth alignment photoresist K4 are located on the display area AA. In this embodiment, the first photoresist K1, the second photoresist K2, the third photoresist K3 and the fourth photoresist K4 are all located on the display area AA. In some embodiments, the peripheral area BA also has a photoresist, but the invention is not limited thereto. In some embodiments, the patterned photoresist layer 120' further includes other members than the photoresist.

Measure the positions of the first photoresist K1, the second photoresist K2, the third photoresist K3 and the fourth photoresist K4 to confirm the first photomask M1, the second photomask M2, Whether the third mask M3 and the fourth mask M4 are aligned during the exposure process. In this way, the accuracy of splicing of the photomask can be improved.

Next, referring to FIG. 1H, the patterned film layer 110 is patterned using the patterned photoresist layer 120' as a mask to form a patterned layer 110'. The method for forming the patterned layer 110' by the patterned film layer 110 includes, for example, etching.

In some embodiments, after the patterned layer 110' is formed, the patterned photoresist layer 120' is selectively removed. The patterned layer 110' is located on the substrate 100. The patterned layer 110' includes a first region R1' defined by the first photomask M1, a second region R2' defined by the second photomask M2, and a third region R3' defined by the third photomask M3 And the fourth region R4' defined by the fourth mask M4. The first region R1', the second region R2', the third region R3' and the fourth region R4' respectively correspond to the first photoresist region R1, the second photoresist region R2, the third photoresist region R3 and the fourth photoresist Location of zone R4.

The first region R1' includes the first alignment mark K1'. The second region R2' includes the second alignment mark K2'. The third region R3' includes the third alignment mark K3'. The fourth region R4' includes the fourth alignment mark K4'. The first alignment mark K1', the second alignment mark K2', the third alignment mark K3' and the fourth alignment mark K4' respectively correspond to the first alignment photoresist K1, the second alignment photoresist K2, The positions of the third alignment photoresist K3 and the fourth alignment photoresist K4. The first alignment mark K1', the second alignment mark K2', the third alignment mark K3', and the fourth alignment mark K4' are located on the display area AA of the substrate 100, for example.

One of the first alignment marks K1' and one of the second alignment marks K2' are adjacent to the junction of the first region R1' and the second region R2'. The other first alignment mark K1' and one of the third alignment marks K3' are adjacent to the junction of the first region R1' and the third region R3'. The other second alignment mark K2' and one of the fourth alignment marks K4' are adjacent to the junction of the second area R2' and the fourth area R4'. The other fourth alignment mark K4' and the other third alignment mark K3' are adjacent to the junction of the third area R3' and the fourth area R4'.

In some embodiments, the positions of the first alignment mark K1', the second alignment mark K2', the third alignment mark K3' and the fourth alignment mark K4' are measured to confirm the first mask M1 Whether the second mask M2, the third mask M3 and the fourth mask M4 are aligned during the exposure process. In this way, the accuracy of splicing of the photomask can be improved.

Although in this embodiment, the first mask M1, the second mask M2, the third mask M3, and the fourth mask M4 define the patterned layer 110', the invention is not limited thereto. In other embodiments, the patterned layer 110' may be defined by more than two photomasks. In other words, the patterned layer 110' may include more than two areas defined by different masks.

In some embodiments, other components are formed before the patterned layer 110' is formed and/or after the patterned layer 110' is formed. In other words, the element substrate 10 may further include other components than the patterned layer 110'.

2A is a schematic top view of an alignment mark and surrounding components according to an embodiment of the invention. FIG. 2A is a partially enlarged view of the display area AA of the substrate 100. FIG. 2B is a schematic cross-sectional view taken along line AA' of FIG. 2A.

2A and 2B, the device substrate 10a includes a substrate 100, a scan line SL, a data line DL, an active device T, a first pixel electrode PE1, and an alignment mark K. The scan line SL, the data line DL, the plurality of active elements T, the first pixel electrode PE1 and the alignment mark K are located on the substrate 100. The data line DL and the scan line SL are interleaved.

The active element T is electrically connected to the scan line SL and the data line DL. The active device T includes a channel layer CH, a gate G, a source S and a drain D. The gate G is electrically connected to the scan line SL. The gate G overlaps the channel layer CH, and a gate insulating layer GI is sandwiched between the gate G and the channel layer CH. The source electrode S and the drain electrode D are located on the gate insulating layer GI, and are electrically connected to the channel layer CH, respectively. The source electrode S is electrically connected to the data line DL. The insulating layer I1 is located on the source S and the drain D. The first pixel electrode PE1 is located on the insulating layer I1, and is electrically connected to the drain electrode D through the opening O of the insulating layer I1. The first pixel electrode PE1 has a plurality of slits t1.

Although in the present embodiment, the active device T is an example of a bottom gate type thin film transistor, the invention is not limited thereto. In other embodiments, the active device T may also be a top gate type or other types of thin film transistors.

In this embodiment, the patterned layer 110' includes an alignment mark K, a data line DL, a source S, and a drain D. The alignment mark K overlaps with the scanning line SL, whereby the loss of aperture ratio can be avoided. The alignment mark K in this embodiment is, for example, the first alignment mark K1', the second alignment mark K2', the third alignment mark K3', and/or the fourth alignment mark K4' of FIG. 1H.

In other embodiments, the alignment mark K belongs to other film layers. For example, the alignment mark K and the scanning line SL belong to the same film layer, and the patterned layer 110' includes the alignment mark K and the scanning line SL. In other embodiments, the alignment mark K and the channel layer CH belong to the same film layer, and the patterned layer 110' includes the alignment mark K and the channel layer CH.

In some embodiments, the position of the alignment mark K is measured to improve the accuracy of reticle stitching.

3 is a schematic top view of an alignment mark and surrounding components according to an embodiment of the invention. It must be noted here that the embodiment of FIG. 3 follows the element numbers and partial contents of the embodiments of FIGS. 2A and 2B, wherein the same or similar reference numbers are used to denote the same or similar elements, and the same technical content is omitted. Instructions. For the description of the omitted parts, reference may be made to the foregoing embodiments, which will not be repeated here.

In this embodiment, the patterned layer 110' of the element substrate 10b includes the first pixel electrode PE1 and the alignment mark K. The alignment mark K includes a second pixel electrode PE2, the second pixel electrode PE2 has a plurality of slits t1, at least part of the side edge of the P1 of the second pixel electrode PE2 is parallel to a first direction E1, and the second pixel At least another part P2 side of the electrode PE2 is parallel to the second direction E2. The first direction E1 is orthogonal to the second direction E2.

The first pixel electrode PE1 and the second pixel electrode PE2 include different shapes. In this embodiment, the alignment mark K further includes an auxiliary mark SK. The auxiliary mark SK is located on the side of the second pixel electrode PE2. The alignment mark K in this embodiment is, for example, the first alignment mark K1', the second alignment mark K2', the third alignment mark K3', and/or the fourth alignment mark K4' of FIG. 1H.

4 is a schematic top view of an alignment mark and surrounding components according to an embodiment of the invention. It must be noted here that the embodiment of FIG. 4 uses the element numbers and partial contents of the embodiment of FIG. 3, wherein the same or similar reference numerals are used to indicate the same or similar elements, and the description of the same technical content is omitted. For the description of the omitted parts, reference may be made to the foregoing embodiments, which will not be repeated here.

In this embodiment, the patterned layer 110' of the element substrate 10c includes the first pixel electrode PE1 and the alignment mark K. The alignment mark K includes a second pixel electrode PE2, the second pixel electrode PE2 has a plurality of slits t2, at least a part of the side edge h1 of the slit t2 is parallel to the first direction E1, and at least a portion of the second pixel electrode PE2 Part of the side P2 is parallel to the second direction E2, and the first direction E1 is orthogonal to the second direction E2. The slit t1 of the first pixel electrode PE1 and the slit t2 of the second pixel electrode PE2 include different shapes.

5 is a schematic top view of an alignment mark and surrounding components according to an embodiment of the invention. It should be noted here that the embodiment of FIG. 5 uses the element numbers and partial contents of the embodiment of FIG. 4, wherein the same or similar reference numerals are used to indicate the same or similar elements, and the description of the same technical content is omitted. For the description of the omitted parts, reference may be made to the foregoing embodiments, which will not be repeated here.

The difference between the element substrate 10d of FIG. 5 and the element substrate 10c of FIG. 4 is that in the slit t2 of the second pixel electrode PE2 of the element substrate 10d, a part of the side h1 parallel to the first direction E1 is longer.

6A and 6B are schematic top views of a manufacturing process of an element substrate 10e according to an embodiment of the invention. It must be noted here that the embodiments of FIGS. 6A and 6B continue to use the element numbers and partial contents of the embodiments of FIGS. 1A to 1H, wherein the same or similar reference numbers are used to indicate the same or similar elements, and the same is omitted Description of technical content. For the description of the omitted parts, reference may be made to the foregoing embodiments, which will not be repeated here.

Please refer to FIGS. 6A and 6B, after the exposure process of the photoresist layer through the first to fourth photomasks, the photoresist layer 120 is developed to define the first photoresist region R1 and the second photoresist The patterned photoresist layer 120' in the region R2, the third photoresist region R3, and the fourth photoresist region R4.

One of the first photoresist K1 and one of the second photoresist K2 are adjacent to the junction of the first photoresist region R1 and the second photoresist region R2. The other first photoresist K1 and the third photoresist K3 are adjacent to the junction of the first photoresist region R1 and the third photoresist region R3. The other second photoresist K2 and the fourth photoresist K4 are adjacent to the junction of the second photoresist region R2 and the fourth photoresist region R4. The other third alignment resist K3 and the other fourth alignment resist K4 are adjacent to the junction of the third photoresist region R3 and the fourth photoresist region R4.

In this embodiment, the junction of the first photoresist region R1 and the second photoresist region R2, the junction of the first photoresist region R1 and the third photoresist region R3, the second photoresist region R2 and the fourth photoresist The junction of the region R4 and the junction of the third photoresist region R3 and the fourth photoresist region R4 are zigzag. At the junction of the first photoresist region R1 and the second photoresist region R2, one first alignment photoresist K1 corresponds to three second alignment photoresist K2, and one first alignment photoresist K1 and three The second alignment photoresist K2 is arranged in a rectangular shape, for example, and constitutes the first alignment unit U1, but the invention is not limited thereto.

At the junction of the third photoresist region R3 and the fourth photoresist region R4, one third photoresist K3 corresponds to three fourth photoresists K4, and one third photoresist K3 and three The fourth alignment photoresist K4 is arranged in a rectangular shape, for example, and constitutes the second alignment unit U2, but the invention is not limited thereto.

At the junction of the first photoresist region R1 and the third photoresist region R3, a third photoresist K3 is set corresponding to three first photoresists K1, and a third photoresist K3 and three The first alignment photoresist K1 is arranged in a rectangular shape, for example, and constitutes the third alignment unit U3, but the invention is not limited thereto.

At the junction of the second photoresist region R2 and the fourth photoresist region R4, one fourth alignment photoresist K4 corresponds to three second alignment photoresist K2, and one fourth alignment photoresist K4 and three The second alignment photoresist K2 is arranged in a rectangular shape, for example, and constitutes a fourth alignment unit U4, but the invention is not limited thereto.

In some embodiments, the positions of the third alignment unit U3 and the fourth alignment unit U4 are measured along the horizontal direction E3. For example, the position of one of the three first alignment photoresists K1 in the third alignment unit U3 and the position of one of the third alignment photoresist K3 are measured along the horizontal direction E3, and along the horizontal The direction E3 measures the position of one of the three second alignment photoresists K2 in the fourth alignment unit U4 and the position of one of the fourth alignment photoresists K4.

In some embodiments, since one of the three first alignment photoresists K1 in the third alignment unit U3, the third alignment photoresist K3 in the third alignment unit U3, and the fourth alignment unit U4 One of the three second alignment photoresists K2 and the fourth alignment photoresist K4 in the alignment unit U4 are on the same horizontal line, so the first alignment can be measured simultaneously along the horizontal direction E3 The positions of the photoresist K1, the second photoresist K2, the third photoresist K3, and the fourth photoresist K4, so only one measurement along the horizontal direction E3 is needed to confirm the first photomask M1 Whether the second mask M2, the third mask M3 and the fourth mask M4 are aligned during the exposure process. In this way, the accuracy of splicing of the photomask can be improved.

In some embodiments, the positions of the first alignment unit U1 and the second alignment unit U2 are measured along the vertical direction E4. For example, measuring the position of one of the three second alignment photoresists K2 in the first alignment unit U1 and the position of one of the first alignment photoresist K1 along the vertical direction E4, and along the vertical The direction E4 measures the position of one of the three fourth alignment resists K4 in the second alignment unit U2 and the position of one of the third alignment resists K3.

In some embodiments, due to one of the three second alignment photoresists K2 in the first alignment unit U1, the first alignment photoresist K1 in the first alignment unit U1, and the second alignment unit U2 One of the three fourth alignment photoresists K4 and the third alignment photoresist K3 in the second alignment unit U2 are located on the same vertical line, so the first measurement can be performed simultaneously along the vertical direction E4 The position of the photoresist K1, the second photoresist K2, the third photoresist K3, and the fourth photoresist K4, so you only need to measure once along the vertical direction E4 to confirm the first photomask Whether M1, the second mask M2, the third mask M3, and the fourth mask M4 are aligned during the exposure process. In this way, the accuracy of splicing of the photomask can be improved.

Referring to FIG. 6B, a patterned film layer is patterned using the patterned photoresist layer 120' as a mask to form a patterned layer 110'.

The patterned layer 110' includes a first region R1' defined by the first photomask M1, a second region R2' defined by the second photomask M2, and a third region R3' defined by the third photomask M3 And the fourth region R4' defined by the fourth mask M4. The first region R1', the second region R2', the third region R3' and the fourth region R4' respectively correspond to the first photoresist region R1, the second photoresist region R2, the third photoresist region R3 and the fourth photoresist Location of zone R4.

At the junction of the first region R1' and the second region R2', one first alignment mark K1' is set corresponding to three second alignment marks K2', and one first alignment mark K1' and three second The alignment marks K2' are arranged in a rectangular shape, for example, and constitute the first alignment unit U1', but the invention is not limited thereto.

At the junction of the third area R3' and the fourth area R4', one third alignment mark K3' corresponds to three fourth alignment marks K4', and one third alignment mark K3' and three fourth The alignment marks K4' are arranged in a rectangular shape, for example, and constitute a second alignment unit U2', but the invention is not limited thereto.

At the junction of the first area R1' and the third area R3', one third alignment mark K3' is set corresponding to three first alignment marks K1', and one third alignment mark K3' and three first alignment marks The alignment marks K1' are arranged in a rectangular shape, for example, and constitute a third alignment unit U3', but the invention is not limited thereto.

At the junction of the second area R2' and the fourth area R4', one fourth alignment mark K4' is set corresponding to three second alignment marks K2', and one fourth alignment mark K4' and three second alignment marks The alignment marks K2' are arranged in a rectangular shape, for example, and constitute a fourth alignment unit U4', but the invention is not limited thereto.

In some embodiments, the positions of the third alignment unit U3' and the fourth alignment unit U4' are measured along the horizontal direction E3. For example, the position of one of the three first alignment marks K1' and the position of one of the third alignment marks K3' in the third alignment unit U3' are measured along the horizontal direction E3, and along The position of one of the three second alignment marks K2' in the fourth alignment unit U4' and the position of one of the fourth alignment marks K4' are measured in the horizontal direction E3.

In some embodiments, due to one of the three first alignment marks K1' in the third alignment unit U3', the third alignment mark K3', the fourth alignment in the third alignment unit U3' One of the three second alignment marks K2' in the unit U4' and the fourth alignment mark K4' in the alignment unit U4' are located on the same horizontal line, therefore, it can be measured simultaneously along the horizontal direction E3 The positions of the first alignment mark K1', the second alignment mark K2', the third alignment mark K3', and the fourth alignment mark K4', therefore, only the measurement along the horizontal direction E3 can confirm the first Whether the mask M1, the second mask M2, the third mask M3, and the fourth mask M4 are aligned during the exposure process. In this way, the accuracy of splicing of the photomask can be improved.

In some embodiments, the positions of the first alignment unit U1' and the second alignment unit U2' are measured along the vertical direction E4. For example, the position of one of the three second alignment marks K2' and the position of one of the first alignment marks K1' in the first alignment unit U1' are measured along the vertical direction E4, and along The position of one of the three fourth alignment marks K4' and the position of one of the third alignment marks K3' in the second alignment unit U2' are measured in the vertical direction E4.

In some embodiments, the positions of the first alignment mark K1', the second alignment mark K2', the third alignment mark K3' and the fourth alignment mark K4' can be measured simultaneously along the vertical direction E4 Therefore, it is only necessary to measure along the vertical direction E4 to confirm whether the first mask M1, the second mask M2, the third mask M3, and the fourth mask M4 are aligned during the exposure process. In this way, the accuracy of splicing of the photomask can be improved.

Although the present invention has been disclosed as above with examples, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be subject to the scope defined in the appended patent application.

10, 10a, 10b, 10c, 10d, 10e: element substrate 100: substrate 110: film layer 110': patterned layer 120: photoresist layer 120': patterned photoresist layer AA: display area BA: peripheral area CH: Channel layer D: Drain pole DL: Data lines E1, E2, E3, E4: Direction G: Gate GI: Gate insulation layer h1: Part of the side I1: Insulation layer K: Alignment mark K1: First alignment resist K2: Second alignment photoresist K3: Third alignment photoresist K4: Fourth alignment photoresist K1': First alignment mark K2': Second alignment mark K3': Third alignment mark K4' : Fourth alignment mark M1: First mask M2: Second mask M3: Third mask M4: Fourth mask O: Opening P1, P2: Part PE1: First pixel electrode PE2: Second picture Element electrode R1: first photoresist area R2: second photoresist area R3: third photoresist area R4: fourth photoresist area R1': first area R2': second area R3': third area R4' : Fourth zone S: source SL: scan line SK: auxiliary mark T: active element t1, t2: slit U1, U1': first alignment unit U2, U2': second alignment unit U3, U3' : Third alignment unit U4, U4': Fourth alignment unit

1A to 1H are schematic top views of a manufacturing process of an element substrate according to an embodiment of the invention. 2A is a schematic top view of an alignment mark and surrounding components according to an embodiment of the invention. FIG. 2B is a schematic cross-sectional view taken along line AA' of FIG. 2A. 3 is a schematic top view of an alignment mark and surrounding components according to an embodiment of the invention. 4 is a schematic top view of an alignment mark and surrounding components according to an embodiment of the invention. 5 is a schematic top view of an alignment mark and surrounding components according to an embodiment of the invention. 6A and 6B are schematic top views of a manufacturing process of an element substrate according to an embodiment of the invention.

10: component substrate

110’: Patterned layer

AA: display area

BA: surrounding area

K1’: First alignment mark

K2’: Second alignment mark

K3’: Third alignment mark

K4’: Fourth alignment mark

R1’: District 1

R2’: District 2

R3’: District 3

R4’: District 4

Claims (19)

An element substrate, comprising: a substrate; and a patterned layer on the substrate, the patterned layer includes a first area defined by a first photomask and a first area defined by a second photomask Two areas, wherein the first area includes a first alignment mark, and the second area includes a second alignment mark, the first alignment mark and the second alignment mark are adjacent to the first area and The junction of this second zone. The device substrate as described in item 1 of the patent application scope further includes: a scanning line located on the substrate; and the patterned layer further includes a data line intersecting the scanning line, the first alignment The mark overlaps the scan line. The element substrate as described in item 1 of the patent application range, wherein the first alignment mark and the second alignment mark each include: a pixel electrode having a plurality of slits, at least part of the sides of the pixel electrode It is parallel to a first direction, and at least another side of the pixel electrode is parallel to a second direction, and the first direction is orthogonal to the second direction. The element substrate according to item 1 of the patent application scope, wherein the first alignment mark and the second alignment mark each include: a pixel electrode having a plurality of slits, at least part of the sides of which are parallel In a first direction, and at least part of the sides of the pixel electrode are parallel to a second direction, and the first direction is orthogonal to the second direction. The element substrate as described in item 1 of the patent application scope, wherein the first alignment mark and the second alignment mark each include: a pixel electrode having a plurality of slits; and an auxiliary mark located on the pixel One side of the electrode. The device substrate as claimed in item 1 of the patent application range, wherein the substrate includes a display area and a peripheral area on at least one side of the display area, and the first alignment mark and the second alignment mark are located on the display area . An element substrate, comprising: a substrate; and a patterned layer on the substrate, the patterned layer includes a first area, a second area, a third area, and a fourth area, wherein the first area Including multiple first alignment marks, the second area includes multiple second alignment marks, the third area includes multiple third alignment marks, and the fourth area includes multiple fourth alignment marks, one of which The first alignment mark and one of the second alignment marks are adjacent to the junction of the first area and the second area, wherein the other first alignment mark and one of the third alignment marks are adjacent to the first The junction of the first zone and the third zone, where another second alignment mark and one of the fourth alignment marks are adjacent to the junction of the second zone and the fourth zone, and the other third alignment The mark and the other fourth alignment mark are adjacent to the junction of the third zone and the fourth zone. The element substrate as described in item 7 of the patent application scope, wherein the junction of the first zone and the second zone, the junction of the first zone and the third zone, the junction of the second zone and the fourth zone The junction and the junction of the third zone and the fourth zone are jagged. The element substrate as described in item 7 of the patent application scope, wherein: at the junction of the first area and the third area, one of the third alignment marks corresponds to three of the first alignment marks; At the junction of the second zone and the fourth zone, one of the fourth alignment marks corresponds to three of the second alignment marks. The component substrate as claimed in item 9 of the patent application scope, wherein one of the third alignment marks, one of the three first alignment marks, the one of the fourth alignment marks, and the three of them One of the third alignment marks is on the same horizontal line. A method for manufacturing an element substrate, comprising: providing a substrate; forming a film layer on the substrate; forming a patterned photoresist layer on the film layer, and forming the patterned photoresist layer method includes: forming a photoresist A layer on the film layer; a first photoresist region is defined by a first photomask on the photoresist layer, wherein the first photoresist region includes a plurality of first alignment photoresists; and a second photoresist A second photoresist region is defined on the photoresist layer, wherein the second photoresist region includes a plurality of second pararesistances, one of the first pararesistance and one of the second pararesistances Adjacent to the junction of the first photoresist region and the second photoresist region; and patterning the film layer with the patterned photoresist layer as a mask to form a patterned layer. According to the manufacturing method described in item 11 of the patent application scope, the method of forming the patterned photoresist layer further includes: a third photoresist area is defined by a third photomask on the photoresist layer, wherein the third light The resist area includes a plurality of third-position photoresists, wherein another first-position photoresist and one of the third-position photoresist are adjacent to the junction of the first photoresist area and the third photoresist area; And a fourth photoresist layer defines a fourth photoresist region in the photoresist layer, wherein the fourth photoresist region includes a plurality of fourth alignment resists, and another second alignment resist and one of them The fourth photoresist is adjacent to the junction of the second photoresist region and the fourth photoresist region, and another third photoresist is adjacent to the fourth photoresist The junction between the third photoresist area and the fourth photoresist area. The manufacturing method as described in item 12 of the patent application scope, wherein the junction of the first photoresist region and the second photoresist region, the junction of the first photoresist region and the third photoresist region, the first The junction between the second photoresist area and the fourth photoresist area and the junction between the third photoresist area and the fourth photoresist area are zigzag. The manufacturing method as described in item 13 of the patent application scope, wherein: at the junction of the first photoresist region and the third photoresist region, one of the third photoresist corresponds to three of the first photoresist Photoresist setting; at the junction of the second photoresist region and the fourth photoresist region, the one of the fourth alignment photoresist corresponds to three of the second alignment photoresist settings. The manufacturing method as described in item 14 of the patent application scope further includes: measuring the position of one of the three first-aligned photoresists and the three second-aligned photoresists along a horizontal direction The position of one of the one, the position of the one of the third alignment resist and the position of the one of the fourth alignment resist. The manufacturing method as described in item 11 of the patent application scope, wherein the patterned layer includes a first area defined by the first photomask and a second area defined by the second photomask, wherein the first A region includes a plurality of first alignment marks corresponding to the first alignment resists, and a second region includes a plurality of second alignment marks corresponding to the second alignment resists, one of the first pairs The bit mark and one of the second alignment marks are adjacent to the junction of the first area and the second area. The manufacturing method as described in Item 16 of the scope of the patent application further includes: measuring the positions of the one of the first alignment marks and the one of the second alignment marks. The manufacturing method described in item 11 of the scope of the patent application further includes: measuring the positions of the one of the first alignment photoresist and the one of the second alignment photoresist. The manufacturing method as described in item 11 of the patent application scope, wherein after the patterned layer is formed, it further includes removing the patterned photoresist layer.

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