TW202015065A - Error handling method, associated data storage device and controller thereof - Google Patents

Abstract

An error handling method, an associated data storage device and the controller thereof are provided. The error handling method may include: uploading an error handling program to a buffer memory equipped with Error Correction Code (ECC) protection capability; in response to at least one error, interrupting execution of a current procedure and activating an interrupt service; executing the error handling program on the buffer memory; disabling a transmission interface circuit; resetting at least one hardware engine and at least one NV memory element; performing cache rearrangement regarding a data cache within the data storage device, and programming rearranged cache data into the NV memory element, to perform data recovery; and through activating a watchdog module and the transmission interface circuit and relinking with a host device, completing soft reset to make the data storage device operate normally again.

Description

Error handling method, data storage device and its controller

The present invention relates to the access of flash memory, especially an error handling method and related data storage device and its controller.

Flash memory can be widely used in various portable or non-portable data storage devices (for example: memory cards that comply with SD/MMC, CF, MS, XD or UFS standards; for example: solid-state hard drives; for example : Embedded storage devices that meet UFS or EMMC specifications). In terms of commonly used NAND flash memory, there are initially single-level cells (SLC), multiple-level cells (MLC) and other types of flash memory. Due to the continuous development of memory technology, newer data storage device products can use triple level cell (TLC) flash memory, or even quadruple level cell (QLC) flash memory. In order to ensure that the data storage device's access control to the flash memory can meet the relevant specifications, the controller of the flash memory is usually equipped with certain management mechanisms to properly manage its internal operations.

According to related technologies, the data storage devices with these management mechanisms still have deficiencies. For example, as the density of devices in semiconductor manufacturing becomes higher and higher, the incidence of soft errors becomes higher. When a soft error occurs, it is often accompanied by a bit flip error. Some suggestions have been made in the related art to try to avoid this situation from getting worse. Regardless of which of these suggestions is adopted, when the number of error bits exceeds the range that can be corrected by a certain error correction mechanism, the traditional architecture typically controls the data storage device to enter a system halt state to prevent various unpredictable Error occurred further. However, such control of the traditional architecture must make the entire data storage device unable to continue to operate, and greatly increase the risk of user data loss (data loss). Therefore, there is a need for a novel method and related architecture to implement a data storage device with a reliable management mechanism without side effects or less likely to cause side effects.

An object of the present invention is to provide an error handling method and related data storage device and its controller to solve the above problems.

Another object of the present invention is to provide an error handling method and related data storage device and its controller, so as to give a reliable management mechanism to the data storage device without side effects or less likely to cause side effects.

At least one embodiment of the present invention provides an error handling method, wherein the error handling method is applied to a data storage device including a non-volatile memory (NV memory) and used to control A memory controller for accessing the non-volatile memory, the non-volatile memory includes at least one non-volatile memory element (NV memory element), and the at least one non-volatile memory element includes a plurality of blocks . The error handling method may include: uploading an error handling program (upload) to a buffer memory with error correction code (ECC) protection capability, wherein the buffer memory system is located in the memory controller; At least one error, interrupt the execution of the current program and start the interrupt service; execute the error handling program on the buffer memory; disable a transmission interface circuit, wherein the transmission interface circuit is located in the memory controller, And is used to communicate with a host device; reset at least one hardware engine and the at least one non-volatile memory component; perform a cache refresh on a data cache in the data storage device, and Programming the refreshed cached data to the at least one non-volatile memory component for data recovery; and by activating one of the watchdog modules in the memory controller and activating the transmission interface The circuit is reconnected with the host to complete a soft reset, so that the data storage device operates normally again.

At least one embodiment of the present invention provides a data storage device, which may include: a non-volatile memory for storing information, wherein the non-volatile memory includes at least one non-volatile memory element, and the at least one non-volatile memory element The volatile memory element includes a plurality of blocks; and a controller, coupled to the non-volatile memory, is used to control the operation of the data storage device. The controller may include a buffer memory for temporarily storing information; a transmission interface circuit conforming to a specific communication standard for communicating according to the specific communication standard; and a processing circuit, wherein the processing circuit may be based on A plurality of host commands of a host device control the controller to allow the host to access the non-volatile memory through the controller. For example: the controller uploads an error handling program to the buffer memory with error correction code (ECC) protection capability; in response to at least one error, the controller interrupts the execution of the current program and starts the interrupt service; the controller executes the Buffer the error handling program on the memory; the controller disables the transmission interface circuit, wherein the transmission interface circuit is used to communicate with the host; the controller resets at least one hardware engine and the at least one non-volatile A memory component; the controller performs a cache refresh on one of the data caches in the data storage device, and programs the refreshed cache data to the at least one non-volatile memory component for data recovery; And the controller completes the soft reset by activating one of the watchdog modules in the memory controller, and activating the transmission interface circuit and reconnecting with the host, so that the data storage device operates normally again .

At least one embodiment of the present invention provides a controller for a data storage device, wherein the data storage device includes the controller and a non-volatile memory, the non-volatile memory includes at least one non-volatile memory element, and the above At least one non-volatile memory device includes a plurality of blocks. The controller may include a buffer memory for temporarily storing information; a transmission interface circuit conforming to a specific communication standard for communicating according to the specific communication standard; and a processing circuit, wherein the processing circuit may be based on A plurality of host commands of a host control the controller to allow the host to access the non-volatile memory through the controller. For example: the controller uploads an error handling program to the buffer memory with error correction code (ECC) protection capability; in response to at least one error, the controller interrupts the execution of the current program and starts the interrupt service; the controller executes the Buffer the error handling program on the memory; the controller disables the transmission interface circuit, wherein the transmission interface circuit is used to communicate with the host; the controller resets at least one hardware engine and the at least one non-volatile A memory component; the controller performs a cache refresh on one of the data caches in the data storage device, and programs the refreshed cache data to the at least one non-volatile memory component for data recovery; And the controller completes the soft reset by activating one of the watchdog modules in the memory controller, and activating the transmission interface circuit and reconnecting with the host, so that the data storage device operates normally again .

One of the advantages of the present invention is that, through a carefully designed management mechanism, the present invention can properly control the operation of the controller, in particular, enable the data storage device to repair itself when a soft error occurs, such as When the data storage device is subject to interference (eg, radiation, noise, etc.). Since the data storage device can repair itself when a soft error occurs, the present invention can reduce the soft error rate (SER), and can also extremely reduce the risk of user data loss. In addition, implementation according to the embodiments of the present invention does not increase many additional costs. Therefore, the problems of the related art can be solved without increasing the overall cost much. Compared with the traditional architecture, the present invention can achieve the optimized performance of the data storage device without side effects or less likely to cause side effects.

Please refer to FIG. 1, which is a schematic diagram of a data storage device 100 and a host device 50 according to a first embodiment of the present invention. For example, the data storage device 100 may be a solid state drive (SSD). In addition, examples of the host 50 may include (but are not limited to): multifunctional mobile phones, tablet computers, and personal computers such as desktop computers and laptop computers. According to this embodiment, the data storage device 100 may include a controller such as a memory controller 110, and may further include a non-volatile memory (NV memory) 120, wherein the controller is used to store The non-volatile memory 120 is accessed, and the non-volatile memory 120 is used to store information.

The non-volatile memory 120 may include a plurality of non-volatile memory elements (NV memory elements) 122-1, 122-2, ..., and 122-N, where the symbol "N" may represent a positive integer greater than one. For example, the non-volatile memory 120 may be a flash memory, and the non-volatile memory elements 122-1, 122-2, ..., and 122-N may be a plurality of flash memory chips, respectively. (Flash memory chip; may be referred to as flash chip) or a plurality of flash memory die (Flash memory die; may be referred to as flash die), but the invention is not limited thereto. In addition, the data storage device 100 may further include a volatile memory element 130 for data buffering, wherein the volatile memory element 130 is preferably a dynamic random access memory (Dynamic Random Access Memory, DRAM for short). Under the control of the memory controller 110, the data storage device 100 may use at least a portion (eg, part or all) of the storage space of the volatile memory element 130 as a data buffer space for temporarily storing data, for example, during access The period of non-volatile memory 120. In addition, the volatile memory element 130 is an unnecessary element.

The memory controller 110 may include a processing circuit such as a microprocessor 112, a storage such as a read-only memory (Read Only Memory, ROM) 112M, a control logic circuit 114, a buffer memory 116, and a transmission interface circuit 118, of which The components can be coupled to each other through a bus bar. The buffer memory 116 is preferably a static random access memory (SRAM). For example, the memory controller 110 may use the buffer memory 116 such as SRAM as the first layer cache and the volatile memory element 130 such as DRAM as the second layer cache. The data storage capacity of the DRAM is preferably greater than the data storage capacity of the buffer memory 116, and the data buffered by the buffer memory 116 may originate from the DRAM or the non-volatile memory 120.

The read-only memory 112M of this embodiment is used to store a code 112C, and the microprocessor 112 is used to execute the code 112C to control access to the non-volatile memory 120. Please note that the code 112C must also be stored in the buffer memory 116 or any form of memory. In addition, the control logic circuit 114 may include at least one Error Correction Code (ECC) circuit (not shown) to protect data and/or perform error correction, and the transmission interface circuit 118 may conform to a specific communication standard ( Such as Serial Advanced Technology Attachment (SATA) standard, Peripheral Component Interconnect Express (PCIE) standard or Non-Volatile Memory Express (NVME) standard) and can be based on The specific communication standard communicates, and in particular, the host 50 can be communicated according to the specific communication standard.

In this embodiment, the host 50 can send a plurality of host commands (Host Command) to the data storage device 100, and the memory controller 110 can access the non-volatile memory 120 according to the host commands (such as reading or writing Data), wherein the above data is preferably user data derived from the host 50. The host command includes a logical address, for example: logical block address (Logical Block Address). The memory controller 110 can receive host commands and translate the host commands into memory operation commands (abbreviated as operation commands), and then use the operation commands to control the non-volatile memory 120 to read, write/program A page with a specific physical address in the non-volatile memory 120. The memory controller 110 records the mapping relationship between the logical address of the data and the physical address in a logical-to-physical address mapping table ("L2P mapping table"), in which The address can be composed of Channel number, Logical Unit Number (LUN), Plane number, Block number, Page number, and Offset. In some embodiments, the implementation of the physical address may be changed. For example, the physical address may include channel number, logical unit number, plane number, block number, page number, and/or offset.

The L2P mapping table can be stored in a system block in the non-volatile memory 120, and can be divided into multiple group (Group) mapping tables. The system block is preferably an encrypted block and the data is processed in SLC mode Programming. The memory controller 110 may load part or all of the plurality of group mapping tables from the non-volatile memory 120 into the buffer memory 116 according to the capacity of the buffer memory 116 for quick reference , But the invention is not limited to this. When the user data is updated, the memory controller 110 may update the group mapping table according to the latest mapping relationship of the user data. The size of any group mapping table in the plurality of group mapping tables is preferably equal to the size of one page of the non-volatile memory element 122-n, for example, 16KB (kilobytes; kilobytes), where the symbol "N" can represent any positive integer in the interval [1, N], but the invention is not limited thereto. The size of any of the above group mapping tables may also be smaller than the size of the page, such as 4KB or 1KB. Of course, the size of any of the above group mapping tables can also be equal to the size of one page of multiple non-volatile memory elements 122, for example, in the case of N = 4, one page of 4 non-volatile memory elements 122 The size is 64KB, and the pages of the four non-volatile memory elements 122 may also be called super pages.

In addition, the smallest unit for the memory controller 110 to program the non-volatile memory 120 may be one page, and the smallest unit for the memory controller 110 to perform the erase operation for the non-volatile memory 120 may be A block. Each block of the plurality of blocks of the non-volatile memory device 122-n includes a plurality of pages.

In the Write Cache mode, the host 50 can issue a write command to request the memory controller 110 to write a piece of user data (referred to as data) to the non-volatile memory 120. The memory controller 110 can receive or download the pen data from the host 50, use the buffer memory 116 to buffer the pen data, and use the volatile memory element 130 to cache the pen data, and then directly reply to the write command to execute The completed message is sent to the host 50. After that, when the writing condition is satisfied, for example, the accumulated data length is equal to or greater than the page length or the super page length, the memory controller 110 then writes the cached data to the data of the non-volatile memory 120.

The microprocessor 112 of the memory controller 110 can perform cache allocation of the data cache, and update the cache head H and cache of the data cache according to the configuration operation and/or related operations The address of the cache tail T is shown in Figure 2, where the cache head H and the cache tail T can be regarded as the cache configuration parameters of the data cache. The horizontal axis shown in the lower part of Figure 2 represents a cache range. Taking the volatile memory device 130 as an example of the above data cache, the cache area corresponds to the cache address range. For the cache address range, the memory controller 110 (for example, the microprocessor 112) allocates the cache space of the volatile memory element 130 in units of 4 KB, for example, according to a predetermined order, for example, by From left to right, the cache space of the volatile memory device 130 is configured. For any two address values in the cache address range, the left address value is smaller than the right address value, but the present invention does not Limited to this.

The microprocessor 112 uses the cache space of the volatile memory element 130 in a cyclic manner, so the cache address range can be regarded as a cyclic address range, and the cache range corresponding to the cache address range can be regarded as a cyclic range. When the microprocessor 112 caches 4 KB of data, the microprocessor 112 moves (from left to right) the address of the cache head H in basic increments (for example, 1), so that the cache head H is moved before The cache space between and after the move can store 4 KB cache data.

The microprocessor 112 configures a First-In First-Out (FIFO) buffer for a piece of 4 KB data of the volatile memory element 130, and the piece of 4 KB data will be written to the non-volatile memory 120. When the configuration of the first-in first-out buffer is completed, the microprocessor 112 moves (from left to right) the cache tail T in basic increments (for example, 1) to update the cache tail T to correspond to the next stroke to be written Load 4KB of data into non-volatile memory 120. In short, the range between the cache head H and the cache tail T is cached data (cache data for short), the remaining cache space is blank or invalid data is stored, and the microprocessor 112 can write the data Enter the blank cache space.

According to some embodiments, the at least one ECC circuit may include a plurality of ECC circuits such as a plurality of ECC engines. The plurality of ECC circuits can generate parity codes (Parity Code) of the data according to a plurality of procedures (Procedure), respectively, and/or correct errors of the data according to the parity codes. In particular, a plurality of ECC circuits can be operated in parallel, so the memory controller 110 (such as the microprocessor 112) can assign a plurality of programs to the plurality of ECC circuits, but the invention is not limited thereto.

In some embodiments, the buffer memory 116 may be used to store important information. Examples of important information may include (but not limited to): user data originating from the host 50, instructions and data of specific program codes, etc. .

FIG. 3 shows a flowchart of an error handling method according to an embodiment of the present invention. This error handling method can be applied to the data storage device 100 and executed by the memory controller 110 of the data storage device 100 In addition, error handling can be performed for soft errors (Soft Error) generated during the operation of the data storage device 100. The error handling method of the present invention enables the data storage device 100 to repair errors and perform a soft reset (Soft Reset), so that the data storage device 100 can quickly return to work in the normal mode.

In the following, the error handling method of the present invention can be divided into three major steps. Steps S10 to S18 can be collectively referred to as the initial steps of the error handling method of the present invention, and steps S20 to S30 can be collectively referred to as data recovery of the error handling method of the present invention ( Recovery) steps, steps S40 ~ S44 can also be collectively referred to as the system recovery step of the error handling method of the present invention, the description of each step is as follows.

In step S10, the memory controller 110 uploads the error handling program to the buffer memory 116. The buffer memory 116 preferably has ECC protection capabilities, in particular, the ability to correct errors based on parity codes. For example, the buffer memory 116 can generate the parity code by itself to protect the error handling program; or, the ECC circuit generates the parity code for the error handling program, and the memory controller 110 uploads the error handling program and the parity code together (upload ) To the buffer memory 116. Since the buffer memory 116 has ECC protection capability, the error handling program can be effectively protected.

In step S11, the memory controller 110 determines whether a soft error has occurred, and if so, step S12 is executed, and if not, step S11 is repeatedly executed. Among them, soft errors include errors generated by the execution of hardware components or firmware (Firmware), after which, the error handling program will be used for error handling instead of the traditional system reboot (Reboot) method for error handling. The memory controller 110 preferably uses a built-in error detection circuit to determine whether a soft error is generated; if the memory controller 110 has multiple cores, one of the multiple cores can be used to determine whether to generate a soft error Soft errors.

FIG. 4 shows implementation details about how the memory controller 110 determines whether a soft error is generated according to an embodiment of the present invention. For example, the hardware architecture of the microprocessor 112 can use reduced instruction set calculation (Reduced Instruction Set Computing (RISC) architecture, such as Argonaut RISC Core (ARC) architecture, can be implemented with built-in instruction Close Coupled Memory (ICCM) and data The near-end is coupled to a memory (Data Close Coupled Memory, DCCM for short), but the invention is not limited thereto. The microprocessor 112 can control the operation of the SATA PHY circuit through a SATA controller (such as a SATA controller engine), and can control related circuits in the logic circuit 114 through a flash memory controller (such as a flash memory controller engine) in the control logic circuit 114. (For example: an input-output interface circuit for interfacing the non-volatile memory 120, the at least one ECC circuit, etc.). Examples of causes of soft errors include:

(A) Host command 1 second timeout (Host command 1 second timeout), which may include: (1) Time-out condition #1: DRAM or ARC DCCM variable (Variable) error causes the firmware to stop (Firmware Halt); (2) Time-out condition #2: An abnormal halt of the hardware system, SATA controller engine, or flash controller engine occurs; and (3) Time-out condition #3: ICCM code address mapping (Address Mapping) error, where ICCM code address mapping error and ICCM code command (exception) error also belong to ICCM code error;

(B) ICCM code instruction (exception) error, such as ICCM code instruction error, ICCM code instruction exception error, and/or ICCM code exception error; and

(C) Uncorrectable ECC error (UECC error), such as UECC error of SRAM or UECC error of DRAM, which means that the data stored in SRAM or DRAM cannot be corrected according to the corresponding parity code, and then generated UECC error.

In step S12, the memory controller 110 interrupts the execution of the current program and starts the interrupt service. When any of the above types of soft errors is detected, the microprocessor 112 records the current program execution address, interrupts the currently running program, and jumps from the execution address to the corresponding interrupt service routine (Interrupt Service Routine, ISR) to start the interrupt service, where one or more soft errors can correspond to an interrupt service routine. For example, an ISR, such as an interrupt handler, can be invoked by an interrupt request from the hardware architecture (Invoke) to forward the interrupt request to the microprocessor 112 to interrupt the currently running program.

In step S14, the memory controller 110 executes an error handling program on the buffer memory 116. The memory controller 110 jumps from the execution address of the current program to the beginning of the error processing program to execute the error processing program.

In step S16, the memory controller 110 disables the transmission interface circuit 118, in particular, the SATA PHY circuit, in which the SATA controller and the SATA PHY circuit are located in the transmission interface circuit 118. According to this embodiment, the memory controller 110 disables the transmission interface circuit 118 to stop the reception and transmission of data to the host 50, including the reception and transmission of data, commands, and acknowledgment (Acknowledgement, ACK) messages, to avoid increasing the number of errors.

In step S18, the memory controller 110 resets at least one hardware engine (eg, one or more hardware engines) and the non-volatile memory element 122 such as a flash memory element (eg, flash chip or flash bare) crystal). The memory controller 110 can reset the at least one hardware engine by resetting the ECC engine, the SATA controller engine, and/or the flash controller engine, and the non-volatile memory element 122 can be reset. The hardware engine and the non-volatile memory element 122 can be restored to a normal state, and can also prevent the erroneous operation of the hardware engine from causing data to be unrecoverable. In addition, the at least one hardware engine may include a hardware engine in which a soft error occurs. If the memory controller 110 can determine the source of the soft error, for example, the source of the soft error is the abnormal stop of the SATA controller engine, then only the SATA controller engine can be reset.

Next, the memory controller 110 may perform a cache refresh as shown in FIG. 5 for the data cache in the data storage device 100 (for example, the volatile memory element 130 such as DRAM), and the refreshed cache The data is retrieved and programmed into the non-volatile memory element 122 for data recovery, but the invention is not limited thereto.

In step S20, the memory controller 110 reallocates the cache data of the volatile memory element 130. To avoid the loss of cache data, the memory controller 110 reconfigures the cache data of the volatile memory element 130 to the FIFO buffer and prepares to write the cache data to the non-volatile memory element 122 such as flash Memory components. In order to increase the efficiency of step S20, the memory controller 110 may relocate the cache data of only one page in the volatile memory element 130 based on the address of the cache tail T, for example, 4KB to the left of the cache tail T Cache data, that is, the basic increment is equal to 1; or, you can reconfigure the cache data of only one Super Page in the volatile memory element 130, that is, the basic increment is equal to 4, for example, the left side of the cache tail T 16KB cache data; or, you can only reconfigure the cache data of a Super String in the volatile memory element 130, that is, the basic increment is equal to 12, for example, the 48KB cache to the left of the cache tail T Data to the FIFO buffer. Therefore, regardless of the size of the reconfiguration range in step S20 (marked "reconfiguration range" in Figure 5, next to the cache tail T), the memory controller 110 can enable the reconfigured cache data Cache data, such as 4KB, 16KB, or 48KB, is prepared in the FIFO buffer to prepare 4KB, 16KB, or 48KB cache data to be written to the non-volatile memory element 122 such as a flash memory element.

In step S22, the memory controller 110 determines whether there is a triggered write command (Triggered Write Command), if it is, step S24 is executed, and if not, step S26 is executed. After the write command in the host command is triggered, the volatile memory element 130 should configure an appropriate cache space to buffer the data from the host 50. For example, the above-mentioned triggered write command may represent at least one write command received from the host 50. When the at least one write command is triggered, the volatile memory device 130 is expected to configure an appropriate cache space to buffer the data from the host 50, but this expected configuration operation may not be performed due to some previous steps . In this case, proceed to step S24 to ensure that this expected configuration operation is performed.

In step S24, the memory controller 110 allocates the cache space of the volatile memory element 130 according to the triggered write command, for example, from the original position of the cache head H. When a write command is triggered, the memory controller 110 moves the cache head H to the right, and makes the right shift amount of the cache head H correspond to the number of write commands triggered or the amount of data. For example, the three pieces of data corresponding to the three triggered write commands may be a total of 12 KB of data to be written. In this case, the microprocessor 112 can configure a local cache space of 12 KB on the volatile memory element 130, and the cache head H is shifted to the right by the basic increment (for example, 1) 3 times ((12 KB / 4 KB ) = 3) to update the address of cache header H. For another example, the two pieces of data corresponding to the two triggered write commands may be a total of 32 KB of data to be written. In this case, the microprocessor 112 can configure a local cache space of 32 KB on the volatile memory element 130, and the cache head H moves to the right by the basic increment (for example, 4) 2 times ((32 KB / 16 KB ) = 2) to update the address of cache header H.

In step S26, the memory controller 110 determines whether the data has not been transferred to the volatile memory device 130 such as DRAM. If yes, step S28 is executed; if not, step S30 is executed. Since the SATA PHY circuit has been disabled in step S16, the data transmission of the SATA PHY circuit has been terminated. Therefore, it is possible that the write command has been triggered, but part of the data of the write command has not been buffered to volatile In the memory device 130, therefore, the cache head H needs to be appropriately corrected so that the cache head H points to valid cache data.

In step S28, the memory controller 110 re-synchronizes the cache space of the volatile memory element 130, for example, pulls the cache head H back and points to the valid cache data, such as the last Buffered data. The memory controller 110 knows the data transfer amount corresponding to the triggered write command according to the return of the SATA PHY circuit. This data transfer amount is the data amount of the cache data, and the memory controller 110 corrects the data amount according to the data amount. The amount of movement of the cache head H. In particular, the correction amount (left shift amount) of the cache head H in the resynchronization operation is determined based on this data amount. For example, the cache head H was originally moved right by a basic increment of 3 times, but the amount of cache data is only 2, and the difference value is 1. Therefore, the memory controller 110 moves the cache head H to the left by a basic increment.

In step S30, the memory controller 110 programs the cache data (in particular, the refreshed cache data described above) to the non-volatile memory element 122, wherein the cache data is preferably programmed to non-volatile in the SLC mode Flushing block in the sexual memory element 122. The fast flash block is selected from idle blocks in the non-volatile memory element 122, and is mainly used for writing data in an emergency. The memory controller 110 selects a flash block (similar to an active block), and programs the cache data to the flash block in units of pages, super pages, or super strings. The memory controller 110 can program the cache data to the flash block in a predetermined programming unit larger than one page. In the case of programming a flash block in units of the predetermined programming unit such as a super page or super string, when the remaining cache data after programming cannot be written to the super page or super string (for example, the remaining cache The data length of the data is less than the predetermined programming unit), the memory controller 110 can combine the remaining cache data with the dummy data (Dummy Data) so that the combined data length is equal to the predetermined programming unit such as a super page or super word String, and then program the remaining cached data and virtual data to the superpage or superstring of the flash block. When the cache data is sequentially programmed to the flash block, the address of the cache head H does not change, and the address of the cache tail T gradually moves to the right. When all the cache data is programmed into the flash block, The address of the cache header H is equal to the address of the cache tail T. When the execution of step S30 is completed, the cache data are all stored in the non-volatile memory element 122.

In step S40, the memory controller 110 stores an error log, in particular, records information about a series of events from the occurrence of soft errors in the error log, wherein the error log can be stored in a non-volatile memory 120 in the system block.

In step S42, the memory controller 110 activates the watchdog module in the memory controller 110. For example, the watchdog module may be a watchdog circuit located in the memory controller 110, and the watchdog circuit may include a watchdog timer, in which the microprocessor 112 may start the watchdog timer to Perform a soft reset (Soft Reset). Soft reset is a system reset by software, for example, re-execute the system execution file (or online programming file, In-System Programming File), or clear the system register (Register) To achieve the purpose of system reset, but the invention is not limited to this.

In step S44, the memory controller 110 activates the transmission interface circuit 118 and reconnects with the host 50 (Re-Link). Since the transmission interface circuit 118 has been restarted, the microprocessor 112 can reconnect and interact with the host 50 through the transmission interface circuit 118. Through the operations of steps S42 and S44, the memory controller 110 (for example, the microprocessor 112) can complete the soft reset to make the data storage device 100 operate normally again.

In summary, when an error occurs in the operation of the data storage device 100, by performing the error handling method of the present invention, the data storage device 100 not only avoids the system stop, but also quickly stores the cached data to non-volatile memory The body 120 avoids the loss of cached data, and the data storage device 100 operates normally again through a soft reset method to achieve the purpose of the present invention. In addition, the error handling method of the present invention also stores an error log, which can be used as a basis for system error detection. The above are only the preferred embodiments of the present invention, and all changes and modifications made in accordance with the scope of the patent application of the present invention shall fall within the scope of the present invention.

50: host 100: data storage device 110: memory controller 112: Microprocessor 112C: Code 112M: read-only memory 114: control logic circuit 116: Buffer memory 118: Transmission interface circuit 120: Non-volatile memory 122, 122-1, 122-2, ..., 122-N: non-volatile memory device 130: volatile memory device H: cache head T: Cache tail S10, S11, S12, S14, S16, S18, S20, S22, S24, S26, S28, S30, S40, S42, S44: Steps

FIG. 1 is a schematic diagram of a data storage device and a host device according to an embodiment of the invention. FIG. 2 illustrates a cache allocation scheme according to an embodiment of the invention. FIG. 3 is a flowchart of an error handling method according to an embodiment of the invention. FIG. 4 illustrates implementation details of how the memory controller shown in FIG. 1 determines whether a soft error is generated according to an embodiment of the invention. FIG. 5 illustrates the cache refresh in the error handling method shown in FIG. 3 according to an embodiment of the present invention.

S10, S11, S12, S14, S16, S18, S20, S22, S24, S26, S28, S30, S40, S42, S44: Steps

Claims (20)

An error handling method, the error handling method is applied to a data storage device, the data storage device includes a non-volatile memory (non-volatile memory (NV memory) and used to control the access of the non-volatile memory A memory controller, the non-volatile memory includes at least one non-volatile memory element (NV memory element), the at least one non-volatile memory element includes a plurality of blocks, and the error handling method includes: Uploading an error handling program to a buffer memory with error correction code (ECC) protection capability, wherein the buffer memory system is located in the memory controller; In response to at least one error, interrupt the execution of the current program and start the interrupt service; Execute the error handling program on the buffer memory; Disable a transmission interface circuit, wherein the transmission interface circuit is located in the memory controller and is used to communicate with a host device; Resetting at least one hardware engine and the at least one non-volatile memory component; Cache refreshing is performed on one of the data caches in the data storage device, and the refreshed cached data is programmed into the at least one non-volatile memory element for data recovery; and By activating one of the watchdog modules in the memory controller, and activating the transmission interface circuit and reconnecting with the host, a soft reset is performed to make the data storage device again Works normally. The error handling method as described in item 1 of the patent application scope, wherein interrupting the execution of the current program in response to the at least one error and starting the interrupt service also includes: In response to the occurrence of any of a variety of soft errors (soft errors), the execution of the current program is interrupted and the interrupt service is started, wherein the at least one error includes any of the soft errors. The error handling method as described in item 1 of the patent application scope, wherein the execution of the error handling program on the buffer memory further includes: Jump from the execution address of the current program to the beginning of the error handling program to execute the error handling program. The error handling method as described in item 1 of the patent application scope, wherein disabling the transmission interface circuit additionally includes: Disable the transmission interface circuit to stop data reception and transmission to the host. The error handling method described in item 1 of the patent application scope, wherein the data storage device further includes a dynamic random access memory (Dynamic Random Access Memory, DRAM), and the data cache is located in the dynamic random access memory body. The error handling method as described in item 1 of the patent application scope, wherein the cache refreshing for the data cache in the data storage device further includes: In a reconfiguration range, reallocate the cached data of the cache, where the reconfiguration range is beside a cache end of the data cache. The error handling method as described in item 6 of the patent application scope, wherein the cache refresh for the data cache in the data storage device further includes: Determine whether there is at least one triggered write command (triggered write command); and In response to the existence of the at least one triggered write command, the cache space of the data cache is allocated according to the triggered write command. The error handling method as described in item 6 of the patent application scope, wherein the cache refresh for the data cache in the data storage device further includes: Determine whether any triggered write command data has not been buffered in the data cache; and Since the data that has any of the triggered write commands has not been buffered into the data cache, re-synchronize the cache space of the data cache. The error handling method as described in item 1 of the patent application scope, wherein programming the refreshed cache data to the at least one non-volatile memory element further includes: Programming the refreshed cached data to one or more flushing blocks (Flushing Block) in the at least one non-volatile memory element, wherein the one or more flashing blocks are selected from the At least one free block in the non-volatile memory device. The error handling method as described in item 9 of the patent application scope, wherein the one or more flash blocks in the at least one non-volatile memory element programmed by the refreshed cache data further include: Programming the refreshed cached data to the one or more flash blocks in a predetermined programming unit larger than one page; and Since the data length of the remaining cached data after programming is less than the predetermined programming unit, combine the remaining cached data with the dummy data (Dummy Data) so that the combined data length is equal to the predetermined programming unit, and then the remaining The cache data and the virtual data are programmed into the one or more flash blocks. A data storage device, including: A non-volatile memory (NV memory) for storing information, wherein the non-volatile memory includes at least one non-volatile memory element (NV memory element), and the at least one non-volatile memory The body element contains multiple blocks; and A controller, coupled to the non-volatile memory, is used to control the operation of the data storage device. The controller includes: A buffer memory for temporarily storing information; A transmission interface circuit conforming to a specific communication standard for communication according to the specific communication standard; and A processing circuit for controlling the controller according to a plurality of host commands from a host device to allow the host to access the non-volatile memory through the controller, wherein: The controller uploads an error handling program to the buffer memory with error correction code (ECC) protection capability; In response to at least one error, the controller interrupts the current program execution and starts the interrupt service; The controller executes the error handling program on the buffer memory; The controller disables the transmission interface circuit, wherein the transmission interface circuit is used to communicate with the host; The controller resets at least one hardware engine and the at least one non-volatile memory element; The controller performs a cache refresh on one of the data caches in the data storage device, and programs the refreshed cache data to the at least one non-volatile memory element for data recovery; and The controller completes a soft reset by activating one of the watchdog modules in the memory controller, and activating the transmission interface circuit and reconnecting with the host, so that the data The storage device is operating normally again. According to the data storage device described in item 11 of the patent application scope, in response to the occurrence of any of a variety of soft errors (soft errors), the controller interrupts the execution of the current program and starts the interrupt service, The at least one error includes any one of the soft errors. The data storage device as described in item 11 of the patent application scope, wherein the controller jumps from the execution address of the current program to the beginning of the error handling program to execute the error handling program. The data storage device as described in item 11 of the patent application scope, wherein the controller disables the transmission interface circuit to stop data reception and transmission to the host. The data storage device as described in item 11 of the patent application scope, wherein the data storage device further includes a dynamic random access memory (Dynamic Random Access Memory, DRAM), and the data cache is located in the dynamic random access memory body. A controller for a data storage device includes the controller and a non-volatile memory (NV memory), the non-volatile memory includes at least one non-volatile memory element (NV memory element), the at least one non-volatile memory element includes a plurality of blocks, and the controller includes: A buffer memory for temporarily storing information; A transmission interface circuit conforming to a specific communication standard for communication according to the specific communication standard; and A processing circuit for controlling the controller according to a plurality of host commands from a host device to allow the host to access the non-volatile memory through the controller, wherein: The controller uploads an error handling program to the buffer memory with error correction code (ECC) protection capability; In response to at least one error, the controller interrupts the current program execution and starts the interrupt service; The controller executes the error handling program on the buffer memory; The controller disables the transmission interface circuit, wherein the transmission interface circuit is used to communicate with the host; The controller resets at least one hardware engine and the at least one non-volatile memory element; The controller performs a cache refresh on one of the data caches in the data storage device, and programs the refreshed cache data to the at least one non-volatile memory element for data recovery; and The controller completes a soft reset by activating one of the watchdog modules in the memory controller, and activating the transmission interface circuit and reconnecting with the host, so that the data The storage device is operating normally again. The controller as described in item 16 of the patent application scope, in response to the occurrence of any of a variety of soft errors (soft errors), the controller interrupts the execution of the current program and starts the interrupt service, of which The at least one error includes the any soft error. The controller according to item 16 of the patent application scope, wherein the controller jumps from the execution address of the current program to the beginning of the error handling program to execute the error handling program. The controller as described in item 16 of the patent application scope, wherein the controller disables the transmission interface circuit to stop data reception and transmission to the host. The controller as described in item 16 of the patent application scope, wherein the data storage device further includes a dynamic random access memory (Dynamic Random Access Memory, DRAM), and the data cache is located in the dynamic random access memory .

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