TW202015045A - Write control method, associated data storage device and controller thereof - Google Patents

Abstract

A write control method, an associated data storage device and the controller thereof are provided. The write control method may include: receiving one or more commands from a host device and executing the one or more commands, and performing determining operations to generate determining results; in response to the determining results, starting performing write collection; collecting and handling one or more write commands to buffer data of the one or more write commands through a buffer memory, and performing other determining operations to generate other determining results; in response to the other determining results, according to a number of one or more collected and handled write commands, determining whether data thereof has filled up a write buffer region of the buffer memory; and in response to the data having filled up the write buffer region, flushing the write buffer region to write the data therein into a non-volatile memory.

Description

Writing control method, data storage device and its controller

The present invention relates to flash memory (Flash memory) access, in particular to a write control method and related data storage device and its controller.

Flash memory can be widely used in various portable or non-portable data storage devices (for example: memory cards that comply with SD/MMC, CF, MS, XD or UFS standards; for example: solid-state hard drives; for example : Embedded storage devices that meet UFS or EMMC specifications). In terms of commonly used NAND flash memory, there are initially single-level cells (SLC), multiple-level cells (MLC) and other types of flash memory. Due to the continuous development of memory technology, newer data storage device products can use triple level cell (TLC) flash memory, or even quadruple level cell (QLC) flash memory. In order to ensure that the data storage device's access control to the flash memory can meet the relevant specifications, the controller of the flash memory is usually equipped with certain management mechanisms to properly manage its internal operations.

According to related technologies, the data storage devices with these management mechanisms still have deficiencies. For example, in a specific mode, the data received by the data storage device from the host device can directly enter the internal memory located in a controller integrated circuit instead of entering outside the controller integrated circuit Of external memory. Since the storage capacity of the internal memory is much smaller than that of the external memory, the buffer space in the internal memory is quite limited. Although the specific mode can be used to improve the writing performance of the data storage device, the limited buffer space of the internal memory can correspond to an early trigger for writing buffered data to the flash memory. Since the amount of buffered data is insufficient, a part of the flash memory die in the flash memory is in an idle state. When the host issues a read command, the flash memory die in the flash memory is not idle at the same time, which may cause the overall transmission bandwidth of the flash memory to decrease, and the overall performance of the data storage device to decrease. Therefore, there is a need for a novel method and related architecture to implement a data storage device with a reliable management mechanism without side effects or less likely to cause side effects.

An object of the present invention is to provide a write control method and related data storage device and its controller to solve the above problems.

Another object of the present invention is to provide a write control method and related data storage device and its controller, so as to give a reliable management mechanism to the data storage device without side effects or less likely to cause side effects.

At least one embodiment of the present invention provides a write control method, wherein the write control method is applied to a data storage device including a non-volatile memory (NV memory) and A memory controller to control access to the non-volatile memory, the non-volatile memory includes at least one non-volatile memory element (NV memory element), and the at least one non-volatile memory element includes a plurality of Block. The write control method may include: receiving at least one command from a host device and executing the at least one command; determining whether the length of a time interval between a current time and a start time reaches a predetermined time length threshold Value; determine whether the number of multiple commands received from the host within the time interval reaches a predetermined command number threshold, where the multiple commands include the at least one command; determine multiple commands in the multiple commands Whether the respective numbers of read commands and multiple write commands are greater than a predetermined threshold of read commands and a predetermined threshold of write commands, respectively; as the length of the time interval reaches the predetermined time length threshold, the The number of the plurality of commands reaches the predetermined command number threshold, and the respective numbers of the plurality of read commands and the plurality of write commands are respectively greater than the predetermined read command number threshold and the predetermined write command Threshold, start write collection; for the write collection, collect a write command received from the host, and handle the write command to buffer the write command data through a buffer memory , Where the buffer memory is located in the memory controller; determine whether the length of another time interval between another current time and another start time is greater than another predetermined time length threshold; determine whether there are no additional host commands; Since the length of the other time interval is not greater than the threshold of the other predetermined time length, and no additional host command does not occur, according to the number of one or more collected and processed write commands Determine whether the data of the one or more collected and processed write commands has filled a write buffer in the buffer memory, wherein the one or more collected and processed write commands include the write Command; and because the data in response to one or more collected and disposed write commands has filled the write buffer, flush the write buffer to flush the data in the write buffer Write to the non-volatile memory.

At least one embodiment of the present invention provides a data storage device, which may include: a non-volatile memory for storing information, wherein the non-volatile memory includes at least one non-volatile memory element, and the at least one non-volatile memory element The volatile memory element includes a plurality of blocks; and a controller, coupled to the non-volatile memory, is used to control the operation of the data storage device. The controller may include a buffer memory for temporarily storing information; and a processing circuit, wherein the processing circuit may control the controller according to a plurality of host commands from a host device (host device), to Allow the host to access the non-volatile memory through the controller. For example: the controller receives at least one command from the host and executes the at least one command; the controller determines whether the length of a time interval between a current time and a start time reaches a predetermined time length threshold; the The controller determines whether the number of multiple commands received from the host within the time interval reaches a predetermined command number threshold, wherein the multiple commands include the at least one command and belong to the multiple host commands; the control The device determines whether the respective numbers of the multiple read commands and the multiple write commands in the plurality of commands are greater than a predetermined read command threshold and a predetermined write command threshold respectively; depending on the time interval The length reaches the predetermined time length threshold, the number of the plurality of commands reaches the predetermined command number threshold, and the respective numbers of the plurality of read commands and the plurality of write commands are respectively greater than the predetermined read Taking the command number threshold and the predetermined write command number threshold, the controller starts a write collection; for the write collection, the controller collects a write command received from the host and handles the write command To buffer the data of the write command through the buffer memory; the controller determines whether the length of another time interval between another current time and another start time is greater than another predetermined time length threshold; the controller determines Whether there is no additional host command; because the length of another time interval is not greater than the threshold of the other predetermined time length, and there is no case where the additional host command is not present, the controller is based on one or more The number of collected and processed write commands determines whether the data of the one or more collected and processed write commands has filled a write buffer in the buffer memory, wherein the one or more collected commands are collected And the write command to be processed includes the write command and belongs to the plurality of host commands; and because the data corresponding to one or more collected and processed write commands has filled the write buffer, the controller Quickly flash the write buffer to write the data in the write buffer to the non-volatile memory.

At least one embodiment of the present invention provides a controller for a data storage device, wherein the data storage device includes the controller and a non-volatile memory, the non-volatile memory includes at least one non-volatile memory element, and the above At least one non-volatile memory device includes a plurality of blocks. The controller may include a buffer memory for temporarily storing information; and a processing circuit, wherein the processing circuit may control the controller according to a plurality of host commands from a host to allow the host to store data through the controller Take the non-volatile memory. For example: the controller receives at least one command from the host and executes the at least one command; the controller determines whether the length of a time interval between a current time and a start time reaches a predetermined time length threshold; the The controller determines whether the number of multiple commands received from the host within the time interval reaches a predetermined command number threshold, wherein the multiple commands include the at least one command and belong to the multiple host commands; the control The device determines whether the respective numbers of the multiple read commands and the multiple write commands in the plurality of commands are greater than a predetermined read command threshold and a predetermined write command threshold respectively; depending on the time interval The length reaches the predetermined time length threshold, the number of the plurality of commands reaches the predetermined command number threshold, and the respective numbers of the plurality of read commands and the plurality of write commands are respectively greater than the predetermined read Taking the command number threshold and the predetermined write command number threshold, the controller starts a write collection; for the write collection, the controller collects a write command received from the host and handles the write command To buffer the data of the write command through the buffer memory; the controller determines whether the length of another time interval between another current time and another start time is greater than another predetermined time length threshold; the controller determines Whether there is no additional host command; because the length of another time interval is not greater than the threshold of the other predetermined time length, and there is no case where the additional host command is not present, the controller is based on one or more The number of collected and processed write commands determines whether the data of the one or more collected and processed write commands has filled a write buffer in the buffer memory, wherein the one or more collected commands are collected And the write command to be processed includes the write command and belongs to the plurality of host commands; and because the data corresponding to one or more collected and processed write commands has filled the write buffer, the controller Quickly flash the write buffer to write the data in the write buffer to the non-volatile memory.

One of the benefits of the present invention is that through carefully designed management mechanisms, the present invention can properly control the operation of the controller, in particular, enable the data storage device to receive numerous commands including write commands and read commands Command rearrangement. Since the data storage device can rearrange the commands when receiving the above many commands, the present invention can greatly reduce the probability of the flash memory die in the flash memory not being idle at the same time, so as to improve the flash memory The overall transmission bandwidth (bandwidth), and improve the overall performance of the data storage device. In addition, implementation according to the embodiments of the present invention does not increase many additional costs. Therefore, the problems of the related art can be solved without increasing the overall cost much. Compared with the traditional architecture, the present invention can achieve the optimized performance of the data storage device without side effects or less likely to cause side effects.

Please refer to FIG. 1, which is a schematic diagram of a data storage device 100 and a host device (Host Device) 50 according to a first embodiment of the present invention. For example, the data storage device 100 may be a solid state drive (SSD). In addition, examples of the host 50 may include (but are not limited to): multifunctional mobile phones (Multifunctional Mobile Phone), tablet computers (Tablet), and personal computers (Personal Computer) such as desktop computers and laptop computers. According to this embodiment, the data storage device 100 may include a controller such as a memory controller 110, and may further include a non-volatile memory (Non-Volatile Memory, NV Memory) 120, wherein the controller is used to store Access (non-volatile) memory 120, and non-volatile memory 120 is used to store information.

The non-volatile memory 120 may include a plurality of non-volatile memory elements (NV memory elements) 122-1, 122-2, ..., and 122-N, where the symbol "N" may represent a positive integer greater than one. For example, the non-volatile memory 120 may be a flash memory, and the non-volatile memory elements 122-1, 122-2, ..., and 122-N may be a plurality of flash memory chips, respectively. Or a plurality of flash memory die (Die), but the present invention is not limited to this. In addition, the data storage device 100 may further include a volatile memory element 130 for data buffering, wherein the volatile memory element 130 is preferably a dynamic random access memory (Dynamic Random Access Memory, DRAM). Under the control of the memory controller 110, the data storage device 100 may use at least a portion (eg, part or all) of the storage space of the volatile memory element 130 as a data buffer space for temporarily storing data, for example, during access The period of non-volatile memory 120. In addition, the volatile memory element 130 is an unnecessary element.

The memory controller 110 may include a processing circuit such as a microprocessor 112, a storage such as a read-only memory (Read Only Memory, ROM) 112M, a control logic circuit 114, a buffer memory 116, and a transmission interface circuit 118, of which The components can be coupled to each other through a bus bar. The buffer memory 116 is preferably a static random access memory (SRAM). For example, the memory controller 110 may use the buffer memory 116 such as SRAM as the first layer cache and the volatile memory element 130 such as DRAM as the second layer cache. The data storage capacity of the DRAM is preferably greater than the data storage capacity of the buffer memory 116, and the data buffered by the buffer memory 116 may originate from the DRAM or the non-volatile memory 120.

The read-only memory 112M of this embodiment is used to store a code 112C, and the microprocessor 112 is used to execute the code 112C to control access to the non-volatile memory 120. Please note that the code 112C must also be stored in the buffer memory 116 or any form of memory. In addition, the control logic circuit 114 may include at least one Error Correction Code (ECC) circuit (not shown) to protect data and/or perform error correction, and the transmission interface circuit 118 may conform to a specific communication standard ( Such as Serial Advanced Technology Attachment (SATA) standard, Peripheral Component Interconnect Express (PCIE) standard or Non-Volatile Memory Express (NVME) standard) and can be based on The specific communication standard communicates, and in particular, the host 50 can be communicated according to the specific communication standard.

In this embodiment, the host 50 can send a plurality of host commands (Host Command) to the data storage device 100, and the memory controller 110 can access the non-volatile memory 120 according to the host commands (such as reading or writing Data), wherein the above data is preferably user data derived from the host 50. The host command includes a logical address, for example: logical block address (Logical Block Address). The memory controller 110 can receive host commands and translate the host commands into memory operation commands (abbreviated as operation commands), and then use the operation commands to control the non-volatile memory 120 to read, write/program A page with a specific physical address in the non-volatile memory 120. The memory controller 110 records the mapping relationship between the logical address of the data and the physical address in a logical-to-physical address mapping table ("L2P mapping table"), in which The address can be composed of Channel number, Logical Unit Number (LUN), Plane number, Block number, Page number, and Offset. In some embodiments, the implementation of the physical address may be changed. For example, the physical address may include channel number, logical unit number, plane number, block number, page number, and/or offset.

The L2P mapping table can be stored in a system block in the non-volatile memory 120, and can be divided into multiple group (Group) mapping tables. The system block is preferably an encrypted block and the data is processed in SLC mode Programming. The memory controller 110 may load part or all of the plurality of group mapping tables from the non-volatile memory 120 into the buffer memory 116 according to the capacity of the buffer memory 116 for quick reference , But the invention is not limited to this. When the user data is updated, the memory controller 110 may update the group mapping table according to the latest mapping relationship of the user data. The size of any group mapping table in the plurality of group mapping tables is preferably equal to the size of one page of the non-volatile memory element 122-n, for example, 16KB (kilobytes; kilobytes), where the symbol "N" can represent any positive integer in the interval [1, N], but the invention is not limited thereto. For example, the size of any of the above group mapping tables may be smaller than the size of the page, such as 4 KB or 1 KB. Of course, the size of any of the above group mapping tables may also be equal to the size of one page of multiple non-volatile memory elements 122-n.

The non-volatile memory device 122-n may include multiple planes (Planes), such as planes #0 and #1, each plane includes multiple blocks, and each block includes multiple pages. In this case, the memory controller 110 may combine one page of each of planes #0 and #1 into one large page, and the size of the large page is equal to twice the size of one page, such as 32 KB.

In addition, the memory controller 110 can combine a large page of each of the non-volatile memory elements 122-n in multiple channels, for example, four channels CH0~CH3, into a Super Page. And the four non-volatile memory elements 122-n can be controlled by the same chip enable (CE) signal. Under this setting, the size of the super page SP_SIZE is equal to 128 KB (for example: (32 KB) * 4 = 128 KB), but the present invention is not limited to this. For example, under the setting that the number of channels is equal to 8, such as channels CH0~CH7, each of the non-volatile memory elements in channels CH0~CH7, a large page composed of a super page size SP_SIZE equal to 256 KB ( For example: (32 KB) * 8 = 256 KB).

In addition, the smallest unit for the memory controller 110 to program the non-volatile memory 120 may be one page, and the smallest unit for the memory controller 110 to perform the erase operation for the non-volatile memory 120 may be A block.

In the Write Cache mode, the host 50 can issue a write command to request the memory controller 110 to write a piece of user data (referred to as data) to the non-volatile memory 120. The memory controller 110 can receive or download the data from the host 50, buffer the data using the buffer memory 116, and temporarily store the data using the volatile memory element 130, and then directly reply to the write command execution The completed message is sent to the host 50. After that, when the writing condition is satisfied, for example, the accumulated data length is equal to or greater than the page length or the super page length, the memory controller 110 then writes the cached data to the data of the non-volatile memory 120, but the present invention Not limited to this.

In addition, in the write cache (Write Cache) mode, the volatile memory element 130 is an optional element. For example, the data storage device 100 temporarily stores the data received from the host 50 in the buffer memory 116 such as SRAM, and then directly responds to the host 50 with the message that the write command execution is completed. Since the storage capacity of SRAM is much smaller than that of DRAM, the size of the write buffer in SRAM is quite limited, for example, it can be 512 KB. Taking the four channels CH0~CH3 as an example, the size of the super page SP_SIZE is equal to 128 KB. Therefore, the buffer memory 116 can temporarily store four pieces of data of the super page size. Taking 8 channels CH0~CH7 as an example, the size of the super page SP_SIZE is equal to 256 KB, therefore, the buffer memory 116 can only temporarily store two pieces of data of the super page size.

In a real situation, the logical block address (Logical Block Address, LBA) sequence of the host 50 can be quite complicated. For example, the host 50 usually issues mixed write commands and read commands to the memory control of the data storage device 100 As shown in Figure 2, if the write command (marked as "W") and read command (marked as "R") can be rearranged (Command Rearrangement), as shown in Figure 2, then the data of the written command Temporarily stored in the buffer memory 116. When the size of the data temporarily stored in the buffer memory 116 is equal to a predetermined data size such as the size of one or more super pages (for example: the predetermined data size is equal to 512KB), the temporary data When the data stored in the buffer memory 116 is written to the super page in the non-volatile memory 120, the execution efficiency of the write command can be significantly improved.

FIG. 3 is a flowchart of a write control method according to an embodiment of the invention. This write control method can be applied to the data storage device 100 and executed by the memory controller 110 of the data storage device 100, and can issue a mixed write command and a read command to the host 50 to write to the data storage device 100 control. The write control method of the present invention enables the data storage device 100 to perform the above-mentioned command rearrangement to greatly improve the execution efficiency of the write command without affecting the execution efficiency of the read command, thereby improving the overall performance of the data storage device 100.

In the workflow shown in FIG. 3, the memory controller 110 can detect whether the host 50 has a significant mixed read and write behavior through steps S10 to S18, and detects that the host 50 has a significant mixed read and write behavior With the writing action, the above command rearrangement is performed without causing any timeout (Timeout) through a series of steps from step S20. Steps S10~S18 can be collectively referred to as the initial steps of the write control method of the present invention, steps S20~S36 can be collectively referred to as the write collection step of the write control method of the present invention and some of its steps such as S26~S30 can be regarded as super Time management steps, the description of each step is as follows.

In step S10, the memory controller 110 records a start time T_start0. The start time T_start0 may represent the reference time of a time window for observing the behavior of the host 50. The memory controller 110 may perform time measurement to determine whether the time interval reaches the predetermined size of the time window according to the length of a time interval starting from the start time T_start0.

In step S12, the memory controller 110 receives at least one command (eg, one or more commands) such as a command CMD from the host 50, and executes the above-mentioned at least one command such as a command CMD.

In step S14, the memory controller 110 determines whether the length of the time interval [T_start0, T_current0] (T_current0-T_start0) between the current time T_current0 and the start time T_start0 reaches (eg, greater than or equal to) a predetermined time length threshold The value Th_Time0. If yes, go to step S16; if no, go to step S12. According to this embodiment, the predetermined time length threshold Th_Time0 is equal to 20 ms (millisecond; milliseconds), but the present invention is not limited to this.

In step S16, the memory controller 110 determines whether the number N_CMD of the plurality of commands {CMD} received from the host 50 within the time interval [T_start0, T_current0] reaches (eg, greater than or equal to) a predetermined command number threshold Th_CMD . If yes, go to step S18; if no, go to step S10. According to this embodiment, Th_CMD = 256, but the invention is not limited to this. The plurality of commands {CMD} in this judgment operation include at least one command such as the command CMD described above (for example, the respective command CMD for multiple executions of step S12). In addition, the length of the time interval [T_start0, T_current0] in step S16 (T_current0-T_start0) may be equal to or slightly greater than the predetermined time length threshold Th_Time0, in particular, it may be regarded as equal to the predetermined time length threshold when ignoring the time error The value Th_Time0.

In step S18, the memory controller 110 determines whether the respective numbers N_RCMD and N_WCMD of the plurality of read commands {RCMD} and the plurality of write commands {WCMD} in the plurality of commands {CMD} are greater than a predetermined Th_RCMD for the number of read commands and Th_WCMD for a predetermined number of write commands. If yes, go to step S20; if no, go to step S10. According to this embodiment, Th_RCMD = 16 and Th_WCMD = 16, but the invention is not limited to this. The judgment result of this judgment operation can indicate whether the host 50 has significant mixed read and write behavior. In response to the continuous execution of steps S14, S16, and S18, the judgment results are "Yes" (this indicates that the host 50 has a significant mixed read and write behavior), the memory controller 110 starts to write collection, for example, Some subsequent steps from step S20 are performed. Since the threshold value Th_Time0 of the predetermined time length is typically very small, these mixed read and write behaviors have just begun to appear when step S20 is entered.

In step S20, the memory controller 110 records a start time T_start1. The start time T_start1 may represent a reference time used to detect whether a timeout is about to occur. The memory controller 110 may perform time measurement to determine whether a timeout is about to occur according to the length of a time interval starting from the start time T_start1.

In step S22, the memory controller 110 sets the index i to an initial value such as 0.

In step S24, the memory controller 110 collects a write command WCMD(i) received from the host 50, and handles the write command WCMD(i) to buffer the write command WCMD(i) through the buffer memory 116 such as SRAM data of. For example, by executing the loops including steps S24, S26, S30, S32, etc. multiple times, the memory controller 110 may start to collect and process the write command {WCMD(0) in subsequent commands of the plurality of commands {CMD} , WCMD(1), …}, but the invention is not limited to this.

In step S26, the memory controller 110 determines whether the length of a time interval [T_start1, T_current1] (T_current1-T_start1) between the current time T_current1 and the start time T_start1 is greater than a predetermined time length threshold Th_Time1 or a cumulative data The amount ACCU_DATA is greater than a predetermined accumulated data amount threshold Th_Data. If it is (for example: (T_current1-T_start1)> Th_Time1 or ACCU_DATA> Th_Data), go to step S28; if not (for example: (T_current1-T_start1)> Th_Time1 and ACCU_DATA> Th_Data), go to step S30. According to this embodiment, the predetermined time length threshold Th_Time1 is equal to 10 ms, the predetermined cumulative data amount threshold Th_Data is equal to 51200 KB, and the cumulative data amount ACCU_DATA is equal to (SP_SIZE * (i + 1)), but the present invention is not limited to this. For example, the predetermined time threshold Th_Time1 and/or the predetermined accumulated data threshold Th_Data may be changed. In some embodiments, the accumulative data amount ACCU_DATA and the predetermined accumulative data amount threshold Th_Data can be replaced by index i and a predetermined index threshold value Th_Index, respectively, where the predetermined index threshold value Th_Index is equal to 399, but the invention is not limited to this . For example, the predetermined index threshold Th_Index may be changed.

In step S28, the memory controller 110 flushes the write buffer in the buffer memory 116, such as SRAM, to write any data in the buffer (for example, any data written to the WCMD command) Write to non-volatile memory 120.

In step S30, the memory controller 110 determines whether there are no additional host commands, such as an additional command CMD from the host 50 (for example, an additional read command RCMD and an additional write command WCMD). If yes, go to step S28; if no, go to step S32.

In step S32, the memory controller 110 determines whether the remainder (i% BW) of the index i divided by the predetermined command number BW is less than (BW-1), according to one or more collected and processed write commands WCMD The quantity determines whether the data of the one or more collected and processed write commands WCMD has filled the write buffer (for example, 512 KB of buffer space), where the predetermined command number BW is a positive integer greater than one, and the sign "%" stands for modulo operator. If yes, go to step S34; if no, go to step S36.

The predetermined number of commands BW can be determined according to the size of the super page SP_SIZE. The memory controller 110 can use the size of the super page SP_SIZE (for example, 128 KB) as a base to collect write commands {WCMD(0), WCMD(1), …}, in particular, write commands {WCMD(0), In WCMD(1), …}, the data amount of each data written to the WCMD command can be equal to the size of the super page SP_SIZE. The memory controller 110 may determine the predetermined number of commands BW as the quotient of the size of the write buffer WBUF_SIZE divided by the size of the super page SP_SIZE (WBUF_SIZE / SP_SIZE). For example, when WBUF_SIZE = 512 (KB) and SP_SIZE = 128 (KB), BW = (512 / 128) = 4. In this case, the memory controller 110 can buffer four consecutive write commands in the write buffer by executing step S24 four times to fill the write buffer (for example, 512 KB of buffer space ).

In step S34, the memory controller 110 increases the index i by an increment such as 1 (marked as "i++" in FIG. 3 for simplicity). Then, it progresses to step S24. The memory controller 110 may collect and process the next write command such as the latest write command WCMD(i) by executing step S24 again.

In step S36, the memory controller 110 flashes the write buffer in the memory 116, such as SRAM, to write the data in the write buffer (for example, the latest collected data of the BW write commands, such as The current write command {WCMD(i-(BW-1)), …, WCMD(i-1), WCMD(i)} corresponding to the current value of index i is written to the non-volatile memory 120.

According to this embodiment, by repeatedly performing loops including steps S24, S26, S30, S32, etc., the memory controller 110 can process the write commands it collects {WCMD(0), WCMD(1), …} This group of write commands {WCMD(i-(BW-1)), …, WCMD(i-1), WCMD(i)}, in particular, this group of write commands {WCMD(i-( BW-1)), …, WCMD(i-1), WCMD(i)} data is buffered in the write buffer, and quickly flash the write buffer to write this set of write commands {WCMD( i-(BW-1)), …, WCMD(i-1), WCMD(i)} data is written to the non-volatile memory 120. For example, when WBUF_SIZE = 512 (KB) and SP_SIZE = 128 (KB), BW = 4. In this case, the memory controller 110 can write the respective data DATA(0), DATA(1), DATA of the write commands {WCMD(0), WCMD(1), WCMD(2), WCMD(3)} (2) and DATA(3) are buffered in the write buffer, and flash the write buffer to write data DATA(0), DATA(1), DATA(2) and DATA(3), respectively In the non-volatile memory 120, there are four super pages SP(0), SP(1), SP(2) and SP(3) distributed in 16 non-volatile memory elements 122 (eg N=16) , As shown in Figure 4.

These four super pages SP(0), SP(1), SP(2) and SP(3) respectively contain four large pages of non-volatile memory elements corresponding to four rows (Row) (on page 4). (Indicated by shading in the figure), and the following four super pages respectively contain the four subsequent large pages of the corresponding non-volatile memory elements in these four columns (indicated by the symbol "..." in Figure 4) And so on. Since the operation of flashing the write buffer allows the memory controller 110 to continue buffering the data of the write command collected subsequently, the memory controller 110 can continuously write the four super pages SP(0), SP( 1), SP(2) and SP(3) and subsequent sets of four super pages, until at least one Timeout Avoidance condition is satisfied (for example, when step S26 or S30 enters step S28). For the significant mixed read and write behavior of the host 50, the write control method of the present invention can greatly increase the overall transmission bandwidth of the non-volatile memory 120 (such as flash memory), and enhance the overall data storage device 100 efficacy.

In addition, the size of the super page SP_SIZE can be expanded. For example, when WBUF_SIZE = 512 (KB) and SP_SIZE = 256 (KB), BW = (512 / 256) = 2. In this case, the memory controller 110 can buffer the respective data DATA(0) and DATA(1) of the write command {WCMD(0), WCMD(1)} in the write buffer, and quickly refresh The write buffer is used to write data DATA(0) and DATA(1) into the non-volatile memory 120, respectively, and become two super-distributed in 16 non-volatile memory elements 122 (eg N=16) Pages SP(0) and SP(1) are shown in Figure 5. For example, the super page SP(0) includes the respective large page groups PR0(0) and PR1(0) of the first row and the second row of non-volatile memory elements, and the super page SP(1) includes the third row The large page groups PR2(0) and PR3(0) of the fourth row of non-volatile memory elements; the super page SP(2) includes the first row and the second row of non-volatile memory elements Subsequent large page groups, and the super page SP(3) includes the subsequent large page groups PR2(0) and PR3(0) of the third and fourth rows of non-volatile memory elements; and so on .

In addition, the size of the super page SP_SIZE can be further expanded. For example, when WBUF_SIZE = 512 (KB) and SP_SIZE = 512 (KB), BW = (512 / 512) = 1. In this case, the memory controller 110 can buffer the data DATA(0) of the write command WCMD(0) in the write buffer, and quickly refresh the write buffer to write the data DATA(0) In the non-volatile memory 120, it becomes a super page SP(0) distributed among 16 non-volatile memory elements 122-n (for example, N=16), as shown in FIG. For example, the super page SP(0) includes the respective large page groups PR0(0), PR1(0), PR2(0), and PR3(0) of the first row to the fourth row of non-volatile memory elements; the super Page SP(1) includes the subsequent large page groups of the first to fourth rows of non-volatile memory elements; and so on.

In response to changes in the structure of the non-volatile memory 120, the size of the write buffer WBUF_SIZE can be enlarged. For example, the non-volatile memory element 122-n may include 4 planes, such as planes #0, #1, #2, and #3. In this case, one page of each of planes #0, #1, #2, and #3 can be combined into one large page, and the size of the large page can be equal to 4 times the size of one page, such as 64 KB. In addition, in the non-volatile memory 120, a large page of each non-volatile memory element corresponding to multiple channels (eg, channels CH0, CH1, CH2, and CH3) can be combined into a super page , And the size of this super page SP_SIZE can include the factor of 4 times. In particular, the plurality of channels may include channels CH0, CH1, CH2, and CH3, and the respective chip enable signals CE0, CE1, CE2, and CE3 of channels CH0, CH1, CH2, and CH3 may be used to control the corresponding non-volatile memories, respectively.体元件。 Body components.

When the super page includes a large page of each of the four non-volatile memory elements 122-n controlled by the chip enable signal CE0 of the channels CH0, CH1, CH2, and CH3, the size of the super page SP_SIZE is equal to 256 KB (for example: (64 KB) * 4 = 256 KB). For example, when WBUF_SIZE = 1024 (KB) and SP_SIZE = 256 (KB), BW = (1024/256) = 4. In this case, the memory controller 110 can write the respective data DATA(0), DATA(1), DATA of the write commands {WCMD(0), WCMD(1), WCMD(2), WCMD(3)} (2) and DATA(3) are buffered in the write buffer, and flash the write buffer to write data DATA(0), DATA(1), DATA(2) and DATA(3), respectively In the non-volatile memory 120, there are four super pages SP(0), SP(1), SP(2) and SP(3) distributed in 16 non-volatile memory elements 122 (eg N=16) , As shown in Figure 4.

When the super page includes a large page of each of the eight non-volatile memory elements 122-n controlled by the chip enable signals CE0 and CE1 of the channels CH0, CH1, CH2, and CH3, the size of the super page SP_SIZE Equal to 512 KB (for example: (64 KB) * 8 = 512 KB). For example, when WBUF_SIZE = 1024 (KB) and SP_SIZE = 512 (KB), BW = (1024 / 512) = 2. In this case, the memory controller 110 can buffer the respective data DATA(0) and DATA(1) of the write command {WCMD(0), WCMD(1)} in the write buffer, and quickly refresh The write buffer is used to write data DATA(0) and DATA(1) into the non-volatile memory 120, respectively, and becomes the second distributed in 16 non-volatile memory elements 122-n (for example, N=16) A super page SP (0) and SP (1), as shown in Figure 5.

When the super page contains a large page of each of the 16 non-volatile memory elements 122-n controlled by the chip enable signals CE0, CE1, CE2, and CE3 of the channels CH0, CH1, CH2, and CH3, the super page The size of the page SP_SIZE is equal to 1024 KB (for example: (64 KB) * 16 = 1024 KB). For example, when WBUF_SIZE = 1024 (KB) and SP_SIZE = 1024 (KB), BW = (1024 / 1024) = 1. In this case, the memory controller 110 can buffer the data DATA(0) of the write command WCMD(0) in the write buffer, and quickly refresh the write buffer to write the data DATA(0) In the non-volatile memory 120, it becomes a super page SP(0) distributed among 16 non-volatile memory elements 122-n (for example, N=16), as shown in FIG.

Certain steps in the workflow shown in FIG. 3 may include judgment operations, and the memory controller 110 may perform subsequent operations in the workflow according to the respective judgment results of these judgment operations, such as corresponding to these judgments Subsequent operation of the result can achieve the optimized performance of the data storage device 100. The above are only the preferred embodiments of the present invention, and all changes and modifications made in accordance with the scope of the patent application of the present invention shall fall within the scope of the present invention.

50: host 100: data storage device 110: memory controller 112: Microprocessor 112C: Code 112M: read-only memory 114: control logic circuit 116: Buffer memory 118: Transmission interface circuit 120: Non-volatile memory 122, 122-1, 122-2, ..., 122-N: non-volatile memory device 130: volatile memory device R, W: data S10, S12, S14, S16, S18, S20, S22, S24, S26, S28, S30, S32, S34, S36: steps CH0, CH1, CH2, CH3: channels CE0, CE1, CE2, CE3: chip enable signal SP(0), SP(1), SP(2), SP(3), ...: super page PR0(0), PR1(0), PR2(0), PR3(0): large page group

FIG. 1 is a schematic diagram of a data storage device and a host device according to an embodiment of the invention. FIG. 2 illustrates a command rearrangement control scheme according to an embodiment of the invention. FIG. 3 is a flowchart of a write control method according to an embodiment of the invention. FIG. 4 illustrates a write control scheme according to the write control method shown in FIG. 3 according to an embodiment of the invention. FIG. 5 illustrates a write control scheme according to another embodiment of the present invention as shown in FIG. 3 in the write control method. FIG. 6 illustrates a write control scheme according to another embodiment of the present invention as shown in FIG. 3 in the write control method.

S10, S12, S14, S16, S18, S20, S22, S24, S26, S28, S30, S32, S34, S36: steps

Claims (20)

A write control method, which is applied to a data storage device including a non-volatile memory (NV memory) and a memory used to control the non-volatile memory Taking a memory controller, the non-volatile memory includes at least one non-volatile memory element (NV memory element), the at least one non-volatile memory element includes a plurality of blocks, and the writing control method includes: : Receiving at least one command from a host (host device), and executing the at least one command; Determine whether the length of a time interval between a current time and a start time reaches a predetermined time length threshold; Judging whether the number of the plurality of commands received from the host within the time interval reaches a predetermined command number threshold, wherein the plurality of commands includes the at least one command; Judging whether the respective numbers of the plurality of read commands and the plurality of write commands in the plurality of commands are respectively greater than a predetermined threshold of read commands and a threshold of predetermined numbers of write commands; In response to the length of the time interval reaching the predetermined time length threshold, the number of the plurality of commands reaching the predetermined command number threshold, and the respective numbers of the plurality of read commands and the plurality of write commands When the threshold value of the predetermined number of read commands and the threshold value of the number of predetermined write commands are respectively greater than that, a write collection is started; For the write collection, collect a write command received from the host, and process the write command to buffer the data of the write command through a buffer memory, where the buffer memory is located in the memory controller; Determine whether the length of another time interval between another current time and another start time is greater than another predetermined time length threshold; Determine if there are no additional host commands; Since the length of the other time interval is not greater than the threshold of the other predetermined time length, and no additional host command does not occur, according to the number of one or more collected and processed write commands Determine whether the data of the one or more collected and processed write commands has filled a write buffer in the buffer memory, wherein the one or more collected and processed write commands include the write Order; and Since the data in response to one or more collected and processed write commands has filled the write buffer, flush the write buffer to write the data in the write buffer to the non-volatile Volatile memory. The write control method as described in item 1 of the patent application scope, wherein the step of receiving the at least one command from the host is executed multiple times, and the plurality of commands include the step of receiving the at least one command from the host Execute their respective commands multiple times. The writing control method as described in item 1 of the patent application scope, wherein it is judged whether the length of the other time interval between the other current time and the other start time is greater than the threshold of the other predetermined time length Steps are performed multiple times to generate a first judgment result and a second judgment result, respectively, wherein the first judgment result and the second judgment result indicate that the length of the other time interval is not greater than the other predetermined time The length threshold and the length of the other time interval are greater than the other predetermined time length threshold; the one or more collected and disposed write commands are determined based on the number of the one or more collected and disposed write commands The step of whether the data of the write command has filled the write buffer in the buffer memory is performed according to the first judgment result; and the method further includes: In response to the second judgment result, the write buffer is quickly refreshed to write any data in the write buffer to the non-volatile memory. The write control method as described in item 3 of the patent application scope, wherein the step of judging whether there is no additional host command is executed multiple times to generate a third judgment result and a fourth judgment result, respectively, wherein the third Each of the judgment result and the fourth judgment result indicates that the situation where the additional host command does not occur does not occur. The write control method as described in item 4 of the patent application scope, wherein the data of the one or more collected and processed write commands are determined based on the number of the one or more collected and processed write commands The step of whether the write buffer in the buffer memory has been filled is executed multiple times to generate a fifth judgment result and a sixth judgment result, respectively, wherein the fifth judgment result and the sixth judgment result indicate respectively The data of the one or more collected and processed write commands has filled the write buffer and the data of the one or more collected and processed write commands has not filled the write buffer The step of flashing the write buffer to write the data in the write buffer to the non-volatile memory is based on the fifth judgment result; and the method further includes: In response to the sixth judgment result, another write command received from the host is collected and the other write command is processed to buffer the data of the other write command through the buffer memory. The writing control method as described in item 1 of the patent application scope, wherein it is judged whether the length of the other time interval between the other current time and the other start time is greater than the threshold of the other predetermined time length The step is performed multiple times to generate a first judgment result and a second judgment result, wherein each of the first judgment result and the second judgment result indicates that the length of the other time interval is not greater than The threshold value of the other predetermined time length. The write control method as described in item 6 of the patent application scope, wherein the step of judging whether there is no additional host command is executed multiple times to generate a third judgment result and a fourth judgment result, respectively, wherein the third The judgment result and the fourth judgment result respectively indicate that the case without the additional host command and the case without the additional host command occur; according to the one or more collected and disposed write commands The step of determining whether the data of the one or more collected and processed write commands has filled the write buffer in the buffer memory is based on the third judgment result; and the method contain: In response to the fourth judgment result, the write buffer is quickly refreshed to write any data in the write buffer to the non-volatile memory. The write control method as described in item 7 of the patent application scope, wherein the data of the one or more collected and processed write commands is determined based on the number of the one or more collected and processed write commands The step of whether the write buffer in the buffer memory has been filled is executed multiple times to generate a fifth judgment result and a sixth judgment result, respectively, wherein the fifth judgment result and the sixth judgment result indicate respectively The data of the one or more collected and processed write commands has filled the write buffer and the data of the one or more collected and processed write commands has not filled the write buffer The step of flashing the write buffer to write the data in the write buffer to the non-volatile memory is based on the fifth judgment result; and the method further includes: In response to the sixth judgment result, another write command received from the host is collected and the other write command is processed to buffer the data of the other write command through the buffer memory. The write control method as described in item 1 of the patent application scope, wherein the data of the one or more collected and processed write commands are determined based on the number of the one or more collected and processed write commands The step of whether the write buffer in the buffer memory has been filled is executed multiple times to generate a fifth judgment result and a sixth judgment result, respectively, wherein the fifth judgment result and the sixth judgment result indicate respectively The data of the one or more collected and processed write commands has filled the write buffer and the data of the one or more collected and processed write commands has not filled the write buffer The step of flashing the write buffer to write the data in the write buffer to the non-volatile memory is based on the fifth judgment result; and the method further includes: In response to the sixth judgment result, another write command received from the host is collected and the other write command is processed to buffer the data of the other write command through the buffer memory. The write control method as described in item 1 of the patent application scope, wherein the one or more write commands that have been collected and disposed are collected from subsequent commands of the plurality of commands. A data storage device, including: A non-volatile memory (NV memory) for storing information, wherein the non-volatile memory includes at least one non-volatile memory element (NV memory element), and the at least one non-volatile memory The body element contains multiple blocks; and A controller, coupled to the non-volatile memory, is used to control the operation of the data storage device. The controller includes: A buffer memory for temporarily storing information; and A processing circuit for controlling the controller according to a plurality of host commands from a host device to allow the host to access the non-volatile memory through the controller, wherein: The controller receives at least one command from the host and executes the at least one command; The controller determines whether the length of a time interval between a current time and a start time reaches a predetermined time length threshold; The controller determines whether the number of commands received from the host within the time interval reaches a predetermined command number threshold, where the commands include the at least one command and belong to the host commands; The controller judges whether the respective numbers of the plurality of read commands and the plurality of write commands in the plurality of commands are respectively greater than a predetermined threshold value of the read command number and a predetermined threshold value of the write command number; In response to the length of the time interval reaching the predetermined time length threshold, the number of the plurality of commands reaching the predetermined command number threshold, and the respective numbers of the plurality of read commands and the plurality of write commands When the threshold value of the predetermined number of read commands and the threshold value of the number of predetermined write commands are respectively greater than that, the controller starts a write collection; For the write collection, the controller collects a write command received from the host, and processes the write command to buffer the data of the write command through the buffer memory; The controller determines whether the length of another time interval between another current time and another start time is greater than another predetermined time length threshold; The controller determines whether there are no additional host commands; Since the length of another time interval is not greater than the threshold of the other predetermined time length, and there is no case where the additional host command is not present, the controller is based on one or more collected and processed writes The number of commands determines whether the data of the one or more collected and processed write commands has filled a write buffer in the buffer memory, wherein the one or more collected and processed write commands include The write command, and belongs to the plurality of host commands; and Since the data in response to one or more collected and processed write commands has filled the write buffer, the controller flushes the write buffer to write the data in the write buffer Write to the non-volatile memory. The data storage device as described in item 11 of the patent application range, wherein the operation of receiving the at least one command from the host is performed multiple times, and the plurality of commands includes the number of operations of receiving the at least one command from the host The respective commands executed at this time. The data storage device as described in item 11 of the patent application scope, wherein the operation of determining whether the length of the other time interval between the other current time and the other start time is greater than the threshold of the other predetermined time length Is executed multiple times to generate a first judgment result and a second judgment result respectively, wherein the first judgment result and the second judgment result respectively indicate that the length of the other time interval is not greater than the other predetermined time length The threshold and the length of the other time interval are greater than the threshold of the other predetermined time length; the one or more collected and processed writes are determined based on the number of the one or more collected and processed write commands Whether the data entered in the command has filled the write buffer in the buffer memory is due to the first judgment result; and according to the second judgment result, the controller quickly flushes the write buffer To write any data in the write buffer to the non-volatile memory. A data storage device as described in item 13 of the patent application scope, wherein the operation of determining whether there is no additional host command is performed multiple times to generate a third determination result and a fourth determination result, respectively, wherein the third determination Each of the judgment result and the fourth judgment result indicates that the situation without the additional host command does not occur. The data storage device as described in item 14 of the patent application scope, wherein whether the data of the one or more collected and processed write commands is judged based on the number of the one or more collected and processed write commands The operation of filling the write buffer in the buffer memory is performed multiple times to generate a fifth judgment result and a sixth judgment result, wherein the fifth judgment result and the sixth judgment result indicate that the The data of one or more collected and processed write commands has filled the write buffer and the data of the one or more collected and processed write commands has not filled the write buffer; The operation of flashing the write buffer to write the data in the write buffer to the non-volatile memory is performed according to the fifth judgment result; and according to the sixth judgment result, the controller collects The host receives another write command and processes the other write command to buffer the data of the other write command through the buffer memory. The data storage device as described in item 11 of the patent application scope, wherein the operation of determining whether the length of the other time interval between the other current time and the other start time is greater than the threshold of the other predetermined time length Is executed multiple times to generate a first judgment result and a second judgment result respectively, wherein each of the first judgment result and the second judgment result indicates that the length of the other time interval is not greater than the Threshold value for another predetermined length of time. The data storage device according to item 16 of the patent application scope, wherein the operation of judging whether or not the additional host command is executed multiple times to generate a third judgment result and a fourth judgment result respectively, wherein the third judgment The result and the fourth judgment result respectively indicate that the case without the additional host command and the case without the additional host command occur; according to the one or more write commands that have been collected and disposed of The quantity determines whether the data of the one or more collected and processed write commands has filled the write buffer in the buffer memory according to the third judgment result; and according to the fourth As a result of the judgment, the controller quickly flashes the write buffer to write any data in the write buffer to the non-volatile memory. The data storage device as described in item 17 of the patent application scope, wherein whether the data of the one or more collected and processed write commands is determined according to the number of the one or more collected and processed write commands The operation of filling the write buffer in the buffer memory is performed multiple times to generate a fifth judgment result and a sixth judgment result, wherein the fifth judgment result and the sixth judgment result indicate that the The data of one or more collected and processed write commands has filled the write buffer and the data of the one or more collected and processed write commands has not filled the write buffer; The operation of flashing the write buffer to write the data in the write buffer to the non-volatile memory is performed according to the fifth judgment result; and according to the sixth judgment result, the controller collects The host receives another write command and processes the other write command to buffer the data of the other write command through the buffer memory. A controller for a data storage device includes the controller and a non-volatile memory (NV memory), the non-volatile memory includes at least one non-volatile memory element (NV memory element), the at least one non-volatile memory element includes a plurality of blocks, and the controller includes: A buffer memory for temporarily storing information; and A processing circuit for controlling the controller according to a plurality of host commands from a host device to allow the host to access the non-volatile memory through the controller, wherein: The controller receives at least one command from the host and executes the at least one command; The controller determines whether the length of a time interval between a current time and a start time reaches a predetermined time length threshold; The controller determines whether the number of commands received from the host within the time interval reaches a predetermined command number threshold, wherein the commands include the at least one command and belong to the host commands; The controller judges whether the respective numbers of the plurality of read commands and the plurality of write commands in the plurality of commands are respectively greater than a predetermined threshold value of the read command number and a predetermined threshold value of the write command number; In response to the length of the time interval reaching the predetermined time length threshold, the number of the plurality of commands reaching the predetermined command number threshold, and the respective numbers of the plurality of read commands and the plurality of write commands When the threshold value of the predetermined number of read commands and the threshold value of the number of predetermined write commands are respectively greater than that, the controller starts a write collection; For the write collection, the controller collects a write command received from the host, and processes the write command to buffer the data of the write command through the buffer memory; The controller determines whether the length of another time interval between another current time and another start time is greater than another predetermined time length threshold; The controller determines whether there are no additional host commands; Since the length of the other time interval is not greater than the threshold of the other predetermined time length, and no additional host command does not occur, the controller is based on one or more collected and processed writes The number of commands determines whether the data of the one or more collected and processed write commands has filled a write buffer in the buffer memory, where the one or more collected and processed write commands include The write command belongs to the plural host commands; and Since the data in response to one or more collected and processed write commands has filled the write buffer, the controller flushes the write buffer to write the data in the write buffer Write to the non-volatile memory. The controller of claim 19, wherein the operation of receiving the at least one command from the host is performed multiple times, and the plurality of commands includes the operation of receiving the at least one command from the host multiple times Execute their respective commands.

Images