TW202013717A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

A high-voltage semiconductor device is provided. The device includes a semiconductor substrate having a high-voltage well region, a gate dielectric layer on the semiconductor substrate, a T-shape gate on the gate dielectric layer, the T-shape gate having overhangs extending beyond a neck portion of the T-shape gate, a dielectric neck support disposed underneath the dielectric neck support, an etch stop feature disposed underneath the dielectric neck support, a pair of drift regions disposed on opposite sides of the T-shape gate in the high-voltage well region, and a pair of source/drain regions in the pair of drift regions.

Description

Semiconductor device and its manufacturing method

The present disclosure relates to a semiconductor device, and more particularly to a high-voltage semiconductor device with an etch stop component.

The high-voltage semiconductor device technology is applicable to the field of high-voltage and high-power integrated circuits. The term “high-voltage” here refers to a high breakdown down voltage. Traditional high-voltage semiconductor devices, such as Double Diffused Drain MOSFET (DDDMOS) and Lateral diffused MOSFET (LDMOS), are mainly used for higher than or about 18V Component application areas. The advantage of high-voltage semiconductor device technology is that it is cost-effective and easily compatible with other processes. It has been widely used in display driver IC components, power supplies, power management, communications, automotive electronics, or industrial control.

The double diffusion drain metal oxide half field effect transistor (DDDMOS) has the characteristics of small size and large output current, and is widely used in switch regulators. The double diffusion drain is formed by two doped regions to form a source electrode or a drain electrode for the high-voltage metal-oxide half-field effect transistor.

Usually when designing DDDMOS, the main considerations are low on-resistance (on-resistance, R _on ) and high breakdown voltage (breakdown voltage, BV). In the design of DDDMOS, if the space between the drain and the channel region is shortened (for example, the drain is self-aligned to the gate spacer by a self-alignment process), the on-resistance of DDDMOS can be reduced. However, the breakdown voltage of DDDMOS will decrease and the leakage current will increase.

Therefore, although the existing high-voltage semiconductor device generally meets its intended purpose, it is not completely satisfactory in all aspects.

An embodiment of the present disclosure provides a semiconductor device, including: a semiconductor substrate having a high-pressure well region; a gate dielectric layer on the semiconductor substrate; and a T-shaped gate electrode on the gate dielectric layer, The T-gate has a plurality of overhangs that extend beyond the neck of the T-gate; a dielectric neck support is provided under the plurality of overhangs of the T-gate; an etching stopper , Located below the dielectric neck support; a pair of drift regions, located in the high-pressure well regions on both sides of the T-gate; and a pair of source/drain regions, located in the drift region.

An embodiment of the present disclosure provides a method for manufacturing a semiconductor device, including: providing a semiconductor substrate having a high voltage well region; forming a gate dielectric layer on the substrate; forming a pair of drift regions in the high voltage well region Forming an etch stop layer on the gate dielectric layer; forming a dielectric neck support on the etch stop layer, wherein the etch stop layer serves as an etching end point when forming the dielectric neck support; A T-shaped gate is formed on the gate dielectric layer, wherein the T-shaped gate has a plurality of overhangs extending over the neck of the T-shaped gate on the dielectric neck support; and on the above A pair of source/drain regions is formed in the drift region.

10‧‧‧High voltage semiconductor device

100‧‧‧Semiconductor substrate

100a‧‧‧Active area

102‧‧‧High pressure well area

104‧‧‧Isolated structure

106‧‧‧ Gate dielectric layer

108‧‧‧Drift zone

110‧‧‧Etching stop layer

110a‧‧‧Etching stop parts

112‧‧‧Dielectric support layer

112a‧‧‧Dielectric neck support

120‧‧‧T gate

120b‧‧‧Bar Department

120b'‧‧‧ prominent structure

120n‧‧‧Neck

120s‧‧‧Side wall

122‧‧‧Side wall spacer

132‧‧‧Source/Drain

134‧‧‧ Top doped region

D1‧‧‧ First distance

D2‧‧‧Second distance

D3‧‧‧ Third distance

D4‧‧‧ Fourth distance

E‧‧‧edge

S‧‧‧Distance

W‧‧‧Width

The embodiments of the present disclosure will be described in detail below in conjunction with the accompanying drawings. It should be noted that according to standard practices in the industry, various features are not drawn to scale and are used for illustration only. In fact, the size of the elements may be arbitrarily enlarged or reduced to clearly show the features of the present disclosure.

FIGS. 1-3, 4A, 4B, 5, and 6 are schematic cross-sectional views illustrating a method of manufacturing a high-voltage semiconductor device according to an embodiment of the present disclosure.

FIG. 7A is a top view illustrating a high-voltage semiconductor device according to an implementation of the present disclosure.

FIG. 7B is a top view illustrating a high-voltage semiconductor device according to another implementation of the present disclosure.

8A-8B are diagrams illustrating the current-voltage relationship of the drain of a high-voltage semiconductor device according to an implementation of the present disclosure.

The following disclosure provides many different embodiments or examples to show the different components of the present disclosure. The following will disclose specific examples of components and arrangements in this specification to simplify the disclosure. Of course, these specific examples are not intended to limit this disclosure. For example, if the following summary of the description of this specification describes the formation of the first component on or above the second component, it means that it includes an embodiment where the formed first and second components are in direct contact, and also includes Additional components can be formed between the first and second components, and the first and second components are embodiments that are not in direct contact. In addition, various examples in this disclosure description may use repeated reference symbols and/or words. The purpose of these repeated symbols or words is to simplify and clarify, not to limit the relationship between the various embodiments and/or the configurations.

Furthermore, in order to conveniently describe the relationship between an element or component and another element or components in the illustration, relative terms such as "below", "below", "lower", "" can be used "Above", "upper" and the like. In addition to the orientation shown in the illustration, the relative spatial terms also cover different orientations of the device in use or operation. When the device is turned to different orientations (for example, rotated 90 degrees or other orientations), the relative adjectives used in space will also be interpreted according to the turned orientation.

The following describes the high-voltage semiconductor device and the method of manufacturing the disclosed embodiment. However, it should be understood that the following embodiments are only used to illustrate that the embodiments of the present invention are made and used by a specific method, and are not intended to limit the scope of the present invention. Those of ordinary skill in the art will readily understand that various modifications can be made within the scope of other embodiments. Furthermore, although the method embodiments described below are described in a specific order, other method embodiments may be performed in another logical order, and may include fewer or more steps than discussed herein.

Embodiments of the present disclosure provide a high-voltage semiconductor device, such as a double-diffused drain metal oxide half field effect transistor (DDDMOS), which uses a dielectric neck support under the edge of the T-gate to increase the breakdown voltage of the high-voltage semiconductor device . In this way, when the distance between the channel region and the drain is increased and the size of the high-voltage semiconductor device is reduced to improve its on-resistance and reduce the leakage current, the high-voltage semiconductor device can still have an appropriate or required breakdown voltage.

In addition, in some embodiments, the present disclosure uses an end point detection etching process (also referred to as end mode etching) to form the dielectric neck support. Different from using a time mode etching process to form the dielectric neck support, using the end mode etching process can more efficiently and accurately control the thickness of the dielectric neck support, and can expand the operating margin.

FIGS. 1 to 6 are schematic cross-sectional views of manufacturing processes at various stages of forming the high-voltage semiconductor device 10 of FIG. 6 according to some embodiments of the present invention. FIGS. 7A and 7B are top views illustrating high-voltage semiconductor devices according to different embodiments of the present disclosure. For simplicity and clarity, not all components are illustrated in FIGS. 7A and 7B. First, referring to FIG. 1, a semiconductor substrate 100 is provided, which has a high-voltage well region 102 and at least one isolation structure 104. The isolation structure 104 is used to define an active area 100 a in the high-voltage well area 102 of the semiconductor substrate 100, and electrically isolate various device structures formed in and/or on the semiconductor substrate 100 in the active area. In an embodiment, the semiconductor substrate 100 may be a silicon substrate, a silicon germanium (SiGe) substrate, a compound semiconductor substrate, a bulk semiconductor substrate, or silicon on insulator , SOI) substrate or similar substrate.

In some embodiments, the isolation structure 104 includes a shallow trench isolation (STI) structure, a local oxidation of silicon (LOCOS) structure, other suitable isolation structure components, or a combination thereof. In some embodiments, the semiconductor substrate 100 may have a first conductivity type, for example, P-type or N-type. Furthermore, the high-pressure well region 102 has a first conductivity type. In one example, the high-pressure well region 102 is P-type and has a doping concentration ranging from about 1.0×10 ¹⁵ ions/cm ³ to about 1.0×10 ¹⁷ ions/cm ³ , for example, about 5.0×10 ¹⁶ ions/cm ³ . In another example, the high-pressure well region 102 is N-type and has a doping concentration ranging from about 1.0×10 ¹⁵ ions/cm ³ to about 1.0×10 ¹⁷ ions/cm ³ , for example, about 6.0×10 ¹⁶ ions/cm ³ .

Referring to FIG. 2, a gate dielectric layer 106 is formed on the high-pressure well region 102. In some embodiments, the gate dielectric layer 106 covers the entire active area 100 a and extends above the isolation structure 104. The gate dielectric layer 106 may be or include silicon oxide, silicon nitride, silicon oxynitride, high-k dielectric material (with dielectric Materials with a constant greater than about 7.0), or any other suitable dielectric material, or a combination of the above. For example, the gate dielectric layer 106 may include silicon dioxide. In one embodiment, the gate dielectric layer 106 has a thickness ranging from about 300Å to about 500Å. Thermal oxidation, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), and/or other suitable methods may be used The above-mentioned gate dielectric layer 106 is formed.

Next, with continued reference to FIG. 2, a drift region 108 is formed in the high-pressure well region 102 corresponding to the active region 100 a. In one embodiment, the depth of the drift region 108 is smaller than the depth of the isolation structure 104. The drift region 108 has a second conductivity type different from the first conductivity type. In one example, the first conductivity type may be P type, and the second conductivity type is N type. In another example, the first conductivity type may be N type, and the second conductivity type is P type. A photolithography process can be used to form an implantation mask (not shown) on the high-pressure well region 102, followed by ion implantation to form the drift region 108, and a channel is defined between the drift regions 108 Area (not shown). Furthermore, after the drift region 108 is formed, an annealing process may be performed on the drift region 108, such as rapid thermal annealing (RTA). The duration of the rapid thermal annealing is about 5 seconds to 20 seconds, such as about 10 seconds.

Referring to FIG. 3, an etch stop layer 110 is formed to cover the gate dielectric layer 106, and a dielectric support layer 112 (also referred to as a dielectric layer 112) is formed on the etch stop layer 110. The termination layer 110 and the dielectric layer 112 will be formed into an etch stop part 110a and a dielectric neck support 112a (as shown in FIGS. 4A-4B) in a subsequent process.

The etch stop layer 110 can be used as a mechanism for etching the end point during the etching process to stop the etching process. This is called an end point detection (end point detection) etching process. Unlike the etching process using the time-limited mode, the end point detection etching process can more efficiently and accurately control the thickness of the dielectric neck support, and can expand the process window. The etch stop layer 110 may be formed of materials with different etch selectivities in adjacent film layers or components (ie, the dielectric layer 112 and/or the gate dielectric layer 106). In some embodiments, this etch stop layer 110 may include or may be a dielectric material, such as a nitrogen-containing material, a silicon-containing material, and/or a carbon-containing material. For example, the etch stop layer 110 may include or be silicon nitride, silicon carbon nitride, carbon nitride, silicon oxynitride, silicon oxynitride ( silicon carbon oxide), similar materials, or a combination of the above.

In other embodiments, the etch stop layer 110 may include or may be a conductive material or a semiconductor material, such as polysilicon. After the etch stop layer 110 is formed as the etch stop part 110a, the etch stop part 110a including a conductive material or a semiconductor material may function as a field plate. The field plate can reconstruct the distribution of the electric field intensity of the channel, which can reduce the peak value of the electric field of the gate electrode (near the drain terminal), thereby increasing the breakdown voltage. The etch stop layer 110 may be formed by a deposition process, electroplating, and/or other suitable methods. For example, the deposition method may be chemical vapor deposition (CVD), physical vapor deposition (eg, sputtering) , Atomic layer deposition (atomic layer deposition, ALD), or other deposition methods.

In some embodiments, the dielectric layer 112 and the gate dielectric layer 106 include the same material. For example, both the dielectric layer 112 and the gate dielectric layer 106 may include silicon dioxide. In other embodiments, the dielectric layer 112 and the gate dielectric layer 106 may include different materials. For example, the gate dielectric layer 106 may include silicon dioxide, and the dielectric layer 112 may include silicon nitride, silicon oxynitride, or other high dielectric constant dielectric materials (eg, HfO ₂ , ZrO ₂ , Al ₂ O ₃ , or TiO ₂ etc.). The dielectric layer 112 may be formed by a deposition method, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or other deposition techniques. In a specific embodiment, the gate dielectric layer 106 is silicon dioxide. In a particular embodiment, the dielectric layer 112 is silicon dioxide. In a specific embodiment, the etch stop layer 110 is silicon nitride. In another specific embodiment, the etch stop layer 110 is polysilicon.

Referring to FIG. 4A, the etch stop layer 110 and the dielectric layer 112 are formed into an etch stop part 110a and a dielectric neck support 112a using photolithography and an etching process, respectively. Generally speaking, the photolithography process includes depositing a photoresist material (not shown), exposing and developing to remove part of the photoresist material. The remaining photoresist material protects the underlying materials (eg, dielectric layer 112 and etch stop layer 110) from subsequent process steps (eg, etching). In some embodiments, a photoresist layer (not shown) is formed to cover the dielectric layer 112, and the photoresist is patterned by exposing the photoresist to light by using an appropriate photomask. The exposed or unexposed portions of the photoresist can then be removed by development, depending on whether positive or negative photoresist is used. Next, the patterned photoresist can be used to etch the dielectric layer 112 and the etch stop layer 110 to form an etch stop part 110a and a dielectric neck support 112a, respectively. The above-mentioned dielectric neck support 112a can reduce the electric field located under the edge of the gate (to be formed in the subsequent process) and reduce the gate-drain capacitance, thereby improving the breakdown voltage of the high-voltage semiconductor device and increasing the switching characteristics of the high-voltage semiconductor device (switching characteristic). In addition, the method of using the etch stop layer 110 as an etch endpoint to etch the dielectric layer 112 to form the above-described dielectric neck support 112a (ie, the end mode etching process) has some advantages, for example, it is different from using the time limit mode (time mode) etching process to form the dielectric neck support 112a, using the end-point mode etching process can more efficiently and accurately control the thickness of the dielectric neck support 112a, and can expand the operating margin. In some embodiments, the etch stop member 110a including a conductive material or a semiconductor material may operate as a field plate to further increase the breakdown voltage of the high-voltage semiconductor device.

In one embodiment, the thickness of the dielectric neck support 112a is approximately in the range of 500Å to 700Å. In one embodiment, the thickness of the etch stop member 110a is approximately in the range of 300Å to 500Å. The above etching process may be a dry etching or a wet etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), a similar process, or a combination thereof. This etching may be anisotropic. In one embodiment, the dielectric neck support 112a has a U-shaped top-view profile (as shown in FIG. 7A), and the dielectric neck support 112a has a width W. In other embodiments, the dielectric neck support 112a has a loop-shaped top-view profile (as shown in FIG. 7B). In addition, in some embodiments, as shown in FIG. 4A, the above-mentioned etching stopper 110a and the dielectric neck support 112a may have the same size. For example, the etch stop part 110a and the dielectric neck support 112a can be simultaneously formed in a single etching step. In other embodiments, as shown in FIG. 4B, the etch stop member 110a and the dielectric neck support 112a may have different sizes. For example, an additional photolithography process may be used to form an additional patterned photoresist to form the etch stop part 110a and the dielectric neck support 112a in two different etching steps.

Please refer to FIG. 5, a T-shaped gate 120 is formed on the gate dielectric layer 106. Next, sidewall spacers 122 are formed on the two opposite sidewalls 120s of the T-gate 120. The T-gate 120 includes a bar portion 120b and a neck portion 120n, wherein the portion of the bar portion 120b extending beyond the neck 120n is an overhang 120b'. In one embodiment, as shown in FIGS. 7A and 7B, a dielectric neck support 112a having a U-shaped or ring-shaped top-view profile protrudes from the side wall 122a of the T-shaped gate 120 by a first distance D1, as described above The first distance D1 is greater than the width of the sidewall spacer 122. In addition, the second distance D2 (i.e., the width of the protruding structure 120b') of the dielectric neck support 112a extending from the sidewall 122a of the T-gate 120 to below the T-gate 120 is greater than the first distance D1. In this way, the electric field under the edge of the T-gate 120 can be reduced and the gate-drain capacitance (Gate-Drain Capacitance, Cgd) can be reduced by the dielectric neck support 112a having a U-shaped or ring-shaped top-view profile ). Furthermore, from the top view, the portion of the dielectric neck support 112a perpendicular to the T-gate 120 protrudes outward from an edge E of the active area 100a by a third distance D3. In addition, a fourth distance D4 that the dielectric neck support 112a extends from an edge E of the active area 100a to the active area 100a is smaller than the third distance D3.

In some embodiments, the T-gate 120 includes polysilicon, metal materials, metal silicides, other suitable conductive materials, or combinations thereof. It can be carried out by an appropriate deposition process (for example, chemical vapor deposition, physical vapor deposition, metal-organic chemical vapor deposition (MOCVD)) and/or silicidation process, lithography process and An etching process (for example, a dry etching process or a wet etching process) forms the T-gate 120 described above. The above-mentioned sidewall spacer 122 includes a material different from that used for the T-gate 120. In some embodiments, the sidewall spacer 122 includes a dielectric material, such as silicon nitride or silicon oxynitride. In one embodiment, after the T-gate 120 is formed, one or more layers (not shown) are formed by conformally depositing a dielectric material on the high-voltage semiconductor device 10. Next, an anisotropic etching process is performed to remove part of the one or more layers to form the sidewall spacer 122.

Referring to FIG. 6, a source/drain region 132 having a first conductivity type is formed in the corresponding drift region 108, and a top doped region 134 is formed on top of the T-gate 120. In one embodiment, the doping concentration of the source/drain region 132 is greater than the drift region 108 as a double-diffused drain region. Furthermore, the source/drain region 132 and the top doped region 134 have the same conductivity type and the same doping concentration. In an embodiment, the source/drain region 132 may be laterally separated from the sidewall spacer 122 by a distance S (ie, the source/drain region 132 is not self-aligned to the sidewall spacer 122) to reduce high voltage semiconductors Leakage current of device 10. The aforementioned distance S ranges from approximately 0.15 to 0.30 microns. In addition, the top doped region 134 can reduce the contact resistance of the T-gate 120.

A photolithography process may be used to form an implantation mask (not shown) on the high-pressure well region 102, followed by ion implantation to form the source/drain region 132, and formed on top of the T-gate 120 The top doped region 134. After forming the source/drain regions 132, a conventional metallization process may be used to form a metallization layer (not shown) on the structure of FIG. In this way, the high-voltage semiconductor device 10 can be formed. In one embodiment, the metallization layer may include an interlayer dielectric (ILD) layer and an interconnect structure located in the interlayer dielectric (ILD) layer. In one embodiment, the interconnect structure at least includes a metal electrode coupled to the source/drain region 132 and the top doped region 134.

Figures 8A/8B are current-voltage curves of the drain of a double-diffused drain metal-oxide half-field transistor with N-type/P-type high-pressure wells according to an embodiment of the present invention. The dotted line represents an embodiment of a double-diffusion drain metal oxide half field effect transistor without a field plate, that is, an embodiment in which the etching stop member is a dielectric material, such as silicon nitride. The solid line represents an embodiment of a double-diffusion drain metal oxide half field effect transistor with a field plate, that is, an embodiment where the etching stop member is a conductive material or a semiconductor material, such as polysilicon. As can be seen from Figures 8A-8B, whether it is a double-diffused drain metal oxide half-field transistor with an N-type/P-type high-pressure well area, a double-diffused drain metal oxide half-field transistor with a field plate is less The double-diffusion drain metal oxide half field effect transistor with field plate has a higher breakdown voltage.

Please refer to FIG. 6. In the embodiment of the present disclosure, the high-voltage semiconductor device 10 includes a semiconductor substrate 100 having a high-voltage well region 102 and at least one isolation structure 104. The isolation structure 104 defines an active area 100 a in the high-voltage well area 102 of the semiconductor substrate 100.

In this embodiment, the high-voltage semiconductor device 10 further includes a gate dielectric layer 106 on the semiconductor substrate 100 and a T-gate 120 on the gate dielectric layer 106. In one embodiment, the gate dielectric layer 106 is located on the high-pressure well region 102, covering the entire active region 100a and extending above the isolation structure 104. In a particular embodiment, the gate dielectric layer 106 may include silicon dioxide. The T-gate 120 includes a bar portion 120b and a neck portion 120n, wherein the portion of the bar portion 120b extending beyond the neck 120n is an overhang 120b', as shown in FIG. 6 As shown. In one embodiment, the T-gate 120 may include polysilicon. In one embodiment, the T-gate 120 has a top doped region 134 to reduce the contact resistance of the T-gate 120.

In this embodiment, the high-voltage semiconductor device 10 further includes a dielectric neck support 112a disposed under the protruding structure 120b' of the T-gate 120, wherein the dielectric neck support 112a extends beyond the protruding structure 120b' edge. The dielectric neck support 112a is located on the high-pressure well area 102. The dielectric neck support 112a is a patterned dielectric layer that does not cover the entire active area 100a or extends above the isolation structure 104. As shown in FIGS. 7A and 7B, the dielectric neck support 112a at least partially surrounds the T-shaped gate 120. In some embodiments, the dielectric neck support 112a may have a U-shaped top-view profile, and in other embodiments, the dielectric neck support 112a may have a ring-shaped top-view profile. In one embodiment, the dielectric neck support 112a and the gate dielectric layer 106 include the same material, such as silicon dioxide. In other embodiments, the dielectric neck support 112a and the gate dielectric layer 106 may include different materials.

In this embodiment, the high-voltage semiconductor device 10 further includes an etch stop member 110a, which is disposed below the dielectric neck support 112a. In some embodiments, the etch stop member 110a has the same size as the dielectric neck support 112a, while in other embodiments, the etch stop member 110a is wider than the width of the dielectric neck support 112a. In some embodiments, the etch stop member 110a includes a conductive material or a semiconductor material to serve as a field plate. In a specific embodiment, the etch stop 110a is polysilicon.

In this embodiment, the high-voltage semiconductor device 10 further includes a pair of drift regions 108 disposed in the high-voltage well regions 102 on both sides of the T-gate 120, and a pair of source/drain electrodes disposed in the drift region 108 District 132.

In this embodiment, the high-voltage semiconductor device 10 further includes a sidewall spacer 122 that covers the dielectric neck support 112a and extends along the protruding structure 120b' of the T-gate 120, wherein the dielectric neck support 112a is higher than the above The width of the sidewall spacer 122 is wide. In one embodiment, the source/drain region 132 is laterally separated from the sidewall spacer 122 by a distance S.

According to the above embodiment, in the process of forming a high-voltage semiconductor device having a U-shaped or ring-shaped dielectric layer, a method of forming a dielectric neck support using an etching stop layer as an etching end point to etch the dielectric support layer (ie , End-point mode etching process) has some advantages, for example, different from the use of time mode etching process to form the dielectric neck support, using the end mode etching process can more efficiently and accurately control the dielectric The thickness of the neck support, and can expand the operating margin. In addition, the etch stop member including conductive material or semiconductor material can have a field plate effect, which can further increase the breakdown voltage of the device. In this way, in the design of high-voltage semiconductor devices, the source/drain regions can be laterally separated from the sidewall spacer to increase the distance between the channel region and the source/drain regions, thereby reducing the high-voltage semiconductor device Leakage current. Furthermore, the on-resistance of the high-voltage semiconductor device can be reduced by reducing the planar size of the high-voltage semiconductor device.

The above outlines the features of several embodiments of the present disclosure, so that those with ordinary knowledge in the art can more easily understand the present disclosure. Those of ordinary skill in the art should understand that this description can be easily used as a basis for changes or design of other structures or processes to perform the same purposes and/or obtain the same advantages as the disclosed embodiments. Any person with ordinary knowledge in the technical field can also understand that the structure or process equivalent to the above does not deviate from the spirit and scope of the disclosure, and can be changed or replaced without departing from the spirit and scope of the disclosure With retouch.

10‧‧‧High voltage semiconductor device

100‧‧‧Semiconductor substrate

100a‧‧‧Active area

102‧‧‧High pressure well area

104‧‧‧Isolated structure

106‧‧‧ Gate dielectric layer

108‧‧‧Drift zone

110a‧‧‧Etching stop parts

112a‧‧‧Dielectric neck support

120‧‧‧T gate

120b‧‧‧Bar Department

120b'‧‧‧ prominent structure

120n‧‧‧Neck

120s‧‧‧Side wall

122‧‧‧Side wall spacer

132‧‧‧Source/Drain

134‧‧‧ Top doped region

S‧‧‧Distance

Claims (20)

A semiconductor device includes: a semiconductor substrate with a high-pressure well region; a gate dielectric layer on the semiconductor substrate; and a T-type gate on the gate dielectric layer, the T-type gate having A plurality of overhangs extending beyond the neck of the T-shaped gate; a dielectric neck support member disposed under the plurality of protruded structures of the T-shaped gate; an etching stop member disposed at the dielectric Below the neck support; a pair of drift regions arranged in the high-pressure well regions on both sides of the T-gate; and a pair of source/drain regions located in the pair of drift regions. The semiconductor device described in item 1 of the patent application further includes a sidewall spacer covering the dielectric neck support and extending along the sidewall of the plurality of protruding structures of the T-gate. The semiconductor device as described in item 2 of the patent application scope, wherein the sidewall spacer is laterally separated from the source/drain region by a distance. The semiconductor device as described in item 2 of the patent application range, wherein the dielectric neck support is wider than the width of the sidewall spacer. The semiconductor device as described in item 1 of the patent application range, wherein in a top view, the dielectric neck support member at least partially surrounds the T-shaped gate. The semiconductor device as described in item 5 of the patent application range, wherein the dielectric neck support has a U-shaped top-view profile. A semiconductor device as described in item 5 of the patent application range, wherein the dielectric neck support has a loop-shaped top-view profile. The semiconductor device as described in item 1 of the patent application range, wherein the dielectric neck support extends beyond the edge of the plurality of protruding structures. The semiconductor device as described in item 1 of the patent application range, wherein the etch stop member is wider than the width of the dielectric neck support. The semiconductor device as described in item 1 of the patent application scope, wherein the etch stop member includes a conductive material or a semiconductor material as a field plate. The semiconductor device as described in item 10 of the patent application range, wherein the etch stop member is polysilicon. A method for manufacturing a semiconductor device includes: providing a semiconductor substrate having a high-pressure well region; forming a gate dielectric layer on the substrate; forming a pair of drift regions in the high-pressure well region; and interposing the gate electrode Forming an etch stop layer on the electrical layer; forming a dielectric neck support on the etch stop layer, wherein the etch stop layer serves as an etching end point when forming the dielectric neck support; on the gate dielectric layer Forming a T-shaped gate, wherein the T-shaped gate has a plurality of overhangs extending beyond the neck of the T-shaped gate on the dielectric neck support; and forming a in the drift region For source/drain regions. The method of manufacturing a semiconductor device as described in item 12 of the patent application scope further includes forming a sidewall spacer that covers the dielectric neck support and extends along the sidewall of the plurality of protruding structures of the T-gate. A method of manufacturing a semiconductor device as described in item 13 of the patent application range, wherein the dielectric neck support is wider than the width of the sidewall spacer. The method of manufacturing a semiconductor device as described in item 12 of the patent application range, wherein in a top view, the dielectric neck support member at least partially surrounds the T-shaped gate. The method for manufacturing a semiconductor device as described in item 12 of the patent application range, wherein the dielectric neck support extends beyond the edge of the plurality of protruding structures. The method of manufacturing a semiconductor device as described in item 12 of the patent application range, wherein the etching stop member is wider than the width of the dielectric neck support. The method for manufacturing a semiconductor device as described in item 12 of the patent application range, wherein the etching stop member includes a conductive material or a semiconductor material to serve as a field plate. The method for manufacturing a semiconductor device as described in item 18 of the patent application range, wherein the etching stop member is polysilicon. The method for manufacturing a semiconductor device as described in item 12 of the patent application range, wherein the T-gate has a top doped region, and the top doped region and the source/drain region have the same conductivity type and the same doping Miscellaneous concentration.

Images