TW202005056A - Memory cells, methods of forming an array of two transistor-one capacitor memory cells, and methods used in fabricating integrated circuitry - Google Patents

Abstract

A memory cell comprises first and second transistors laterally displaced relative one another. A capacitor is above the first and second transistors. The capacitor comprises a container-shape conductive first capacitor node electrically coupled with a first current node of the first transistor, a conductive second capacitor node electrically coupled with a first current node of the second transistor, and a capacitor dielectric material between the first capacitor node and the second capacitor node. The capacitor dielectric material extends across a top of the container-shape first capacitor node. Additional embodiments and aspects, including method, are disclosed.

Description

Memory cell, method for forming two transistor-capacitor memory cell array, and method for manufacturing integrated circuit

The embodiments disclosed herein relate to memory cells, methods of forming memory cells, and methods used in manufacturing integrated circuits.

Dynamic random access memory (DRAM) is used in modern computing architectures. Compared with other types of memory, DRAM can provide the advantages of simplified structure, low cost and speed. Currently, DRAMs usually have individual memory cells (so-called 1T-1C memory cells) combined with a capacitor and a field effect transistor, where the capacitor is coupled to one of the source/drain regions of the transistor. One of the limiting factors for the scalability of the current 1T-1C configuration is that it is difficult to incorporate capacitors with sufficiently high capacitance into a highly integrated architecture. Therefore, it is desirable to develop new memory cell configurations suitable for incorporation into highly integrated modern memory architectures. Although the object of the present invention is an architecture and method associated with memory cells other than 1T-1C memory cells, some aspects of the present invention are by no means limited to this and can be applied to any memory cell and manufacturing Any method used in integrated circuits.

Embodiments of the invention include memory cells that are independent of the manufacturing method. Embodiments of the present invention also include a method of forming an array of two transistor-capacitor (2T-1C) memory cells and a method used in manufacturing integrated circuits. Although not limited by this limitation, the drawings provided illustrate manufacturing methods and structures associated with a 2T-1C memory cell, such as the schematic illustration shown in FIG. 1. An exemplary 2T-1C memory cell MC has two transistors T1 and T2 and a capacitor CAP. One source/drain region of T1 is connected to a first conductive node of the capacitor CAP, and the other source/drain region of T1 is connected to a first comparison bit line (eg, BL-T). The gate of T1 is connected to a word line WL. One source/drain region of T2 is connected to a second conductive node of the capacitor CAP, and the other source/drain region of T2 is connected to a second comparison bit line (eg, BL-C). One gate of T2 is connected to the word line WL. The comparison bit lines BL-T and BL-C extend to the circuit 4, and the circuit 4 compares the electrical properties (eg, voltage) of the two to determine a memory state of the memory cell MC. The 2T-1C configuration of Figure 1 can be used in DRAM and/or other types of memory. First, an exemplary embodiment of a method of forming an array of 2T-1C memory cells MC is described with reference to FIGS. 2-21. 2 and 3, these figures illustrate a portion of a substrate segment of a structure 12 and eventually a plurality of memory cells MC (not shown) will be manufactured within the structure 12. The material may be located next to the material depicted in FIGS. 2 and 3, vertically inward or vertically outward from the material depicted in FIGS. 2 and 3. For example, other partially manufactured or fully manufactured components of the integrated circuit may be provided around or somewhere within the structure 12. In any case, any of the materials, regions, and structures described herein may be homogeneous or heterogeneous, and in any case, the above items may be continuous or discontinuous above any material they cover . In addition, unless otherwise stated, any material suitable or yet to be developed can be used to form each material, including atomic layer deposition, chemical vapor deposition, physical vapor deposition, epitaxial growth, diffusion doping, and ion implantation systems Examples. The structure 12 includes a base substrate 13 that may include conductive/conductor (ie, electrically conductive herein) materials, semi-conductive materials, or insulating/insulator/insulating ) (That is, electrically isolated in this article) any one or more of the materials. The structure 12 includes a plurality of columns 16 of first transistors 18 and second transistors 20 (respectively). Any suitable transistor can be used, such as field effect transistors (with or without non-volatile programmable regions), bipolar junction transistors, etc. However, the manufacturing of the memory cell MC shown in FIG. 1 is mainly discussed, wherein the exemplary first transistor 18 and the second transistor 20 are field effect transistors. In addition, the references to "first" and "second" with respect to different components or materials are merely for ease of explanation when referring to different components, different materials, and/or the same materials or components formed at different times. Therefore and unless otherwise indicated, "first" and "second" can be interchanged independently of the relative position within the finished circuit structure and independent of the manufacturing order. Structure 12 is shown to include dielectric material 29 (eg, silicon nitride and/or doped or undoped silicon dioxide) around transistors 18, 20. In the top view of FIG. 2, only some of the underlying components are shown with dashed lines and they are related to the example horizontal layout of these components. In addition, in order to make it clearer in FIG. 2, the conductive material of the access line 22 of FIG. 3 (explained below) is shown in FIG. 2 using the stippling method. In one embodiment and as shown, the first field effect transistor 18 and the second field effect transistor 20 extend vertically and alternate relative to each other along the individual columns 16 (ie, alternate within their series) . In this document, unless otherwise indicated, "vertical (ground)", "higher", "upper", "lower", "top", "on top", "bottom", "upper", ""Below","Below","Bottom","Up" and "Down" usually refer to the vertical direction. In addition, as used herein, "vertical" and "horizontal" in three-dimensional space are generally independent of the orientation of the substrate and perpendicular to each other. In addition, "extend (ing) elevationally and elevationally-extending" encompasses a range from vertical to no more than 45° from vertical. In addition, regarding the "extend(ing) elevationally and elevationally-extending" of a field effect transistor, the orientation of the channel length of the reference transistor is referenced. In operation, the current flows along the channel length in the source/drain region. Time flows. For bipolar junction transistors, "extend(ing) elevationally and elevationally-extending" refers to the orientation of the substrate length, and current flows between the emitter and collector along the length of the substrate during operation . In one embodiment and as shown, the alternating transistors in the first column and the alternating transistors in the second column are each perpendicular or within 10° of the vertical, and in one embodiment are relative to They are in a common horizontal plane. In one embodiment and as shown, the first transistor 18 and the second transistor 20 are interleaved in the immediate column (ie, interleaved between their series). Alternating field effect transistors 18, 20 individually include a first current node 26 (eg, a vertical outer source/drain region) and a second current node 24 (eg, a vertical inner source/drain electrode) Zone) and a passage zone 28 located therebetween. The access line or word line 22 extends along the column 16. The first transistor 18 and the second transistor 20 include a gate, which can be considered to form part of an individual access line 22, and it is shown to surround individual channel regions 28 as appropriate. A suitable gate insulator 23 is located between a gate/access line 22 and a channel area 28. Field effect transistors 18, 20 can be manufactured using any existing or yet to be developed technology and can have source/drain regions, channel regions, gates and/or gates of alternately configured sizes and shapes Insulator. Exemplary regions 24, 26, and 28 may include suitably doped semiconductor materials, and an exemplary conductive composition for access line 22 is an elemental metal, a mixture or alloy of one or more of two or more elements, a conductive metal One or more of compounds and semiconducting materials that are conductively doped. The configuration 12 includes a number of rows of sensing lines 14, with a number of columns of access lines 22 above the sensing lines 14. The use of "columns" and "rows" in this document is to facilitate distinction between one series or orientation of features and another series or orientation of features, and components have been or will be formed along "columns" and "rows". Columns can be straight and/or curved, and/or parallel and/or non-parallel with respect to each other, as can rows. In addition, the columns and rows may intersect at 90° or one or more other angles relative to each other. The sensing line 14 may be any suitable conductive composition, and the conductive composition may be the same as or different from the conductive composition of the access line 22. Within individual columns, the immediately adjacent pair of sense lines 14 may be BL-T and BL-C in the schematic diagram of FIG. 1 (and therefore alternate within the series). In addition, the same sensing lines in the immediate column can be BL-C and BL-T, respectively (and therefore alternate between series in operation). The vertical inner source/drain regions 24 of the alternating field effect transistors 18, 20 are electrically coupled (in one embodiment, directly electrically coupled) to a separate sensing line 14. In this document, if current can flow continuously from one zone/material/component to another zone/material/component during normal operation and these sub-atomic positive charges and/or negative charges are generated mainly by these charges When moving and flowing, the zones/materials/components are "electrically coupled" with respect to each other. Another electronic component may be located between the regions/materials/components and electrically coupled to the regions/materials/components. In contrast, when a zone/material/component is called "direct electrical coupling", there are no intervening electronic components between the zone/material/component directly coupled (eg, no diodes, transistors, Resistors, transducers, switches, fuses, etc.). In one embodiment, the vertical inner source/drain region 24 is directly above a separate sensing line 14. In this document, "directly above" requires that the two said zones/materials/components overlap with each other at least to some extent laterally (ie horizontally). In addition, not using “directly” in front of “above” only requires that a portion of the zone/material/component above another zone/material/component is vertically outward from the other zone/material/component (ie, with It does not matter whether there is any lateral overlap of the two said zones/materials/components). Material 30 is vertically outward from transistors 18, 20. In one embodiment, the material 30 includes a vertical inner dielectric material 32 (eg, silicon nitride 31 and doped or undoped silicon dioxide 33) and a vertical outer material 34. In one embodiment and as shown, the material 34 includes a vertical inner material 36 and a vertical outer material 38, the vertical outer material 38 having a composition different from that of the material 36 (eg, material 36 Contains silicon nitride, material 38 contains carbon). Referring to FIGS. 4-6, a plurality of openings 40 (in one embodiment, capacitor openings) have been formed in the material 30 and individually extend to a first current node 26 of an individual first transistor 18. The ring of material 29 will be located around the node 26, but is not shown in FIG. 4 for clarity in FIG. 4. In one embodiment and as shown, the openings 40 are staggered in the immediate column (ie, staggered between their series). Exemplary techniques for forming opening 40 include photolithography patterning and etching and may include pitch multiplication. In one embodiment, the opening 40 has a minimum horizontal opening size of 1.5F immediately adjacent to the top 27 of the material 33, where "F" is the largest vertical outermost surface of one of the first current nodes 26 Horizontal size. 7 and 8, a conductive material has been deposited to line and not completely fill the opening 40, and then in one embodiment the conductive material is etched back so that its top 43 is lower than one of the inner dielectric materials 32 The top 27 thus forms a first capacitor node 42. In one embodiment and as shown, the first capacitor node 42 is container-shaped. Regardless, in one embodiment and as shown, the first capacitor node 42 is electrically coupled (in one embodiment, directly electrically coupled) to the first current node 26 of the individual first transistor 18, and in In the embodiment, it directly abuts an upper surface of the first current node 26. In this document, when a material, region or structure has at least some kind of physical contact with each other, the material, region or structure "directly abuts" another material, region or structure. In contrast, there is no "direct""above","upper","adjacent","along" and "abutment" in front of the "continuous abutment" and the intervening materials, areas or structures that lead to the said materials , Area or structure with respect to each other does not exist in physical contact with the structure. In one embodiment and as shown, the first capacitor node 42 is directly above the first current node 26 of the first transistor 18, and in one embodiment, the container-like first capacitor node 42 is The crystal 18 is longitudinally coaxial (eg, in the illustrated embodiment, along a common vertical axis). Any suitable conductive composition may be used for the first capacitor node 42, and the conductive composition may be the same as or different from the conductive composition of one or both of the access line 22 and the sensing line 14. An exemplary first capacitor node 42 may be formed by first depositing a conductive material that is much greater than one of the thicknesses shown, followed by isotropic or anisotropic etch back to leave a node above the first current node 26 42 one base. Alternatively, the conductive material may be deposited to roughly its final thickness, followed by filling the opening with sacrificial material, then performing etchback, and then removing the sacrificial material. Referring to FIG. 9, the capacitor dielectric 44 has been deposited to line and not completely fill the remaining volume of the opening 40. In one embodiment and as shown, the capacitor dielectric material 44 extends across the top 43 of the container-like first capacitor node 42 and in one embodiment directly abuts the top 43. Exemplary materials for capacitor dielectric 44 are non-ferroelectric materials, such as any one or more of silicon dioxide, silicon nitride, aluminum nitride, hafnium oxide, zirconium oxide, and the like. Alternatively, the above materials may include ferroelectric materials, such as any one or more of transition metal oxides, zirconium, zirconium oxide, hafnium, hafnium oxide, lead zirconate titanate, tantalum oxide, and barium strontium titanate; and There is a dopant therein, and the dopant includes one or more of silicon, aluminum, lanthanum, yttrium, erbium, calcium, magnesium, niobium, strontium, and rare earth elements. Referring to FIGS. 10 and 11, a conductive material has been deposited over the capacitor dielectric 44, and subsequently the conductive material is planarized and the capacitor dielectric material 44 is at least reduced to the top of one of the materials 34, thus forming a second conductive Capacitor node 46. The conductive materials of the capacitor nodes 46 and 42 may be the same or different compositions with respect to each other. Regardless, the features 42, 44 and 46 form a post 47 in the individual opening 40. In one embodiment and as shown, the post 47 is a capacitor post. Referring to FIG. 12, the material 30 in which the opening 40 is formed has been recessed so that the uppermost portion 50 of the post 47 protrudes vertically outward relative to one of the upper surfaces 49 of the material 30, so the vertical outermost of the material 30 in FIG. 3 Partly sacrificial. In one embodiment and as shown, at least some of the material 34 has been removed vertically inwards to form an upper surface 49, the posts project vertically outward relative to the upper surface 49, and in one embodiment As shown, the vertical inward removal includes selectively etching away all vertical outer material 38 relative to the vertical inner material 36 (not shown). In this document, a selective etch or removal is one in which one material of another material is removed or etched or removed at a ratio of at least 2:1. Alternatively, by way of example only, a single composition material (not shown) may be used (ie, without different composition layers 36 and 38), for example, where the material A timed etching of 34 is performed to produce an etchback of a structure similar to that shown in FIG. Referring to FIGS. 13 to 15, a ring 52 of shielding material 53 has been circumferentially formed around the protruding portion 50 of the individual post 47. The rings 52 form individual mask openings 54 that are defined by four closely surrounding rings 52 in the immediate row 16. The mask openings 54 are staggered within the row and immediately adjacent the openings 40 in the row and between the adjacent openings 40 in the row. The material 53 of the ring 52 may be completely sacrificial and therefore may include any conductive, insulating and/or semi-conductive material. As an ideal example, the ring 52 may be formed by depositing the material 53 to a lateral thickness less than F (for example, one-half of the F thickness shown), followed by anisotropic masked etching of the material at intervals Therefore, the maximum and/or minimum lateral dimension of the vertical section of the opening 54 is sub-F and/or sub-lithographic. The maximum length of the opening 54 may be sub-F and/or sub-lithographic. In one embodiment and as best shown in the enlarged view of FIG. 15, at least the horizontal cross-section at the vertical outer portion of the individual mask opening 54 has an hourglass shape. In this document, an "hourglass shape" requires that the opposite longitudinal ends of the shape are each wider (regardless of whether the width is the same) or a central portion of the shape. The illustrated hourglass shape of the mask opening 54 can be considered to include a longitudinally extending side surface 58 and a laterally extending end surface 57 (FIG. 15). In one embodiment and as shown, the laterally extending outermost surface 57 of the hourglass shape is round and concave. In one embodiment and as shown, the longitudinally extending outermost surface 58 of the hourglass shape is rounded and concave between the longitudinal ends of the hourglass shape (eg, surface 57). Referring to FIG. 16, when the material 30 is etched through the mask opening 54 to form the individual via opening 60 to the individual first current node 26 of the individual second transistor 20, the ring 52 and the pillar 47 have been used as a mask cover. One or more of any suitable anisotropic etching chemistries and techniques currently available or yet to be developed can be used to perform this step. If the horizontal cross section of the individual mask opening 54 has an hourglass shape, the shape may not be transferred to the bottom of the through-hole opening 60 in whole, in part, or at all. Referring to FIG. 17, a conductive material 62 has been formed in the individual via opening 60 to electrically couple with the first current node 26 of the second transistor 20 (in one embodiment, direct electrical coupling). The conductive material 62 may have a composition that is the same as or different from the material of the capacitor nodes 42 and/or 46. In one embodiment and as shown, conductive material 62 is deposited to overfill via opening 60 and vertically outward from ring 52 and post 47. 18 and 19, the protruding portion 50 (not shown) and the ring 52 (not shown) of the capacitor post 47 have been removed from above the material 30 (and material 33), thus forming the post 67 of the conductive material 62 and including the dielectric Capacitor 44 and capacitor 71 of capacitor nodes 42 and 46. This step can be performed by any existing or yet to be developed technology such as etching, resist etch back or chemical mechanical polishing. In one embodiment and as shown, this removal is sufficient to completely remove material 36 (not shown) from the substrate, for example, at least receding to the top 27 of dielectric material 33. In one embodiment and as shown, at least a majority (ie, more than half and including all) of the protruding portion 50 (not shown) and the ring 52 (not shown) are removed within the via opening 60 to form conductive material After 62. In one embodiment, the conductive post 67 has a vertical outer portion having an hourglass shape in horizontal section. In this embodiment, the entire vertical thickness of the conductive pillar 67 may have various horizontal sections in the shape of an hourglass, or its vertical inner portion may not have this shape. Referring to FIGS. 20 and 21, the conductive material 64 has been deposited and patterned to electrically couple (in one embodiment, direct electrical coupling) the conductive material 62 in the individual via opening 60 with the four tightly surrounding capacitor pillars One of 47, thus forming an individual 2T-1C memory cell MC (for clarity, only one MC profile is shown in FIG. 21). This memory unit can be formed by patterning and etching with or without pitch doubling, and with or without mosaic doubling. Regardless and in one embodiment, the above example process shows: the formation of conductive material 62 in via opening 60 and the electrical coupling of their via openings to one of four tightly surrounding capacitor pillars 47 It is carried out in two separate conductive material deposition steps with a time interval. The conductive material 64 may have the same or different composition relative to the conductive material 62 and the conductive materials of the capacitor nodes 42 and/or 46. FIGS. 20 and 21 show that the conductive material 64 electrically couples the conductive material 62 of the individual pillar 67 to the capacitor pillar 47 immediately to the left, but in some embodiments the conductive material 62 of the individual pillar 67 may alternatively be connected to three other capacitor pillars Any of 47 is electrically coupled. The conductive materials 62 and 64 effectively form part of the second capacitor node 46 (and therefore capacitor 71), which is the direct electrical coupling of these materials relative to each other (eg, the conductive material 64 directly abuts the capacitor node 46 within the opening 40 Conductive material, and the conductive material 62 directly abuts the result of the conductive material 64). Therefore and in one embodiment, the second capacitor node 46/64/62 directly abuts the top 59 of one of the capacitor dielectric materials 44. In any case and as shown in one embodiment, the second capacitor node 46/64/62 is located directly above the first current node 26 of the second transistor 20, and in one embodiment is also located directly on the first circuit Above the first current node 26 of the crystal 18. In one embodiment and as shown, the first capacitor node 42 is directly electrically coupled with the first current node 26 of the first transistor 18, and the second capacitor node 46 is the first current with the second transistor 20 Node 26 is directly electrically coupled. In one embodiment and as shown, the post 67 formed by the material 62 is longitudinally coaxial with the second transistor 20. Embodiments of the present invention include methods independent of forming an array of 2T-1C memory cells, methods independent of forming memory cells, and methods independent of forming capacitors. For example, embodiments of the present invention include inter-column staggered column openings (e.g., 40) (e.g., FIG. 4) that form a plurality of columns (e.g., 16), and whether or not those openings will contain a memory cell or integrated body One of the circuit capacitors or other components) one method. A post (such as 47, and regardless of whether the post includes a capacitor that is still part of the finished circuit construction or a material of other operative circuit components) is formed in individual ones of the post openings. The pillars are formed to project vertically outward relative to an upper surface of the material in which the pillar openings are formed (e.g., FIG. 12 and regardless of the technique for forming such projecting pillars). A ring of shielding material (eg, ring 52 of material 53) is formed circumferentially around individual posts. The rings form individual mask openings (e.g., 54), which are defined by four closely surrounding rings in the immediate row, where the rings are interleaved in the adjacent column opening row and are located between the adjacent pillar openings . When the material in which the pillar openings are formed (e.g., FIG. 16) is etched through the mask openings to form individual through-hole openings (e.g., 60) interleaved in the row of adjacent pillar openings and located between the pillar openings, the The ring and column are used as a mask. A conductive material (eg, 62) is formed in the via opening and one of the operational circuit components (eg, 71, and the circuit component formed in one of the four pillar openings that tightly surround the individual via openings) It does not matter whether it is a capacitor or not) electrical coupling (for example by material 64, and in one embodiment direct electrical coupling). In one embodiment, the operational circuit component includes a capacitor, and the post is formed to include a conductive material of the capacitor (eg, the material of the capacitor node 46) and a capacitor dielectric material (eg, 44), and the conductive material And the capacitor dielectric material is still part of the finished circuit structure. The vertically protruding portions of the pillars include conductive materials and capacitor dielectrics. In one embodiment, the capacitor includes two conductive nodes separated by a dielectric of the capacitor, and the conductive material of only one of the conductive nodes is oriented vertically with respect to the upper surface of the material in which the pillar opening is formed External protrusions (eg, materials 46 and 44 as shown in FIG. 12 protrude relative to surface 49). FIG. 22 is a diagrammatic representation of a structure 10 that is somewhat similar to FIG. 13 (ie, the same configuration and scale), showing the column opening 40, the ring 52, the mask opening 54 and also showing the source/drain region 26 Outline, but the conductive material of the capacitor electrode 46 is not shown. It is believed that if the idealized circle forming the opening 40 is centered on the vertex of the regular hexagon 70, there will be a theoretically regular hexagon 70 (ie, congruent sides and congruent inner angles), which will form these One of the openings is theoretically a 2D hexagonal close packed (HCP) array. It is believed that in the illustrated actual example embodiment configuration, an irregular hexagon 72 has concentric circles 40/26 centered on the vertices of the hexagon. Both hexagon 70 and hexagon 72 are shown centered on a central circle 40z/26z. As can be seen and in one embodiment, the hexagon 72 can be viewed as a result of stretching the hexagon 70 in the "x" direction but not stretching or shrinking in the "y" direction. The ring 52 is shown graphically as having individually a circular perimeter that overlaps the immediately adjacent ring 52 diagonally. Therefore and in one embodiment, whether or not these rings 52 form a circle, the rings are not tangent to each other. Fig. 23 shows an alternative embodiment configuration 10a in which immediately adjacent diagonal rings 52 are tangent with respect to each other. The same numbering from the embodiments explained above has been used where appropriate, with the suffix "a" indicating some structural differences. In the configuration 10a, the hexagon 72a has been expanded relative to the hexagon 70 in both "x" and "y" directions, so that the immediately adjacent rings 52 on the diagonal are tangent to each other. FIG. 24 shows an alternative embodiment configuration 10b in which the immediately adjacent diagonal rings 52 are not tangent with respect to each other, and the hexagon 72b is relative to the hexagon 70 in both directions "x" and "y" Different (for example, stretch along "x" and shrink along "y"). The same numbering from the embodiments explained above has been used where appropriate, with the suffix "b" showing some structural differences. As is apparent from FIGS. 22 to 24, the mask openings 54/54a/54b have different longitudinal lengths and different degrees of “hourglass” (that is, a larger width of the longitudinal end relative to the middle means a greater degree of “hourglass”). In one embodiment and as shown, the column openings 40 are arranged into a 2D centered rectangular Bravais lattice. Embodiments of the present invention include a memory unit that is independent of the manufacturing method. However, any of these memory cells may have any of the attributes described above with respect to the structure in the method embodiment. In one embodiment, a memory cell (eg, MC) includes a first transistor and a second transistor (eg, 18 and 20, respectively) that are laterally displaced relative to each other. A capacitor (eg, 71) is located above the first transistor and the second transistor, and includes a container-like first conductive capacitor node (eg, electrically coupled to a first current node (eg, 26) of a first transistor , 42). A second conductive capacitor node (eg, 46/64/62) is electrically coupled to a first current node (eg, 26) of one of the second transistors. A capacitor dielectric material (eg, 44) is located between the first capacitor node and the second capacitor node. The capacitor dielectric material extends across the top (eg, 43) of one of the container-like first capacitor nodes. Any other attributes or aspects shown and/or described above may be used. In one embodiment, a memory cell includes a first transistor and a second transistor that are laterally displaced relative to each other. A capacitor is located above the first transistor and the second transistor, and includes a first conductive capacitor node electrically coupled to a first current node of a first transistor (regardless of whether it is a container). A second conductive capacitor node is electrically coupled to a first current node of a second transistor. A capacitor dielectric material is located between the first capacitor node and the second capacitor node. The second capacitor node directly abuts one of the capacitor dielectric materials (eg, 59) between the first capacitor node and the second capacitor node. Any other attributes or aspects shown and/or described above may be used. In one embodiment, a 2T-1C one capacitor memory cell includes a first transistor and a second transistor that are laterally displaced relative to each other. A capacitor is located above the first transistor and the second transistor. The capacitor includes a first conductive capacitor node directly above a first current node of one of the first transistors and electrically coupled to the first current node (regardless of whether it is a container). A second conductive capacitor node is directly above the first transistor and the second transistor and is electrically coupled to a first current node of the second transistor. A capacitor dielectric material is located between the first capacitor node and the second capacitor node, at least at a vertical outer portion. The second capacitor node includes a vertically extending conductive post (for example, 67), which is directly above the first current node of the second transistor. The conductive column has a vertical outer portion with a horizontal cross section in the shape of an hourglass. The entire vertical thickness of the conductive pillar may be a different horizontal section of an hourglass shape, or its vertical inner portion may not have this shape. In one embodiment, the memory cell occupies no more than one of the maximum horizontal area of 5.2F ² (for example, 5.2F ² in FIG. 22), where "F" is the first transistor and the second transistor The minimum horizontal width of the smaller (if any) of the top of the vertical outermost surface of a current node. In one such embodiment, the maximum horizontal area is less than 5.2F ² (Figure 24). Any other attributes or aspects shown and/or described above may be used. Summary In some embodiments, a memory cell includes a first transistor and a second transistor that are laterally displaced relative to each other. A capacitor is located above the first transistor and the second transistor. The capacitor includes: a container-like first conductive capacitor node electrically coupled to a first current node of a first transistor; a second conductive capacitor node electrically coupled to a first current node of a second transistor ; And a capacitor dielectric material, which is located between the first capacitor node and the second capacitor node. The capacitor dielectric material extends across the top of one of the container-like first capacitor nodes. In some embodiments, a memory cell includes a first transistor and a second transistor that are laterally displaced relative to each other. A capacitor is located above the first transistor and the second transistor. The capacitor includes: a first conductive capacitor node electrically coupled to a first current node of a first transistor; a second conductive capacitor node electrically coupled to a first current node of a second transistor; and a A capacitor dielectric material located between the first capacitor node and the second capacitor node. The second capacitor node directly abuts one of the capacitor dielectric materials between the first capacitor node and the second capacitor node. In some embodiments, a two-transistor-capacitor memory cell includes a first transistor and a second transistor that are laterally displaced relative to each other. A capacitor is located above the first transistor and the second transistor. The capacitor includes: a first conductive capacitor node directly above a first current node of the first transistor and electrically coupled to the first current node; a second conductive capacitor node directly located on the first transistor and Above the second transistor and electrically coupled to a first current node of the second transistor; and a capacitor dielectric material, which is located between the first capacitor node and the second capacitor node. The second capacitor node includes a vertically extending conductive pillar directly above the first current node of the second transistor. The conductive column has a vertical outer portion with a horizontal cross section in the shape of an hourglass. In some embodiments, one method used in manufacturing an integrated circuit includes forming staggered pillar openings between a plurality of columns. A pillar is formed in the individual in the openings of the pillars. The pillars protrude vertically outward relative to an upper surface of the material in which the pillar opening is formed. A ring of shielding material is formed circumferentially around the individual posts. The rings form individual mask openings, which are defined by four closely surrounding rings located in the immediate row and interleaved with the adjacent column opening row and between the immediately adjacent column openings. When the material in which the pillar openings are formed is etched through the mask openings to form individual through-hole openings interleaved in the row of adjacent pillar openings and located between the pillar openings, the ring and pillar are used as a mask. A conductive material is formed in the individual via openings, the conductive material being directly electrically coupled to one of the operative circuit components formed in one of the four pillar openings that tightly surround the individual via openings. In some embodiments, a method of forming an array of two transistor-capacitor memory cells includes forming rows of sensing lines. A plurality of columns of vertically extending alternating field effect transistors in the first column and alternating field effect transistors in the second column are formed, and the field effect transistors individually have their vertical inner source/drain regions electrically coupled To the individual in the sensing line. The first transistor and the second transistor include an access line located above the sensing line. The individual ones of the first transistor and the second transistor include a gate, which constitutes a part of the individual of the access lines. A plurality of capacitor openings are formed, and the capacitor openings individually extend to a vertical outer source/drain region of an individual first transistor. A capacitor post is formed in the individual of the capacitor openings. The capacitor column includes: a first conductive capacitor node electrically coupled to the individual in the vertical outer source/drain region of the individual first transistor; a second conductive capacitor node; and a capacitor dielectric material, It is located between the first capacitor node and the second capacitor node. The material in which the capacitor opening is formed is recessed so that the uppermost portion of the capacitor column protrudes vertically outward with respect to one of the upper surfaces of the material in which the capacitor opening is formed. A ring of shielding material is circumferentially formed around the protruding portions of the individual capacitor columns in the capacitor columns. The rings form individual mask openings, which are defined by four tightly surrounding rings located in the immediate row and interleaved with the adjacent capacitor opening row in the row and between the adjacent capacitor openings in the row. When the material in which the capacitor opening is formed is etched through the mask opening to form an individual through-hole opening to the individual in the vertical outer source/drain region of the individual second transistor, the ring and pillar Used as a mask. Remove the protruding portion and ring of the capacitor post from above the material in which the capacitor opening is formed. A conductive material is formed in the individual via openings, the conductive material is electrically coupled to the individual vertical outer source/drain regions of the individual second transistors and electrically coupled to one of the four tightly surrounding capacitor pillars. In accordance with the regulations, the subject matter disclosed in this article has been explained in language that is unique or not unique to structural and methodological features. However, it should be understood that, since the components disclosed herein include example embodiments, the scope of patent application is not limited to the specific features shown and described. Therefore, the scope of patent application is provided by the literal wording to provide the full scope, and it is properly interpreted according to the teaching of equivalent content.

3-3‧‧‧line 4‧‧‧ circuit 5-5‧‧‧ line 6-6‧‧‧ line 8-8‧‧‧ line 10‧‧‧Structure 10a‧‧‧Alternative embodiment structure/structure 10b‧‧‧Alternative embodiment structure/structure 11-11‧‧‧ line 12‧‧‧Structure 13‧‧‧ Base substrate 14‧‧‧sensing line/adjacent pair of sensing lines 14-14‧‧‧ line 16‧‧‧Column 18‧‧‧First transistor/transistor/first field effect transistor/alternating field effect transistor/field effect transistor/individual first transistor 20‧‧‧Second transistor/transistor/second field effect transistor/alternating field effect transistor/field effect transistor 21-21‧‧‧ line 22‧‧‧Access line/Word line/Gate/Access line 23‧‧‧Gate insulator 24‧‧‧Second current node/exemplary area/vertical internal source/drain area 26‧‧‧First current node/exemplary area/node/source/drain area 27‧‧‧Top 28‧‧‧channel area/example area 29‧‧‧Dielectric material/material 30‧‧‧Material 31‧‧‧Silicon nitride 32‧‧‧Vertical inner dielectric material/inner dielectric material 33‧‧‧ Silicon dioxide/material/dielectric material 34‧‧‧Vertical outer material/material 36‧‧‧Vertical inner material/material/composition layer 38‧‧‧Vertical outer material/material/composition layer 40‧‧‧ openings/immediate openings in columns/staggered column openings/columns 40/26‧‧‧Concentric circles 40z/26z‧‧‧Center circle 42‧‧‧Container-shaped first capacitor node/node/capacitor node/feature/first capacitor node/container-shaped first conductive capacitor node/exemplary first capacitor node 43‧‧‧Top 44‧‧‧Capacitor Dielectrics/Features/Dielectrics/Capacitor Dielectric Materials/Materials 46‧‧‧Second conductive capacitor node/capacitor node/second capacitor node/material/capacitor electrode 47‧‧‧post/capacitor post 49‧‧‧Upper surface/surface 50‧‧‧Top part/protruding part 52‧‧‧ Ring/Diagonal next to the ring 53‧‧‧Shading material/material 54‧‧‧Mask opening/opening 54a‧‧‧mask opening 54b‧‧‧mask opening 57‧‧‧Laterally extending end surface/Laterally extending outermost surface/surface 58‧‧‧longitudinal extension side surface/longitudinal extension outermost surface 59‧‧‧Top 60‧‧‧Through hole opening 62‧‧‧conductive material/second capacitor node/material/second conductive capacitor node 64‧‧‧conductive material/second capacitor node/material/second conductive capacitor node 67‧‧‧pillar/conductive column/vertical extension conductive column 70‧‧‧regular hexagon/theoretically regular hexagon/hexagon 71‧‧‧Capacitor/Operating Circuit Assembly 72‧‧‧ Irregular hexagon/Hexagon 72a‧‧‧Hexagon 72b‧‧‧Hexagon BL-C‧‧‧second comparison bit line/comparison bit line BL-T‧‧‧First comparison bit line/comparison bit line CAP‧‧‧Capacitor MC‧‧‧Example two-transistor-capacitor memory unit/memory unit/two-transistor-capacitor memory unit T1‧‧‧transistor T2‧‧‧transistor WL‧‧‧Word line

Figure 1 shows a schematic diagram of a non-structural diagram of a 2T-1C memory cell. 2 is a schematic top plan view of a structure including a 2T-1C memory cell array under manufacture according to an embodiment of the invention. FIG. 3 is a cross-sectional view taken through line 3-3 in FIG. 2. 4 is a view of the configuration of FIG. 2 at a processing step after the step shown by FIG. 2. FIG. 5 is a cross-sectional view taken through line 5-5 in FIG. 4. FIG. 6 is a cross-sectional view taken through line 6-6 in FIG. 7 is a view of the configuration of FIG. 4 at a processing step after the step shown by FIG. 4. FIG. 8 is a cross-sectional view taken through line 8-8 in FIG. 7. FIG. 9 is a view of the configuration of FIG. 8 at a processing step after the step shown by FIG. 8. 10 is a top plan view of the configuration of FIG. 9 at a processing step after the step shown by FIG. 9. FIG. 11 is a cross-sectional view taken through line 11-11 in FIG. 10. 12 is a view of the configuration of FIG. 11 at a processing step after the step shown by FIG. 11. 13 is a top plan view of the configuration of FIG. 12 at a processing step following the step shown by FIG. 14 is a cross-sectional view taken through line 14-14 in FIG. FIG. 15 is an enlarged view of a part of FIG. 14. 16 is a view of the configuration of FIG. 14 at a processing step after the step shown by FIG. 14. FIG. 17 is a view of the configuration of FIG. 16 at a processing step after the step shown by FIG. 16. 18 is a top plan view of the configuration of FIG. 17 at a processing step after the step shown by FIG. 17. FIG. 19 is a cross-sectional view taken through line 19-19 in FIG. 18. FIG. 20 is a view of the configuration of FIG. 18 at a processing step after the step shown by FIG. 18. 21 is a cross-sectional view taken through line 21-21 in FIG. 20. 22, 23, and 24 are diagrammatic top plan views of an array according to an embodiment of the invention.

12‧‧‧Structure

13‧‧‧ Base substrate

14‧‧‧sensing line/adjacent pair of sensing lines

18‧‧‧First transistor/transistor/first field effect transistor/alternating field effect transistor/field effect transistor/individual first transistor

20‧‧‧Second transistor/transistor/second field effect transistor/alternating field effect transistor/field effect transistor

22‧‧‧Access line/Word line/Gate/Access line

23‧‧‧Gate insulator

24‧‧‧Second current node/exemplary area/vertical internal source/drain area

26‧‧‧Second current node/exemplary area/vertical internal source/drain area

27‧‧‧Top

28‧‧‧channel area/example area

29‧‧‧Dielectric material/material

30‧‧‧Material

31‧‧‧Silicon nitride

33‧‧‧ Silicon dioxide/material/dielectric material

42‧‧‧Container-shaped first capacitor node/node/capacitor node/feature/first capacitor node/container-shaped first conductive capacitor node/exemplary first capacitor node

43‧‧‧Top

44‧‧‧Capacitor Dielectrics/Features/Dielectrics/Capacitor Dielectric Materials/Materials

46‧‧‧Second conductive capacitor node/capacitor node/second capacitor node/material/capacitor electrode

47‧‧‧post/capacitor post

59‧‧‧Top

62‧‧‧conductive material/second capacitor node/material/second conductive capacitor node

64‧‧‧conductive material/second capacitor node/material/second conductive capacitor node

67‧‧‧pillar/conductive column/vertical extension conductive column

MC‧‧‧Example two-transistor-capacitor memory unit/memory unit/two-transistor-capacitor memory unit

Claims (15)

A method used in manufacturing an integrated circuit, which includes: Forming a plurality of column openings, which are inter-row staggered; Forming a pillar in the individual of the pillar openings, the pillars projecting elevationally outward with respect to an upper surface of the material in which the pillar openings are formed; A ring of shielding material is formed circumferentially around the individual posts, the rings forming individual shield openings, the shield openings are defined by four tightly surrounding rings in the rings The tightly looped ring is located in the immediate row of the columns and is inter-row-staggered with the immediate column opening row in the column openings and between the adjacent column openings; When the material in which the column openings are formed is etched through the mask openings to form individual through-hole openings interleaved in the column opening rows immediately adjacent to the column openings and between the column openings , Use the rings and columns as a shield; and A conductive material is formed in the individual via openings, the conductive material being directly electrically coupled to one of the operative circuit components formed in one of the four pillar openings that tightly surround the individual via openings. The method of claim 1, which includes, after the etching, removing all portions of the rings of the masking material and the pillars that protrude vertically outward relative to the upper surface. The method of claim 2, comprising performing at least a majority of the removal after forming the conductive material in the via openings. The method of claim 1, which includes performing the formation of the conductive material in the through-hole openings and the electrical coupling in two separate time-spaced conductive material deposition steps. The method of claim 1, wherein the circuit component is a capacitor, and the method includes: The post is formed as a portion including the conductive material and capacitor dielectric material of the capacitor and still incorporating the finished circuit structure of the capacitor, and the vertically outwardly protruding portions of the posts include the conductive material and the capacitor dielectric Electricity. The method of claim 5, wherein the capacitor includes two conductive nodes separated by the dielectric of the capacitor, the conductive material of only one of the conductive nodes relative to the material in which the pillar openings are formed The upper surface protrudes vertically outward. The method of claim 1, wherein the immediately adjacent diagonal lines in the rings are not tangent with respect to each other. The method of claim 1, wherein the immediately adjacent diagonal lines in the rings are tangent with respect to each other. The method of claim 1 includes forming the individual mask openings into a hourglass shape with a horizontal cross section. The method of claim 1 includes: Forming the material in which the pillar openings are formed to include a vertical inner dielectric material and a vertical outer material; and The formation of these pillars includes: After the pillars are formed in the pillar openings, at least some of the vertical outer material is vertically removed inwards to form the upper surface, the pillars are oriented vertically with respect to the upper surface Outstanding. The method of claim 10, wherein the vertical outer material includes a vertical outer material and a vertical inner material, the vertical inner material has a composition different from that of the vertical outer material, and the removing includes : Selectively etch away all the vertical outer material relative to the vertical inner material, and directly abut the vertical inner material to form the rings. The method of claim 1, wherein the openings of the pillars are arranged into a 2D centered rectangular Bravais lattice. A method for forming an array of two transistor-capacitor memory cells, including: Forming several rows of sensing lines; A plurality of columns of vertically extending alternating field effect transistors in the first column and alternate field effect transistors in the second column are formed, and the alternating field effect transistors in the columns individually make one of the source/drain regions vertical The inner source/drain regions are electrically coupled to individual ones of the sensing lines, the first transistor and the second transistor include an access line located above the sensing lines, the first transistor and the The individual in the second transistor includes a gate including the part of the individual in the access lines; Forming a plurality of capacitor openings individually extending to the vertical outer source/drain regions of the individual first transistors; Forming a capacitor post in individual ones of the capacitor openings; the capacitor post includes: a first conductive capacitor node in the vertical outer source/drain regions of the respective first transistors Individuals are electrically coupled; a second conductive capacitor node; and a capacitor dielectric material between the first capacitor node and the second capacitor node; Recessing the material in which the capacitor openings are formed, so that the uppermost portion of the capacitor pillars protrudes vertically outward relative to an upper surface of the material in which the capacitor openings are formed; A ring of shielding material is circumferentially formed around the protrusions of the individual ones of the capacitor columns, the rings forming individual shield openings, which are tightly surrounded by four of the rings A ring is defined, the four tightly surrounding rings are located in the immediately adjacent rows of the columns and are interleaved in the row of capacitor openings immediately adjacent in the rows of the capacitor openings, and between the adjacent capacitor openings in the rows ; When etching the material in which the capacitor openings are formed through the mask openings to form individual via openings to individual ones of the vertical outer source/drain regions of the individual second transistors , Use the rings and columns as a mask; Removing the protruding portions of the capacitor columns and the rings from above the material in which the capacitor openings are formed; and A conductive material is formed in the openings of the individual vias, the conductive material is electrically coupled to the individual vertical outer source/drain regions of the individual second transistors, and is in contact with four of the capacitor pillars One of the tightly surrounding capacitor columns is electrically coupled. The method of claim 13, wherein at least a majority of the removal occurs after forming the conductive material in the via openings. The method of claim 13, which includes performing the formation of the conductive material in the openings of the vias and the electrical coupling in two separate time-deposited conductive material deposition steps.

Images