TW202005000A - Formation of staircase structure in 3D memory - Google Patents

Abstract

A forming method of a staircase structure of a 3D memory including: forming an alternating layer stack on a substrate; forming a plurality of staircase regions, wherein each of the staircase regions has a staircase structure having step(s) with a first number (M) in a first direction; forming a first shielding layer stack to expose a plurality of the staircase regions; removing M layer(s) of layer stacks at the exposing staircase regions; forming a second shielding layer on the alternating layer stack to expose at least an edge of each of the staircase regions in a second direction; and repeatedly removing a portion of 2M layers of layer stacks and trimming the second shielding layer in sequence.

Description

Step formation in three-dimensional memory

Embodiments of the present disclosure relate to three-dimensional (3D) memory devices and methods of making the same.

Through the improvement of process technology, circuit design, programming algorithms and manufacturing processes, the planar storage unit is scaled to a smaller size. However, as the feature size of the storage unit approaches the lower limit, the planar manufacturing process and manufacturing technology become more challenging and the cost is higher. Therefore, the storage density of the planar storage unit is close to the upper limit.

The 3D memory architecture can solve the density limitation in planar storage units. The 3D memory architecture includes a memory array and peripheral devices for controlling signals to and from the memory array. A typical 3D memory architecture includes a stacked layer of gate electrodes arranged above a substrate, where a plurality of semiconductor channels pass through the word line and cross the word line into the substrate. The intersection of the word line and the semiconductor channel forms a memory cell.

The 3D memory architecture requires an electrical contact scheme to allow control of each individual memory unit. One electrical contact planning is to form a stepped structure of word lines connected to each individual memory cell. The ladder structure has been used to connect more than 32 word lines along the semiconductor channels in a typical 3D memory device.

As semiconductor technology advances, 3D memory devices, such as 3D NAND memory devices, continue to scale more oxide/nitride (ON) layers. As a result, the existing multi-cycle trimming and etching processes used to form such stepped structures suffer from low throughput and are costly.

Disclosed herein is an embodiment of a method for forming a stepped structure of a 3D memory device. The disclosed structures and methods provide many benefits, including but not limited to reducing the manufacturing complexity and manufacturing cost of 3D memory devices.

In some embodiments, a method for forming a 3D memory device includes: forming an alternately stacked layer including a plurality of pairs of dielectric layers disposed above a substrate, and forming a stepped region, wherein, in the stepped region Each has a stepped structure having a first number (M) of steps in the first direction, wherein each of the M steps exposes a portion of the surface of the stacked layer of the alternating stacked layers, and The first number M is a positive number. The method also includes removing the M stacked layers of the alternately stacked layers at the first plurality of stepped regions. The method further includes: removing a portion of the 2M stacked layers of the alternately stacked layers at each of the stepped regions using the first mask stacked layer; trimming the first mask stacked layer; and in turn Repeat the following two processes: using the first mask stack layer to remove a portion of the 2M stacked layers of the alternately stacked layers at each of the stepped regions and trimming the first mask stack layer .

In some embodiments, forming the stepped region further includes: forming a second mask stack layer on the alternating stack layer; using a lithography process to pattern the second mask stack layer to form A stepped area is defined above the alternately stacked layers; the second mask stack layer is used to remove a portion of the topmost dielectric layer pair; the second mask stack layer is trimmed; and the removal and trimming are repeated sequentially until the M is formed Steps.

In some embodiments, removing the M stacked layers of the alternately stacked layers includes dry etching, wet etching, or a combination thereof.

In some embodiments, trimming the first mask stack layer includes using isotropic dry etching, wet etching, or a combination thereof to etch the first mask stack layer inward and incrementally.

In some embodiments, the first mask stack layer is patterned through a lithography process to expose the edges of each of the step areas at least in the first direction and to cover the step areas widely in the second direction Everyone.

In some embodiments, the first direction is perpendicular to the second direction, and both the first and second directions are parallel to the top surface of the substrate.

In some embodiments, the method further includes forming a plurality of vertical semiconductor channels in the stacked storage area on the substrate, wherein each of the stepped areas is adjacent to the stacked storage area.

In some embodiments, the lithography process will define the first plurality of step areas and other step areas, wherein the first plurality of step areas and the other step areas are separated by the stacked storage area.

In some embodiments, a method for forming a 3D memory device includes: forming an alternately stacked layer over a substrate; removing the first of the alternately stacked layers over a first portion of the surface of the alternately stacked layer A number (M) of stacked layers, where M is greater than one; and a stepped structure is formed above the second portion of the surface of the alternately stacked layers, wherein the second portion of the surface includes the surface The first part, and each of the stepped structures has M steps in the first direction, wherein each of the M steps is one level, thereby exposing the stacked layers of the alternating stacked layers The part of the surface.

In some embodiments, the method further includes sequentially repeating the following two processes: using a first mask stacked layer to remove 2M stacked layers of the alternate stacked layers at each of the stepped structures and Trim the first mask stack layer.

In some embodiments, the first mask stack layer is patterned through a lithography process to cover a portion of each step structure.

In some embodiments, forming the alternately stacked layers includes depositing the layers using chemical vapor deposition, physical vapor deposition, plasma enhanced CVD, sputtering, metal organic chemical vapor deposition, atomic layer deposition, or a combination thereof .

In some embodiments, forming alternating stacked layers on the substrate includes providing a plurality of pairs of dielectric layers on the substrate.

In some embodiments, forming the alternately stacked layers includes arranging alternating pairs of conductor/dielectric layers in the vertical direction.

In some embodiments, the 3D memory device includes alternating stacked layers disposed above the substrate; a storage structure including a plurality of vertical semiconductor channels; a first stepped region adjacent to the storage structure; and the storage A second stepped region adjacent to the structure, wherein the second stepped region is horizontally separated from the first stepped region by the storage structure; and provided at each of the first and second stepped regions to expose the A stepped structure of a portion of a plurality of stacked layers in an alternately stacked layer, wherein the stepped structure includes a plurality of steps in a first direction and a first number (M) of steps in a second direction, wherein, the Each of the steps in the first direction has a 2M level.

In some embodiments, the first direction is perpendicular to the second direction, and both the first and second directions are parallel to the top surface of the substrate.

In some embodiments, each of the steps in the second direction of the stepped structure is one level.

In some embodiments, the topmost stacked layer of the stepped structure in the second stepped region is M levels lower than the topmost stacked layer in the first stepped region.

In some embodiments, each of the alternately stacked layers includes an insulating material layer and a sacrificial material layer.

In some embodiments, each of the alternately stacked layers includes an insulating material layer and a conductive material layer.

In some embodiments, the insulating material layer includes silicon oxide or aluminum oxide, and the sacrificial material includes polycrystalline silicon, silicon nitride, polycrystalline germanium, polycrystalline germanium silicon, or a combination thereof.

In some embodiments, the conductive material layer includes polysilicon, silicide, nickel, titanium, platinum, aluminum, titanium nitride, tantalum nitride, tungsten nitride, or a combination thereof.

Those skilled in the art can understand other aspects of the present disclosure based on the description, claims, and drawings of the present disclosure.

Although specific configurations and arrangements have been discussed, it should be understood that this is for exemplary purposes only. Those skilled in the relevant art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of the present disclosure. It will be apparent to those skilled in the relevant art that the present disclosure can also be used in a variety of other applications.

It should be noted that references to "one embodiment", "embodiments", "exemplary embodiments", "some embodiments", etc. in the specification indicate that the described embodiments may include specific features, structures or characteristics, but Not every embodiment includes this particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. In addition, when a specific feature, structure, or characteristic is described in conjunction with an embodiment, it should be within the knowledge of those skilled in the relevant art to implement such feature, structure, or characteristic in combination with other embodiments (whether or not explicitly described).

Generally, terminology can be understood at least in part from use in context. For example, depending at least in part on the context, the term "one or plural" as used herein may be used to describe features, structures, or characteristics in the singular, or may be used to describe combinations of features, structures, or characteristics in the plural. Similarly, depending at least in part on the context, terms such as "a" or "said" can also be understood to convey singular usage or plural usage. Furthermore, the term "based on" may be understood as a set of factors that are not necessarily intended to convey an exclusivity, and on the contrary may allow additional factors that are not necessarily explicitly described, which are also at least partially dependent on the context.

It should be easily understood that the meanings of "on", "above", and "on" in this disclosure should be interpreted in the broadest way so that "on" not only means "directly on" The thing "on" also includes something on "on" with intervening features or layers in between. In addition, "above" or "above" not only means "above" or "above" something, but also includes "above" or "above" something. And there is no meaning of intervening features or layers (ie, directly on something).

In addition, space-related terms such as "below", "below", "lower", "above", "upper", etc. are used herein to describe one element or feature and another for convenience of description Or the relationship of multiple elements or features, as shown in the drawings. Spatially related terms are intended to cover different orientations in the use or steps of the device than those depicted in the drawings. The device can be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially related descriptors used herein can be similarly interpreted accordingly.

As used herein, the term "substrate" refers to a material on which subsequent materials are added. The substrate includes a top surface and a bottom surface. The top surface of the substrate is where the semiconductor device is formed, and therefore the semiconductor device is formed on the top side of the substrate. The bottom surface is opposite the top surface, and therefore the bottom side of the substrate is opposite the top side of the substrate. The substrate itself can be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. In addition, the substrate may include a wide range of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, and the like. Alternatively, the substrate may be made of a non-conductive material such as glass, plastic or sapphire wafer.

As used herein, the term "layer" refers to a portion of material that includes regions with thickness. The layer has a top side and a bottom side, where the bottom side is the side of the layer that is relatively close to the substrate, and the top side is the layer that is relatively far from the substrate. The layer can extend over the entirety of the underlying or superstructure, or can have a range that is less than the extent of the underlying or superstructure. In addition, the layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than that of the continuous structure. For example, the layer may be located between the top and bottom surfaces of the continuous structure or between any horizontal plane groups at the top and bottom surfaces. The layer may extend horizontally, vertically and/or along inclined surfaces. The substrate may be a layer, which may include one or a plurality of layers, and/or may have one or a plurality of layers on, above, and/or below it. The layer may include a plurality of layers. For example, the interconnect layer may include one or a plurality of conductors and contact layers (in which contacts, interconnect lines and/or vias are formed) and one or a plurality of dielectric layers.

As used herein, the term “nominal/nominally” refers to a desired or target value of a characteristic or parameter for a component or process step set during the design phase of a product or process, and above and/or below The range of expected values. The range of values may be due to slight changes in the manufacturing process or tolerances. As used herein, the term "about" indicates a given amount of value that may vary based on the specific technology node associated with the subject semiconductor device. Based on a particular technology node, the term "about" may indicate a given amount of value, which varies, for example, within 10%-30% of the value (eg, ±10%, ±20%, or ±30% of the value).

As used herein, the term "3D memory device" refers to a string of vertically aligned memory cell transistors (referred to herein as a "memory string", such as a NAND string) on a laterally oriented substrate A semiconductor device so that the memory string extends in a vertical direction relative to the substrate. As used herein, the term "vertically/vertically" refers to a lateral surface that is nominally perpendicular to the substrate.

In some embodiments, NAND strings or 3D memory devices include semiconductor channels (eg, silicon channels) that extend vertically through a plurality of conductor/dielectric layer pairs. The multiple conductor/dielectric layer pairs are also referred to herein as "alternating semiconductor/dielectric stack layers". The conductor layers in the alternating conductor/dielectric stack can be used as word lines (to electrically connect one or more control gates). The intersection of the word line and the semiconductor channel forms a memory cell. Vertically oriented memory strings require electrical connections between conductive materials (word line boards or control gates) and access lines (eg, word lines) to enable unique selection along the memory string or in 3D memory Each of the storage units in the file is used for writing or reading functions.

In the 3D memory device architecture, storage units for storing data are vertically stacked to form a stacked storage structure. The 3D memory device may include a stepped structure formed on one or a plurality of sides of the stacked storage structure for, for example, word line fan-out purposes, wherein the stacked storage structure includes a plurality of semiconductor channels, wherein the semiconductor channels It can be vertical or horizontal. As the demand for higher storage capacity continues to increase, the number of vertical stages of stacked storage structures also increases. Accordingly, a thicker mask layer (for example, a photoresist (PR) layer) is required to etch a stepped structure having an increased number of levels. However, the increase in the thickness of the mask layer can make the etching control of the stepped structure more challenging.

In this disclosure, a stepped structure refers to a set of surfaces that includes at least two horizontal surfaces (eg, along the xy plane) and at least two (eg, first and second) vertical surfaces (eg, along the z-axis) , So that each horizontal surface abuts the first vertical surface extending upward from the first edge of the horizontal surface, and abuts the second vertical surface extending downward from the second edge of the horizontal surface. Each of the horizontal surfaces is called a "step" or "step" of a stepped structure. In the present disclosure, the horizontal direction may refer to a direction (for example, x-axis or y-axis) parallel to the top surface of a substrate (for example, a substrate providing a fabrication platform on which a structure is formed), and a vertical direction It may refer to a direction perpendicular to the top surface of the structure (eg, z-axis).

The stepped structure may be formed of a dielectric stack layer by repeatedly etching the dielectric stack layer using a mask layer formed on the dielectric stack layer. In some embodiments, the mask layer may include a photoresist (PR) layer. In the present disclosure, the dielectric stack layer includes a plurality of alternately arranged pairs of dielectric layers, and the thickness of each dielectric layer pair is one level. In other words, each of the pair of dielectric layers has a height of one level in the vertical direction. In the present disclosure, the terms "step" and "step" are used interchangeably to refer to one or more steps of a step structure, and the step (or step) exposes a portion of the surface of the pair of dielectric layers. In some embodiments, the pair of dielectric layers includes alternating layers of first and second materials. In some embodiments, the first material layer includes an insulating material layer. In some embodiments, the second material layer includes a sacrificial material layer or a conductive material layer. In some embodiments, the first material layer and the second material layer in a dielectric layer pair may nominally have the same height above the substrate, so that one group may form a step. During the formation of the stepped structure, the mask layer is trimmed (eg, etched inwardly and incrementally from the boundary of the dielectric stack layer) and used as an etching mask, thereby etching the exposed portion of the dielectric stack layer. The amount of masking layer that is trimmed can be directly related to the size of the step (eg, determined by it). Appropriate etching (eg, isotropic dry etching or wet etching) may be used to obtain trimming of the mask layer. One or more mask layers can be formed and trimmed one after another to form a stepped structure. After trimming the mask layer, each dielectric layer pair may be etched using an appropriate etchant to remove portions of both the first material layer and the second material layer. After the stepped structure is formed, the mask layer can be removed. In some embodiments, the second material layer is a conductive material layer, and thus may be a gate electrode (or word line) of a 3D memory structure. In some embodiments, the second material layer of the stepped structure is a sacrificial material layer, and can then be replaced with a metal/conductor layer to form a gate electrode (or word line) of the 3D memory structure.

The ladder structure can provide an interconnection scheme as a word line fan-out to control the semiconductor channel after the interconnect formation process. Each of the pair of dielectric layers in the stepped structure crosses a portion of the semiconductor channel. After replacing each of the sacrificial layers with a metal/conductor layer, each of the conductive material layers in the stepped structure can control the portion of the semiconductor channel. Examples of the interconnect formation process include disposing or otherwise depositing a second insulating material such as silicon oxide, spin-on dielectric or borophosphosilicate glass (BPSG) over the stepped structure, and planarizing the second insulating material. Each of the conductive material layers in the stepped structure is exposed to open a plurality of contact holes in the planarized second insulating material, and the contact holes are filled with one or more conductive materials such as titanium nitride and tungsten, In order to form a plurality of VIA (Vertical Interconnect Access) structure.

In this disclosure, the term "SC" refers to a pair of dielectric layers within a stepped structure. In some embodiments, the stepped structure includes alternating stacked layers, each stacked layer representing an SC layer.

FIG. 1 shows a structure 100 having a plurality of SC layers formed on a substrate (not shown) (eg, formed on the top side of the substrate). Each of the SC layers may include a pair of dielectric layers having a first material layer 102 and a second material layer 104. The mask stack layer material (eg, photoresist layer) is deposited and patterned to form the mask stack layer 152 over the SC layer. The mask stack layer 152 defines the regions 101 and 103 of the SC layer. The top surface of the SC layer at the area 101 is exposed, and the SC layer at the area 103 is covered by the mask stack layer 152. In some embodiments, the mask stack layer 152 may include a photoresist or a carbon-based polymer material. In some embodiments, both region 101 and region 103 are defined through mask stack layer 152 using one or more processes including lithography and etching processes.

The first material layer 102 may be an insulating layer including silicon oxide, and the second material layer 104 may be a sacrificial layer including silicon nitride, and vice versa. In some embodiments, the sacrificial layer is replaced with a conductive material layer (for example, a gate metal material) to form a word line of the 3D memory device. In some embodiments, the second material layer may be a conductive material layer.

In some embodiments, the substrate on which the structure 100 is formed may include any suitable material for supporting the 3D memory structure. For example, the substrate may include silicon, silicon germanium, silicon carbide, silicon on insulator (SOI), germanium on insulator (GOI), glass, gallium nitride, gallium arsenide, any suitable III-V compound, any other suitable materials and /Or their combination.

In some embodiments, the thickness of each SC layer may be the same as or different from each other. In some embodiments, the sacrificial layer includes any suitable material other than an insulating material layer. For example, the sacrificial layer may include one or more of polycrystalline silicon, silicon nitride, polycrystalline germanium, polycrystalline germanium silicon, any other suitable material, and/or combinations thereof. In some embodiments, the sacrificial layer may include silicon nitride. The insulating layer may include any suitable insulating material, for example, silicon oxide or aluminum oxide. The conductive material layer may include any suitable conductive material. In some embodiments, the conductive material layer may include one of polysilicon, silicide, nickel, titanium, platinum, aluminum, titanium nitride, tantalum nitride, tungsten nitride, any other suitable material, and/or combinations thereof Or more. The formation of the insulating material layer, the sacrificial material layer, and the conductive material layer may include any suitable deposition method, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma assisted CVD (PECVD), sputtering, Metal organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), any other suitable deposition method, and/or combinations thereof. In some embodiments, the insulating layer, the sacrificial layer, and the conductive material layer are all formed by CVD.

Referring to FIG. 2, the stepped structure 200 is formed by creating a step 105 (step with one step) on the structure 100 and removing the mask stack layer 152. In some embodiments, the mask stack layer 152 is removed after the step 105 is formed. The step 105 has one level, including layers 246 and 248, and the step 105 is formed by performing an etching process to remove at least part of a single SC layer from the first region 101 defined by the mask stack layer 152. In some embodiments, the etching process includes using any suitable etchant (eg, wet etching and/or dry etching) to sequentially remove portions of the first material layer 102 and the second material layer 104. In some embodiments, two different etchants are used to remove portions of the first material layer 102 and the second material layer 104, respectively. The etchant for the first material layer 102 has a sufficiently high etch selectivity relative to the second material layer 104, and vice versa. Accordingly, the lower SC layer can function as an etch stop layer, thereby patterning/etching only a single SC layer. In some embodiments, the first material layer and the second material layer are etched using anisotropic etching such as reactive ion etching (RIE) or other dry etching. In some embodiments, the etchant includes a fluorocarbon (CF4)-based gas or a hexafluoroethane (C2F6)-based gas. In some embodiments, an etchant (eg, of a timed wet etching process) is used to remove both the first material layer and the second material layer, and the etchant includes phosphoric acid. In various embodiments, the method and etchant for removing a single SC layer should not be limited by the embodiments of the present disclosure.

Referring to FIG. 3, the stepped structure 300 is formed by patterning the mask stack layer 352 over a portion of the top surface of the stepped structure 200. In some embodiments, the mask stack layer 352 covers the step 105. In some embodiments, the mask stack layer 352 covers the boundary between the area 101 and the area 103. In some embodiments, the mask stack layer 352 may include a photoresist or a carbon-based polymer material, for example, a photoresist layer. In some embodiments, the mask stack layer 352 may include any suitable material.

Figures 4-5 show structures 400 and 500 using an etch-trimming process, which includes an etching process (shown in Figure 4) and a trim process (shown in Figure 5).

Referring to FIG. 4, two successive SC layers are removed from the step structure 300 through an etching process, thereby creating a second step having two levels. In some embodiments, the etching process may include repeating the etching process twice. In some embodiments, a step with two levels is created. In some embodiments, the etching process may be performed twice in succession, thereby removing portions of two successive SC layers to be on the layers 438, 440, 442, and 444 in the first region 101 and/or in the second region 103 Steps are formed on the inner layers 442, 444, 446, and 448.

Referring to FIG. 5, the mask stack layer 552 is formed after applying the trimming process to the mask stack layer 352. The trimming process includes appropriate etching (eg, isotropic dry etching or wet etching), and occurs in a direction parallel to the substrate surface. The amount of mask layer that is trimmed can be directly related to the lateral dimension of the step. In some embodiments, the mask stack layer 552 covers the first step created by the etching process (shown in FIG. 2).

Referring to FIG. 6, a staggered step structure 600 is formed by repeatedly performing an etching-trimming process on the step structure 300 and then peeling off the mask stack layer 352. In some embodiments, the repeated etching-trimming process exposes the odd SC layer at the second region 103 (eg, layer 102/104, layer 610/612, layer 618/620, layer 626/628, layer 634/636 Etc.) of the top surface of the even SC layer (eg, layer 606/608, layer 614/616, layer 622/624, layer 630/632, layer 638/640, etc.) at the region 101. In some embodiments, the topmost SC layer (eg, layer 646/648) may be exposed at the top of the staggered step structure 600. In some embodiments, the topmost SC layer (eg, layer 646/648) is exposed at both regions 101 and 103. In some embodiments, each of the SC layers may be exposed at the region 101 or the region 103.

7A-7B show a top view and corresponding cross-sectional representation of a 3D memory device 700 according to some embodiments of the present disclosure.

Referring to FIG. 7A, the 3D memory device 700 includes a stacked storage structure region 760 and a plurality of stepped regions 780 and 790 separated by a slit 770. Although FIG. 7A shows one slit 770, the 3D memory member 700 may include a plurality of slits. The stacked storage structure region 760 may include a plurality of semiconductor channels. In some embodiments, the stepped regions 780 and 790 are distributed in different regions adjacent to the stacked storage structure region 760. In some embodiments, each of the stepped areas 780 and each of the stepped areas 790 are separated by a stacked storage area 760 in a direction parallel to the substrate surface (eg, x direction). In some embodiments, after the interconnect formation process, the stepped regions 780 and 790 provide word line fan-out, thereby uniquely selecting each of the memory cells along the semiconductor channel in the stacked storage structure region 760.

FIG. 7B presents a cross-sectional view of the stepped region 780 along the line AA′ specified in FIG. 7A. A plurality of SC layers 720 are formed on the substrate (not shown) in the stepped region 780. Each of the plurality of SC layers 720 may be composed of alternately stacked layers of the first material layer and the second material layer. For example, the SC layer 701 is conceptually equivalent to the combination of the layer 102 and the layer 104 shown in FIG. 1, and so on. The mask stack layer 750 is formed over the SC layer, and covers the top surface of the SC layer 720 at the stepped region 780. In some embodiments, the mask stack layer 750 may include a photoresist or a carbon-based polymer material. In some embodiments, the cross-sectional view of the stepped region 790 is equivalent to the cross-sectional view of the stepped region 780.

FIG. 8A shows some embodiments of the top view of the 3D memory piece 800 after the first stepped structure is formed at each of the stepped regions 880 and 890. FIG. The first stepped structure is formed by applying a repeated etching-trimming process at the stepped area 780 of the 3D memory device 700. In some embodiments, the first stepped structure has three steps at each of the stepped regions 880 and 890, and each of the three steps has one level. As a result, the first step exposes the three topmost SC layers. In some embodiments, the first stepped structure has a first number (M) of steps at each of the stepped regions 880 and 890, and each of the M steps is one level, where the first number M Greater than 2 (M>2). In some embodiments, the first stepped structure is not formed at the stacked storage area 860.

FIG. 8B represents a 3D view of FIG. 8A in which the first step structure has three steps (M=3) at each of the step regions 880 and 890. As shown in FIG. 8B, the first step structure exhibits three steps (M=3), and each of the three steps is one level. In some embodiments, more than two steps (M>2) are formed in the first step along a horizontal direction parallel to the substrate surface (eg, along the y direction or x direction), where the first step exposes M The top part of the SC layer.

9A shows a top view of the 3D memory piece 900 after forming an interwoven step structure at each of a plurality of step regions 980 and 990. The interlaced step structure is formed by forming a second step structure on the first step structure at each of the step regions 880 and 890 of the 3D memory device 800 (for example, superimposing the second step structure on the first step Structurally). The formation of the second stepped structure includes applying a repeated etching-trimming process using a mask stack layer (not shown) formed and patterned on the top surface of the 3D memory device 800. In some embodiments, the mask stack layer may include a photoresist or a carbon-based polymer material. The mask stack layer exposes the edges of each of the stepped regions 880 and 890 in the first direction (eg, x direction), and widely covers the 3D memory device 800 in the second direction (eg, y direction). In some embodiments, the first direction is perpendicular to the second direction, and both the first and second directions are parallel to the surface of the substrate. As a result, the etching-trimming process only occurs in the first direction (eg, x direction) of FIG. 9A. The etching-trimming process will remove M successive SC layers, and therefore may include repeated etching processes or any other wet/dry etching processes. Therefore, the interleaved step structure generated at each of the step regions 980 and 990 includes the second number (N) of steps in the first direction (eg, x direction) and the second direction (eg, y direction) M steps. Each of the N steps in the first direction has M levels, and each of the M steps in the second direction has one level. Thereafter, the mask stack layer is removed to expose the top surface of the 3D memory device 900. In some embodiments, the staggered step structure has four steps (N=4) in a first direction (eg, x direction) and a second direction (eg, y direction) at each of the step regions 980 Three steps (M=3). In some embodiments, the interleaved step structure has two or more steps (N≧2) in the first direction (eg, x direction) at each of the step regions 980 and 990. In some embodiments, the second stepped structure is not formed at the stacked storage area 960.

9B represents an embodiment in which the interleaved step structure has four (N=4) steps in a first direction (eg, x direction) and a second direction (eg, y direction) at each of the step regions 980 ) On the three steps (M=3). The cross-sectional view along the line AA′ designated in FIG. 9A exhibits the stepped region 980 in the first direction (for example, the x direction). Referring to FIG. 9B, four (N=4) steps are shown along the first direction (for example, the x direction), and four (N=4) step regions are formed (indicated by A ₁ -A ₄ in FIG. 9A ), where each of the four (N=4) steps has three (M=3) levels. Since the adjacent regions A ₁ and A ₂ region, and thus the first topmost layer SC (SC layer 912) A ₁ at the second region than the topmost layer SC (SC layer 909) at the Middle area A ₂ (M = 3 )level. In some embodiments, three steps (M=3) are formed in the second direction (for example, y direction) in the area A ₂ , and the height of each step is one level, and the topmost SC layer (for example, SC layer 909) than the top most layer of the SC region a ₁ (e.g., SC layer 912) lower three (M = 3). In some embodiments, the interleaved step structure has a plurality of steps (eg, N=any positive number) in the first direction (eg, x direction) at each of the step regions 980, and the complex number in the first direction Each of the steps has M levels. In some embodiments, the stepped regions A ₃ and A ₄ have the same or similar structure as the regions A ₁ and A ₂ . In some embodiments, the cross-sectional view of the stepped region 990 is equivalent to the cross-sectional view of the stepped region 980.

FIG. 9C shows an exemplary 3D view of the interleaved step structure at each of the step areas 980 and 990 of the 3D memory piece 900. The interleaved step structure includes N steps in a first direction (for example, x direction) and M steps in a second direction (for example, y direction). Each of the N steps in the first direction has M levels, and each of the M steps in the second direction has one level. In some embodiments, the interleaved step structure has twenty-four steps (N=24) in the first direction (eg, x direction) and three steps (M=3) in the second direction (eg, y direction) ), where each of the steps in the first direction has three (M=3) levels, and each of the steps in the second direction has one level. In some embodiments, the interleaved step structure has a second number (N) of steps in a first direction (eg, x direction) and a first number (M) of steps in a second direction (eg, y direction), Among them, each of the steps in the first direction has M levels, and each of the steps in the second direction has one level.

Figures 10-11C show an embodiment of a stepped structure that is interleaved and interleaved. Beginning with the 3D memory device 800, a mask stack layer (not shown) is used to expose the first plurality of stepped regions (eg, stepped regions 890) and cover the second plurality of stepped regions (eg, stepped regions 880). In some embodiments, the mask stack layer may include a photoresist or a carbon-based polymer material. In some embodiments, the mask stack layer covers the stacked storage area 860. An etching process is applied to remove the M successive SC layers at the exposed step area. As a result, as shown in FIG. 10, the topmost SC layer at the stepped region 1090 exposed through the mask stack layer is lower than the topmost SC layer at the stepped region 1080 by M levels. Then, the mask stack layer is removed after the etching process. In some embodiments, the etching process may be a repetition of the etching process or any other dry/wet etching process.

FIG. 11 shows a top view of a 3D memory piece 1100 having a staggered and interlaced step structure at each of a plurality of step areas 1180 and 1190. The interleaved and interleaved step structure is formed by forming a third step structure at each of the step regions 1080 and 1090. The formation of the third step structure includes applying a repeated etching-trimming process using a mask stack layer (not shown) formed and patterned on the top surface of the 3D memory device 1000. In some embodiments, the mask stack layer may include a photoresist or a carbon-based polymer material. The mask stack layer exposes the edges of each of the stepped regions 1080 and 1090 in the first direction (eg, x direction), and widely covers the 3D memory device 1000 in the second direction (eg, y direction). As a result, the etching-trimming process mostly occurs in the first direction (for example, the x direction) of FIG. 11A. The etching-trimming process will remove twice the M (2M) successive SC layers, and therefore may include repeated etching processes or any other wet/dry etching process. Therefore, the interleaved and interleaved step structure generated at each of the step regions 1180 and 1190 includes a total of a third number (Q) of steps in the first direction (for example, the x direction), where Q steps Each of them has (2M) level. The topmost SC layer from the stepped region 1190 is lower than the topmost SC layer from the stepped region 1180 by M levels. Thereafter, the mask stack layer is removed to expose the 3D memory device 1100. In some embodiments, the interleaved and interleaved step structure has four steps (Q=4) in each of the step regions 1180 and 1190 in the first direction (eg, x direction), and four steps Each of them has (2M) level. In some embodiments, the interleaved and interleaved step structure has two or more steps (Q≧2) in the first direction (eg, x direction) at each of the step regions 1180 and 1190, and Q Each of the steps has a (2M) level. In some embodiments, the interlaced and interlaced structure has a third number (Q) of steps in the first direction (eg, x direction) and the second direction at each of the step regions of the 3D memory device ( For example, the first number (M) of steps in the y direction), where each of the Q steps in the first direction has a level of 2M, and each of the M steps in the second direction has a level , And the topmost SC layer at the first plurality of step regions is lower than the topmost SC layer at the second plurality of step regions by M levels. In some embodiments, the numbers M, N, and Q can be any positive numbers. In some embodiments, after the interconnect formation process, one of the stepped regions 1180 and one of the stepped regions 1190 provides word line fan-out, thereby uniquely selecting each of the memory cells along the semiconductor channel in the stacked storage structure region 1160 One.

11B and 11C represent exemplary 3D views of the interleaved and interlaced step structure at each of the step areas 1180 and 1190 of the 3D memory device 1100, respectively. Referring to FIGS. 11B and 11C, the interleaved and interleaved step structure has four (Q=4) steps in the first direction (for example, x direction), and each of the Q steps is in the step regions 1180 and 1190 There are six steps (2×M=2×3=6) in the second direction (for example, the y direction) at each of. The first topmost SC layer (eg, layer 1120) from the stepped region 1190 is three levels lower (M=3) than the second topmost SC layer (eg, layer 1122) from the stepped region 1180. The lines AA', BB', CC', and DD' correspond to those in Fig. 11A. In some embodiments, each of the stepped regions 1190 and 1180 exhibit a staggered and interleaved stepped structure that includes Q steps in a first direction (eg, x direction) and a second direction (eg, y Direction) M steps. Each of the Q steps in the first direction has a (2M) level, and each of the M steps in the second direction has a level. At least one of the stepped regions 1190 is lower than at least one of the stepped regions 1180 by M levels. In some embodiments, the interleaved and interleaved step structure has five steps (Q=5) in the first direction (eg, x direction) and three steps (M= in the second direction (eg, y direction) 3), where each of the Q steps in the first direction (for example, x direction) has six steps (2×M=2×3=6), and the second direction (for example, y direction) Each of the M steps has one level, and at least one of the stepped regions 1190 is three (M=3) steps lower than at least one of the stepped regions 1180. In some embodiments, the interleaved and interleaved step structure has four steps (Q=4) in the first direction (eg, x direction) and four steps (M= in the second direction (eg, y direction) 4), where each of the Q steps in the first direction (for example, x direction) has eight levels (2×M=2×4=8), and M steps in the second direction (y direction) Each of the steps has one level, and the stepped area 1190 is four steps lower than the stepped area 1180 (M=4). In some embodiments, after the interconnect formation process, at least one of the stepped regions 1180 and at least one of the stepped regions 1190 provide word line fan-out, thereby uniquely along the semiconductor channel in the stacked storage structure region 1160 Select each of the storage units.

Embodiments of the present disclosure also provide a method for forming a staggered and interwoven step structure in a 3D memory piece. FIG. 12 illustrates an exemplary method 1200 for forming a 3D memory device according to some embodiments. The steps of method 1200 may be used to form the memory device structure shown in FIGS. 1-11C. It should be understood that the steps shown in method 1200 are not exhaustive, and that other steps may be performed before, after, or between the shown steps. In some embodiments, some steps of the exemplary method 1200 may be omitted or may include other steps not described here for simplicity. In some embodiments, the steps of method 1200 may be performed in a different order and/or there may be changes.

In step 1210, a substrate for forming a 3D memory device is provided. The substrate may include any suitable material for forming a three-dimensional storage structure. For example, the substrate may include silicon, silicon germanium, silicon carbide, SOI, GOI, glass, gallium nitride, gallium arsenide, plastic plates, and/or other suitable III-V compounds.

In step 1220, alternately stacked layers are deposited over the substrate. Each stacked layer of alternately stacked layers represents an SC layer. The SC layer may include a pair of dielectric layers having a first material layer and a second material layer. In some embodiments, the first material layer may be an insulating layer, and the second material layer may be a sacrificial layer, and vice versa. In some embodiments, the first material layer may be an insulating layer, and the second material layer may be a conductive material layer, and vice versa. The sacrificial layer may include materials such as silicon nitride, polycrystalline silicon, polycrystalline germanium, polycrystalline silicon germanium, any other suitable materials, and/or combinations thereof. The insulating layer may include materials such as silicon oxide, aluminum oxide, or other suitable materials. The conductive material layer may include materials such as tungsten, titanium nitride, tantalum nitride, tungsten nitride, any other suitable materials, and/or combinations thereof. Each of the insulating material layer, the sacrificial material layer, and the conductive material layer may include materials deposited through one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. An example of a plurality of SC layers may be alternating layers 102 and 104 as described above in FIG. 1.

At step 1230, a plurality of step areas on the top surface of the stacked storage area and the SC layer are patterned using the mask stack layer. Each of the stepped areas is adjacent to the stacked storage area. In some embodiments, the first plurality of stepped areas and the plurality of second stepped areas are horizontally separated by the stacked storage area. In some embodiments, the stacked storage area and the plurality of stepped areas are patterned through the mask stack layer using various processes including lithography. In some embodiments, the mask stack layer may include a photoresist or a carbon-based polymer material. An example of stacked storage areas and plural SC layers may be areas 760, 780, and 790 as described above in FIG. 7A. A first step structure is formed at each of the step regions. The first stepped structure may be formed at each of the stepped regions by repeatedly performing the etching-trimming process using the mask stack layer. The etching-dressing process includes an etching process and a finishing process. In some embodiments, the etching process etches a portion of the SC layer. In some embodiments, the etching process etches portions of the plurality of SC layers. In some embodiments, one or more etchants are used during the etching process, and each of the etchants etch the first material layer at a much higher etch rate than the second material layer, The vice versa (for example, high etch selectivity between the first material layer and the second material layer). In some embodiments, due to the high etch selectivity between the first material layer and the second material layer, the etching process can accurately control the etching of the SC layer. The trimming process includes proper etching of the mask stack layer (eg, isotropic dry etching or wet etching), and the trimming process occurs in a direction parallel to the surface of the substrate. The amount of trimmed mask stack layer is directly related to the lateral dimension of the first stepped structure. After the repeated etching-trimming process, the resulting first step structure includes a first number (M) of steps, where each of the M steps is one level. The etching-trimming process can refer to the description of FIGS. 1-6. For the formation of the first stepped structure, reference may be made to the description of FIGS. 8A-8B.

At step 1240, the mask stack layer is patterned to expose the first plurality of step areas and cover the second plurality of step areas. In some embodiments, the mask stack layer covers the stacked storage area. In some embodiments, the mask stack layer is patterned through a lithography process. An etching process similar to the etching process used in the etching-trimming process is applied to remove the first number (M) of the SC layer from the exposed first stepped region. The mask stack layer is removed after the etching process. As a result, the topmost SC layer at the first plurality of step regions is lower than the topmost SC layer at the second plurality of step regions by M levels. For an example of step 1250, reference may be made to the description of FIG. 10.

At step 1250, the mask stack layer is patterned to expose the edge of each of the step regions in the first direction (eg, x direction). In some embodiments, the mask stack layer widely covers the 3D memory device in the second direction (eg, the y direction). The mask stack layer can be used to form a staggered and interwoven step structure through repeated etching-trimming processes. The etching-trimming process includes a trimming process and an etching process. The etching process etches twice as many M (2M) SC layers. Since the mask stack layer widely covers the 3D memory device in the second direction, the entire repeated etching-trimming process occurs mostly in the first direction. Thereafter, the mask stack layer is removed after the repeated etching-trimming process is completed. The formation of the interleaved and interleaved step structure can refer to the description of FIGS. 11A to 11C.

The final interleaved and interleaved step structure includes a plurality of steps in the first horizontal direction and M steps in the second horizontal direction. The height of each of the plurality of steps in the first horizontal direction is 2M levels, and the height of each of the M steps in the second horizontal direction is one level. The topmost SC layer at the first plurality of step areas is lower than the topmost SC layer at the second plurality of step areas by M levels. The first horizontal direction is perpendicular to the second horizontal direction, and both the first and second horizontal directions are parallel to the substrate surface. The first plurality of step areas and the second plurality of step areas are separated by the stacked storage area. As a result, the interleaved and interlaced step structure from one of the first plurality of step regions and one of the second plurality of step regions can expose a portion of the top surface of each SC layer.

At step 1260, a storage structure including semiconductor channels is formed in the stacked storage region. Other processing steps may include forming an interconnect structure at each of the stepped areas of the 3D memory piece. In some embodiments, a semiconductor channel is formed and extends through the SC layer at the stacked storage area. The word lines of the 3D memory device are formed by replacing the sacrificial material layer of each SC layer with a conductor layer. The interleaved and interlaced stepped structure at one of the first plurality of stepped regions and one of the second plurality of stepped regions exposes the portion of each word line at the 3D memory device, which allows interconnection structures (eg, VIA structures ) Provides fan-out of each word line to control each of the semiconductor channels.

The present disclosure describes various embodiments of 3D memory devices and methods of making the same. In some embodiments, the 3D memory device includes alternating stacked layers disposed on the substrate, a storage structure including a plurality of vertical semiconductor channels, a first plurality of stepped regions adjacent to the storage structure, and adjacent to the storage structure The second plurality of step regions, wherein the first plurality and the second plurality of step regions are horizontally separated by the storage structure. Each of the first stepped region and the second stepped region also includes a stepped structure having a first number (M) of first-level steps in the first direction and a plurality of M-level steps in the second direction. The topmost stacked layer of the staircase structure in the second stepped region is M levels lower than the topmost stacked layer in the first stepped region.

In some embodiments, a method for forming a 3D memory device includes: forming an alternately stacked layer including a plurality of pairs of dielectric layers disposed on a substrate; forming a stepped region, wherein each of the stepped regions One has a stepped structure having a first number (M) of steps in the first direction, wherein each of the M steps exposes a portion of the surface of the stacked layer in the alternately stacked layers, and the The first number M is a positive number. The method further includes removing M stacked layers of the first plurality of alternating stacked layers at the stepped regions, and using the first mask stacked layer to remove 2M of the alternately stacked layers at each of the stepped regions Part of the stacked layer, trimming the first mask stacked layer, and sequentially using the first mask stacked layer repeatedly to remove the part of the 2M stacked layers of the alternate stacked layers at each of the stepped regions And trimming the first mask stack layer. The formation of the stepped region further includes forming a second mask stacked layer on top of the alternately stacked layers, patterning the second mask stacked layer using a lithography process to define a stepped region above the alternately stacked layer, using the The second mask stack layer removes a portion of the topmost dielectric layer pair, trims the second mask stack layer, and repeats the removal and the trimming sequentially until the M steps are formed. The removal of the M stacked layers in the alternate stacked layers includes dry etching, wet etching, or a combination thereof. Trimming the first mask stack layer includes using isotropic dry etching, wet etching, or a combination thereof to etch the first mask stack layer inward and incrementally. Patterning the first mask stack layer through the lithography process so as to expose the edges of each of the step regions at least in the first direction and to cover each of the step regions widely in the second direction, Wherein the first direction is perpendicular to the second direction, and both the first direction and the second direction are parallel to the top surface of the substrate. The method also includes forming a plurality of vertical semiconductor channels in the stacked storage area on the substrate, wherein each of the stepped areas is adjacent to the stacked storage area. The lithography process is used to define a first plurality of step areas and other step areas, wherein the first plurality of step areas and other step areas are separated by the stacked storage area.

In some embodiments, a method for forming a 3D memory device includes: forming an alternately stacked layer over a substrate; removing the first of the alternately stacked layers over a first portion of the surface of the alternately stacked layer A number (M) of stacked layers, where M is greater than one; and a stepped structure is formed above the second portion of the surface of the alternately stacked layers, wherein the second portion of the surface includes the surface The first part, and each of the stepped structures has M steps in the first direction, wherein each of the M steps is one level, thereby exposing the stacked layers of the alternating stacked layers The part of the surface. The method further includes sequentially and repeatedly using the first mask stack layer to remove 2M stacked layers of the alternate stack layers at each of the stepped structures and trimming the first mask stack layer. The first mask stack layer is patterned through a lithography process to cover the part of each step structure. Forming alternating stacked layers includes depositing the layers using chemical vapor deposition, physical vapor deposition, plasma assisted CVD, sputtering, metal organic chemical vapor deposition, atomic layer deposition, or a combination thereof. Forming the alternately stacked layers on the substrate includes providing a plurality of pairs of dielectric layers on the substrate. Forming alternating stacked layers includes arranging alternating pairs of conductor/dielectric layers in the vertical direction.

In some embodiments, the 3D memory device includes: alternating stacked layers disposed on the substrate; a storage structure including a plurality of vertical semiconductor channels; a first stepped region adjacent to the storage structure; The second stepped region adjacent to the storage structure, wherein the second stepped region is horizontally separated from the first stepped region by the storage structure. The 3D memory device further includes a stepped structure provided at each of the first stepped region and the second stepped region to expose portions of the plurality of stacked layers of the alternating stacked layers, wherein the stepped The structure includes a plurality of steps in the first direction and a first number (M) of steps in the second direction, where each of the steps in the first direction has a level of 2M. The first direction is perpendicular to the second direction, and both the first and second directions are parallel to the top surface of the substrate. Each of the steps in the second direction of the stepped structure is one level. The topmost stacked layer of the staircase structure in the second stepped region is M levels lower than the topmost stacked layer in the first stepped region. Each of the alternately stacked layers includes an insulating material layer and a sacrificial material layer, or includes an insulating material layer and a conductive material layer. The insulating material layer includes silicon oxide or aluminum oxide. The sacrificial layer includes polycrystalline silicon, silicon nitride, polycrystalline germanium, polycrystalline germanium silicon, or a combination thereof. The conductive material layer includes polysilicon, silicide, nickel, titanium, platinum, aluminum, titanium nitride, tantalum nitride, tungsten nitride, or a combination thereof.

The above description of specific embodiments will therefore fully reveal the general nature of the present disclosure, enabling others to easily modify and/or adjust such specific embodiments for various applications by applying knowledge within the skill of the art, and There is no need for undue experimentation and without departing from the general concept of this disclosure. Therefore, based on the teachings and guidance presented herein, such adjustments and modifications are intended to be within the meaning and scope of equivalents of the disclosed embodiments. It should be understood that the wording or terminology herein is for illustrative purposes and not for limitation, so that the terminology or wording of this specification will be interpreted by the skilled person in accordance with the teaching and guidance.

The embodiments of the present disclosure have been described above with the aid of functional blocks that exemplify implementations specifying functions and their relationships. The boundaries of these functional blocks are arbitrarily defined herein for the convenience of description. Alternative boundaries can be defined as long as the specified functions and their relationships are properly performed.

The summary and abstract sections may illustrate one or more exemplary embodiments of the present disclosure envisioned by the inventor, but not necessarily all exemplary embodiments, and therefore, are not intended to limit the present disclosure and the appended claims in any way .

The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, and should be limited only by the following claims and their equivalents.

100, 400, 500‧‧‧ Structure 101, 103‧‧‧ Region 102‧‧‧ First material layer 104‧‧‧ Second material layer 105‧‧‧ Steps 152, 352, 552, 750‧‧‧ Mask stack Layer 200, 300, 600 ‧‧‧ ladder structure 246, 248, 438~448, 606~648, 1120, 1122‧‧‧ layer 700, 800, 900, 1000, 1100‧‧‧ 3D memory device 701, 720, 909, 912‧‧‧SC layer 760, 1160‧‧‧ stacked storage structure area 770, 970‧‧‧ slit 780~790, 880~890, 980~990, 1080~1090, 1180~1190‧‧‧ ladder area 860, 960‧‧‧ Stacked storage area 1210~1260‧‧‧ Step A ₁ -A ₄ ‧‧‧ area x, y‧‧‧ axis

The drawings incorporated herein and forming a part of the specification illustrate embodiments of the present disclosure and together with the specification are further used to explain the principles of the present disclosure and enable those skilled in the relevant art to make and use the present disclosure. FIG. 1 shows a cross-sectional view of a plurality of pairs of dielectric layers covered by a patterned photoresist stack according to some embodiments. 2 illustrates a cross-sectional view of forming a first step with one stage according to some embodiments. FIGS. 3-5 show perspective representations of various stages of an etch-trimming process to form a step with two levels according to some embodiments. 6 shows a cross-sectional view of a staggered step structure according to some embodiments. 7A shows a top view of an exemplary 3D memory structure according to some embodiments. 7B shows a cross-sectional view of a stepped area according to some embodiments. FIG. 8A illustrates a top view of an exemplary 3D memory structure after forming a stepped structure at each of the stepped regions according to some embodiments. FIG. 8B shows a 3D view of the stepped area according to some embodiments. 9A shows a top view of an exemplary 3D memory structure after forming an interwoven step structure at each of the step regions according to some embodiments. 9B shows a cross-sectional view of a stepped area according to some embodiments. 9C shows a 3D view of the stepped area of FIG. 9A. FIG. 10 shows a top view of an exemplary 3D memory structure according to some embodiments. 11A shows a top view of an exemplary 3D memory structure after forming an interlaced and interleaved step structure at each of the step regions, according to some embodiments. 11B-11C show a 3D view of the stepped area of FIG. 11A. 12 is a flowchart of an exemplary method for forming a 3D memory device according to some embodiments.

900‧‧‧3D memory

960‧‧‧Stacked storage area

970‧‧‧Slit

980, 990‧‧‧ ladder area

A ₁ ~A ₄ ‧‧‧Area

x, y‧‧‧ axis

Claims (20)

A method for forming a 3D memory device includes: forming an alternately stacked layer including a plurality of pairs of dielectric layers disposed above a substrate; forming a stepped region, wherein each of the stepped regions has a A stepped structure having a first number (M) of steps in one direction, wherein each of the M steps exposes a portion of the surface of the stacked layers in the alternately stacked layers, and the first number M is a positive number; Removing the M stacked layers of the first plurality of the alternately stacked layers at the stepped region; using the first mask stacked layer to remove a portion of the 2M stacked layers at each of the stepped regions; Trimming the first mask stack layer; and repeating the following two processes in sequence: using the first mask stack layer to remove the 2M stacked layers of the alternately stacked layers at each of the stepped regions And trimming the first mask stack layer. The method of claim 1, wherein forming the stepped region further comprises: forming a second mask stack layer on the alternating stack layer; patterning the second mask stack layer using a lithography process To define the stepped area above the alternately stacked layers; use the second mask stack to remove the topmost dielectric layer pair; trim the second mask stack; and repeat sequentially The removing and trimming until the M steps are formed. The method of claim 1, wherein removing the M stacked layers of the alternating stacked layers includes dry etching, wet etching, or a combination thereof. The method of claim 1, wherein trimming the first mask stack layer comprises using isotropic dry etching, wet etching, or a combination thereof to etch the first mask stack layer inward and incrementally . The method of claim 1, wherein the first mask stack layer is patterned through a lithography process to expose the edge of each of the step regions in at least the first direction Each of the stepped areas is widely covered in two directions. The method of claim 5, wherein the first direction is perpendicular to the second direction, and both the first direction and the second direction are parallel to the top surface of the substrate. The method of claim 1, further comprising forming a plurality of vertical semiconductor channels in a stacked storage area on the substrate, wherein each of the stepped areas is adjacent to the stacked storage area. The method of claim 7, wherein the lithography process will define the first plurality of step regions and other step regions, wherein the first plurality of step regions and the other step regions are stored through the stack The areas are separated. A method for forming a 3D memory device, comprising: forming an alternately stacked layer over a substrate; removing a first number (M) of the alternately stacked layer over a first portion of a surface of the alternately stacked layer A stacked layer of, wherein M is greater than one; and a stepped structure is formed above the second portion of the surface of the alternately stacked layers, wherein the second portion of the surface includes the first portion of the surface A portion, and each of the stepped structures has M steps in the first direction, wherein each of the M steps is one level, thereby exposing the surface of the stacked layers in the alternating stacked layers part. The method according to claim 9, further comprising sequentially repeating the following two processes: using a first mask stacked layer to remove 2M stacked layers of the alternating stacked layers at each of the stepped structures and Finishing the first mask stack layer. The method of claim 9, wherein forming the alternately stacked layers includes using chemical vapor deposition, physical vapor deposition, plasma assisted CVD, sputtering, metal organic chemical vapor deposition, atomic layer deposition, or a combination thereof To deposit the layer. The method of claim 9, wherein forming the alternately stacked layers on the substrate includes providing a plurality of pairs of dielectric layers on the substrate. A 3D memory device, including: alternating stacked layers disposed on a substrate; the storage structure includes a plurality of vertical semiconductor channels; a first stepped area adjacent to the storage structure; adjacent to the storage structure A second stepped region, wherein the second stepped region and the first stepped region are horizontally separated by the storage structure; and a stepped structure is provided in the first stepped region and the second stepped region At each of the layers to expose portions of the plurality of stacked layers in the alternately stacked layers, wherein the stepped structure includes a plurality of steps in the first direction and a first number (M) of in the second direction Steps, wherein each of the steps in the first direction has a level of 2M. The 3D memory device according to claim 13, wherein the first direction is perpendicular to the second direction, and both the first direction and the second direction are parallel to the top surface of the substrate . The 3D memory device according to claim 13, wherein each of the steps in the second direction of the stepped structure is one level. The 3D memory device according to claim 13, wherein the topmost stacked layer of the stepped structure in the second stepped area is lower than the topmost stacked layer in the first stepped area by M levels. The 3D memory device according to claim 13, wherein each of the alternately stacked layers includes an insulating material layer and a sacrificial material layer. The 3D memory device according to claim 13, wherein each of the alternately stacked layers includes an insulating material layer and a conductive material layer. The 3D memory device according to claim 18, wherein the insulating material layer includes silicon oxide or aluminum oxide, and the sacrificial material includes polycrystalline silicon, silicon nitride, polycrystalline germanium, polycrystalline germanium silicon, or a combination thereof. The 3D memory device according to claim 18, wherein the conductive material layer comprises polysilicon, silicide, nickel, titanium, platinum, aluminum, titanium nitride, tantalum nitride, tungsten nitride, or a combination thereof.

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