TW202004932A - 半導體裝置及其之製造方法 - Google Patents

半導體裝置及其之製造方法 Download PDF

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TW202004932A
TW202004932A TW107144091A TW107144091A TW202004932A TW 202004932 A TW202004932 A TW 202004932A TW 107144091 A TW107144091 A TW 107144091A TW 107144091 A TW107144091 A TW 107144091A TW 202004932 A TW202004932 A TW 202004932A
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silicon oxide
semiconductor substrate
insulating film
film
oxide film
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TW107144091A
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TWI690002B (zh
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久米一平
松田竹人
奧田真也
村野仁彥
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日商東芝記憶體股份有限公司
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Abstract

實施形態提供一種能夠抑制缺陷產生之具有TSV之半導體裝置及其之製造方法。 實施形態之半導體裝置具有：半導體基板，其設置有自第1面貫通至與上述第1面為相反側之第2面之貫通孔；金屬部，其形成於貫通孔之內部；第1絕緣膜，其設置於半導體基板之第2面上及貫通孔之側面；及第2絕緣膜，其設置於半導體基板之貫通孔之側面上之金屬部側之第1絕緣膜上。

Description

半導體裝置及其之製造方法
本實施形態係關於一種半導體裝置及其之製造方法。
採用TSV(Through-Silicon Via，矽穿孔)之半導體裝置之製作方法中，有於半導體基板上製作器件(半導體電路等)之後，將Si薄膜化而形成TSV之方法(Via Last(後穿孔)構造)。與器件微細化之發展相對地，因係藉由TSV自器件之外側連接，故而並不依賴於製程節點，微細化之必要性較低。又，因係於形成製造難度不斷提高之微細器件之後形成TSV，故而不易影響器件良率。
然而，必須將半導體基板利用可再剝離之黏接劑貼合於支持基板，而一面使Si薄膜化一面形成TSV。形成TSV時，必須以低溫進行製作。
實施形態提供一種能夠抑制缺陷產生之具有TSV之半導體裝置及其之製造方法。
實施形態之半導體裝置具有：半導體基板，其設置有自第1面貫通至與上述第1面為相反側之第2面之貫通孔；金屬部，其形成於貫通孔之內部；第1絕緣膜，其設置於半導體基板之第2面上及貫通孔之側面；及第2絕緣膜，其設置於半導體基板之貫通孔之側面上之金屬部側之第1絕緣膜上。
以下，參照圖式，對實施形態之半導體裝置及半導體裝置之製造方法進行詳細說明。再者，並不利用該實施形態限定本發明。又，於以下之說明中，將元件形成對象之半導體基板中之元件形成面設為第1面，將與該第1面為相反側之面設為第2面。
圖1係表示實施形態之半導體裝置之概略構成例之剖視圖。如圖1所示，半導體裝置1具備半導體基板10、絕緣層11、STI(Shallow Trench Isolation，淺溝槽隔離)12、絕緣層13、第1貫通電極14、第2貫通電極18、及接合材料(凸塊)19。
半導體基板10例如係矽基板。該半導體基板10亦可將厚度減薄至50 μm(微米)以下、例如30±5 μm左右。
於半導體基板10之第1面，具有形成半導體元件之主動區域及將主動區域間電分離之STI12。於主動區域形成有記憶單元陣列、電晶體、電阻元件、電容器元件等半導體元件(未圖示)。STI12例如使用氧化矽膜等絕緣膜。於STI12上，設置有將半導體元件電性連接至第2貫通電極18之第1貫通電極14及配線構造35。配線構造35設置於STI12上，且電性連接於設置在半導體基板10之第1面上之半導體元件(例如電晶體)。半導體元件及配線構造35由絕緣層11、13被覆。於半導體基板10之第2面，設置有電性連接於第2貫通電極18之接合材料19等。
絕緣層13為了保護配線構造35而覆蓋配線構造35。該絕緣層13中亦可包含覆蓋配線構造35之鈍化膜、及覆蓋鈍化膜之有機層。鈍化膜可為氮化矽膜(SiN)、氧化矽膜(SiO2 )或氮氧化矽膜(SiON)之單層膜、或其等中兩者以上之積層膜。有機層可使用感光性聚醯亞胺等樹脂材料。
第1貫通電極14與配線構造35接觸。第1貫通電極14亦可包含至少覆蓋貫通孔內表面之障壁金屬層141、障壁金屬層141上之晶種金屬層142、及晶種金屬層142上之貫通電極143。亦可省略障壁金屬層141。亦可於貫通電極143上設置將半導體裝置1縱向積體化時發揮功能之材料膜144。
障壁金屬層141可使用鈦(Ti)、鉭(Ta)、釕(Ru)等。晶種金屬層142可使用銅(Cu)或鎳與銅之積層膜(Ni/Cu)等。貫通電極143可使用鎳(Ni)等。材料膜144可使用金(Au)、錫(Sn)、銅(Cu)、錫-銅(SnCu)、錫-金(SnAu)、錫-銀(SnAg)等。但第1貫通電極14之層構造及材料可根據目的適當變更。例如可根據貫通電極143使用之導電性材料或形成方法而適當變更障壁金屬層141/晶種金屬層142或材料膜144之層構造或材料。
第2貫通電極18藉由與配線構造35接觸，將配線構造35電引出至半導體基板10之第2面上。
第2貫通電極18亦可包含至少覆蓋貫通孔內表面之障壁金屬層(第1金屬層)181、障壁金屬層181上之晶種金屬層(第2金屬層)182、及晶種金屬層182上之貫通電極(金屬部、第3金屬層)183。各自使用之金屬材料可與第1貫通電極14之障壁金屬層141、晶種金屬層142及貫通電極143相同。亦可於貫通電極183之內部形成空隙。又，亦可於貫通電極183上設置用以在將複數個半導體裝置1縱向(半導體基板10之厚度方向)積體化時將半導體裝置1分別接合之接合材料19。該接合材料19可使用錫(Sn)、銅(Cu)、錫-銅(SnCu)、錫-金(SnAu)、錫-銀(SnAg)等焊料。
於半導體基板10之第2面上，設置有氧化矽膜171，於氧化矽膜171上設置有吸濕性較氧化矽膜171低之第1絕緣膜172。即，第1絕緣膜172與氧化矽膜171相比不含水分。藉此，防止氧化矽膜171露出，提高氧化矽膜171之防濕效果。第1絕緣膜172例如係氮化矽膜，膜厚較佳為50 nm以上。
在形成於半導體基板10之貫通孔內之內側面及半導體基板10之第2面上，設置有氧化矽膜171，在氧化矽膜171上設置有第1絕緣膜172。即，氧化矽膜171設置於半導體基板10與第1絕緣膜172之間。
第2絕緣膜173在貫通孔之側面設置於金屬部183側之第1絕緣膜上。第2絕緣膜173未設置於半導體基板10之第2面上。第2絕緣膜173之相對介電常數低於第1絕緣膜172之相對介電常數，第2絕緣膜173之相對介電常數較佳為6.5以下。又，第2絕緣膜173之膜厚厚於氧化矽膜171之膜厚。藉此，提高了防止第2貫通電極18與半導體基板10發生電短路之效果。第2絕緣膜173係以矽氧化物為主成分之膜。即，第2絕緣膜係氧化矽膜。
其次，以下參照圖式，對實施形態之半導體裝置1之製造方法進行詳細說明。圖2～圖8係表示實施形態之半導體裝置之製造方法之製程剖視圖。再者，於圖2～圖8中，使用與圖1相同之截面進行說明。但於圖2中，為了便於說明，截面之上下關係與圖1及圖3～圖8之上下關係相反。
首先，如圖2所示，於半導體基板10之第1面上形成STI12，規定主動區域。半導體基板10例如係矽基板。STI12例如係氧化矽膜。繼而，於主動區域形成半導體元件(未圖示)。半導體元件例如可為記憶單元陣列、電晶體、電阻元件、電容器元件等。形成半導體元件時，於STI12上，例如形成配線構造35。半導體元件及配線構造35由絕緣層11、13被覆。再者，絕緣層13中亦可包含覆蓋配線構造35之鈍化膜、及覆蓋鈍化膜上之有機層。有機層使用感光性聚醯亞胺等，將用以形成第1貫通電極14之開口圖案轉印至該有機層。開口圖案之開口直徑例如可為10 μm左右。
繼而，例如將有機層作為遮罩對絕緣層13之鈍化膜及絕緣層12進行蝕刻，藉此使配線構造35露出。鈍化膜及絕緣層12之蝕刻可採用反應性離子蝕刻(RIE)等。繼而，於包含貫通孔內部之絕緣層13整體上依序積層使用鈦(Ti)之障壁金屬層與使用銅(Cu)之晶種金屬層。障壁金屬層與晶種金屬層之成膜分別可採用濺鍍法或化學氣相沈積(CVD)法等。晶種金屬層之膜厚例如可為500 nm左右。
繼而，採用例如PEP(Photo Engraving Process，光刻製程)技術，於晶種金屬層上形成用以形成貫通電極143之遮罩。於該遮罩之與形成於絕緣層13之貫通孔對應之位置，形成有開口。繼而，於自遮罩之開口露出之晶種金屬層上形成使用鎳(Ni)之貫通電極143。貫通電極143之形成可採用共形鍍覆等。
繼而，去除遮罩之後，將露出之晶種金屬層與障壁金屬層去除。藉此，將貫通電極143下之晶種金屬層142與障壁金屬層141圖案化。再者，晶種金屬層142與障壁金屬層141之圖案化可採用濕式蝕刻。
繼而，於所形成之貫通電極143之上表面上，形成使用金(Au)之材料膜144。材料膜144之形成可採用舉離等形成方法。其結果，如圖2所示，於半導體基板10之元件形成面(第1面)側，形成將配線構造35引出至絕緣層13上之第1貫通電極14。
繼而，如圖3所示，於形成有第1貫通電極14之絕緣層13上塗佈黏接劑，並將支持基板16貼合於該黏接劑，藉此，如圖3所示，於半導體裝置1之元件形成面側黏接支持基板16。繼而，於將支持基板16固定於平台之狀態下對半導體基板10自與元件形成面(第1面)為相反側之第2面進行研磨，藉此將半導體基板10之厚度減薄至例如30±5 μm左右。
繼而，如圖4所示，於半導體基板10上塗佈感光性光阻劑180M，將用以形成第2貫通電極18之開口圖案轉印至該光阻劑180M。再者，開口圖案之開口直徑例如可為10 μm左右。繼而，將轉印有開口圖案之光阻劑180M作為遮罩對半導體基板10自第2面側進行刻蝕，藉此形成到達至配線構造35之貫通孔180H。半導體基板10之刻蝕可採用能夠獲得高縱橫比之各向異性乾式蝕刻等。
繼而，如圖5所示，於包含貫通孔180H之內部之半導體基板10之第2面整體上，成膜氧化矽膜171。氧化矽膜171之成膜例如採用CVD法等。氧化矽膜171例如以150℃以下之條件成膜。其原因在於，於以高於150℃之溫度條件成膜氧化矽膜171之情形時，有黏接劑15劣化而導致支持基板16自第1貫通電極14及絕緣層13剝落之虞。進而，採用例如CVD法，以相同之溫度條件，於氧化矽膜171上形成第1絕緣膜172及第2絕緣膜173。第1絕緣膜係吸濕性較氧化矽膜171低之膜，例如係氮化矽膜。第2絕緣膜係相對介電常數較第1絕緣膜低之膜。第2絕緣膜之相對介電常數較理想為6.5以下。藉此，能夠提高防止第2貫通電極18與半導體基板10發生電短路之效果。
此處，發明人對分別以150℃及400℃形成氧化矽膜時之膜中Si-OH鍵量與Si-O鍵量之比進行了調查。
圖9(a)表示以各溫度進行熱處理時之氧化矽膜之測定結果。圖9(b)表示根據圖9(a)所獲得之解析結果。圖9(b)之解析結果係根據圖9(a)中之氧化矽膜所包含之Si-OH鍵及Si-O鍵之峰值強度比而獲得。如圖9(a)所示，以150℃成膜之氧化矽膜(A)之Si-OH鍵之峰值強度與以400℃成膜之氧化矽膜(A)之Si-OH鍵之峰值強度相比較大。如圖9(b)所示，以400℃成膜之氧化矽膜(B)中之Si-OH/Si-O鍵量比為2.3%，與此相對，以150℃成膜之氧化矽膜(A)中之Si-OH/Si-O鍵量比為11.1%。即，氧化矽膜(A)中之Si-OH/Si-O鍵量比為5%以上且15%以下。因此，以150℃成膜之氧化矽膜(A)與以400℃成膜之氧化矽膜(B)相比包含更多之Si-OH鍵。以150℃成膜之氧化矽膜(B)與以400℃成膜之氧化矽膜(A)相比容易包含更多之水。其原因在於，例如，Si-OH容易與H原子形成氫鍵。此種情形時，以150℃成膜之氧化矽膜(B)容易因含水而膨潤。氧化矽膜(B)以某固定量膨潤時會產生裂紋(缺陷)。又，亦可對以150℃成膜之氧化矽膜以400℃進行熱處理而使Si-OH/Si-O鍵量比成為3%以下，與成膜時將溫度設定為400℃同樣地，能夠獲得吸濕性較低之膜。
本實施形態中，於半導體基板之第2面上所形成之氧化矽膜171上，形成吸濕性較氧化矽膜171低之第1絕緣膜172。如上所述，第1絕緣膜172既可為氮化矽膜，亦可為以400℃成膜之氧化矽膜。藉此，防止氧化矽膜171露出。藉此，防止氧化矽膜171膨潤而於氧化矽膜171產生裂紋。藉由防止於氧化矽膜171產生裂紋，能夠提高半導體裝置之良率。
繼而，如圖6所示，藉由RIE對STI12進行回蝕，藉此將形成於貫通孔180H之底部之STI12去除。該回蝕進行至STI12被去除從而配線構造35露出為止。又，藉由RIE將形成於半導體基板10之第2面上之第2絕緣膜173去除。其結果，於半導體基板10之第2面上第1絕緣膜172露出，並且貫通孔180H之內側面由形成於第2絕緣膜173上之第2絕緣膜173覆蓋，進而，於貫通孔180H之底部配線構造35露出。
繼而，如圖7所示，於包含貫通孔內部之第2絕緣膜173整體上依序積層使用鈦(Ti)之障壁金屬層181A與使用銅(Cu)之晶種金屬層182A。障壁金屬層181A及晶種金屬層182A有時簡稱為金屬層。晶種金屬層182A之膜厚亦可較晶種金屬層142A厚。
繼而，採用例如PEP技術，於晶種金屬層182A上形成用以形成貫通電極183之遮罩183M。於該遮罩183M之與形成於半導體基板10之貫通孔180H對應之位置，形成有開口。繼而，如圖8所示，於自遮罩183M之開口露出之晶種金屬層182A上，形成鎳(Ni)之貫通電極183。貫通電極183之形成可採用共形鍍覆等。
繼而，去除遮罩183M之後，將露出之晶種金屬層182A與障壁金屬層181A去除。晶種金屬層182A與障壁金屬層181A之去除可採用濕式蝕刻。
繼而，於貫通電極183之上表面上形成接合材料19。接合材料19之形成可採用電解電鍍法或無電解電鍍法等。藉由經過以上步驟，形成將配線構造35電引出至半導體基板10之第2面側之第2貫通電極18，製造具備圖1所示之截面構造之半導體裝置1。
以上，根據本實施形態，於半導體基板之第2面上所形成之氧化矽膜171上，形成吸濕性較氧化矽膜171低之第1絕緣膜172。藉此，可防止氧化矽膜171露出，從而防止於氧化矽膜171產生裂紋。
已對本發明之實施形態進行了說明，但該實施形態係作為示例而提出，並非意圖限定發明之範圍。該新穎之實施形態能以其他各種形態實施，且能夠於不脫離發明主旨之範圍內進行各種省略、替換、變更。該實施形態及其之變化包含於發明之範圍及主旨中，並且包含於申請專利範圍所記載之發明及其之均等範圍內。 [相關申請]
本申請享有以日本發明專利申請2018-99669號(申請日：2018年5月24日)為基礎申請之優先權。本申請藉由參照該基礎申請而包含基礎申請之全部內容。
1‧‧‧半導體裝置 10‧‧‧半導體基板 11‧‧‧絕緣層 12‧‧‧STI 13‧‧‧絕緣層 14‧‧‧第2貫通電極 15‧‧‧黏接劑 16‧‧‧支持基板 18‧‧‧第1貫通電極 19‧‧‧接合材料 35‧‧‧配線構造 141‧‧‧障壁金屬層 142‧‧‧晶種金屬層 143‧‧‧貫通電極 144‧‧‧材料膜 171‧‧‧氧化矽膜 172‧‧‧第1絕緣膜 173‧‧‧第2絕緣膜 180H‧‧‧貫通孔 180M‧‧‧光阻劑 181‧‧‧障壁金屬層 181A‧‧‧障壁金屬層 182‧‧‧晶種金屬層 182A‧‧‧晶種金屬層 183‧‧‧貫通電極(金屬部) 183M‧‧‧遮罩
圖1係表示實施形態之半導體裝置之概略構成例之剖視圖。 圖2～8係表示實施形態之半導體裝置之製造方法之製程剖視圖。 圖9(a)及(b)係表示以各溫度進行熱處理時之氧化矽膜之測定結果之圖。
1‧‧‧半導體裝置
10‧‧‧半導體基板
11‧‧‧絕緣層
12‧‧‧STI
13‧‧‧絕緣層
14‧‧‧第2貫通電極
18‧‧‧第1貫通電極
19‧‧‧接合材料
35‧‧‧配線構造
141‧‧‧障壁金屬層
142‧‧‧晶種金屬層
143‧‧‧貫通電極
144‧‧‧材料膜
171‧‧‧氧化矽膜
172‧‧‧第1絕緣膜
173‧‧‧第2絕緣膜
181‧‧‧障壁金屬層
182‧‧‧晶種金屬層
183‧‧‧貫通電極(金屬部)

Claims (10)

  1. 一種半導體裝置，其具有： 半導體基板，其設置有自第1面貫通至與上述第1面為相反側之第2面之貫通孔； 金屬部，其形成於上述貫通孔之內部； 第1絕緣膜，其設置於上述半導體基板之上述第2面上及上述貫通孔之側面；及 第2絕緣膜，其設置於上述半導體基板之貫通孔之側面上之上述金屬部側之第1絕緣膜上。
  2. 如請求項1之半導體裝置，其中於上述半導體基板與上述第1絕緣膜之間形成有第1氧化矽膜。
  3. 如請求項2之半導體裝置，其中上述第1絕緣膜與上述第1氧化矽膜相比，Si-OH/Si-O鍵量比較低。
  4. 如請求項1至3中任一項之半導體裝置，其中上述第1絕緣膜係氮化矽膜。
  5. 如請求項4之半導體裝置，其中上述第2絕緣膜之相對介電常數為6.5以下。
  6. 如請求項5之半導體裝置，其中上述第2絕緣膜係第2氧化矽膜。
  7. 一種半導體裝置之製造方法，其包含如下步驟： 形成貫通半導體基板並開口之貫通孔； 於上述半導體基板上之第2面上及上述貫通孔之內部，以150℃以下成膜第1氧化矽膜； 於上述半導體基板上之第2面上及上述貫通孔之內部之上述第1氧化矽膜上，成膜第1絕緣膜； 於上述半導體基板上之第2面上及上述貫通孔之內部之上述第1絕緣膜上，成膜相對介電常數為6.5以下之第2絕緣膜； 將上述半導體基板上之第2面上之上述第2絕緣膜去除；及 於上述貫通孔之內部形成金屬部。
  8. 如請求項7之半導體裝置之製造方法，其中上述第1絕緣膜與上述第1氧化矽膜相比，Si-OH/Si-O鍵量比較低。
  9. 如請求項7或8之半導體裝置之製造方法，其中上述第1絕緣膜係氮化矽膜，上述第2絕緣膜係第2氧化矽膜。
  10. 一種半導體裝置之製造方法，其包含如下步驟： 形成貫通半導體基板並開口之貫通孔； 如下所述之任一個步驟，即，於上述半導體基板上之第2面上及上述貫通孔之內部，以150℃以下成膜氧化矽膜，然後以400℃以上進行熱處理；或者於上述半導體基板上之第2面上及上述貫通孔之內部，以400℃以上成膜氧化矽膜；及 於上述貫通孔之內部形成金屬部。
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