TW202002098A - Processing reaction chamber capable of inhibiting chamber volume from enlarging in vertical direction and occupying space - Google Patents
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- 238000006243 chemical reaction Methods 0.000 title claims description 52
- 230000002401 inhibitory effect Effects 0.000 title 1
- 239000004065 semiconductor Substances 0.000 claims description 60
- 239000000758 substrate Substances 0.000 claims description 53
- 238000000034 method Methods 0.000 claims description 49
- 230000003028 elevating effect Effects 0.000 claims description 15
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 claims description 12
- 230000001174 ascending effect Effects 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 description 7
- 238000010438 heat treatment Methods 0.000 description 6
- 238000001816 cooling Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 229910052736 halogen Inorganic materials 0.000 description 3
- 150000002367 halogens Chemical class 0.000 description 3
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
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Abstract
Description
本發明係有關一種製程反應腔體。The invention relates to a process reaction chamber.
有關半導體製造裝置,於半導體基板譬如經由熱處理進行成膜之製程反應腔體,係一向為人所知。Regarding semiconductor manufacturing apparatuses, the reaction chamber of a semiconductor substrate, such as a process for forming a film by heat treatment, has been known.
有關這類製程反應腔體,於下列專利文獻1中公開了具有能夠上升之基座的結構。 [專利文獻1]日本特開2014-222693號公報。Regarding the reaction chamber of such a process, the following Patent Document 1 discloses a structure having a susceptor that can be raised. [Patent Document 1] Japanese Unexamined Patent Publication No. 2014-222693.
[發明所欲解決之技術問題] 然而,在專利文獻1所記載之發明中,由於基座能夠上升,而產生了製程反應腔體整體的體積會在上下方向增大並佔空間的問題。[Technical problem to be solved by the invention] However, in the invention described in Patent Document 1, since the susceptor can be raised, there is a problem that the volume of the entire process reaction chamber increases in the vertical direction and takes up space.
本發明之目的係在提供一種製程反應腔體,能夠抑制其體積在上下方向增大並佔空間。The object of the present invention is to provide a process reaction chamber which can suppress its volume from increasing in the vertical direction and occupy space.
[技術手段] 為了解決前述技術問題,本發明的製程反應腔體係為一種對半導體基板進行反應處理之製程反應腔體;其具有:基座,其在該製程反應腔體內被固定配置於上下方向位置,並載置有該半導體基板;升降構件,配置於該基座下方且能夠上升;第1頂銷,係隨著該升降構件上升,且為該升降構件所舉升而將該半導體基板從基座上面朝上方位移;在該基座形成有讓該第1頂銷通過之貫通孔,且在該升降構件中,於和該第1頂銷在上下方向相對處配置有第2頂銷;該第2頂銷係於上下方向延伸並隨著上升動作,使其上端部和該第1頂銷下端部抵接。[Technical means] In order to solve the aforementioned technical problems, the process reaction chamber system of the present invention is a process reaction chamber for performing a reaction process on a semiconductor substrate; it has: a pedestal, which is fixedly arranged in an up-down direction position in the process reaction chamber, and carries The semiconductor substrate is placed; the lifting member is arranged under the base and can be raised; the first ejector pin is raised with the lifting member and lifted by the lifting member to face the semiconductor substrate from the top of the base Displaced upwards; a through hole is formed in the base to let the first ejector pin pass, and in the elevating member, a second ejector pin is arranged opposite to the first ejector pin in the up-down direction; the second ejector pin The pin extends in the up-down direction and ascends so that its upper end contacts the lower end of the first ejector pin.
此外,還具有:從下方支撐該基座的基座支撐架,從上方來看,該第1頂銷可以是配置為比該基座支撐架的外端部還要外側。In addition, there is a base support frame that supports the base from below, and the first ejector pin may be arranged outside the outer end of the base support frame when viewed from above.
此外,還進一步具有:從下方支撐該基座、並以該中心軸線為中心放射狀延伸之基座支撐架,該升降構件具有:在上下方向延伸的支撐管、和從該支撐管在與該中心軸線垂直直徑方向延伸的複數支撐臂;從下方來看,該複數支撐臂和該基座支撐架,在環繞該中心軸線周圍圓周方向的位置可以彼此相異。In addition, it further includes: a base support frame that supports the base from below and extends radially about the center axis, and the lifting member includes a support tube extending in the vertical direction, and a support tube extending from the support tube A plurality of support arms extending perpendicularly to the diameter direction of the central axis; viewed from below, the positions of the plurality of support arms and the base support frame in the circumferential direction around the central axis may be different from each other.
[發明效果] 本發明之製程反應腔體,具有在上下方向位置被固定配置的基座。並且能夠在不使基座上升的情況下,能夠經由讓通過基座貫通孔的第1頂銷上升來把半導體基板朝上方位移。 為此,與譬如使基座上升來把半導體基板朝上位移之結構相比,能夠縮減在上下方向位移之部分結構,而抑制製程反應腔體的體積在上下方向增大並佔空間。[Effect of the invention] The process reaction chamber of the present invention has a pedestal fixedly arranged in the vertical direction. In addition, without raising the base, the semiconductor substrate can be displaced upward by raising the first ejector pin that passes through the base through-hole. For this reason, compared with a structure in which, for example, the pedestal is raised to displace the semiconductor substrate upward, it is possible to reduce the partial structure displaced in the vertical direction, and to suppress the volume of the process reaction chamber from increasing in the vertical direction and occupying space.
此外,在使第1頂銷上升的升降構件中,在與第1頂銷於上下方向相對處配置有第2頂銷,且其上端部和第1頂銷下端部抵接。因此,與譬如在升降構件沒有配置第2頂銷之結構相比,能夠確保升降構件中第2頂銷以外部分和基座在上下方向之距離。 經由此,能夠抑制基座對升降構件的熱傳導,且除了能夠有效利用半導體基板的反應處理熱以外,同時還能夠抑制升降構件之熱疲勞。In addition, in the elevating member that raises the first ejector pin, the second ejector pin is disposed at a position opposed to the first ejector pin in the vertical direction, and the upper end portion and the lower end portion of the first ejector pin abut. Therefore, compared with a structure in which the second ejector pin is not provided in the elevating member, for example, the vertical distance between the portion other than the second ejector pin and the base in the elevating member can be ensured. Through this, it is possible to suppress the thermal conduction of the pedestal to the elevating member, and in addition to being able to effectively use the reaction processing heat of the semiconductor substrate, it is also possible to suppress the thermal fatigue of the elevating member.
其次,參照附圖,說明本發明實施形態之相關製程反應腔體2。
本實施形態相關之製程反應腔體2,係為半導體製造裝置1中,進行經由熱處理等來對半導體基板S成膜之反應處理的腔體。首先,說明半導體製造裝置1之結構。Next, referring to the drawings, a description will be given of a
如圖1所示,半導體製造裝置1具有製程反應腔體2、在製程反應腔體2內部搬送半導體基板S的搬送腔體3、以及和搬送腔體3連接的加載鎖定腔體4。
搬送腔體3配置於製程反應腔體2和加載鎖定腔體4之間。As shown in FIG. 1, the semiconductor manufacturing apparatus 1 includes a
搬送腔體3具有搬運部7。搬運部7具有3個搬運臂5。搬運臂5配置在旋轉軸A周圍能自由轉動。搬運臂5經由在旋轉軸A周圍轉動而能夠於水平方向延伸收縮。The
在複數搬運臂5中,位於最上方部分的尖端設置有葉片(blade)5A。在葉片5A上面承載半導體基板S的狀態下,經由3個搬運臂5在水平方向延伸收縮來搬送半導體基板S。
搬送腔體3中,配置有冷卻裝置6。搬送腔體3中,在與製程反應腔體2連接處配置有L型閘閥8。經由此一結構,能夠確保製程反應腔體2和搬送腔體3之氣密狀態。In the
在加載鎖定腔體4,為了從搬送腔體3將半導體基板S搬進搬出,於加載鎖定腔體4中,在和搬送腔體3連接處配置有氣密門。經由此一結構,能夠確保加載鎖定腔體4和搬送腔體3之氣密狀態。In the
製程反應腔體2具有承載半導體基板S的基座單元10、和在內部承載有基座單元10的腔體本體20。
在腔體本體20,於腔體本體20上側及下側配置有用來加熱半導體基板S的鹵素燈(圖未示)。The
其次,詳述基座單元10之結構。
基座單元10具有:承載半導體基板S的基座11、配置於基座11下方的升降構件12、以及把半導體基板S從基座11的上面朝上移位之第1頂銷13。Next, the structure of the
如圖2及圖3所示,基座11係固定配置在製程反應腔體2的上下方向之位置。在基座11上面承載半導體基板S。基座11,係由基座支撐架15從下方支撐。基座11,從上方來看呈現為圓板狀。
在以下說明中,將與基座11垂直而通過其中心的直線稱為中心軸線O1。同時,把與中心軸線O1垂直的方向稱為直徑方向,環繞中心軸線O1方向稱為圓周方向。As shown in FIGS. 2 and 3, the
基座11及基座支撐架15能夠在圓周方向旋轉。在基座11形成有在上下方向貫穿基座11的貫通孔14。
貫通孔14,於圓周方向間隔開地配置複數個。如圖式的示例中,將3個貫通孔14在圓周方向等間隔地加以配置。貫通孔14上端部的內孔徑往上逐漸增大。The
基座支撐架15具有:以中心軸線O1為中心呈現放射狀延伸之支撐柱15A、和支持支撐柱15A的支撐軸15B。
支撐軸15B與支撐柱15A為一體形成。但是,支撐軸15B與支撐柱15A也可以是個別形成。The
支撐柱15A,係從支撐軸15B的上端部朝直徑方向外側做放射狀延伸。如圖所示,支撐柱15A以120°等間隔地延伸為三個方向。
經由把支撐柱15A於直徑方向的外端部與基座11底部連接,使得基座11為基座支撐架15所支撐。The
升降構件12能夠上升。升降構件12具有:在上下方向延伸之支撐管12A、和從支撐管12A的上端部在直徑方向延伸的複數支撐臂12B。
支撐管12A和支撐臂12B為一體形成。但是,支撐管12A和支撐臂12B也可以是個別形成。The
支撐管12A為配置成與基座支撐架15的支撐軸15B同軸。支撐軸15B貫穿於支撐管12A內側。支撐管12A能對支撐軸15B在上下方向及圓周方向位移。
支撐臂12B,係從支撐管12A的上端部朝直徑方向外側呈放射狀延伸。如圖所示,支撐臂12B以120°等間隔地配置3個。The
第1頂銷13,係能夠隨著升降構件12上升而被升降構件12所舉升。
第1頂銷13,係插入到貫通孔14內側而隨著上升移動通過貫通孔14。第1頂銷13,係分別配置在3個貫通孔14內側。第1頂銷13係配置在不干擾搬運臂5的葉片5A之位置。The
第1頂銷13上端部之外徑係往上逐漸增大。並且,第1頂銷13上端部和貫通孔14上端部在上下方向接合,以使得將第1頂銷13保持在貫通孔14內部。
第1頂銷13之下端部,係從基座11朝下方凸出。第1頂銷13中,朝上的上端面係與基座11的上面為同一面。The outer diameter of the upper end of the
第1頂銷13係位於基座11的外周部。從上方來看,第1頂銷13被配置為比基座支撐架15的支撐柱15A的外端部在直徑方向還要外側。
升降構件12的支撐臂12B在直徑方向之尺寸,係大於基座支撐架15的支撐柱15A在直徑方向之尺寸。The
升降構件12中,在和第1頂銷13於上下方向相對處配置了上下方向延伸並隨著上升之第2頂銷12C,其上端部與第1頂銷13下端部抵接。
第2頂銷12C,係分別配置於升降構件12中支撐臂12B直徑方向之外端部。第2頂銷12C下端緣與支撐臂12B之上面連接。
第2頂銷12C與支撐臂12B係一體形成。但是,第2頂銷12C也可以是和支撐臂12B個別形成。In the elevating
第2頂銷12C係配置為與第1頂銷13同軸。第2頂銷12C的外徑大於第1頂銷13。
第1頂銷13和第2頂銷12C各自在上下方向之長度相等。但是,第1頂銷13的上下方向之長度也可以是長於或短於第2頂銷12C的上下方向之長度。The
並且,如圖3(b)所示,從下方來看,使得複數的支撐臂12B和基座支撐架15,在中心軸線O1周圍之圓周方向的位置互異。
如圖所示,3個支撐臂12B和基座支撐架15的3個支撐柱15A,配置為互相在圓周方向等間隔。但是,也可以使得3個支撐臂12B和基座支撐架15的3個支撐柱15A,在圓周方向之位置於圓周方向不等間隔地互異。Further, as shown in FIG. 3( b ), the plurality of
其次,說明製程反應腔體2內的半導體基板S之處理程序。
首先,以圖4來說明將半導體基板S搬送到製程反應腔體2之製程。
如圖4(a)所示,使搬運臂5的葉片5A從搬送口進入製程反應腔體2內。此時,葉片5A的上面載置稍後進行反應處理的半導體基板S。並且,如圖4(b)所示,使半導體基板S位於基座11上方。Next, the processing procedure of the semiconductor substrate S in the
其次,如圖4(c)所示,使得升降構件12上升。此時,經由使第2頂銷12C的上端部和第1頂銷13下端部抵接來將第1頂銷13舉起。
經由此,讓第1頂銷13把半導體基板S朝上方位移,半導體基板S和搬運臂5的葉片5A之間在上下方向形成間隙。Next, as shown in FIG. 4(c), the lifting
並且,如圖4(d)所示,把搬運臂5的葉片5A朝向搬送口水平方向移動,使得半導體基板S被保持在第1頂銷13的狀態下留置在製程反應腔體2內。其後,使搬運臂5的葉片5A從製程反應腔體2內退出。Then, as shown in FIG. 4( d ), the
其次,使用圖5說明以製程反應腔體2對半導體基板S進行反應處理之製程。
首先,如圖5(a)所示,使升降構件12下降來使第1頂銷13下降。經由此,讓由第1頂銷13保持的半導體基板S朝下方位移,並被載置於基座11上面。
此時,讓升降構件12下降到使得第2頂銷12C和第1頂銷13之間在上下方向產生間隙之位置。經由此,在稍後的反應處理中,能夠抑制基座11和半導體基板S熱傳導到升降構件12。Next, a process of reacting the semiconductor substrate S with the
接著,如圖5(b)所示,對半導體基板S加熱進行反應處理。此時,經由讓基座11於基座支撐架15一起在圓周方向旋轉,來使得半導體基板S在圓周方向的熱傳導均一。經由此,在半導體基板S表面成膜。Next, as shown in FIG. 5(b), the semiconductor substrate S is heated to perform a reaction process. At this time, by rotating the
最後,使用圖6說明從製程反應腔體2取出半導體基板S之製程。
首先,如圖6(a)所示,搬運臂5的葉片5A進入製程反應腔體2內部,同時,經由使升降構件12上升,與前述同樣地讓反應處理後的半導體基板S朝上方位移。並且,使得在半導體基板S和基座11之間在上下方向形成間隙。Finally, the process of taking out the semiconductor substrate S from the
其次,如圖6(b)所示,使葉片5A移動到水平方向的基座11一側,並配置於半導體基板S和基座11之間的間隙。
並且,如圖6(c)所示,使升降構件12下降來將半導體基板S載置到葉片5A上面。
最後,經由使葉片5A在水平方向移動到搬送口,將半導體基板S從製程反應腔體2搬出。其後,對半導體基板S施以後段製程。Next, as shown in FIG. 6( b ), the
如上述說明,本實施形態的製程反應腔體2具有在上下方向位置被固定配置的基座11。並且,能夠在不使基座11上升之情況下,經由貫通基座11的貫通孔14之第1頂銷13上升讓半導體基板S朝上位移。
因此,與譬如使基座11上升來把半導體基板S朝上位移之結構相比,能夠縮減在上下方向位移部分之結構,而能夠抑制製程反應腔體2的體積在上下方向的增大而佔空間。As described above, the
並且,在使第1頂銷13上升的升降構件12中,在與第1頂銷13上下方向相對處配置有第2頂銷12C,其上端部與第1頂銷13下端部抵接。
為此,與譬如在升降構件12沒有形成第2頂銷12C之結構相比,能夠確保升降構件12中第2頂銷12C以外的部分和基座11在上下方向之距離。
經由此,能夠抑制從基座11向升降構件12之熱傳導,而能夠有效利用用於半導體基板S的反應處理之熱,同時也能夠抑制升降構件12之熱疲勞。In addition, in the elevating
並且,經由利用第1頂銷13和第2頂銷12C來使半導體基板S朝上方位移,與譬如只使用第1頂銷13之結構相比,能夠使得第1頂銷13在上下方向縮短。經由此,鹵素燈加熱對象的熱容量變小,而能夠縮短加熱時間。In addition, by displacing the semiconductor substrate S upward by using the
並且,使得第1頂銷13配置在比基座支撐架15的支撐柱15A的直徑方向之外端部還要外側。
為此,第1頂銷13將半導體基板S朝上方位移時,能夠舉升半導體基板S的外周部,使得以第1頂銷13朝上方位移時的半導體基板S的姿勢穩定。In addition, the
並且,由於使得支撐臂12B和基座支撐架15在圓周方向的位置互異,而能夠避免使得從下方傳導到基座11的輻射熱在被支撐臂12B和基座支撐架15所遮住的部分於圓周方向重疊。經由此,能夠抑制傳導到基座11的輻射熱在圓周方向有所偏差(不勻)。Moreover, since the positions of the
並且,即使在使得第1頂銷13短於第2頂銷12C的情況下,由於鹵素燈的加熱對象之熱容量變小,也能夠縮短加熱時間。In addition, even when the
此外,前述實施形態僅為本發明具代表性之一種實施形態。因此,在不脫離本發明意旨的範圍下,能夠對前述實施形態進行種種改變。In addition, the foregoing embodiments are only representative embodiments of the present invention. Therefore, various changes can be made to the aforementioned embodiment without departing from the scope of the invention.
譬如,在前述實施形態中,雖然顯示了第1頂銷13配置為比基座支撐架15外端部還要外側之結構,但不受限於此一形態。第1頂銷13也可以是配置為比基座支撐架15外端部還要內側。For example, in the foregoing embodiment, although the structure in which the
並且,在前述實施形態中,雖然顯示了從下方來看複數的支撐臂12B和基座支撐架15在圓周方向的位置互異之結構,但並不受限於此一形態。也可以是使得複數支撐臂12B和基座支撐架15在圓周方向位置互相一致。In addition, in the foregoing embodiment, although the structure in which the
並且,不受限於前述變形例,也可以選擇這些變形例加以適當組合施行,或是實施其他變形例。In addition, it is not limited to the aforementioned modified examples, and these modified examples may be selected and combined in appropriate combinations, or other modified examples may be implemented.
1‧‧‧半導體製造裝置
2‧‧‧製程反應腔體
3‧‧‧搬送腔體
4‧‧‧加載鎖定腔體
5‧‧‧搬運臂
5A‧‧‧葉片
6‧‧‧冷卻裝置
7‧‧‧搬運部
8‧‧‧L型閘閥
10‧‧‧基座單元
11‧‧‧基座
12‧‧‧升降構件
12A‧‧‧支撐管
12B‧‧‧支撐臂
12C‧‧‧第2頂銷
13‧‧‧第1頂銷
14‧‧‧貫通孔
15‧‧‧基座支撐架
15A‧‧‧支撐柱
15B‧‧‧支撐軸
20‧‧‧腔體本體
A‧‧‧旋轉軸
O1‧‧‧中心軸線
S‧‧‧半導體基板1‧‧‧
圖1係為本發明一種實施形態所示之具有製程反應腔體半導體製造裝置之縱剖面圖。 圖2(a)係在圖1所示之製程反應腔體中基座單元之透視圖,圖2(b)為圖2(a)基座之透視圖; 圖3(a)係為圖2(a)所示之基座單元的前視圖,圖3(b)係為圖2(b)所示基座單元的俯視圖; 圖4係為在圖1所示之製程反應腔體內搬送半導體基板之製程圖; 圖5係為在圖1所示之製程反應腔體內反應處理半導體基板之製程圖; 圖6係為在圖1所示之製程反應腔體內取出半導體基板之製程圖。1 is a longitudinal cross-sectional view of a semiconductor manufacturing apparatus having a process reaction chamber shown in an embodiment of the present invention. 2(a) is a perspective view of the base unit in the process reaction chamber shown in FIG. 1, and FIG. 2(b) is a perspective view of the base of FIG. 2(a); 3(a) is a front view of the base unit shown in FIG. 2(a), and FIG. 3(b) is a top view of the base unit shown in FIG. 2(b); FIG. 4 is a process diagram of transporting a semiconductor substrate in the process reaction chamber shown in FIG. 1; FIG. 5 is a process diagram of a reaction processing semiconductor substrate in the process reaction chamber shown in FIG. 1; FIG. 6 is a process diagram of taking out a semiconductor substrate in the process reaction chamber shown in FIG. 1.
1‧‧‧半導體製造裝置 1‧‧‧Semiconductor manufacturing equipment
2‧‧‧製程反應腔體 2‧‧‧Process reaction chamber
3‧‧‧搬送腔體 3‧‧‧Transport cavity
4‧‧‧加載鎖定腔體 4‧‧‧Load lock cavity
5‧‧‧搬運臂 5‧‧‧carrying arm
5A‧‧‧葉片 5A‧‧‧Blade
6‧‧‧冷卻裝置 6‧‧‧cooling device
7‧‧‧搬運部 7‧‧‧Transport Department
8‧‧‧L型閘閥 8‧‧‧L gate valve
10‧‧‧基座單元 10‧‧‧Base unit
20‧‧‧腔體本體 20‧‧‧Cavity body
A‧‧‧旋轉軸 A‧‧‧Rotating axis
S‧‧‧半導體基板 S‧‧‧Semiconductor substrate
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US201762524973P | 2017-06-26 | 2017-06-26 | |
PCT/JP2018/024176 WO2019004201A1 (en) | 2017-06-26 | 2018-06-26 | Processing chamber |
WOPCT/JP2018/024176 | 2018-06-26 |
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TWI817683B (en) * | 2021-08-31 | 2023-10-01 | 大陸商北京北方華創微電子裝備有限公司 | Semiconductor process chamber, semiconductor process equipment and semiconductor process method |
CN118422169A (en) * | 2024-07-03 | 2024-08-02 | 上海陛通半导体能源科技股份有限公司 | Semiconductor device based on electric cylinder lifting wafer |
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WO2021014657A1 (en) * | 2019-07-25 | 2021-01-28 | エピクルー株式会社 | Process chamber of epitaxial growth apparatus |
US20240339352A1 (en) * | 2023-04-07 | 2024-10-10 | Applied Materials, Inc. | Susceptor for process chamber |
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JPH09205130A (en) * | 1996-01-17 | 1997-08-05 | Applied Materials Inc | Wafer supporting device |
JP2001024047A (en) * | 1999-07-07 | 2001-01-26 | Applied Materials Inc | Substrate support apparatus |
JP2001274225A (en) * | 2000-03-24 | 2001-10-05 | Tokyo Electron Ltd | Treatment apparatus |
JP2003197719A (en) * | 2001-12-21 | 2003-07-11 | Komatsu Electronic Metals Co Ltd | Device for manufacturing semiconductor and structure for supporting substrate |
JP4687534B2 (en) * | 2005-09-30 | 2011-05-25 | 東京エレクトロン株式会社 | Substrate mounting mechanism and substrate processing apparatus |
JP5148955B2 (en) * | 2007-09-11 | 2013-02-20 | 東京エレクトロン株式会社 | Substrate mounting mechanism and substrate processing apparatus |
JP2010232220A (en) * | 2009-03-25 | 2010-10-14 | Tokyo Electron Ltd | Placing table structure, method for manufacturing the same, and processing apparatus |
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TWI817683B (en) * | 2021-08-31 | 2023-10-01 | 大陸商北京北方華創微電子裝備有限公司 | Semiconductor process chamber, semiconductor process equipment and semiconductor process method |
CN118422169A (en) * | 2024-07-03 | 2024-08-02 | 上海陛通半导体能源科技股份有限公司 | Semiconductor device based on electric cylinder lifting wafer |
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