TW201946292A - Light-emitting device - Google Patents

Light-emitting device Download PDF

Info

Publication number
TW201946292A
TW201946292A TW108128752A TW108128752A TW201946292A TW 201946292 A TW201946292 A TW 201946292A TW 108128752 A TW108128752 A TW 108128752A TW 108128752 A TW108128752 A TW 108128752A TW 201946292 A TW201946292 A TW 201946292A
Authority
TW
Taiwan
Prior art keywords
layer
light
semiconductor
emitting element
contact
Prior art date
Application number
TW108128752A
Other languages
Chinese (zh)
Other versions
TWI704698B (en
Inventor
陳昭興
蕭長泰
王佳琨
許啟祥
陳之皓
林永翔
歐瑞 郭
Original Assignee
晶元光電股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 晶元光電股份有限公司 filed Critical 晶元光電股份有限公司
Publication of TW201946292A publication Critical patent/TW201946292A/en
Application granted granted Critical
Publication of TWI704698B publication Critical patent/TWI704698B/en

Links

Abstract

A light-emitting device includes a first semiconductor layer; a plurality of semiconductor pillars separated from each other and formed on the first semiconductor layer, the plurality of semiconductor pillars respectively includes a second semiconductor layer and an active layer; a first electrode covering one portion of the plurality of semiconductor pillars; and a second electrode covering another portion of the plurality of semiconductor pillars, wherein the plurality of semiconductor pillars under a covering region of the first electrode are separated from each other by a first space, the plurality of semiconductor pillars outside the covering region of the first electrode are separated from each other by a second space, and the first space is larger than the second space.

Description

發光元件Light emitting element

本發明係關於一種發光元件,且特別係關於一種可發出一紫外光之發光元件,其包含一第一半導體層及複數個半導體柱位於第一半導體層上。The present invention relates to a light-emitting element, and more particularly, to a light-emitting element capable of emitting an ultraviolet light. The light-emitting element includes a first semiconductor layer and a plurality of semiconductor pillars on the first semiconductor layer.

發光二極體(Light-Emitting Diode, LED)為固態半導體發光元件,其優點為功耗低,產生的熱能低,工作壽命長,防震,體積小,反應速度快和具有良好的光電特性,例如穩定的發光波長。因此發光二極體被廣泛應用於家用電器,設備指示燈,及光電產品等。Light-Emitting Diode (LED) is a solid-state semiconductor light-emitting element, which has the advantages of low power consumption, low thermal energy generation, long working life, shock resistance, small size, fast response speed, and good photoelectric characteristics, such as Stable emission wavelength. Therefore, light-emitting diodes are widely used in household appliances, equipment indicators, and optoelectronic products.

一發光元件包含一第一半導體層;複數個半導體柱彼此分離且位於第一半導體層上,複數個半導體柱各包含一第二半導體層及一活性層;一第一電極覆蓋複數個半導體柱之一部份;以及一第二電極覆蓋複數個半導體柱之另一部份,其中位於第一電極之一覆蓋區域下方的複數個半導體柱包含一第一間距以彼此分離,位於第一電極之覆蓋區域以外的複數個半導體柱包含一第二間距以彼此分離,及第一間距大於第二間距。A light-emitting element includes a first semiconductor layer; a plurality of semiconductor pillars are separated from each other and are located on the first semiconductor layer; each of the plurality of semiconductor pillars includes a second semiconductor layer and an active layer; a first electrode covers a plurality of semiconductor pillars; A portion; and a second electrode covering another portion of the plurality of semiconductor pillars, wherein the plurality of semiconductor pillars located below a coverage area of the first electrode include a first pitch to be separated from each other and are located on the cover of the first electrode The plurality of semiconductor pillars outside the region include a second pitch to be separated from each other, and the first pitch is greater than the second pitch.

一發光元件包含一第一半導體層;複數個半導體柱彼此分離且位於第一半導體層上,複數個半導體柱各包含一第二半導體層及一活性層;一第一電極覆蓋複數個半導體柱之一部份;一第二電極覆蓋複數個半導體柱之另一部份;以及一半導體平台包含第一半導體層、活性層及/或第二半導體層位於第一電極下方,其中位於第一電極之一覆蓋區域以外的複數個半導體柱包含一間距以彼此分離,及半導體平台包含一寬度大於複數個半導體柱間之間距。A light-emitting element includes a first semiconductor layer; a plurality of semiconductor pillars are separated from each other and are located on the first semiconductor layer; each of the plurality of semiconductor pillars includes a second semiconductor layer and an active layer; a first electrode covers a plurality of semiconductor pillars; A portion; a second electrode covering another portion of the plurality of semiconductor pillars; and a semiconductor platform including a first semiconductor layer, an active layer, and / or a second semiconductor layer under the first electrode, wherein A plurality of semiconductor pillars outside a coverage area include a pitch to separate them from each other, and the semiconductor platform includes a width greater than the interval between the plurality of semiconductor pillars.

一發光元件包含一第一半導體層;複數個半導體柱彼此分離且位於第一半導體層上,複數個半導體柱各包含一第二半導體層及一活性層;一第一接觸層包含一第一接觸部及一第一延伸部,第一接觸部包含一面積大於複數個半導體柱之一的一面積,第一延伸部延伸自第一接觸部並環繞複數個半導體柱;一第一電極覆蓋複數個半導體柱之一部份;以及一第二電極覆蓋複數個半導體柱之另一部份,其中第一接觸部係位於第一電極或第二電極下方,第一延伸部位於第一電極或第二電極下方。A light emitting element includes a first semiconductor layer; a plurality of semiconductor pillars are separated from each other and are located on the first semiconductor layer; each of the plurality of semiconductor pillars includes a second semiconductor layer and an active layer; a first contact layer includes a first contact And a first extension, the first contact includes an area larger than one of the plurality of semiconductor pillars, the first extension extends from the first contact and surrounds the plurality of semiconductor pillars; a first electrode covers the plurality of semiconductor pillars; A portion of a semiconductor pillar; and a second electrode covering another portion of the plurality of semiconductor pillars, wherein the first contact portion is located under the first electrode or the second electrode, and the first extension portion is located at the first electrode or the second electrode Under the electrode.

一發光元件包含一第一半導體層包含一第一上表面;一活性層包含一表面位於第一半導體層上並露出第一半導體層之第一上表面;以及一第二半導體層位於活性層上並露出活性層之表面,其中發光元件可發出一UV光。A light emitting element includes a first semiconductor layer including a first upper surface; an active layer including a surface on the first semiconductor layer and exposing a first upper surface of the first semiconductor layer; and a second semiconductor layer on the active layer The surface of the active layer is exposed, and the light-emitting element can emit a UV light.

為了使本發明之敘述更加詳盡與完備,請參照下列實施例之描述並配合相關圖示。惟,以下所示之實施例係用於例示本發明之發光元件,並非將本發明限定於以下之實施例。又,本說明書記載於實施例中的構成零件之尺寸、材質、形狀、相對配置等在沒有限定之記載下,本發明之範圍並非限定於此,而僅是單純之說明而已。且各圖示所示構件之大小或位置關係等,會由於為了明確說明有加以誇大之情形。更且,於以下之描述中,為了適切省略詳細說明,對於同一或同性質之構件用同一名稱、符號顯示。In order to make the description of the present invention more detailed and complete, please refer to the description of the following embodiments and cooperate with related drawings. However, the examples shown below are for exemplifying the light-emitting element of the present invention, and the present invention is not limited to the following examples. In addition, the dimensions, materials, shapes, relative arrangement, etc. of the component parts described in the examples in the present specification are not limited, and the scope of the present invention is not limited thereto, but merely a simple description. In addition, the size or positional relationship of the components shown in each illustration may be exaggerated for clarity. Furthermore, in the following description, in order to appropriately omit detailed descriptions, components of the same or the same nature are displayed with the same name and symbol.

第1圖係本發明一實施例中所揭示之一發光元件1的上視圖。第2圖係沿第1圖線段A-A’之的剖面圖。FIG. 1 is a top view of a light-emitting element 1 disclosed in an embodiment of the present invention. Fig. 2 is a sectional view taken along line A-A 'of Fig. 1;

如第1圖及第2圖所示,一發光元件1包含一基板11;以及一半導體疊層位於基板11上,其中半導體疊層包含一第一半導體層111,以及複數個半導體柱12彼此分離且位於第一半導體層111上。複數個半導體柱12各包含一第二半導體層122及一活性層123。於本發明之一實施例中,半導體柱12更包含第一半導體層111之一部份,且活性層123位於第一半導體層111及第二半導體層122之間。As shown in FIGS. 1 and 2, a light-emitting element 1 includes a substrate 11; and a semiconductor stack is located on the substrate 11, wherein the semiconductor stack includes a first semiconductor layer 111 and a plurality of semiconductor pillars 12 are separated from each other. And located on the first semiconductor layer 111. Each of the plurality of semiconductor pillars 12 includes a second semiconductor layer 122 and an active layer 123. In one embodiment of the present invention, the semiconductor pillar 12 further includes a portion of the first semiconductor layer 111, and the active layer 123 is located between the first semiconductor layer 111 and the second semiconductor layer 122.

於本發明之一實施例中,基板11為一成長基板,包括用以成長磷化鋁鎵銦(AlGaInP)之砷化鎵(GaAs)晶圓,或用以成長氮化鎵(GaN)、氮化銦鎵(InGaN)或氮化鋁鎵(AlGaN)之藍寶石(Al2O3)晶圓、氮化鎵(GaN)晶圓或碳化矽(SiC)晶圓。In one embodiment of the present invention, the substrate 11 is a growth substrate including a gallium arsenide (GaAs) wafer for growing aluminum gallium indium phosphide (AlGaInP), or for growing gallium nitride (GaN), nitrogen Indium gallium (InGaN) or aluminum gallium nitride (AlGaN) sapphire (Al2O3) wafer, gallium nitride (GaN) wafer or silicon carbide (SiC) wafer.

於本發明之一實施例中,藉由有機金屬化學氣相沉積法(MOCVD)、分子束磊晶(MBE)、氫化物氣相沉積法(HVPE)、物理氣相沉積法(PVD)或離子電鍍方法以於基板11上形成由半導體材料構成具有光電特性之複數層半導體材料層,其中物理氣象沉積法包含濺鍍 (Sputtering)或蒸鍍(Evoaporation)法。再藉由微影、蝕刻之方式圖案化半導體材料層,移除部分的半導體材料層以形成包含第一半導體層111、及由活性層123及第二半導體層122所構成的複數個半導體柱12的半導體疊層。第一半導體層111和第二半導體層122,可為包覆層(cladding layer),兩者具有不同的導電型態、電性、極性,或依摻雜的元素以提供電子或電洞,例如第一半導體層111為n型電性的半導體,第二半導體層122為p型電性的半導體。活性層123形成在第一半導體層111和第二半導體層122之間,電子與電洞於一電流驅動下在活性層123複合,將電能轉換成光能,以發出一光線。藉由改變半導體疊層中一層或多層的物理及化學組成以調整發光元件1發出光線的波長。半導體疊層之材料包含Ⅲ-Ⅴ族半導體材料,例如AlxInyGa(1-x-y)N或AlxInyGa(1-x-y)P,其中0≦x,y≦1;(x+y)≦1。依據活性層123之材料,當半導體疊層材料為AlInGaP系列材料時,可發出波長介於610 nm及650 nm之間的紅光,波長介於530 nm及570 nm之間的綠光,當半導體疊層材料為InGaN系列材料時,可發出波長介於450 nm及490 nm之間的藍光,或是當半導體疊層材料為AlGaN系列或AlInGaN系列材料時,可發出波長介於400 nm及250 nm之間的紫外光。活性層123可為單異質結構(single heterostructure, SH),雙異質結構(double heterostructure, DH),雙側雙異質結構(double-side double heterostructure, DDH),多層量子井結構(multi-quantum well, MQW) 。活性層123之材料可為中性、p型或n型電性的半導體。In one embodiment of the present invention, organic metal chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), hydride vapor deposition (HVPE), physical vapor deposition (PVD), or ions are used. The electroplating method is to form a plurality of semiconductor material layers composed of semiconductor materials and having optoelectronic characteristics on the substrate 11. The physical weather deposition method includes a sputtering method or an evaporation method. Then, the semiconductor material layer is patterned by lithography and etching, and a part of the semiconductor material layer is removed to form a plurality of semiconductor pillars 12 including a first semiconductor layer 111 and an active layer 123 and a second semiconductor layer 122. Semiconductor stack. The first semiconductor layer 111 and the second semiconductor layer 122 may be cladding layers, both of which have different conductivity types, electrical properties, polarities, or doped elements to provide electrons or holes, for example, The first semiconductor layer 111 is an n-type electrical semiconductor, and the second semiconductor layer 122 is a p-type electrical semiconductor. The active layer 123 is formed between the first semiconductor layer 111 and the second semiconductor layer 122. Electrons and holes are recombined in the active layer 123 under a current drive to convert electric energy into light energy to emit a light. The wavelength of light emitted by the light-emitting element 1 is adjusted by changing the physical and chemical composition of one or more layers in the semiconductor stack. The material of the semiconductor stack includes III-V semiconductor materials, such as AlxInyGa (1-x-y) N or AlxInyGa (1-x-y) P, where 0 ≦ x, y ≦ 1; (x + y) ≦ 1. According to the material of the active layer 123, when the semiconductor stack material is an AlInGaP series material, it can emit red light with a wavelength between 610 nm and 650 nm, and green light with a wavelength between 530 nm and 570 nm. When the laminated material is an InGaN series material, it can emit blue light with a wavelength between 450 nm and 490 nm, or when the semiconductor laminated material is an AlGaN series or an AlInGaN series material, it can emit a wavelength between 400 nm and 250 nm Between ultraviolet light. The active layer 123 may be a single heterostructure (SH), a double heterostructure (DH), a double-side double heterostructure (DDH), a multi-quantum well, MQW). The material of the active layer 123 may be a neutral, p-type or n-type electrical semiconductor.

於本發明之一實施例中,更包含ㄧ緩衝層(圖未示),形成於半導體疊層及基板11之間,用以改善半導體疊層的磊晶品質。在一實施例中,可以氮化鋁(AlN)做為緩衝層。在一實施例中,用以形成氮化鋁(AlN)的方式為PVD,其靶材係由氮化鋁所組成。在另一實施例中,係使用PVD方式由鋁組成的靶材,於氮源的環境下與鋁靶材反應性形成氮化鋁。In one embodiment of the present invention, a rhenium buffer layer (not shown) is further formed between the semiconductor stack and the substrate 11 to improve the epitaxial quality of the semiconductor stack. In one embodiment, aluminum nitride (AlN) can be used as the buffer layer. In one embodiment, the method for forming aluminum nitride (AlN) is PVD, and the target material is composed of aluminum nitride. In another embodiment, a target made of aluminum using PVD method is used to react with the aluminum target to form aluminum nitride under the environment of a nitrogen source.

於本發明之一實施例中,基板11包含藍寶石(Al2O3)基板,第一半導體層111包含氮化鋁鎵(AlGaN)層。為了減少氮化鋁鎵層與藍寶石基板之間因晶格差異所造成的磊晶缺陷,以氮化鋁(AlN)做為緩衝層形成於氮化鋁鎵層與藍寶石基板之間,其中氮化鋁緩衝層包含一厚度大於300 nm,較佳大於1000 nm,更加大於2500 nm以填補磊晶缺陷。氮化鋁緩衝層包含摻雜濃度低於2E+17的碳(C)、氫(H)及/或氧(O)。氮化鋁緩衝層所包含的鋁(Al)組成百分比大於氮化鋁鎵第一半導體層111所包含的鋁(Al)組成百分比。In one embodiment of the present invention, the substrate 11 includes a sapphire (Al2O3) substrate, and the first semiconductor layer 111 includes an aluminum gallium nitride (AlGaN) layer. In order to reduce the epitaxial defects caused by the lattice difference between the aluminum gallium nitride layer and the sapphire substrate, aluminum nitride (AlN) is used as a buffer layer to be formed between the aluminum gallium nitride layer and the sapphire substrate. The aluminum buffer layer includes a thickness greater than 300 nm, preferably greater than 1000 nm, and more than 2500 nm to fill epitaxial defects. The aluminum nitride buffer layer includes carbon (C), hydrogen (H), and / or oxygen (O) with a doping concentration lower than 2E + 17. The aluminum (Al) composition percentage included in the aluminum nitride buffer layer is greater than the aluminum (Al) composition percentage included in the aluminum gallium nitride first semiconductor layer 111.

如第1圖之上視圖及第2圖之沿第1圖線段A-A’之剖面圖所示,於複數個半導體層形成在基板11上之後,藉由微影、蝕刻之方式圖案化複數個半導體層,移除部分的半導體層,形成包含第一半導體層111及複數個彼此分離的半導體柱12的半導體結構,其中複數個半導體柱12各包含第二半導體層122及活性層123。As shown in the top view in FIG. 1 and the cross-sectional view along line AA ′ in FIG. 2 after the plurality of semiconductor layers are formed on the substrate 11, the plurality are patterned by lithography and etching. A plurality of semiconductor layers are removed to form a semiconductor structure including a first semiconductor layer 111 and a plurality of semiconductor pillars 12 separated from each other. Each of the plurality of semiconductor pillars 12 includes a second semiconductor layer 122 and an active layer 123.

於本發明之一實施例中,複數個半導體柱12係彼此分離以露出第一半導體層111之表面S1。基板11包含一第一側壁11s,第一半導體層111包含一第二側壁111s,複數個半導體柱12各包含一第三側壁12s。如第2圖所示,基板11之第一側壁11s與第一半導體層111之第二側壁111s齊平,半導體柱12之第三側壁12s與第一半導體層111之表面S1之間具有一斜角或一直角。In one embodiment of the present invention, the plurality of semiconductor pillars 12 are separated from each other to expose the surface S1 of the first semiconductor layer 111. The substrate 11 includes a first sidewall 11s, the first semiconductor layer 111 includes a second sidewall 111s, and each of the plurality of semiconductor pillars 12 includes a third sidewall 12s. As shown in FIG. 2, the first sidewall 11 s of the substrate 11 is flush with the second sidewall 111 s of the first semiconductor layer 111, and the third sidewall 12 s of the semiconductor pillar 12 and the surface S1 of the first semiconductor layer 111 have a slant. Angle or straight angle.

於本發明之一實施例中,半導體柱12之第三側壁12s與第一半導體層111之表面S1之間的斜角包含一角度介於10度至80度之間,較佳小於60度,更佳為小於40度。In an embodiment of the present invention, the oblique angle between the third sidewall 12s of the semiconductor pillar 12 and the surface S1 of the first semiconductor layer 111 includes an angle between 10 degrees and 80 degrees, and preferably less than 60 degrees. More preferably, it is less than 40 degrees.

於本發明之一實施例中(圖未示),基板11之第一側壁11s與第一半導體層111之第二側壁111s係相隔一距離以露出基板11之一表面S2。第一半導體層111之第二側壁111s與基板11之表面S2之間具有一鈍角或一直角。In one embodiment of the present invention (not shown), the first sidewall 11 s of the substrate 11 and the second sidewall 111 s of the first semiconductor layer 111 are spaced apart to expose a surface S2 of the substrate 11. There is an obtuse angle or a right angle between the second sidewall 111s of the first semiconductor layer 111 and the surface S2 of the substrate 11.

於本發明之一實施例中,第一半導體層111之第二側壁111s與基板11之表面S2之間具有一斜角包含一角度介於10度至80度之間,較佳小於60度,更佳為小於40度。第一半導體層111之表面S1與基板11之表面S2之間具有一高度大於4000 Å,較佳大於6000 Å,更佳為大於8000 Å。In one embodiment of the present invention, there is an oblique angle between the second sidewall 111s of the first semiconductor layer 111 and the surface S2 of the substrate 11 including an angle between 10 degrees and 80 degrees, preferably less than 60 degrees. More preferably, it is less than 40 degrees. A height between the surface S1 of the first semiconductor layer 111 and the surface S2 of the substrate 11 is greater than 4000 Å, preferably greater than 6000 Å, and more preferably greater than 8000 Å.

於本發明之一實施例中,基板11之表面S2為一平坦的表面,其中所述平坦的表面包含一粗糙度(Root mean square roughness, Rq)小於8 nm,較佳小於5 nm,更佳小於2 nm。In one embodiment of the present invention, the surface S2 of the substrate 11 is a flat surface, wherein the flat surface includes a roughness (Root mean square roughness, Rq) of less than 8 nm, preferably less than 5 nm, and more preferably Less than 2 nm.

於本發明之一實施例中,基板11之表面S2包含一圖案化表面(圖未示),其中所述圖案化表面包含複數個凹部自基板11之表面S2往基板11之內部延伸或複數個凸部自基板11之表面S2往第一半導體層111之表面S1延伸。自發光元件1之上視圖觀之,複數個凹部或凸部各包含圓形、橢圓形、矩形、多邊形、或是其他任意形狀。自發光元件1之上視圖觀之,複數個凹部或複數個凸部各包含一底部與基板11之表面S2齊平,以及一頂部與底部相對,其中頂部可為一平面或一尖點。頂部與底部之間包含一深度或高度介於0.1μm ~2μm之間,較佳為介於0.2μm ~0.9μm之間,更佳為介於0.5μm ~0.7μm之間。底部包含一寬度或直徑介於0.05μm ~1μm之間,較佳為介於0.2μm ~0.8μm之間,更佳為介於0.3μm ~0.5μm之間。In an embodiment of the present invention, the surface S2 of the substrate 11 includes a patterned surface (not shown), wherein the patterned surface includes a plurality of recesses extending from the surface S2 of the substrate 11 to the interior of the substrate 11 or a plurality of The convex portion extends from the surface S2 of the substrate 11 to the surface S1 of the first semiconductor layer 111. Viewed from a top view of the light emitting element 1, each of the plurality of concave portions or convex portions includes a circle, an oval, a rectangle, a polygon, or any other shape. Viewed from a top view of the light-emitting element 1, each of the plurality of concave portions or the plurality of convex portions includes a bottom flush with the surface S2 of the substrate 11, and a top opposite to the bottom, wherein the top may be a flat surface or a sharp point. A depth or a height between the top and the bottom includes between 0.1 μm and 2 μm, preferably between 0.2 μm and 0.9 μm, and more preferably between 0.5 μm and 0.7 μm. The bottom contains a width or diameter between 0.05 μm and 1 μm, preferably between 0.2 μm and 0.8 μm, and more preferably between 0.3 μm and 0.5 μm.

於本發明之一實施例中,由第1圖所示之發光元件1之上視圖觀之,半導體柱12各包含圓形、橢圓形、矩形、多邊形、或是任意形狀。In an embodiment of the present invention, viewed from the top view of the light-emitting element 1 shown in FIG. 1, the semiconductor pillars 12 each include a circle, an oval, a rectangle, a polygon, or any shape.

於本發明之一實施例中,減小半導體柱12所包含之直徑或寬度可降低發光元件1之順向電壓(forward voltage, Vf),並提升發光元件1之亮度。自發光元件1之上視圖觀之,半導體柱12包含一直徑或一寬度大於4 μm及/或小於80μm,較佳為小於50μm,更佳為小於20μm。In one embodiment of the present invention, reducing the diameter or width included in the semiconductor pillar 12 can reduce the forward voltage (Vf) of the light-emitting element 1 and increase the brightness of the light-emitting element 1. Viewed from a top view of the light-emitting element 1, the semiconductor pillar 12 includes a diameter or a width greater than 4 μm and / or less than 80 μm, preferably less than 50 μm, and more preferably less than 20 μm.

於本發明之一實施例中,半導體柱12可排列成複數列,任相鄰兩列或每相鄰兩列上的半導體柱12可彼此對齊或是錯開。In an embodiment of the present invention, the semiconductor pillars 12 may be arranged in a plurality of columns, and the semiconductor pillars 12 on any two adjacent columns or each adjacent two columns may be aligned with each other or staggered.

於本發明之一實施例中,半導體柱12可排列成一第一列與一第二列,位於同一列上的兩相鄰半導體柱12之間包含一第一最短距離,位於第一列上的半導體柱12與其相鄰之位於第二列上的半導體柱12之間包含一第二最短距離,其中第一最短距離大於或小於第二最短距離。當一外部電流注入發光元件1時,藉由多個半導體柱12的分散配置,可使發光元件1的光場分佈均勻化,並可降低發光元件1的正向電壓。In one embodiment of the present invention, the semiconductor pillars 12 may be arranged in a first row and a second row. Two adjacent semiconductor pillars 12 on the same row include a first shortest distance. The semiconductor pillar 12 and a neighboring semiconductor pillar 12 located on the second column include a second shortest distance, wherein the first shortest distance is greater than or less than the second shortest distance. When an external current is injected into the light-emitting element 1, by dispersing the plurality of semiconductor pillars 12, the light field distribution of the light-emitting element 1 can be made uniform, and the forward voltage of the light-emitting element 1 can be reduced.

於本發明之一實施例中,多個半導體柱12可排列成一第一列,一第二列與一第三列,位於第一列上的半導體柱12與位於第二列上的半導體柱12之間包含一第一最短距離,位於第二列上的半導體柱12與位於第三列上的半導體柱12之間包含一第二最短距離,其中第一最短距離小於第二最短距離。當一外部電流注入發光元件1時,藉由多個半導體柱12的分散配置,可使發光元件1的光場分佈均勻化,並可降低發光元件1的正向電壓。In one embodiment of the present invention, the plurality of semiconductor pillars 12 may be arranged in a first row, a second row, and a third row. The semiconductor pillars 12 on the first row and the semiconductor pillars 12 on the second row. A first shortest distance is included between them, and a second shortest distance is included between the semiconductor pillars 12 on the second column and a semiconductor pillar 12 on the third column, where the first shortest distance is less than the second shortest distance. When an external current is injected into the light-emitting element 1, by dispersing the plurality of semiconductor pillars 12, the light field distribution of the light-emitting element 1 can be made uniform, and the forward voltage of the light-emitting element 1 can be reduced.

一第一接觸層131藉由物理氣相沉積法或化學氣相沉積法等方式形成於第一半導體層111之表面S1上。第一接觸層131之材料包含金屬材料,例如鉻(Cr)、鈦(Ti)、鎢(W)、金(Au)、鋁(Al)、銦(In)、錫(Sn)、鎳(Ni)、鉑(Pt)、銠(Rh)等金屬或上述材料之合金。A first contact layer 131 is formed on the surface S1 of the first semiconductor layer 111 by a physical vapor deposition method or a chemical vapor deposition method. The material of the first contact layer 131 includes a metal material, such as chromium (Cr), titanium (Ti), tungsten (W), gold (Au), aluminum (Al), indium (In), tin (Sn), nickel (Ni ), Platinum (Pt), rhodium (Rh) and other metals or alloys of the above materials.

於本發明之一實施例中,發光元件1發出的光包含一波長大於370 nm,第一接觸層131之材料包含具有高反射率之金屬,例如銀(Ag)、鋁(Al)、鉑(Pt)或銠(Rh)。為了增加第一接觸層131之反射率,包含銀(Ag)、鋁(Al)、鉑(Pt)或銠(Rh)之金屬層具有一厚度大於400埃,較佳大於800埃,更佳大於1200埃。In one embodiment of the present invention, the light emitted by the light-emitting element 1 includes a wavelength greater than 370 nm, and the material of the first contact layer 131 includes a metal having high reflectivity, such as silver (Ag), aluminum (Al), and platinum ( Pt) or rhodium (Rh). In order to increase the reflectivity of the first contact layer 131, the metal layer containing silver (Ag), aluminum (Al), platinum (Pt), or rhodium (Rh) has a thickness greater than 400 angstroms, preferably greater than 800 angstroms, more preferably greater than 1200 Angstroms.

於本發明之一實施例中,發光元件1發出的光包含一波長小於370nm,第一接觸層131之材料不包含銀(Ag)。In one embodiment of the present invention, the light emitted by the light-emitting element 1 includes a wavelength less than 370 nm, and the material of the first contact layer 131 does not include silver (Ag).

於本發明之一實施例中,第一接觸層131與第一半導體層111之表面S1相接觸之一側包含鉻(Cr)或鈦(Ti),以增加第一接觸層131與第一半導體層111的接合強度。為了減少光損失,鉻(Cr)或鈦(Ti)層的厚度小於1000埃,較佳小於800埃,更佳小於500埃。並且,為了維持足夠的接合強度,鉻(Cr)及/或鈦(Ti)層包含一厚度大於10埃,較佳大於50埃,更佳大於100埃。In one embodiment of the present invention, one side of the first contact layer 131 in contact with the surface S1 of the first semiconductor layer 111 includes chromium (Cr) or titanium (Ti) to increase the first contact layer 131 and the first semiconductor. The bonding strength of the layer 111. To reduce light loss, the thickness of the chromium (Cr) or titanium (Ti) layer is less than 1000 angstroms, preferably less than 800 angstroms, and more preferably less than 500 angstroms. In addition, in order to maintain sufficient bonding strength, the chromium (Cr) and / or titanium (Ti) layer includes a thickness greater than 10 angstroms, preferably greater than 50 angstroms, more preferably greater than 100 angstroms.

於本發明之一實施例中,第一半導體層111包含AlxGa(1-x)N,其中0.3>x>0.8,較佳0.35>x>0.7,更佳0.4>x>0.6。為了使第一接觸層131與第一半導體層111之表面S1形成歐姆接觸並維持足夠的接合強度,第一接觸層131包含鈦(Ti)和鋁(Al),其中鈦(Ti)/鋁(Al)具有一比值介於0.1~0.2之間。In one embodiment of the present invention, the first semiconductor layer 111 includes AlxGa (1-x) N, where 0.3> x> 0.8, preferably 0.35> x> 0.7, and more preferably 0.4> x> 0.6. In order to make the first contact layer 131 make ohmic contact with the surface S1 of the first semiconductor layer 111 and maintain sufficient bonding strength, the first contact layer 131 includes titanium (Ti) and aluminum (Al), where titanium (Ti) / aluminum ( Al) has a ratio between 0.1 and 0.2.

於本發明之一實施例中,第一接觸層131包含一第一接觸部P1及一第一延伸部E1。第一接觸部P1包含位於第一半導體層111上之一投影面積,其大於複數個半導體柱12之一位於第一半導體層111上的一投影面積,其中所述投影面積係指垂直於基板11之表面S2之一法線方向上的投影面積。如第1圖所示,第一延伸部E1延伸自第一接觸部P1並環繞複數個半導體柱12。In one embodiment of the present invention, the first contact layer 131 includes a first contact portion P1 and a first extension portion E1. The first contact portion P1 includes a projected area on the first semiconductor layer 111, which is larger than a projected area of one of the plurality of semiconductor pillars 12 on the first semiconductor layer 111, wherein the projected area is perpendicular to the substrate 11. The projected area of one of the surfaces S2 in the normal direction. As shown in FIG. 1, the first extension portion E1 extends from the first contact portion P1 and surrounds the plurality of semiconductor pillars 12.

於本發明之一實施例中,第一接觸層131包含複數個第一接觸部P1及複數個第一延伸部E1,其中複數個第一延伸部E1係延伸自複數個第一接觸部P1且彼此相連,及複數個第一接觸部P1係藉由複數個第一延伸部E1相連接。In one embodiment of the present invention, the first contact layer 131 includes a plurality of first contact portions P1 and a plurality of first extension portions E1, wherein the plurality of first extension portions E1 extend from the plurality of first contact portions P1 and They are connected to each other, and the plurality of first contact portions P1 are connected by a plurality of first extension portions E1.

如第2圖所示,於本發明之一實施例中,第一接觸層131之第一接觸部P1包含一寬度大於第一延伸部E1之一寬度。As shown in FIG. 2, in an embodiment of the present invention, the first contact portion P1 of the first contact layer 131 includes a width larger than a width of the first extension portion E1.

一第二接觸層132藉由物理氣相沉積法或化學氣相沉積法等方式形成於半導體柱12之第二半導體層122上。第二接觸層132之材料包含金屬材料,例如鉻(Cr)、鈦(Ti)、鎢(W)、金(Au)、鋁(Al)、銦(In)、錫(Sn)、鎳(Ni)、鉑(Pt)、銠(Rh)等金屬或上述材料之合金。A second contact layer 132 is formed on the second semiconductor layer 122 of the semiconductor pillar 12 by a physical vapor deposition method or a chemical vapor deposition method. The material of the second contact layer 132 includes a metal material, such as chromium (Cr), titanium (Ti), tungsten (W), gold (Au), aluminum (Al), indium (In), tin (Sn), nickel (Ni ), Platinum (Pt), rhodium (Rh) and other metals or alloys of the above materials.

於本發明之一實施例中,發光元件1發出的光包含一波長大於370 nm,第二接觸層132之材料包含具有高反射率之金屬,例如銀(Ag)、鋁(Al)、鉑(Pt)或銠(Rh)。為了增加第二接觸層132之反射率,包含銀(Ag)、鋁(Al)、鉑(Pt)或銠(Rh)之金屬層具有一厚度大於400埃,較佳大於800埃,更佳大於1200埃。In one embodiment of the present invention, the light emitted by the light-emitting element 1 includes a wavelength greater than 370 nm, and the material of the second contact layer 132 includes a metal with high reflectivity, such as silver (Ag), aluminum (Al), and platinum ( Pt) or rhodium (Rh). In order to increase the reflectivity of the second contact layer 132, the metal layer including silver (Ag), aluminum (Al), platinum (Pt) or rhodium (Rh) has a thickness greater than 400 angstroms, preferably greater than 800 angstroms, more preferably greater than 1200 Angstroms.

於本發明之一實施例中,發光元件1發出的光包含一波長小於370 nm,第二接觸層132之材料不包含銀(Ag)。In one embodiment of the present invention, the light emitted by the light-emitting element 1 includes a wavelength less than 370 nm, and the material of the second contact layer 132 does not include silver (Ag).

於本發明之一實施例中,複數個第二接觸層132係分別形成於複數個半導體柱12之第二半導體層122上,且複數個第二接觸層132係彼此分離。In one embodiment of the present invention, the plurality of second contact layers 132 are respectively formed on the second semiconductor layers 122 of the plurality of semiconductor pillars 12, and the plurality of second contact layers 132 are separated from each other.

於本發明之一實施例中,第二半導體層122包含氮化鎵(GaN)、氮化鋁鎵(AlGaN)或氮化硼(BN),且第二半導體層122包含一摻雜元素,例如鎂(Mg),以形成p型電性的半導體,其中摻雜元素具有一濃度大於9E+18,較佳大於4E+19,更佳大於1E+20。第二接觸層132包含對於活性層123所發出的光線為透明,並且可與第二半導體層122形成歐姆接觸的透明導電材料。透明導電材料包含非金屬材料,例如石墨烯,金屬或金屬氧化物,例如氧化銦錫(ITO)、或氧化銦鋅(IZO)。由於第二接觸層132形成於第二半導體層122之大致整個面,並與第二半導體層122相接觸,因此,電流藉由第二接觸層132以均勻擴散於第二半導體層122之整體。In one embodiment of the present invention, the second semiconductor layer 122 includes gallium nitride (GaN), aluminum gallium nitride (AlGaN), or boron nitride (BN), and the second semiconductor layer 122 includes a doping element, such as Magnesium (Mg) to form a p-type electrical semiconductor, wherein the doping element has a concentration greater than 9E + 18, preferably greater than 4E + 19, and more preferably greater than 1E + 20. The second contact layer 132 includes a transparent conductive material that is transparent to light emitted from the active layer 123 and can form an ohmic contact with the second semiconductor layer 122. Transparent conductive materials include non-metal materials, such as graphene, metals or metal oxides, such as indium tin oxide (ITO), or indium zinc oxide (IZO). Since the second contact layer 132 is formed on substantially the entire surface of the second semiconductor layer 122 and is in contact with the second semiconductor layer 122, the current is uniformly diffused throughout the second semiconductor layer 122 through the second contact layer 132.

於本發明之一實施例中,第二接觸層132包含石墨烯,第二接觸層132更包含薄金屬層或薄金屬氧化物層,其材料例如為氧化鎳(NiO) 、氧化鈷(Co3O4)或氧化銅(Cu2O),位於第二半導體層122及石墨烯之間以與第二半導體層122形成歐姆接觸。薄金屬層或薄金屬氧化物層包含一厚度介於0.1至50 nm之間,較佳介於0.1至20 nm之間,更佳介於0.1至10 nm之間。In one embodiment of the present invention, the second contact layer 132 includes graphene, and the second contact layer 132 further includes a thin metal layer or a thin metal oxide layer. The material is, for example, nickel oxide (NiO) or cobalt oxide (Co3O4). Or copper oxide (Cu2O) is located between the second semiconductor layer 122 and graphene to form an ohmic contact with the second semiconductor layer 122. The thin metal layer or thin metal oxide layer includes a thickness between 0.1 and 50 nm, preferably between 0.1 and 20 nm, and more preferably between 0.1 and 10 nm.

於本發明之一實施例中,第二接觸層132的厚度可在0.1 nm至100 nm的範圍內。若第二接觸層132的厚度小於0.1 nm,則由於厚度太薄而不能有效地與第二半導體層122形成歐姆接觸。並且,若第二接觸層132的厚度大於100 nm,則由於厚度太厚而部分吸收活性層123所發出光線,從而導致發光元件1的亮度減少的問題。In one embodiment of the present invention, the thickness of the second contact layer 132 may be in a range of 0.1 nm to 100 nm. If the thickness of the second contact layer 132 is less than 0.1 nm, the ohmic contact with the second semiconductor layer 122 cannot be effectively formed because the thickness is too thin. In addition, if the thickness of the second contact layer 132 is greater than 100 nm, the thickness of the second contact layer 132 partially absorbs light emitted from the active layer 123, thereby causing a problem that the brightness of the light-emitting element 1 decreases.

於本發明之一實施例中,第一接觸層131及第二接觸層132形成於半導體疊層上之位置係錯置,互不重疊。In one embodiment of the present invention, the positions of the first contact layer 131 and the second contact layer 132 formed on the semiconductor stack are staggered and do not overlap each other.

一第一絕緣層14藉由物理氣相沉積法或化學氣相沉積法等方式沉積一絕緣材料層於第一接觸層131及第二接觸層132上。再藉由微影、蝕刻之方式圖案化部分絕緣材料層形成第一絕緣層14,以及於第一接觸層131上形成第一絕緣層14之ㄧ第一開口1401以露出第一接觸層131及於第二接觸層132上形成第一絕緣層14之ㄧ第二開口1402以露出第二接觸層132。A first insulating layer 14 deposits an insulating material layer on the first contact layer 131 and the second contact layer 132 by a physical vapor deposition method or a chemical vapor deposition method. Then, a part of the insulating material layer is patterned by lithography and etching to form the first insulating layer 14, and a first opening 1401 of the first insulating layer 14 is formed on the first contact layer 131 to expose the first contact layer 131 and A second opening 1402 of the first insulating layer 14 is formed on the second contact layer 132 to expose the second contact layer 132.

於本發明之一實施例中,第一接觸層131包含複數個第一接觸部P1及複數個第一延伸部E1。第一絕緣層14包含複數個第一開口1401分別位於複數個第一接觸部P1上,其中複數個第一延伸部E1為第一絕緣層14所覆蓋。In one embodiment of the present invention, the first contact layer 131 includes a plurality of first contact portions P1 and a plurality of first extension portions E1. The first insulation layer 14 includes a plurality of first openings 1401 located on the plurality of first contact portions P1, respectively, wherein the plurality of first extension portions E1 are covered by the first insulation layer 14.

於本發明之一實施例中,第一絕緣層14包含複數個第二開口1402以分別位於複數個半導體柱12上。換言之,複數個第二開口1402包含一數目與複數個半導體柱12之一數目相同。In one embodiment of the present invention, the first insulating layer 14 includes a plurality of second openings 1402 to be respectively located on the plurality of semiconductor pillars 12. In other words, the plurality of second openings 1402 includes a number equal to the number of one of the plurality of semiconductor pillars 12.

於本發明之一實施例中,第一絕緣層14之複數個第二開口1402包含一數目多於複數個第一開口1401之一數目。In one embodiment of the present invention, the plurality of second openings 1402 of the first insulating layer 14 includes a number greater than one of the plurality of first openings 1401.

於本發明之一實施例中,第一絕緣層14之第二開口1402包含一寬度小於第一開口1401之一寬度。In one embodiment of the present invention, the second opening 1402 of the first insulating layer 14 includes a width smaller than a width of the first opening 1401.

於本發明之一實施例中,第一絕緣層14包覆複數個半導體柱12之第三側壁12s,覆蓋第一半導體層111之表面S1,覆蓋第一半導體層111之第二側壁111s,及/或覆蓋基板11之表面S2。In one embodiment of the present invention, the first insulating layer 14 covers the third sidewall 12s of the plurality of semiconductor pillars 12, covers the surface S1 of the first semiconductor layer 111, and covers the second sidewall 111s of the first semiconductor layer 111, and And / or cover the surface S2 of the substrate 11.

於本發明之一實施例中,第一絕緣層14除了可保護半導體結構外,還可藉由其包含不同折射率的兩種以上之材料交替堆疊以形成一布拉格反射鏡(DBR)結構,選擇性地反射特定波長之光。第一絕緣層14係為非導電材料所形成,包含有機材料,例如Su8、苯并環丁烯(BCB)、過氟環丁烷(PFCB)、環氧樹脂(Epoxy)、丙烯酸樹脂(Acrylic Resin)、環烯烴聚合物(COC)、聚甲基丙烯酸甲酯(PMMA)、聚對苯二甲酸乙二酯(PET)、聚碳酸酯(PC)、聚醚醯亞胺(Polyetherimide)或氟碳聚合物(Fluorocarbon Polymer),或是無機材料,例如矽膠(Silicone)或玻璃(Glass),或是介電材料,例如氧化鋁(Al2O3)、氮化矽(SiNx)、氧化矽(SiOx)、氧化鈦(TiOx)或氟化鎂(MgFx)。In one embodiment of the present invention, in addition to protecting the semiconductor structure, the first insulating layer 14 may be alternately stacked to form a Bragg reflector (DBR) structure by using two or more materials containing different refractive indices. Reflects light at a specific wavelength. The first insulating layer 14 is formed of a non-conductive material and includes organic materials such as Su8, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), epoxy resin (Epoxy), and acrylic resin (Acrylic Resin). ), Cycloolefin polymer (COC), polymethyl methacrylate (PMMA), polyethylene terephthalate (PET), polycarbonate (PC), polyetherimide or fluorocarbon Polymer (Fluorocarbon Polymer), or inorganic materials, such as Silicone or Glass, or dielectric materials, such as aluminum oxide (Al2O3), silicon nitride (SiNx), silicon oxide (SiOx), oxide Titanium (TiOx) or magnesium fluoride (MgFx).

一第一電極接觸層151及一第二電極接觸層152藉由物理氣相沉積法或化學氣相沉積法等方式分別形成於第一絕緣層14之第一開口1401及第二開口1402中,並延伸覆蓋於第一絕緣層14之部份表面上。第一電極接觸層151藉由第一絕緣層14之第一開口1401與第一接觸層131之第一接觸部P1相連接。第二電極接觸層152藉由第一絕緣層14之第二開口1402與複數個第二接觸層132相連接。A first electrode contact layer 151 and a second electrode contact layer 152 are respectively formed in the first opening 1401 and the second opening 1402 of the first insulating layer 14 by a physical vapor deposition method or a chemical vapor deposition method. It extends and covers a part of the surface of the first insulating layer 14. The first electrode contact layer 151 is connected to the first contact portion P1 of the first contact layer 131 through the first opening 1401 of the first insulating layer 14. The second electrode contact layer 152 is connected to the plurality of second contact layers 132 through the second opening 1402 of the first insulating layer 14.

於本發明之一實施例中,第二電極接觸層152覆蓋複數個半導體柱12及第一接觸層131之部份,其中第二電極接觸層152藉由第一絕緣層14以與第一接觸層131電性隔離。In one embodiment of the present invention, the second electrode contact layer 152 covers a portion of the plurality of semiconductor pillars 12 and the first contact layer 131, wherein the second electrode contact layer 152 is in contact with the first through the first insulating layer 14. The layer 131 is electrically isolated.

於本發明之一實施例中,第一接觸層131包含第一接觸部P1,具有一寬度W1大於半導體柱12之一寬度W2,第一接觸層131之第一接觸部P1的寬度W1大於第一電極接觸層151之一寬度W3,且第一電極接觸層151之寬度W3大於半導體柱12之寬度W2。In one embodiment of the present invention, the first contact layer 131 includes a first contact portion P1 having a width W1 larger than a width W2 of the semiconductor pillar 12, and a width W1 of the first contact portion P1 of the first contact layer 131 is larger than that of the first contact portion 131. A width W3 of one of the electrode contact layers 151 is greater than a width W2 of the first electrode contact layer 151.

於本發明之一實施例中,第一電極接觸層151覆蓋部份的第一接觸層131,第二電極接觸層152覆蓋全部的第二接觸層132。In one embodiment of the present invention, the first electrode contact layer 151 covers a portion of the first contact layer 131, and the second electrode contact layer 152 covers the entire second contact layer 132.

於本發明之一實施例中,第一電極接觸層151覆蓋部份的第一接觸層131,且第二電極接觸層152覆蓋部份的第二接觸層132。In one embodiment of the present invention, the first electrode contact layer 151 covers a portion of the first contact layer 131, and the second electrode contact layer 152 covers a portion of the second contact layer 132.

於本發明之一實施例中,第一電極接觸層151覆蓋全部的第一接觸層131,且第二電極接觸層152覆蓋部份的第二接觸層132。In one embodiment of the present invention, the first electrode contact layer 151 covers the entire first contact layer 131, and the second electrode contact layer 152 covers a part of the second contact layer 132.

於本發明之一實施例中,第一電極接觸層151與第二電極接觸層152彼此相隔一距離。於發光元件1之上視圖上,第二電極接觸層152環繞第一電極接觸層151之多個側壁。In one embodiment of the present invention, the first electrode contact layer 151 and the second electrode contact layer 152 are separated from each other by a distance. In a top view of the light emitting element 1, the second electrode contact layer 152 surrounds a plurality of sidewalls of the first electrode contact layer 151.

於本發明之一實施例中,於發光元件1之上視圖上,第二電極接觸層152包含一面積大於第一電極接觸層151之一面積。In one embodiment of the present invention, the second electrode contact layer 152 includes an area larger than an area of the first electrode contact layer 151 in a top view of the light emitting element 1.

於本發明之一實施例中,當一外部電流注入發光元件1時,電流藉由第一電極接觸層151與第二電極接觸層152以傳導至第一半導體層111及第二半導體層122。In one embodiment of the present invention, when an external current is injected into the light emitting device 1, the current is conducted to the first semiconductor layer 111 and the second semiconductor layer 122 through the first electrode contact layer 151 and the second electrode contact layer 152.

如第1圖所示,第一電極接觸層151係靠近基板11之一側,例如基板11中心線之左側或右側。As shown in FIG. 1, the first electrode contact layer 151 is close to one side of the substrate 11, for example, to the left or right of the center line of the substrate 11.

於本發明之一實施例中,第一電極接觸層151與第二電極接觸層152之材料包含金屬材料,例如鉻(Cr)、鈦(Ti)、鎢(W)、金(Au)、鋁(Al)、銦(In)、錫(Sn)、鎳(Ni)、鉑(Pt)、銠(Rh)等金屬或上述材料之合金。In one embodiment of the present invention, the materials of the first electrode contact layer 151 and the second electrode contact layer 152 include metal materials, such as chromium (Cr), titanium (Ti), tungsten (W), gold (Au), and aluminum. (Al), indium (In), tin (Sn), nickel (Ni), platinum (Pt), rhodium (Rh) and other metals or alloys of the above materials.

於本發明之一實施例中,發光元件1發出的光包含一波長小於370nm,且第一電極接觸層151與第二電極接觸層152之材料不包含銀(Ag)。第一電極接觸層151與第二電極接觸層152之材料包含對於紫外光具有高反射率之金屬,例如鋁(Al)、鉑(Pt)或銠(Rh)。為了增加第一電極接觸層151與第二電極接觸層152對於紫外光之反射率,包含鋁(Al)、鉑(Pt)或銠(Rh)之層包含一厚度大於4000埃,較佳大於8000埃,更佳大於10000埃。In one embodiment of the present invention, the light emitted by the light-emitting element 1 includes a wavelength less than 370 nm, and the material of the first electrode contact layer 151 and the second electrode contact layer 152 does not include silver (Ag). The material of the first electrode contact layer 151 and the second electrode contact layer 152 includes a metal having a high reflectivity to ultraviolet light, such as aluminum (Al), platinum (Pt), or rhodium (Rh). In order to increase the reflectivity of the first electrode contact layer 151 and the second electrode contact layer 152 to ultraviolet light, the layer containing aluminum (Al), platinum (Pt) or rhodium (Rh) includes a thickness greater than 4000 angstroms, preferably greater than 8000 Angstroms, more preferably greater than 10,000 Angstroms.

於本發明之一實施例中,第一電極接觸層151與第一接觸層131相接觸之一側包含鉻(Cr)或鈦(Ti),以增加第一電極接觸層151與第一接觸層131的接合強度。第二電極接觸層152與第二接觸層132相接觸之一側包含鉻(Cr)或鈦(Ti),以增加第二電極接觸層152與第二接觸層132的接合強度。為了減少鉻(Cr)或鈦(Ti)對於紫外光造成的光損失,包含鉻(Cr)或鈦(Ti)之層具有一厚度小於1000埃,較佳小於800埃,更佳小於500埃。並且,為了維持足夠的接合強度,包含鉻(Cr)及/或鈦(Ti)之層具有一厚度大於10埃,較佳大於50埃,更佳大於100埃。In one embodiment of the present invention, one side of the first electrode contact layer 151 in contact with the first contact layer 131 includes chromium (Cr) or titanium (Ti) to increase the first electrode contact layer 151 and the first contact layer. 131 joint strength. One side of the second electrode contact layer 152 in contact with the second contact layer 132 includes chromium (Cr) or titanium (Ti) to increase the bonding strength between the second electrode contact layer 152 and the second contact layer 132. In order to reduce the light loss caused by chromium (Cr) or titanium (Ti) to ultraviolet light, the layer containing chromium (Cr) or titanium (Ti) has a thickness of less than 1000 angstroms, preferably less than 800 angstroms, more preferably less than 500 angstroms. Moreover, in order to maintain sufficient joint strength, the layer containing chromium (Cr) and / or titanium (Ti) has a thickness of more than 10 angstroms, preferably more than 50 angstroms, more preferably more than 100 angstroms.

一第二絕緣層16藉由物理氣相沉積法或化學氣相沉積法等方式形成ㄧ絕緣材料層於第一電極接觸層151與第二電極接觸層152上。再藉由微影、蝕刻之方式圖案化絕緣材料層以形成第二絕緣層16,以及形成第二絕緣層16之第一開口1601及第二開口1602以分別露出第一電極接觸層151與第二電極接觸層152。A second insulating layer 16 is formed on the first electrode contact layer 151 and the second electrode contact layer 152 by a physical vapor deposition method or a chemical vapor deposition method. Then, the insulating material layer is patterned by lithography and etching to form the second insulating layer 16, and the first opening 1601 and the second opening 1602 of the second insulating layer 16 are formed to expose the first electrode contact layer 151 and the first opening respectively. Two electrode contact layer 152.

於本發明之一實施例中,第二絕緣層16包含一或複數個第一開口1601及一或複數個第二開口1602,其中複數個第一開口1601之數目與複數個第二開口1602之數目可相同或不同。In one embodiment of the present invention, the second insulating layer 16 includes one or more first openings 1601 and one or more second openings 1602, wherein the number of the first openings 1601 and the number of the second openings 1602 are The number can be the same or different.

於本發明之一實施例中,第二絕緣層16之複數個第一開口1601分別位於複數個第一電極接觸層151上,其中複數個第一開口1601之數目與複數個第一電極接觸層151之數目相同。In one embodiment of the present invention, the plurality of first openings 1601 of the second insulating layer 16 are respectively located on the plurality of first electrode contact layers 151, wherein the number of the plurality of first openings 1601 and the plurality of first electrode contact layers are The number of 151 is the same.

於第1圖之上視圖上,第二絕緣層16之第一開口1601與第二開口1602分別位於基板11中心線之兩側。例如第二絕緣層16之第一開口1601位於基板11中心線之右側,第二絕緣層16之第二開口1602位於基板11中心線之左側。In the top view of FIG. 1, the first opening 1601 and the second opening 1602 of the second insulating layer 16 are located on both sides of the centerline of the substrate 11, respectively. For example, the first opening 1601 of the second insulating layer 16 is located on the right side of the center line of the substrate 11, and the second opening 1602 of the second insulating layer 16 is located on the left side of the center line of the substrate 11.

於本發明之一實施例中,第二絕緣層16之第一開口1601包含一寬度小於第一絕緣層14之第一開口1401的寬度。In one embodiment of the present invention, the first opening 1601 of the second insulating layer 16 includes a width smaller than that of the first opening 1401 of the first insulating layer 14.

於本發明之一實施例中,第二絕緣層16之第一開口1601與第一絕緣層14之第一開口1401的位置係重疊,第二絕緣層16之第一開口1601與第一絕緣層14之第一開口1401皆位於第一接觸層131上。In one embodiment of the present invention, the positions of the first opening 1601 of the second insulating layer 16 and the first opening 1401 of the first insulating layer 14 overlap, and the first opening 1601 of the second insulating layer 16 and the first insulating layer The first openings 1401 of 14 are all located on the first contact layer 131.

於本發明之一實施例中,第二絕緣層16之第二開口1602與第一絕緣層14之第二開口1402的位置係錯置。具體而言,第一絕緣層14之第二開口1402位於第二接觸層132上,第二絕緣層16之第二開口1602位於第一接觸層131上。In one embodiment of the present invention, the positions of the second opening 1602 of the second insulating layer 16 and the second opening 1402 of the first insulating layer 14 are offset. Specifically, the second opening 1402 of the first insulating layer 14 is located on the second contact layer 132, and the second opening 1602 of the second insulating layer 16 is located on the first contact layer 131.

於本發明之一實施例中,當第二絕緣層16為一疊層結構時,疊層結構包含二或複數層,由具有不同折射率的兩種材料交替堆疊以形成一布拉格反射鏡(DBR)結構,選擇性地反射特定波長之光。第二絕緣層16係為非導電材料所形成,包含有機材料,例如Su8、苯并環丁烯(BCB)、過氟環丁烷(PFCB)、環氧樹脂(Epoxy)、丙烯酸樹脂(Acrylic Resin)、環烯烴聚合物(COC)、聚甲基丙烯酸甲酯(PMMA)、聚對苯二甲酸乙二酯(PET)、聚碳酸酯(PC)、聚醚醯亞胺(Polyetherimide)或氟碳聚合物(Fluorocarbon Polymer),或是無機材料,例如矽膠(Silicone)或玻璃(Glass),或是介電材料,例如氧化鋁(Al2O3)、氮化矽(SiNx)、氧化矽(SiOx)、氧化鈦(TiOx)或氟化鎂(MgFx)。In one embodiment of the present invention, when the second insulating layer 16 is a laminated structure, the laminated structure includes two or more layers, and two materials with different refractive indexes are alternately stacked to form a Bragg reflector (DBR). ) Structure to selectively reflect light of a specific wavelength. The second insulating layer 16 is formed of a non-conductive material and includes organic materials such as Su8, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), epoxy resin (Epoxy), and acrylic resin (Acrylic Resin). ), Cycloolefin polymer (COC), polymethyl methacrylate (PMMA), polyethylene terephthalate (PET), polycarbonate (PC), polyetherimide or fluorocarbon Polymer (Fluorocarbon Polymer), or inorganic materials, such as Silicone or Glass, or dielectric materials, such as aluminum oxide (Al2O3), silicon nitride (SiNx), silicon oxide (SiOx), oxide Titanium (TiOx) or magnesium fluoride (MgFx).

一第一電極171及一第二電極172藉由電鍍、物理氣相沉積法或化學氣相沉積法等方式形成於第二絕緣層16上。於第1圖之上視圖上,第一電極171靠近基板11之一側,例如基板11中心線之右側,第二電極172靠近基板11之另一側,例如基板11中心線之左側。第一電極171覆蓋第二絕緣層16之第一開口1601,以與第一電極接觸層151相接觸,並透過第一接觸層131與第一半導體層111形成電連接。第二電極172覆蓋第二絕緣層16之第二開口1602,與第二電極接觸層152相接觸,並透過第二接觸層132以與第二半導體層122形成電連接。A first electrode 171 and a second electrode 172 are formed on the second insulating layer 16 by electroplating, physical vapor deposition or chemical vapor deposition. In the top view of FIG. 1, the first electrode 171 is close to one side of the substrate 11, for example, to the right of the centerline of the substrate 11, and the second electrode 172 is close to the other side of the substrate 11, for example, to the left of the centerline of the substrate 11. The first electrode 171 covers the first opening 1601 of the second insulating layer 16 to be in contact with the first electrode contact layer 151 and forms an electrical connection with the first semiconductor layer 111 through the first contact layer 131. The second electrode 172 covers the second opening 1602 of the second insulating layer 16, is in contact with the second electrode contact layer 152, and passes through the second contact layer 132 to form an electrical connection with the second semiconductor layer 122.

於本發明之一實施例中,位於第一電極171之一覆蓋區域下方的複數個半導體柱12包含一第一間距D1以彼此分離,位於第一電極171之覆蓋區域以外的複數個半導體柱12包含一第二間距D2以彼此分離,及第一間距D1大於第二間距D2。In one embodiment of the present invention, the plurality of semiconductor pillars 12 located below a covered area of the first electrode 171 include a first distance D1 to separate them from each other. The plurality of semiconductor pillars 12 located outside the covered area of the first electrode 171 A second distance D2 is included to be separated from each other, and the first distance D1 is larger than the second distance D2.

於本發明之一實施例中,發光元件1更包含一半導體平台。半導體平台包含第一半導體層、活性層及第二半導體層,並位於第一電極171下方,其中位於第一電極171之一覆蓋區域以外的複數個半導體柱12包含一第二間距D2以彼此分離,及半導體平台之第二半導體層包含一寬度大於複數個半導體柱間之第二間距D2。In one embodiment of the present invention, the light emitting device 1 further includes a semiconductor platform. The semiconductor platform includes a first semiconductor layer, an active layer, and a second semiconductor layer, and is located below the first electrode 171, wherein the plurality of semiconductor pillars 12 located outside a covered area of the first electrode 171 include a second distance D2 to be separated from each other. And the second semiconductor layer of the semiconductor platform includes a width D2 which is larger than the second distance D2 between the plurality of semiconductor pillars.

於本發明之一實施例中,第一接觸層131之第一接觸部P1係位於第一電極171及/或第二電極172之下方,第一接觸層131之第一延伸部E1位於第一電極171及第二電極172下方。In one embodiment of the present invention, the first contact portion P1 of the first contact layer 131 is located below the first electrode 171 and / or the second electrode 172, and the first extension portion E1 of the first contact layer 131 is located at the first Below the electrode 171 and the second electrode 172.

於本發明之一實施例中,第一電極171包含一尺寸與第二電極172之一尺寸相同或不同,此尺寸可為寬度或面積。In one embodiment of the present invention, the first electrode 171 includes a size that is the same as or different from one of the second electrodes 172, and the size may be a width or an area.

於本發明之一實施例中,於發光元件1之上視圖上,第一電極171的形狀與第二電極172的形狀相同或近似,例如第一電極171及第二電極172的形狀為矩形,如第1圖所示。In an embodiment of the present invention, in a top view of the light emitting element 1, the shape of the first electrode 171 is the same as or similar to the shape of the second electrode 172. For example, the shapes of the first electrode 171 and the second electrode 172 are rectangular. As shown in Figure 1.

於本發明之一實施例中,第一電極171及第二電極172之材料包含金屬材料,例如鉻(Cr)、鈦(Ti)、鎢(W)、鋁(Al)、銦(In)、錫(Sn)、鎳(Ni)、鉑(Pt)等金屬或上述材料之合金。第一電極171及第二電極172可為單層或疊層結構。當第一電極171及第二電極172為疊層結構時,第一電極171包含一第一上層焊墊及一第一下層焊墊,第二電極172包含一第二上層焊墊及一第二下層焊墊。上層焊墊與下層焊墊分別具有不同的功能。In an embodiment of the present invention, the material of the first electrode 171 and the second electrode 172 includes a metal material, such as chromium (Cr), titanium (Ti), tungsten (W), aluminum (Al), indium (In), Metals such as tin (Sn), nickel (Ni), platinum (Pt), or alloys of the above materials. The first electrode 171 and the second electrode 172 may have a single layer or a stacked structure. When the first electrode 171 and the second electrode 172 are in a stacked structure, the first electrode 171 includes a first upper layer pad and a first lower layer pad, and the second electrode 172 includes a second upper layer pad and a first layer Two lower pads. The upper pads and the lower pads have different functions.

於本發明之一實施例中,上層焊墊的功能主要用於焊接與形成引線。藉由上層焊墊,發光元件1能夠以倒裝晶片形式,使用焊料(solder)或藉由例如AuSn材料共晶接合而安裝於封裝基板上。上層焊墊的金屬材料包含高延展性的材料,例如錫(Sn)、鎳(Ni)、鈷(Co)、鐵(Fe)、鈦(Ti)、銅(Cu)、金(Au)、鎢(W)、鋯(Zr)、鉬(Mo)、鉭(Ta)、鋁(Al)、銀(Ag)、鉑(Pt)、鈀(Pd)、銠(Rh)、銥(Ir)、釕(Ru)、鋨(Os)等金屬或上述材料之合金。上層焊墊可以為上述材料的單層或疊層結構。於本發明之一實施例中,上層焊墊之材料包含鎳(Ni)及/或金(Au),且上層焊墊為單層或疊層結構。In one embodiment of the present invention, the function of the upper layer pad is mainly used for soldering and forming a lead. With the upper bonding pad, the light-emitting element 1 can be mounted on the package substrate in the form of a flip chip, using solder, or by eutectic bonding of an AuSn material, for example. The metal material of the upper pad includes highly ductile materials such as tin (Sn), nickel (Ni), cobalt (Co), iron (Fe), titanium (Ti), copper (Cu), gold (Au), tungsten (W), zirconium (Zr), molybdenum (Mo), tantalum (Ta), aluminum (Al), silver (Ag), platinum (Pt), palladium (Pd), rhodium (Rh), iridium (Ir), ruthenium (Ru), osmium (Os) and other metals or alloys of the above materials. The upper bonding pad may be a single layer or a stacked structure of the above materials. In one embodiment of the present invention, the material of the upper pad includes nickel (Ni) and / or gold (Au), and the upper pad has a single-layer or stacked structure.

於本發明之一實施例中,下層焊墊的功能係與第一電極接觸層151及第二電極接觸層152形成穩定的介面,例如提高第一下層焊墊與第一電極接觸層151的介面接合強度,或是提高第二下層焊墊與第二電極接觸層152的介面接合強度。下層焊墊的另一功能為防止焊料或AuSn共晶中的錫(Sn)擴散進入到反射結構中,破壞反射結構的反射率。因此,下層焊墊包含金(Au)、銅(Cu)以外之金屬材料,例如鎳(Ni)、鈷(Co)、鐵(Fe)、鈦(Ti)、鎢(W)、鋯(Zr)、鉬(Mo)、鉭(Ta)、鋁(Al)、銀(Ag)、鉑(Pt)、鈀(Pd)、銠(Rh)、銥(Ir)、釕(Ru)、鋨(Os)等金屬或上述材料之合金。下層焊墊可以為上述材料的單層或疊層結構。於本發明之一實施例中,下層焊墊包含鈦(Ti)/鋁(Al)之疊層結構,或是鉻(Cr)/鋁(Al) 之疊層結構。In one embodiment of the present invention, the function of the lower bonding pad is to form a stable interface with the first electrode contact layer 151 and the second electrode contact layer 152. For example, the function of the first lower contact pad and the first electrode contact layer 151 is improved. The interface bonding strength, or the interface bonding strength of the second lower bonding pad and the second electrode contact layer 152 is increased. Another function of the lower solder pad is to prevent solder (Sn) in the AuSn eutectic from diffusing into the reflective structure and destroying the reflectivity of the reflective structure. Therefore, the lower pads include metal materials other than gold (Au) and copper (Cu), such as nickel (Ni), cobalt (Co), iron (Fe), titanium (Ti), tungsten (W), and zirconium (Zr). , Molybdenum (Mo), Tantalum (Ta), Aluminum (Al), Silver (Ag), Platinum (Pt), Palladium (Pd), Rhodium (Rh), Iridium (Ir), Ruthenium (Ru), Osmium (Os) And other metals or alloys of the above. The lower bonding pad may be a single layer or a stacked structure of the above materials. In one embodiment of the present invention, the lower bonding pad includes a stacked structure of titanium (Ti) / aluminum (Al), or a stacked structure of chromium (Cr) / aluminum (Al).

於本發明之一實施例中,為防止焊料或AuSn共晶中的錫(Sn)擴散進入到反射結構中,破壞反射結構的反射率。因此,第一電極接觸層151與第一電極171相接之一側包含一金屬材料係選自鈦(Ti)及鉑(Pt)所構成之一群組。第二電極接觸層152與第二電極172相接之一側包含一金屬材料係選自鈦(Ti)及鉑(Pt)所構成之一群組。In one embodiment of the present invention, in order to prevent the tin (Sn) in the solder or the AuSn eutectic from diffusing into the reflective structure, the reflectivity of the reflective structure is destroyed. Therefore, one side of the first electrode contact layer 151 in contact with the first electrode 171 includes a metal material selected from the group consisting of titanium (Ti) and platinum (Pt). One side of the second electrode contact layer 152 in contact with the second electrode 172 includes a metal material selected from the group consisting of titanium (Ti) and platinum (Pt).

第3A圖係本發明一實施例中所揭示之一發光元件2A的部份剖面圖。第3B圖係本發明一實施例中所揭示之發光元件2A的部份上視圖。發光元件2A與發光元件1具有大致相同之結構,因此發光元件2A與發光元件1具有相同之構造,在此會適當省略說明或是不再贅述。FIG. 3A is a partial cross-sectional view of a light-emitting element 2A disclosed in an embodiment of the present invention. FIG. 3B is a partial top view of the light-emitting element 2A disclosed in an embodiment of the present invention. The light-emitting element 2A and the light-emitting element 1 have substantially the same structure. Therefore, the light-emitting element 2A and the light-emitting element 1 have the same structure, and the description will be omitted or omitted here.

如第3A圖、第3B圖所示,發光元件2A係為第2圖之發光元件1所示之半導體柱12的一結構變化實施例。於本發明之一實施例中,半導體疊層包含一第一半導體層221、一活性層223、及一半導體柱22位於活性層223上。活性層223包含一或複數個井層及一或複數個阻障層彼此交替排列,其中井層包含AlxGa1-xN且0.2>x>0.4,及阻障層包含AlyGa1-yN且0.4>y>0.7。第2圖之發光元件1所示之半導體柱12可變化為第3A圖、第3B圖所示之半導體柱22,其各包含一第二半導體層222。於發明之一實施例中,半導體柱22更包含活性層223之一部份,活性層223位於第一半導體層221及第二半導體層222之間,且活性層223可發出一UV光。As shown in FIG. 3A and FIG. 3B, the light-emitting element 2A is a structural variation example of the semiconductor pillar 12 shown in the light-emitting element 1 of FIG. 2. In one embodiment of the present invention, the semiconductor stack includes a first semiconductor layer 221, an active layer 223, and a semiconductor pillar 22 on the active layer 223. The active layer 223 includes one or more well layers and one or more barrier layers arranged alternately with each other, wherein the well layers include AlxGa1-xN and 0.2> x> 0.4, and the barrier layers include AlyGa1-yN and 0.4> y> 0.7 . The semiconductor pillars 12 shown in the light-emitting element 1 of FIG. 2 can be changed into the semiconductor pillars 22 shown in FIGS. 3A and 3B, each of which includes a second semiconductor layer 222. In one embodiment of the invention, the semiconductor pillar 22 further includes a part of the active layer 223. The active layer 223 is located between the first semiconductor layer 221 and the second semiconductor layer 222, and the active layer 223 can emit a UV light.

於本發明之一實施例中,基板11包含第一側壁11s,第一半導體層221包含第二側壁221s,第二半導體層222包含一第三側壁222s,活性層223包含一側壁223s。如第3A圖所示,第二半導體層222之第三側壁222s與活性層223之側壁223s係相隔一距離以露出活性層223之ㄧ表面S3,其中所述活性層223之露出表面S3可為井層或阻障層,井層包含AlxGa1-xN且0.2>x>0.4,及阻障層包含AlyGa1-yN且0.4>y>0.7。第二半導體層222之第三側壁222s與活性層223之表面S3之間具有一鈍角或一直角。In one embodiment of the present invention, the substrate 11 includes a first sidewall 11s, the first semiconductor layer 221 includes a second sidewall 221s, the second semiconductor layer 222 includes a third sidewall 222s, and the active layer 223 includes a sidewall 223s. As shown in FIG. 3A, the third sidewall 222s of the second semiconductor layer 222 and the sidewall 223s of the active layer 223 are spaced apart to expose the surface S3 of the active layer 223. The exposed surface S3 of the active layer 223 may be Well layer or barrier layer, the well layer includes AlxGa1-xN and 0.2> x> 0.4, and the barrier layer includes AlyGa1-yN and 0.4> y> 0.7. There is an obtuse angle or a straight angle between the third sidewall 222s of the second semiconductor layer 222 and the surface S3 of the active layer 223.

於本發明之一實施例中,由第3B圖所示之發光元件2A之上視圖觀之,第二半導體層222包含圓形、橢圓形、矩形、多邊形、或是任意形狀。第二半導體層222為活性層223所環繞,且活性層223之部份表面S3係露出於第二半導體層222之覆蓋區域以外。活性層223之部份表面S3未被第二半導體層222所覆蓋,其中所述活性層223之露出表面S3可為井層或阻障層,井層包含AlxGa1-xN且0.2>x>0.4,及阻障層包含AlyGa1-yN且0.4>y>0.7。In an embodiment of the present invention, viewed from a top view of the light-emitting element 2A shown in FIG. 3B, the second semiconductor layer 222 includes a circle, an oval, a rectangle, a polygon, or any shape. The second semiconductor layer 222 is surrounded by the active layer 223, and a part of the surface S3 of the active layer 223 is exposed outside the covered area of the second semiconductor layer 222. A part of the surface S3 of the active layer 223 is not covered by the second semiconductor layer 222. The exposed surface S3 of the active layer 223 may be a well layer or a barrier layer. The well layer includes AlxGa1-xN and 0.2> x> 0.4. And the barrier layer includes AlyGa1-yN and 0.4> y> 0.7.

於本發明之一實施例中,活性層223為第一半導體層221所環繞,且第一半導體層221之部份表面S1係露出於活性層223之覆蓋區域以外,其中第一半導體層221包含AlGaN。第一半導體層221之部份表面S1不被活性層223所覆蓋。In one embodiment of the present invention, the active layer 223 is surrounded by the first semiconductor layer 221, and a part of the surface S1 of the first semiconductor layer 221 is exposed outside the coverage area of the active layer 223. The first semiconductor layer 221 includes AlGaN. A part of the surface S1 of the first semiconductor layer 221 is not covered by the active layer 223.

第4A圖係本發明一實施例中所揭示之一發光元件2B的部份剖面圖。第4B圖係本發明一實施例中所揭示之發光元件2B的部份上視圖。發光元件2B與發光元件1具有大致相同之結構,因此發光元件2B與發光元件1具有相同之構造,在此會適當省略說明或是不再贅述。FIG. 4A is a partial cross-sectional view of a light-emitting element 2B disclosed in an embodiment of the present invention. FIG. 4B is a partial top view of the light-emitting element 2B disclosed in an embodiment of the present invention. The light-emitting element 2B and the light-emitting element 1 have substantially the same structure. Therefore, the light-emitting element 2B and the light-emitting element 1 have the same structure, and the description will be appropriately omitted or omitted here.

如第4A圖、第4B圖所示,發光元件2B係為第2圖之發光元件1所示之半導體柱12的一結構變化實施例。於本發明之一實施例中,半導體疊層包含一第一半導體層321、一活性層323、及複數個半導體柱32位於第一半導體層321上。半導體柱32各包含一第二半導體層322,且活性層323可發出一UV光。As shown in FIGS. 4A and 4B, the light-emitting element 2B is a structural variation example of the semiconductor pillar 12 shown in the light-emitting element 1 of FIG. 2. In one embodiment of the present invention, the semiconductor stack includes a first semiconductor layer 321, an active layer 323, and a plurality of semiconductor pillars 32 on the first semiconductor layer 321. The semiconductor pillars 32 each include a second semiconductor layer 322, and the active layer 323 can emit a UV light.

於發明之一實施例中,半導體柱32更包含活性層323之一部份,活性層323位於第一半導體層321及第二半導體層322之間,且活性層323可發出一UV光。In one embodiment of the invention, the semiconductor pillar 32 further includes a part of the active layer 323. The active layer 323 is located between the first semiconductor layer 321 and the second semiconductor layer 322, and the active layer 323 can emit a UV light.

於本發明之一實施例中,由第4B圖所示之發光元件2B之上視圖觀之,第二半導體層322包含圓形、橢圓形、矩形、多邊形、或是任意形狀。第二半導體層322為活性層323所環繞,且活性層323之部份表面S3係露出於第二半導體層322之覆蓋區域以外。活性層323之部份表面S3不被第二半導體層322所覆蓋。活性層323為第一半導體層321所環繞,且第一半導體層321之部份表面S1係露出於活性層323之覆蓋區域以外,第一半導體層321之部份表面S1不被活性層323所覆蓋,其中第一半導體層221包含AlGaN。In an embodiment of the present invention, viewed from a top view of the light-emitting element 2B shown in FIG. 4B, the second semiconductor layer 322 includes a circle, an oval, a rectangle, a polygon, or any shape. The second semiconductor layer 322 is surrounded by the active layer 323, and a part of the surface S3 of the active layer 323 is exposed outside the covered area of the second semiconductor layer 322. A part of the surface S3 of the active layer 323 is not covered by the second semiconductor layer 322. The active layer 323 is surrounded by the first semiconductor layer 321, and a part of the surface S1 of the first semiconductor layer 321 is exposed outside the covered area of the active layer 323. A part of the surface S1 of the first semiconductor layer 321 is not covered by the active layer 323. Covering, wherein the first semiconductor layer 221 includes AlGaN.

第5圖係為依本發明一實施例之發光裝置3之示意圖。將前述實施例中的發光元件1、發光元件2A、或發光元件2B以倒裝晶片之形式安裝於封裝基板51 之第一墊片511、第二墊片512上。第一墊片511、第二墊片512之間藉由一包含絕緣材料之絕緣部53做電性絕緣。倒裝晶片安裝係將與用以形成電極之焊墊形成面相對之成長基板之側朝上設置,使成長基板側為主要的光取出面。為了增加發光裝置3之光取出效率,可於發光元件1、發光元件2A、或發光元件2B之周圍設置一反射結構54。FIG. 5 is a schematic diagram of a light emitting device 3 according to an embodiment of the present invention. The light-emitting element 1, the light-emitting element 2A, or the light-emitting element 2B in the foregoing embodiment is mounted on the first pad 511 and the second pad 512 of the package substrate 51 in the form of a flip chip. The first gasket 511 and the second gasket 512 are electrically insulated by an insulating portion 53 including an insulating material. Flip-chip mounting is to set the side of the growth substrate opposite to the pad formation surface used to form the electrode upward, with the growth substrate side as the main light extraction surface. In order to increase the light extraction efficiency of the light emitting device 3, a reflective structure 54 may be provided around the light emitting element 1, the light emitting element 2A, or the light emitting element 2B.

第6圖係為依本發明一實施例之發光裝置4之示意圖。發光裝置4為一球泡燈包括一燈罩602、一反射鏡604、一發光模組610、一燈座612、一散熱片614、一連接部616以及一電連接元件618。發光模組610包含一承載部606,以及複數個發光單元608位於承載部606上,其中複數個發光單元608可為前述實施例中的發光元件1、發光元件2A、發光元件2B、或發光裝置3。FIG. 6 is a schematic diagram of a light emitting device 4 according to an embodiment of the present invention. The light-emitting device 4 is a bulb lamp including a lamp cover 602, a reflector 604, a light-emitting module 610, a lamp holder 612, a heat sink 614, a connection portion 616, and an electrical connection element 618. The light emitting module 610 includes a carrying portion 606 and a plurality of light emitting units 608 are located on the carrying portion 606. The plurality of light emitting units 608 may be the light emitting element 1, the light emitting element 2A, the light emitting element 2B, or the light emitting device in the foregoing embodiment. 3.

本發明所列舉之各實施例僅用以說明本發明,並非用以限制本發明之範圍。任何人對本發明所作之任何顯而易知之修飾或變更皆不脫離本發明之精神與範圍。The embodiments listed in the present invention are only used to illustrate the present invention and are not intended to limit the scope of the present invention. Any obvious modification or change made by anyone to the present invention will not depart from the spirit and scope of the present invention.

1,2A,2B‧‧‧發光元件1,2A, 2B‧‧‧‧Light-emitting element

3,4‧‧‧發光裝置3, 4‧‧‧ light-emitting devices

11‧‧‧基板11‧‧‧ substrate

111,221,321‧‧‧第一半導體層111, 221, 321‧‧‧ the first semiconductor layer

122,222,322‧‧‧第二半導體層122, 222, 322‧‧‧Second semiconductor layer

123,223,323‧‧‧活性層123,223,323‧‧‧‧active layer

12,22,32‧‧‧半導體柱12, 22, 32‧‧‧ semiconductor pillar

S1‧‧‧第一半導體層之表面S1‧‧‧ Surface of the first semiconductor layer

S2‧‧‧基板之表面S2‧‧‧ Surface of substrate

S3‧‧‧活性層之表面S3‧‧‧ surface of active layer

11s‧‧‧第一側壁1111s‧‧‧first side wall 11

111s,221s‧‧‧第二側壁111s, 221s‧‧‧Second sidewall

131‧‧‧第一接觸層131‧‧‧first contact layer

P1‧‧‧第一接觸部P1‧‧‧First contact

14‧‧‧第一絕緣層14‧‧‧The first insulation layer

1402‧‧‧第一絕緣層之第二開口1402‧‧‧Second opening of the first insulating layer

12s,222s‧‧‧第三側壁12s, 222s

132‧‧‧第二接觸層132‧‧‧Second contact layer

E1‧‧‧第一延伸部E1‧‧‧First extension

1401‧‧‧第一絕緣層之第一開口1401‧‧‧First opening of first insulating layer

151‧‧‧第一電極接觸層151‧‧‧first electrode contact layer

152‧‧‧第二電極接觸層152‧‧‧Second electrode contact layer

16‧‧‧第二絕緣層16‧‧‧Second insulation layer

1601‧‧‧第二絕緣層之第一開口1601‧‧‧First opening of second insulating layer

1602‧‧‧第二絕緣層之第二開口1602‧‧‧Second opening of the second insulating layer

171‧‧‧第一電極171‧‧‧first electrode

172‧‧‧第二電極172‧‧‧Second electrode

51‧‧‧封裝基板51‧‧‧Packaging substrate

511‧‧‧第一墊片511‧‧‧first gasket

512‧‧‧第二墊片512‧‧‧Second gasket

53‧‧‧絕緣部53‧‧‧Insulation Department

54‧‧‧反射結構54‧‧‧Reflective structure

602‧‧‧燈罩602‧‧‧Shade

604‧‧‧反射鏡604‧‧‧Mirror

606‧‧‧承載部606‧‧‧bearing department

608‧‧‧發光單元608‧‧‧light-emitting unit

610‧‧‧發光模組610‧‧‧light emitting module

612‧‧‧燈座612‧‧‧ lamp holder

614‧‧‧散熱片614‧‧‧ heat sink

616‧‧‧連接部616‧‧‧Connection Department

618‧‧‧電連接元件618‧‧‧Electrical connection element

第1圖係本發明一實施例中所揭示之一發光元件1的上視圖。FIG. 1 is a top view of a light-emitting element 1 disclosed in an embodiment of the present invention.

第2圖係本發明一實施例中所揭示之發光元件1的剖面圖。FIG. 2 is a cross-sectional view of a light-emitting element 1 disclosed in an embodiment of the present invention.

第3A圖係本發明一實施例中所揭示之一發光元件2A的部份剖面圖。FIG. 3A is a partial cross-sectional view of a light-emitting element 2A disclosed in an embodiment of the present invention.

第3B圖係本發明一實施例中所揭示之發光元件2A的部份上視圖。FIG. 3B is a partial top view of the light-emitting element 2A disclosed in an embodiment of the present invention.

第4A圖係本發明一實施例中所揭示之一發光元件2B的部份剖面圖。FIG. 4A is a partial cross-sectional view of a light-emitting element 2B disclosed in an embodiment of the present invention.

第4B圖係本發明一實施例中所揭示之發光元件2B的部份上視圖。FIG. 4B is a partial top view of the light-emitting element 2B disclosed in an embodiment of the present invention.

第5圖係為依本發明一實施例之發光裝置3之示意圖。FIG. 5 is a schematic diagram of a light emitting device 3 according to an embodiment of the present invention.

第6圖係為依本發明一實施例之發光裝置4之示意圖。FIG. 6 is a schematic diagram of a light emitting device 4 according to an embodiment of the present invention.

Claims (10)

一發光元件可發出一UV光,包含: 一基板; 一氮化鋁緩衝層位於該基板上; 一第一半導體層包含含Alx Ga(1-x) N位於該氮化鋁緩衝層上,其中x>0; 一半導體柱位於該第一半導體層上,該半導體柱包含一第二半導體層及一活性層; 一第一接觸層位於該第一半導體層上,包含一第一接觸部及一第一延伸部,其中該第一延伸部環繞該半導體柱; 一第二接觸層位於該第二半導體層上; 一絕緣層位於該第一接觸電極及該第二接觸層上,其中該絕緣層包含一第一開口露出該第一接觸層之該第一接觸部及一第二開口露出該第二接觸層; 一第一電極覆蓋該第一開口;以及 一第二電極覆蓋該第二開口。A light-emitting element can emit a UV light and includes: a substrate; an aluminum nitride buffer layer on the substrate; a first semiconductor layer containing Al x Ga (1-x) N on the aluminum nitride buffer layer, Where x>0; a semiconductor pillar is located on the first semiconductor layer, the semiconductor pillar includes a second semiconductor layer and an active layer; a first contact layer is located on the first semiconductor layer, and includes a first contact portion and A first extension portion, wherein the first extension portion surrounds the semiconductor pillar; a second contact layer on the second semiconductor layer; an insulating layer on the first contact electrode and the second contact layer, wherein the insulation The layer includes a first opening exposing the first contact portion of the first contact layer and a second opening exposing the second contact layer; a first electrode covers the first opening; and a second electrode covers the second opening . 如申請專利範圍第1項所述的發光元件,其中該基板為一平坦的表面。The light-emitting element according to item 1 of the patent application scope, wherein the substrate is a flat surface. 如申請專利範圍第1項所述的發光元件,其中該第一接觸層之材料不包含銀(Ag)。The light-emitting element according to item 1 of the application, wherein the material of the first contact layer does not include silver (Ag). 如申請專利範圍第1項所述的發光元件,其中該第一接觸層與該第一半導體層相接觸之一側包含鉻(Cr)或鈦(Ti)。The light-emitting element according to item 1 of the patent application scope, wherein one side of the first contact layer in contact with the first semiconductor layer includes chromium (Cr) or titanium (Ti). 如申請專利範圍第1項所述的發光元件,其中0.3>x>0.8。The light-emitting element according to item 1 of the patent application scope, wherein 0.3> x> 0.8. 如申請專利範圍第1項所述的發光元件,其中於該發光元件之一上視圖上,該第二電極接觸層包含一面積大於該第一電極接觸層之一面積。The light-emitting element according to item 1 of the patent application scope, wherein in a top view of one of the light-emitting elements, the second electrode contact layer includes an area larger than an area of the first electrode contact layer. 如申請專利範圍第1項所述的發光元件,其中該UV光包含一波長小於370nm。The light-emitting element according to item 1 of the patent application scope, wherein the UV light includes a wavelength less than 370 nm. 如申請專利範圍第1項所述的發光元件,其中該活性層包含一或複數個井層及一或複數個阻障層彼此交替排列,其中該井層包含Alx Ga1-x N且0.2>x>0.4,及該阻障層包含Aly Ga1-y N且0.4>y>0.7。The light-emitting element according to item 1 of the patent application scope, wherein the active layer comprises one or more well layers and one or more barrier layers are alternately arranged with each other, wherein the well layer comprises Al x Ga 1-x N and 0.2 >x> 0.4, and the barrier layer includes Al y Ga 1-y N and 0.4>y> 0.7. 如申請專利範圍第1項所述的發光元件,其中該第二接觸層包含透明導電材料或金屬材料。The light-emitting element according to item 1 of the patent application scope, wherein the second contact layer comprises a transparent conductive material or a metal material. 如申請專利範圍第1項所述的發光元件,其中該第二接觸層直接接觸該第二半導體層,該第二接觸層包含鉻(Cr)、鈦(Ti)、鎢(W)、金(Au)、鋁(Al)、銦(In)、錫(Sn)、鎳(Ni)、鉑(Pt)、銠(Rh)等金屬或上述材料之合金。The light-emitting element according to item 1 of the scope of patent application, wherein the second contact layer directly contacts the second semiconductor layer, and the second contact layer includes chromium (Cr), titanium (Ti), tungsten (W), and gold ( Au), aluminum (Al), indium (In), tin (Sn), nickel (Ni), platinum (Pt), rhodium (Rh) and other metals or alloys of the above materials.
TW108128752A 2017-07-13 2018-07-04 Light-emitting device TWI704698B (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
TW106123445 2017-07-13
CN106123445 2017-07-13
TW106123445 2017-07-13

Publications (2)

Publication Number Publication Date
TW201946292A true TW201946292A (en) 2019-12-01
TWI704698B TWI704698B (en) 2020-09-11

Family

ID=66590335

Family Applications (2)

Application Number Title Priority Date Filing Date
TW107123088A TWI672826B (en) 2017-07-13 2018-07-04 Light-emitting device
TW108128752A TWI704698B (en) 2017-07-13 2018-07-04 Light-emitting device

Family Applications Before (1)

Application Number Title Priority Date Filing Date
TW107123088A TWI672826B (en) 2017-07-13 2018-07-04 Light-emitting device

Country Status (1)

Country Link
TW (2) TWI672826B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI817129B (en) * 2021-05-28 2023-10-01 晶元光電股份有限公司 Light-emitting device

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007001098A1 (en) * 2005-06-25 2007-01-04 Seoul Opto Device Co., Ltd. Nanostructure having a nitride-based quantum well and light emitting diode employing the same
FR2902237B1 (en) * 2006-06-09 2008-10-10 Commissariat Energie Atomique METHOD FOR PRODUCING A MICROELECTRONIC SEMICONDUCTOR NANOWAR LIGHT EMITTING DEVICE FORMED ON A METALLIC SUBSTRATE
TWI401729B (en) * 2008-10-16 2013-07-11 Advanced Optoelectronic Tech Method for interdicting dislocation of semiconductor with dislocation defects
JP2011119491A (en) * 2009-12-04 2011-06-16 Showa Denko Kk Semiconductor light-emitting element, electronic apparatus, and light-emitting device
TWI478382B (en) * 2012-06-26 2015-03-21 Lextar Electronics Corp Light emitting diode and method for manufacturing the same
US9761774B2 (en) * 2014-12-16 2017-09-12 Epistar Corporation Light-emitting element with protective cushioning

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI817129B (en) * 2021-05-28 2023-10-01 晶元光電股份有限公司 Light-emitting device

Also Published As

Publication number Publication date
TWI704698B (en) 2020-09-11
TW201909444A (en) 2019-03-01
TWI672826B (en) 2019-09-21

Similar Documents

Publication Publication Date Title
US11721791B2 (en) Light-emitting device with semiconductor stack and reflective layer on semiconductor stack
US11658269B2 (en) Light-emitting device
US10361342B2 (en) Light-emitting device
TWI755245B (en) Light-emitting device
US11437430B2 (en) Light-emitting device
US20230135799A1 (en) Light-emitting device
TW201935708A (en) Light-emitting device
TWI704698B (en) Light-emitting device
TWI804437B (en) Light-emitting device
TWM593068U (en) Light-emitting device