TW201939701A - Production method for nonvolatile storage device - Google Patents

Abstract

A production method for a nonvolatile storage device. The production method includes: a step for forming a first hole in a multilayer film that has been formed by alternatingly laminating insulation layers and sacrificial layers and has stair-shaped end parts; a step for etching the insulation layers at an inside wall of the first hole such that a portion of each of the sacrificial layers protrudes further toward the radial-direction inside of the first hole than the insulation layers; a step for depositing an insulating film along the inside wall of the first hole; a step for replacing the sacrificial layers with conductive layers; a step for removing the portion of the insulating film that covers an upper surface of a protruding part of the uppermost conductive layer inside the first hole; and a step for filling the inside of the first hole with a conductive material.

Description

Manufacturing method of non-volatile memory device

The technology disclosed in the present invention relates to a method for manufacturing a non-volatile memory device.

As a small and large-capacity non-volatile memory device, we have known a NAND-type flash memory. In addition, in order to pursue a higher density of memory cells, a NAND-type flash memory having a stacked structure in which a plurality of memory cells are three-dimensionally arranged is known to me.

A NAND-type flash memory having a stacked structure is required to form a contact for a conductive layer that functions as a word line of each memory cell. The contact is formed, for example, by performing etching using the conductive layer in each layer as an etch stop layer to form a contact hole reaching the conductive layer in each layer. Then, a conductive material is filled in the contact hole so that the material is in contact with the conductive layer in each layer. Thereby, a contact for the conductive layer in each layer is formed.
[Xizhi technical literature]
[Patent Literature]

Patent Document 1: US Patent Application Publication No. 2017/0110365

[Problems to be Solved by the Invention]

However, in order to further increase the density of a NAND-type flash memory with a stacked structure, it is envisaged to further increase the number of stacked memory cells. As the number of stacked memory cells increases, the distance between the uppermost conductive layer and the lowermost conductive layer increases. Therefore, when the etching using the conductive layer in each layer as an etching stopper is performed, before the contact hole reaches the conductive layer arranged on the lowest layer, the conductive layer arranged on the upper layer undergoes damage caused by the etching. Suspects of over-etching occurred. As a result, contact holes reaching the conductive layers in each layer are not formed normally, and it is difficult to properly form contacts for the conductive layers in each layer.

Therefore, in a NAND-type flash memory having a stacked structure, it is expected that a contact for a conductive layer in each layer is appropriately formed.
[Technical means to solve the problem]

The method for manufacturing a non-volatile memory device disclosed in the present invention includes, in an implementation form, the following steps: a first hole forming step, which is constituted by alternately laminating an insulating layer and a sacrificial layer, and the ends are formed in a stepped shape The multilayer film is formed with a first hole penetrating the end portion in a lamination direction of the multilayer film. Each insulating layer etching step etches each of the insulating layers in an inner side wall of the first hole to make each sacrificial layer. One part protrudes toward the radially inner side of the first hole than each of the insulating layers; the insulating film deposition step deposits an insulating film along the inner wall of the first hole; the sacrificial layer replacement step replaces each sacrificial layer with Conductive layer; a step of partially removing the insulating film, among the insulating films deposited along the inner side wall of the first hole, covering the conductive layer disposed on the uppermost layer in the first hole toward the first hole A portion of the top surface of the convex portion protruding radially inward is removed; and a conductive material filling step, the top surface of the convex portion of the conductive layer disposed on the uppermost layer in the first hole is exposed from the insulating film In this state, filling the first hole with a guide Electrical material.
[Effect of the present invention]

According to one aspect of the method for manufacturing a non-volatile memory device disclosed in the present invention, the following effect is achieved: In a NAND-type flash memory with a stacked structure, a contact for a conductive layer in each layer can be appropriately formed.

Hereinafter, embodiments of the method for manufacturing a non-volatile memory device disclosed in the present invention will be described in detail with reference to the drawings. In addition, the manufacturing method of the non-volatile memory device disclosed in the present invention is not limited by this embodiment.

[Structure of NAND-type flash memory 10]
FIG. 1 is a longitudinal sectional view showing an example of the structure of a NAND flash memory 10 according to this embodiment. The NAND-type flash memory 10 shown in FIG. 1 is a NAND-type flash memory having a stacked structure in which a plurality of memory cells (not shown) are three-dimensionally arranged. The NAND flash memory 10 includes a substrate 12, a multilayer film 14, an insulating film 16, and a plurality of contact plugs 18. In the following description, the lamination direction of the multilayer film 14 shown in FIG. 1 is defined as the Z direction, and the direction perpendicular to the paper surface in FIG. 1 is defined as the X direction in the plane of each layer, and the parallel to the paper surface in FIG. 1 is defined. The direction is defined as the Y direction.

The substrate 12 is, for example, a substrate formed of a semiconductor such as silicon.

The multilayer film 14 has a structure in which a conductive layer 22 and an insulating layer 24 are alternately laminated, and end portions are formed in a stepped shape. The plurality of pairs of conductive layers 22 and insulating layers 24 correspond to a plurality of memory cells arranged three-dimensionally in the Z direction, respectively. Each conductive layer 22 functions as a word line of each memory cell, for example. Each conductive layer 22 is made of, for example, a metal such as W. Each insulating layer 24 functions as an interlayer insulating film, and insulates the conductive layers 22 adjacent to each other in the Z direction. Each of the insulating layers 24 is, for example, a silicon oxide film. In addition, at the ends of the multilayer film 14, the conductive layer 22 and the insulating layer 24 of each pair are not covered by the other pairs arranged on the upper layer.

The insulating film 16 is formed on the multilayer film 14 so as to cover the multilayer film 14. The insulating film 16 functions as an interlayer insulating film, and insulates the multilayer film 14 from a wiring layer disposed on the insulating film 16. The insulating film 16 is, for example, a silicon oxide film.

In this embodiment, a plurality of contact holes CH are formed in the multilayer film 14 and the insulating film 16 so as to penetrate the ends of the multilayer film 14 in the Z direction. The plurality of contact holes CH are formed together by, for example, etching to reach the substrate 12. However, in the case where each contact hole CH is formed by etching, in the multilayer film 14, each conductive layer 22 is not used as an etching stopper.

In addition, in the inner sidewall of each contact hole CH, a part of each conductive layer 22 protrudes more radially inward of the contact hole CH than each insulating layer 24.

In addition, an insulating film 32 is formed along the inner sidewall of each contact hole CH. The insulating film 32 is, for example, a silicon oxide film. The insulating film 32 is provided with an opening 32 a at a position corresponding to the top surface of the convex portion protruding in the radial direction of the contact hole CH of the conductive layer 22 disposed on the uppermost layer in each contact hole CH. The top surface of the convex portion of the conductive layer 22 disposed on the uppermost layer in each contact hole CH is exposed from the opening 32 a of the insulating film 32.

Each contact plug 18 is arranged in each contact hole CH. Each contact plug 18 is made of a metal such as W, for example. Each contact plug 18 is in contact with the top surface of the convex portion of the conductive layer 22 disposed on the uppermost layer in the corresponding contact hole CH through the opening 32 a of the insulating film 32. In contrast, each contact plug 18 is electrically insulated from the conductive layer 22 other than the conductive layer 22 disposed on the uppermost layer in the corresponding contact hole CH through the insulating film 32.

In this way, in the NAND flash memory 10 of this embodiment, each contact plug 18 is in contact with the top surface of the convex portion of the conductive layer 22 disposed on the uppermost layer in the corresponding contact hole CH, and the insulating film 32 and electrically insulated from other conductive layers 22. Here, in the case where each contact hole CH is formed by etching, each conductive layer 22 in the multilayer film 14 is not used as an etching stopper. Therefore, each of the contact plugs 18 can be electrically connected to the conductive layer 22 disposed on the uppermost layer in the corresponding contact hole CH without using the conductive layer 22 in each layer as an etch stop layer. As a result, in the NAND-type flash memory 10 having a stacked structure, contacts for the conductive layer 22 in each layer are appropriately formed.

[Manufacturing method of NAND flash memory 10]
Next, a method for manufacturing the NAND flash memory 10 according to this embodiment will be described. FIG. 2 is a flowchart showing an example of a method of manufacturing the NAND flash memory 10 according to the present embodiment. 3 to 5 and 7 to 12 are diagrams for explaining an example of a method of manufacturing the NAND flash memory 10 according to the present embodiment.

As shown in step S101 and FIG. 3 in FIG. 2, a multilayer film 44 and an insulating film 46 are fabricated on the substrate 42: the multilayer film 44 alternately stacks the sacrificial layer 52 and the insulating layer 54 to form the end portion in a stepped shape; insulation The film 46 covers the multilayer film 44. In the multilayer film 44 shown in FIG. 3, the sacrificial layer 52 is made of, for example, SiN. The insulating layer 54 is made of a material for forming the insulating layer 24 such as SiO ₂ . The lamination direction of the multilayer film 44 shown in FIG. 3 is defined as the Z direction. Among the layers, the direction perpendicular to the paper surface in FIG. 3 is defined as the X direction, and the direction parallel to the paper surface in FIG. 3 is defined as Y direction.

Then, as shown in step S102 and FIG. 4 of FIG. 2, a plurality of contact holes CH ′ are formed in the multilayer film 44 and the insulating film 46 and penetrate the ends of the multilayer film 14 in the Z direction. The plurality of contact holes CH´ are formed, for example, by anisotropic etching such as RIE (Reactive Ion Etching) to reach the substrate 42. The contact hole CH´ is an example of the first hole. The etching method of the contact hole CH´ is, for example, dry etching; as an etching device, a capacitive coupling plasma (CCP) type device can be used. The specific conditions of the etching at this time are as follows:
・ Etching gas: CF ₄ , mixed gas of Ar and O ₂・ Gas flow rate: CF ₄ / Ar / O ₂ = 100 ～ 300sccm / 500 ～ 1000sccm ／ 50 ～ 100sccm
・ Etching temperature: 20 ～ 100 ℃
・ Etching time: 1 to 300 minutes ・ Etching power: Frequency 13 to 60 MHz and 500 to 3000 W

Then, as shown in step S103 of FIG. 2 and FIG. 5, the insulating layers 54 are etched in the inner sidewalls of the contact holes CH ′, so that a part of each of the sacrificial layers 52 faces the contact holes CH ′ than the insulating layers 54. Protruding radially inward. As a result, a convex portion 52 a is formed on each sacrificial layer 52 so as to protrude radially inward of the contact hole CH ′ than each of the insulating layers 54. In addition, in the etching in step S103, the insulating film 46 is etched in the radial direction of the contact hole CH´ together with the insulating layers 54. For the etching of each insulating layer 54 and the etching of the insulating film 46, for example, isotropic etching such as dry etching is used. The specific conditions of the etching at this time are as follows:
・ Etching gas: CF ₄ , mixed gas of Ar and O ₂・ Gas flow rate: CF ₄ / Ar / O ₂ = 100 ～ 300sccm / 500 ～ 1000sccm ／ 50 ～ 100sccm
・ Etching temperature: 100 ～ 300 ℃
・ Etching time: 1 to 300 minutes ・ Etching power: Frequency 13 to 60 MHz and 500 to 3000 W

Here, the etching of each insulating layer 54 will be described in more detail with reference to FIG. 6. FIG. 6 is a diagram for explaining the etching of each insulating layer 54 in more detail. FIG. 6 is a schematic plan view corresponding to the case where each contact hole CH´ is viewed from the Z-axis direction. In FIG. 6, a cross-sectional area of a portion of the contact hole CH´ surrounded by each insulating layer 54 is A1, and a cross-sectional area of a portion of the contact hole CH´ surrounded by each sacrificial layer 52 is A2. In this case, each insulating layer 54 is etched until the difference (A1-A2) between the cross-sectional area A1 and the cross-sectional area A2 becomes equal to or larger than the cross-sectional area A2. Thereby, the surface area of the top surface of the convex portion 52a of each sacrificial layer 52 is sufficiently ensured. Therefore, in the case where each sacrificial layer 52 is replaced with a conductive layer 72 described later, the surface area for forming contacts for the conductive layer 72 is sufficiently secured. Surface area. As a result, the contact resistance corresponding to the contact to the conductive layer 72 is reduced.

Then, as shown in step S104 of FIG. 2 and FIG. 7, an insulating film 62 is deposited along the inner sidewall of each contact hole CH´. As a result, an insulating film 62 is deposited on the inner side wall of each contact hole CH´ along the convex portion 52a of each sacrificial layer 52. The insulating film 62 is made of a material for forming the insulating film 32 such as SiO ₂ . The insulating film 62 is deposited along, for example, CVD (Chemical Vapor Deposition, Chemical Vapor Deposition, Chemical Vapor Deposition) or ALD (Atomic Layer Deposition, Atomic Layer Deposition) along the inner sidewall of each contact hole CH´. The specific conditions applied to the deposition of the insulating film 62 are as follows:
・ Raw materials: TEOS (tetraethoxysilane), O ₂
・ Forming temperature: 400 ～ 900 ℃
・ Formation time: 5 to 12 hours. Alternatively, the PVD (Physical Vapor Deposition) method or the spin coating method may be used to form the insulating film 62. Forming temperature CVD method, may be set to 300 ~ 1200 ℃, it may be replaced O _2, using O _3. As a raw material, perhydropolyazilane can also be used, but in this case, the insulating film 62 can be formed into a film by a spin coating method.

Then, as shown in step S105 of FIG. 2 and FIG. 8, an organic material 48 is filled in the contact hole CH´ where the insulating film 62 is deposited. The organic material 48 is, for example, SOC (spin-on carbon). The organic material 48 is filled by, for example, CVD or coating.

Then, as shown in step S106 of FIG. 2 and FIG. 9, each sacrificial layer 52 is replaced with a conductive layer 72 in a state where an insulating film 62 is deposited along the inner sidewall of each contact hole CH ′. That is, in the replacement in step S106, first, each sacrificial layer 52 is removed by, for example, isotropic etching such as wet etching. Then, the space obtained by removing each sacrificial layer 52 is filled with a metal material, and a conductive layer 72 is disposed. The metal material filled in the space obtained by removing each sacrificial layer 52 is, for example, a metal material for forming the conductive layer 22 such as W (tungsten). By replacing each sacrificial layer 52 with a conductive layer 72, a convex portion 72a is formed on each conductive layer 72 that protrudes in the radial direction of the contact hole CH 'than each insulating layer 54. The convex portions 72 a of the conductive layers 72 are arranged at positions where the convex portions 52 a of the sacrificial layers 52 are arranged. The specific conditions of wet etching at this time are as follows:
・ Etching liquid: For example, SC-1 (H ₂ O: H ₂ O ₂ : NH ₄ OH = 5: 1: 1 to 5: 1: 0.05 mixed liquid) or SPM (H ₂ SO ₄ : H ₂ O ₂ = 1: 1 mixed solution of 4: 1)
・ Etching temperature: 200 ～ 350 ℃
・ Etching time: 30 to 180 minutes. For filling of metallic materials, for example, in addition to tungsten, WF ₆ or W can be used.
(CO) ₆ conventional materials.

Then, as shown in step S107 of FIG. 2 and FIG. 10, the organic material 48 is removed. The organic material 48 is removed, for example, by ashing.

Then, as shown in step S108 and FIG. 11 of FIG. 2, the convex portion 72 a protruding in the radial direction of the contact hole CH´ is covered with the conductive layer 72 disposed on the uppermost layer of the contact hole CH´ in the insulating film 62. A portion of the top surface is etched away. Thereby, as shown in FIG. 11, an opening 62 a is formed in the insulating film 62 so that the top surface of the convex portion 72 a of the conductive layer 72 disposed on the uppermost layer in the contact hole CH´ is exposed from the opening 62 a of the insulating film 62. The etching method at this time is dry etching; as an etching device, a capacitive coupling plasma (CCP) type device can be used. The specific conditions of the etching at this time are as follows:
・ Etching gas: CF ₄ , mixed gas of Ar and O ₂・ Gas flow rate: CF ₄ / Ar / O ₂ = 100 ～ 300sccm / 500 ～ 1000sccm ／ 50 ～ 100sccm
・ Etching temperature: 20 ～ 100 ℃
・ Etching time: 1 to 300 minutes ・ Etching power: Frequency 13 to 60 MHz and 500 to 3000 W

Then, as shown in step S109 of FIG. 2 and FIG. 12, in a state where the top surface of the convex portion 72a of the conductive layer 72 disposed on the uppermost layer in the contact holes CH´ is exposed, a metal material is filled in each contact hole CH´. 78. Thereby, as shown in FIG. 12, the metal material 78 is in contact with the top surface of the convex portion 72 a of the conductive layer 72 disposed on the uppermost layer in the contact hole CH´. On the other hand, the insulating material 62 electrically isolates the metal material 78 from the conductive layer 72 other than the conductive layer 72 disposed on the uppermost layer in the contact hole CH´. The metal material 78 is a metal material for forming the contact plug 18 such as W (tungsten). The metal material 78 is an example of a material having conductivity. In this way, the NAND-type flash memory 10 of this embodiment is manufactured. The substrate 42 functions as the substrate 12; the conductive layer 72 functions as the conductive layer 22; the insulating layer 54 functions as the insulating layer 24; and the insulating film 46 functions as the insulating film 16. In addition, the metal material 78 functions as the contact plug 18; the insulating film 62 functions as the insulating film 32; and the contact hole CH´ functions as the contact hole CH. For the filling of metal materials, for example, in addition to tungsten, conventional techniques using raw materials such as WF ₆ or W (CO) ₆ can be used.

As described above, according to the manufacturing method of the NAND flash memory 10 according to this embodiment, in a state where the top surface of the convex portion 72a of the conductive layer 72 disposed on the uppermost layer in the contact hole CH´ is exposed from the insulating film 32, Each contact hole CH´ is filled with a metal material 78. Thereby, the metal material 78 is in contact with the top surface of the convex portion 72a of the conductive layer 72 disposed on the uppermost layer in the contact hole CH´, and is electrically insulated from other conductive layers 72 through the insulating film 62. Here, when each contact hole CH´ is formed by etching, each conductive layer 72 is not used as an etching stopper. Therefore, the metal material 78 can be electrically connected to the conductive layer 72 disposed on the uppermost layer in the contact hole CH´ without using the conductive layer 72 in each layer as an etch stop layer. As a result, in the NAND-type flash memory 10 having a stacked structure, contacts to the conductive layer 72 in each layer are appropriately formed.

In addition, according to this embodiment, each insulating layer 54 is etched until the difference between the cross-sectional area A1 of the portion surrounded by each insulating layer 54 of the contact hole CH´ and the cross-sectional area A2 of the portion surrounded by each sacrificial layer 52 (A1 -A2) until the cross-sectional area is A2 or more. Thereby, the surface area of the top surface of the convex portion 52a of each sacrificial layer 52 is sufficiently ensured. Therefore, when each sacrificial layer 52 is replaced with the conductive layer 72, the surface area for forming a contact with the conductive layer 72 is sufficiently ensured. . The surface area for forming the contact with the conductive layer 72 is, for example, equivalent to the surface area of the top surface of the convex portion 72 a of the conductive layer 72 disposed on the uppermost layer in the contact hole CH´. As a result, the contact resistance corresponding to the contact to the conductive layer 72 is reduced.

[Other embodiments]
The technology disclosed in the present invention is not limited to the above-mentioned embodiment, and various modifications can be made within the scope of the gist thereof. Therefore, other embodiments will be described below.

Although the above embodiment exemplifies the case where the multilayer film 44 forms a contact hole CH´ penetrating the end of the multilayer film 44 in the Z direction, the technology disclosed in the present invention is not limited to this embodiment. For example, in the step of forming the contact hole CH´, another contact hole may be formed in the multilayer film 44 while the contact hole CH´ is formed, and the other contact hole penetrates in the Z direction other portions different from the end of the multilayer film 44 . Other contact holes are, for example, memory holes for three-dimensionally arranging a plurality of memory cells. Other contact holes are an example of the second hole.

10‧‧‧NAND flash memory

12, 42‧‧‧ substrate

14, 44‧‧‧ multilayer film

16, 32, 46, 62‧‧‧ insulating film

18‧‧‧ contact plug

22, 72‧‧‧ conductive layer

24, 54‧‧‧ Insulation

32a, 62a‧‧‧ opening

48‧‧‧ Organic Materials

52‧‧‧ sacrificial layer

52a, 72a‧‧‧ convex

78‧‧‧ metallic materials

A1, A2‧‧‧ cross-sectional area

CH, CH´‧‧‧ contact hole

FIG. 1 is a longitudinal sectional view showing an example of the structure of a NAND flash memory according to this embodiment.

FIG. 2 is a flowchart showing an example of a method for manufacturing a NAND flash memory according to this embodiment.

FIG. 3 is a diagram for explaining an example of a method of manufacturing a NAND flash memory according to the present embodiment.

FIG. 4 is a diagram for explaining an example of a method of manufacturing a NAND-type flash memory according to this embodiment.

FIG. 5 is a diagram for explaining an example of a method of manufacturing a NAND flash memory according to the present embodiment.

FIG. 6 is a diagram for explaining the etching of each insulating layer in more detail.

FIG. 7 is a diagram for explaining an example of a method of manufacturing a NAND flash memory according to the present embodiment.

FIG. 8 is a diagram for explaining an example of a method of manufacturing a NAND flash memory according to the present embodiment.

FIG. 9 is a diagram for explaining an example of a method of manufacturing a NAND-type flash memory according to this embodiment.

FIG. 10 is a diagram for explaining an example of a method of manufacturing a NAND flash memory according to the present embodiment.

FIG. 11 is a diagram for explaining an example of a method of manufacturing a NAND-type flash memory according to this embodiment.

FIG. 12 is a diagram for explaining an example of a method of manufacturing a NAND flash memory according to this embodiment.

Claims (3)

A method for manufacturing a non-volatile memory device is characterized by including the following steps: The first hole forming step includes forming a first hole penetrating the end portion in a multilayer film formed by alternately stacking an insulating layer and a sacrificial layer and forming an end portion in a stepped shape; Etching step of each insulating layer, etching each of the insulating layers in the inner side wall of the first hole, so that a part of each of the sacrificial layers protrudes more radially inward of the first hole than each of the insulating layers; An insulating film deposition step, depositing an insulating film along the inner sidewall of the first hole; A sacrificial layer replacement step, each of which is replaced with a conductive layer; In the step of removing the insulating film, the insulating film deposited along the inner side wall of the first hole is covered in the first hole and radially inward of the conductive layer disposed on the uppermost layer toward the first hole. The part of the top surface of the protruding part is removed; and In the conductive material filling step, a conductive material is filled into the first hole in a state where a top surface of the convex portion of the conductive layer disposed on the uppermost layer in the first hole is exposed from the insulating film. For example, the method for manufacturing a non-volatile memory device under the scope of patent application, wherein, In the step of etching each insulating layer, each of the insulating layers is etched until the first cross-sectional area of the portion of the first hole surrounded by the insulating layer and the portion of the first hole surrounded by the sacrificial layer The difference in the second cross-sectional area is equal to or greater than the second cross-sectional area. For example, the method for manufacturing a non-volatile memory device under the scope of patent application No. 1 or 2, wherein: In the first hole forming step, a second hole is formed at the same time as the first hole is formed in the multilayer film, and the second hole is formed in the lamination direction of the multilayer film to penetrate other portions different from the end portion.