TW201935445A - Electronic device - Google Patents

Abstract

A electronic device including a first substrate, a second substrate, a medium layer, at least two sub-pixels, at least two pixel electrodes, at least one scan line, at least two common electrodes, and at least three side electrodes is provided. The media layer is disposed between the first and second substrate. The pixel electrodes are disposed in a first and second region of each sub-pixel respectively, and each sub-pixel has a first and second main pattern that crossed each other. The common electrodes, which includes a first branch and a second branch connected thereof, are disposed in the first and second region respectively. The first and second branches extend along the first and second main pattern respectively, and partially overlap the first and second main pattern respectively. The side electrodes dispose on the side-surface of the first substrate, and electrically connect with the second branches and the scan line respectively.

Description

Electronic device

The invention relates to an electronic device, and more particularly to an electronic device that can be arbitrarily cut.

Display panels have been widely used in different fields and environments at present, and the aspect ratios of common screen sizes are, for example, about 4: 3, 16: 9, 16:10 and other standard specifications. However, the general panel design method cannot be arbitrarily cut to readjust the size of the display panel. In other words, the display panels of the existing shapes and sizes mentioned above cannot meet the needs of various shapes and sizes of panels in various fields, such as medical instruments, electronic signages, radar instructions, polar coordinate displays, etc.

In addition, even if the display panel can be arbitrarily cut to readjust the size of the display panel, after cutting, it will still be limited by the process of the side packaging technology, making the accuracy of the circuit board following the display panel poor. As a result, the display signal is abnormal. For example, the distance between adjacent signal lines (such as gate lines or common electrode lines) is insufficient, so it is easy to be affected by accuracy during the packaging process and cause a short circuit between the two.

The invention provides an electronic device, which can improve the problem that a short circuit easily occurs between an adjacent gate line and a common electrode line, so that the electronic device has good stability.

An embodiment of the present invention provides an electronic device including a first substrate, a second substrate, a dielectric layer, at least two sub-pixels, at least two pixel electrodes, at least one scan line, a first switching element, a second switching element, and at least Two common electrodes, adhesive and at least three side electrodes. The dielectric layer is sandwiched between the first substrate and the second substrate. The sub-pixels are disposed on the inner surface of the first substrate, and each sub-pixel has a first region and a second region. The pixel electrodes are respectively disposed in the first region and the second region of each sub-pixel, wherein each pixel electrode has a first main pattern and a second main pattern. The scanning line, the first switching element, and the second switching element are disposed on the first substrate, and the pixel electrodes located in each sub-pixel are electrically connected to the scanning line via the first switching element and the second switching element, respectively. The common electrodes are respectively disposed in the first region and the second region of each sub-pixel, wherein each common electrode includes a first branch and a second branch connected to the first branch. The first branches located in the first and second regions, respectively, at least partially overlap the first main pattern and extend substantially along the first main pattern. The second branches located in the first region and the second region respectively overlap the second main pattern at least partially and extend substantially along the second main pattern. The adhesive is disposed between the first substrate and the second substrate, wherein the adhesive covers part of the scanning lines located in one of the sub-pixels, part of the pixel electrodes and part of the common electrode in the first and second regions. The side electrodes are disposed on at least one side of the first substrate, wherein the side electrodes are separated from each other, and the side electrodes are electrically connected to the second branch of the first region, the second branch of the second region, and the scan line, respectively.

Another embodiment of the present invention provides an electronic device including a first substrate, a second substrate, a dielectric layer, a first group of sub-pixels, a second group of sub-pixels, a plurality of pixel electrodes, a plurality of scanning lines, and a plurality of pixels. Switching elements, at least two common electrodes, adhesive and at least three side electrodes. The dielectric layer is sandwiched between the first substrate and the second substrate. The first group of sub pixels and the second group of sub pixels are disposed on the first substrate, and the first group of sub pixels and the second group of sub pixels have two adjacent first and second sub pixels, respectively. Pixels. The pixel electrodes are respectively disposed in the first sub-pixel and the second sub-pixel, wherein each pixel electrode has a first main pattern and a second main pattern. The scanning lines and the switching elements are disposed on the first substrate, and the pixel electrodes are electrically connected to the corresponding scanning lines through the corresponding switching elements. The common electrodes are respectively disposed on the first substrate, and each of the common electrodes includes a first branch and a second branch interlaced with the first branch. The first branch at least partially overlaps the first main pattern and extends substantially along the first main pattern. The second branch is respectively located between the first subpixel and the second subpixel adjacent to the first subpixel and the second subpixel. The adhesive is disposed between the first substrate and the second substrate, wherein the adhesive covers a part of the corresponding scanning line of the first sub-pixel and the second sub-pixel adjacent to the first group of sub-pixels, corresponding to A part of the pixel electrodes and a part of the corresponding common electrode. The side electrodes are disposed on at least one side of the first substrate, wherein the side electrodes are separated from each other, and the side electrodes respectively correspond to two adjacent first sub-pixels and the second sub-pixel of the first group of sub-pixels. The scanning line is electrically connected to the corresponding second branch.

Based on the above, in the electronic device of the above embodiment of the present invention, the first branches located in the first region and the second region respectively extend substantially along the first main pattern, and are located in the second regions of the first region and the second region, respectively. The branches extend substantially along the second main pattern. In this way, when the adjacent scan lines and the common electrode are connected to each other, the position where the side electrode is connected to the common electrode can be extended to the second branch, so that the sides of the adjacent scan line and the common electrode can be connected respectively. There is sufficient space between the electrodes to avoid the short circuit caused by the electrodes on the same side being electrically connected to the scan line and the common electrode at the same time, so that the electronic device has good stability.

In order to make the above features and advantages of the present invention more comprehensible, embodiments are hereinafter described in detail with reference to the accompanying drawings.

Hereinafter, the present invention will be explained more fully with reference to the drawings of this embodiment. However, the present invention may be embodied in various forms and should not be limited to the embodiments described herein. The thicknesses of layers and regions in the drawings are exaggerated for clarity. The same or similar reference numbers indicate the same or similar elements, and the following paragraphs will not repeat them one by one. In addition, the directional terms mentioned in the embodiments, such as: up, down, left, right, front, or rear, are only directions referring to the attached drawings. Therefore, the directional terms used are used to illustrate and not to limit the present invention.

In the drawings, the thicknesses of layers, films, panels, regions, etc. are exaggerated for clarity. Throughout the description, the same reference numerals denote the same elements. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "connected to" another element, it can be directly on or connected to the other element, or Intermediate elements may also be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements present. As used herein, "connected" may refer to a physical and / or electrical connection. However, "electrically connected" or "coupled (connected)" may mean that there are other elements between the two elements.

As used herein, "about", "approximately" or "substantially" includes the stated value and an average value within an acceptable deviation range of a particular value determined by one of ordinary skill in the art, taking into account the measurements in question and the measurements A specific number of related errors (ie, limitations of the measurement system). For example, "about" can mean within one or more standard deviations of the value, or within ± 30%, ± 20%, ± 10%, ± 5%. Furthermore, "about", "approximately" or "substantially" as used herein may select a more acceptable range of deviations or standard deviations based on optical properties, etching properties, or other properties, and all properties can be applied without one standard deviation .

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted to have meanings consistent with their meanings in the context of the related art and the present invention, and will not be interpreted as idealized or excessive Formal meaning unless explicitly defined as such in this article.

Exemplary embodiments are described herein with reference to cross-sectional views that are schematic views of idealized embodiments. Accordingly, variations in the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Therefore, the embodiments described herein should not be construed as limited to the particular shape of the area as shown herein, but include shape deviations caused by, for example, manufacturing. For example, a region shown or described as flat may generally have rough and / or non-linear characteristics. Furthermore, the acute angles shown may be round. Therefore, the regions shown in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region and are not intended to limit the scope of patenting.

FIG. 1 is a schematic exploded perspective view of an electronic device according to an embodiment of the present invention. FIG. 2 is a schematic top view of a sub-pixel according to an embodiment of the present invention. FIG. 3 is a schematic exploded perspective view of FIG. 1 after cutting along line A-A '. Fig. 4 is a schematic plan view after cutting along Fig. 2 along line A-A '. It should be noted that, in order to clearly show the relative positions of the first branch COM1, the second branch COM2, and the third branch COM3 of the common electrode and the scan line SL, the switching element, the pixel electrode, and the portion are omitted in FIG. 1. Signal line.

Please refer to FIGS. 1 and 2 first. Before the electronic device 10 is cut along the AA ′ line, it may include a first substrate 100, a second substrate 102, a dielectric layer 104, at least two sub-pixels PX1, PX2, and an adhesive.胶 110。 The rubber 110. The dielectric layer 104 is interposed between the first substrate 100 and the second substrate 102. The medium layer 104 may be a display medium layer, such as a liquid crystal layer, but is not limited thereto. The dielectric layer 104 may include liquid crystal molecules that can be rotated or in-plane-switched by a horizontal electric field or liquid crystal molecules that can be rotated or switched by a vertical electric field, but the invention is not limited thereto. In other embodiments, the dielectric layer 104 may also be a self-luminous material (for example, organic materials, inorganic materials, quantum dots or quantum dot rods, perovskite and its derivatives, or other suitable materials) or other non-self-luminous materials. Luminescent materials (such as electrophoresis, electrowetting, electrodust, or other suitable materials) without using liquid crystals. In some embodiments, the first substrate 100 may be an active array substrate, and the second substrate 102 may be a color conversion substrate. For example, the second substrate 102 has a color conversion layer (eg, a color filter layer, not shown). However, the present invention is not limited to this. In other embodiments, the first substrate 100 may be an active array substrate and a color conversion layer (eg, a color filter layer, not shown), and the second substrate 102 may optionally have no color conversion layer (not shown). (Illustrated), and may optionally be provided with or without other film layers (for example, a flat layer, an electrode, or other suitable film layers). In addition, the first substrate 100 may also be a color conversion substrate. For example, the first substrate 100 has a color conversion layer (eg, a color filter layer, not shown), and the second substrate 102 may be an active array substrate, but The invention is not limited to this. In other embodiments, the second substrate 102 may be an active array substrate and a color conversion layer (eg, a color filter layer, not shown), and the first substrate 100 may optionally not have a color conversion layer (not shown). (Illustrated), and may optionally be provided with or without other film layers (for example, a flat layer, an electrode, or other suitable film layers).

In this embodiment, the sub-pixel PX1 is one of the first group of sub-pixels 106, and the sub-pixel PX2 is one of the second group of sub-pixels 108, where the sub-pixel PX1 and the sub-pixel The pixels PX2 are adjacent to each other. If it is not divided into two groups of sub-pixels, among the more than 10 sub-pixels of the electronic device (for example, the same row or the same column), there are also at least two adjacent sub-pixels PX1 and PX2. The sub pixels PX1 and PX2 are disposed between the first substrate 100 and the second substrate 102. For example, the sub pixels PX1 and PX2 may be disposed on the inner surface of the first substrate 100, and the sub pixels PX1 and PX2 may be respectively disposed. The first region R1 and the second region R2 (for example, each sub-pixel PX1, PX2 has the first region R1 and the second region R2, but is not limited thereto), but is not limited thereto. In some embodiments, each sub-pixel PX1, PX2 may include a first switching element TFT1, a second switching element TFT2, at least one scan line SL, and at least two pixel electrodes PE1, PE2. In this embodiment, the scan line SL, the first switching element TFT1 and the second switching element TFT2 are provided on the first substrate 100 as an example for description (for example, the first substrate 100 is an active array substrate). In this embodiment, the first region R1 and the second region R2 of the sub-pixels PX1 and PX2 may be located on opposite sides (or called different sides) of the scan line SL, respectively, but the present invention is not limited thereto. In other embodiments, the first region R1 and the second region R2 of the sub-pixels PX1 and PX2 may be located on the same side of the scan line SL, respectively.

The first switching element TFT1 can be electrically connected to the corresponding data line DL and the corresponding pixel electrode PE1. For example, the first switching element TFT1 may be electrically connected to the pixel electrode PE1 disposed in the first region R1. The first switching element TFT1 includes a gate G1, a semiconductor layer CH1, a source S1, and a drain D1. In some embodiments, the gate electrode G1 is electrically connected to the corresponding scan line SL (also referred to as the gate line), the source electrode S1 is electrically connected to the corresponding data line DL, and the drain electrode D1 can pass through the contact window C1. It is electrically connected to the corresponding pixel electrode PE1 (for example, the pixel electrode PE1 located in the first region R1), but is not limited thereto. In other embodiments, the drain electrode D1 may be connected to the corresponding pixel electrode PE1 (for example, the pixel electrode PE1 located in the first region R1) without passing through the contact window C1. In addition, at least a part of the semiconductor layer CH1 is located between the gate G1 and the source S1 and the drain D1. In some embodiments, the gate electrode G1 and the scan line SL may be formed of the same patterned conductive layer, and the scan line SL and the data line DL may belong to different patterned conductive layers.

The second switching element TFT2 may be electrically connected to the corresponding pixel electrode PE2. For example, the second switching element TFT2 may be electrically connected to the pixel electrode PE2 disposed in the second region R2. The second switching element TFT2 may include a gate electrode G2, a semiconductor layer CH2, a source electrode S2, and a drain electrode D2. In some embodiments, the gate electrode G2 may be electrically connected to the corresponding scan line SL, the source electrode S2 may be electrically connected to the corresponding data line DL, and the drain electrode D2 may be connected to the corresponding pixel electrode PE2 through the contact window C2. (For example, the pixel electrode PE2 located in the second region R2) is electrically connected, but is not limited thereto. In other embodiments, the drain electrode D2 may be connected to the corresponding pixel electrode PE2 (for example, the pixel electrode PE2 located in the first region R2) without passing through the contact window C2. In addition, at least part of the semiconductor layer CH2 may be located between the gate G2 and the source S2 and the drain D2. In some embodiments, the gate G2 and the scan line SL may be formed of the same patterned conductive layer, and the scan line SL and the data line DL may belong to different patterned conductive layers.

In some embodiments, the source S1 of the first switching element TFT1 and the source S2 of the second switching element TFT2 are connected to the same data line DL, and the gate G1 of the first switching element TFT1 and the second switching element TFT2 The gate G2 is connected to the same scan line SL, so the aperture ratio and related electrical properties of the sub-pixels PX1 and PX2 can be improved, but it is not limited thereto. In other embodiments, the source S1 of the first switching element TFT1 and the source S2 of the second switching element TFT2 may be connected to different data lines DL, respectively, and the gate G1 of the first switching element TFT1 and the second switch The gate G2 of the element TFT2 may be connected to the same scan line SL or may be respectively connected to different scan lines SL. In other embodiments, the source S1 of the first switching element TFT1 and the source S2 of the second switching element TFT2 may be connected to the same data line DL, respectively, and the gate G1 of the first switching element TFT1 and the second switching element The gates G2 of the TFT2 can be connected to different scan lines SL, respectively.

In some embodiments, if each of the sub-pixels PX1 and PX2 may include a first switching element TFT1 and a second switching element TFT2, the first switching element TFT1 and the corresponding circuit and the second switching element TFT2 and the corresponding circuit may refer to the foregoing. description. However, the source S2 of the second switching element TFT2 may be electrically connected to the source S1 of the first switching TFT1; and the gate G2 of the second switching element TFT2 may be electrically connected to the gate G1 of the first switching TFT1. For example, the gate G2 of the second switching element TFT2 and the gate G1 of the first switching TFT1 are electrically connected to the corresponding scanning line SL, and the source S1 of the first switching TFT1 is connected to the source of the second switching element TFT2. The pole S2 is electrically connected to the corresponding data line DL, but is not limited thereto.

In other embodiments, if each of the sub-pixels PX1 and PX2 can optionally further include a third switching element ST (for example, a sharing element), it can be disposed on the first substrate 100. The third switching element ST includes a gate SG, a semiconductor layer SCH, a source SS, and a drain SD. The source SS is electrically connected to the corresponding pixel electrode (for example, the pixel electrode PE2 located in the second region R2) through the contact window C2, and the source SS of the third switching element ST is electrically connected to the second switching element TFT2. The drain D2 is not limited to this. In some embodiments, the drain SD can be connected to the corresponding pixel electrode PE2 (for example, the pixel electrode PE2 located in the first region R2) or the corresponding switching element (for example, the second switching element) without passing through the contact window C2. The drain D2 of the TFT2 is connected. Viewed from another aspect, the third switching element ST of each sub-pixel PX1, PX2 is electrically connected to the second switching element TFT2. In addition, the drain SD of the third switching element ST is electrically connected to the common electrode line CML. The gate SG of the third switching element ST is electrically connected to the corresponding scan line SL. At least part of the semiconductor layer SCH is located between the gate SG and the source SS and the drain SD. In this embodiment, the pixel electrode PE2 in the second region R2 may be a secondary pixel electrode; and the pixel electrode PE1 in the first region R1 may be a primary pixel electrode, but the present invention is not limited thereto. In other embodiments, when the source SS of the third switching element ST is electrically connected to the pixel electrode PE1 of the first region R1 (for example, the source SS of the switching element ST passes through the drain D1 of the first switching element TFT1). In the case of being electrically connected to the pixel electrode PE1 in the first region R1, the pixel electrode PE1 in the first region R1 may be a secondary pixel electrode, and the pixel electrode PE2 in the second region R2 may be a primary pixel electrode. .

At least one of the first switching element TFT1, the second switching element TFT2, and the third switching element ST may be a bottom-gate transistor, a top-gate transistor, a three-dimensional transistor, or another suitable transistor. The gate of the bottom-gate transistor is located below the semiconductor layer, the gate of the top-gate transistor is located above the semiconductor layer, and the channel extension of the semiconductor layer of the three-dimensional transistor is not on a plane. The semiconductor layer can be a single-layer or multi-layer structure, and its material includes amorphous silicon, microcrystalline silicon, nanocrystalline silicon, polycrystalline silicon, single crystal silicon, organic semiconductor materials, oxide semiconductor materials, nano carbon tubes / rods, or other Suitable materials or combinations of the foregoing.

The pixel electrodes PE1 and PE2 may be respectively disposed in the first region R1 and the second region R2 in the sub-pixels PX1 and PX2. For example, the pixel electrodes PE1 and PE2 are disposed in the first region R1 and the second region of the sub-pixel PX1. The first region R1 and the second region R2 of R2 and the sub-pixel PX2. In some embodiments, each of the pixel electrodes PE1 and PE2 has a first main pattern MB1 and a second main pattern MB2 as an example. Preferably, the first main pattern MB1 and the second main pattern MB2 can be staggered with each other, but not Limited to this. For example, the first main pattern MB1 may extend along a predetermined direction (for example: the first direction Y), and the second main pattern MB2 may extend along another predetermined direction (for example: the second direction X). In some embodiments, the first main pattern MB1 can divide each pixel electrode PE1 and PE2 into at least two regions (for example, left and right regions), and the second main pattern MB2 can separate each pixel electrode PE1 and PE2. It is divided into at least two other areas (for example, the upper and lower areas). That is, the first main pattern MB1 and the second main pattern MB2 may be interlaced (or referred to as interlace, for example, interlace). In some embodiments, the first main pattern MB1 and / or the second main pattern MB2 may have a pixel electrode (eg, PE1 and / or PE2) film layer, and may be referred to as a first trunk and / or a second trunk. . In other embodiments, the first main pattern MB1 and / or the second main pattern MB2 may have no pixel electrode (eg, PE1 and / or PE2) film layer (eg, the pixel electrode film layer in the main pattern area is removed). ), And may be called the first main slit and / or the second slit.

In some embodiments, the pixel electrodes PE1 and PE2 may optionally further include a plurality of slits Sli having different extending directions or a plurality of slits Sli having substantially the same extending direction. Therefore, the film layer of the pixel electrode (for example: PE1 and / or PE2) existing between two adjacent slits Sli can be called a branch (not labeled), and each of the pixel electrodes PE1 and PE2 can also have multiple layers. Branches (not labeled) with different extension directions or multiple branches (not labeled) with substantially the same extension direction. In this embodiment, the first main pattern MB1 may be located at the junction of the slits Sli in different extending directions of the pixel electrodes PE1 and PE2, and the second main pattern MB2 may be located in substantially the same extending direction of the pixel electrodes PE1 and PE2. The slit Sli junction, but it is not limited to this.

In this embodiment, the common electrode line CML may substantially overlap with the first main pattern MB1 of the pixel electrodes PE1 and PE2, and the pixel electrodes PE1 and PE2 may be divided into at least two regions. For example, at least part of the common electrode line CML may be located at the junction of the slits in different extending directions of the pixel electrode PE, and the common electrode line CML may extend substantially along the extending direction of the first main pattern MB1, but is not limited to this. In other embodiments, the extending direction of the common electrode line CML may be changed according to requirements and / or effects.

At least two common electrodes COM may be respectively disposed in the first region R1 and the second region R2 of the sub-pixels PX1 and PX2. For example, at least two common electrodes COM are disposed in the first region R1 and the second region of the sub-pixel PX1. The first region R1 and the second region R2 of R2 and the sub-pixel PX2. The common electrode COM includes a first branch COM1 and a second branch COM2 connected to the first branch COM1. In this embodiment, the first branch COM1 and the first main pattern MB1 respectively located in the first region R1 and the second region R2 at least partially overlap and extend substantially along the first main pattern MB1 (eg, along the first direction) Y extension). In addition, the second branch COM2 and the second main pattern MB2 respectively located in the first region R1 and the second region R2 at least partially overlap and extend substantially along the second main pattern MB2 (for example, extending along the second direction X). In some embodiments, the common electrode COM may optionally further include at least two third branches COM3, which may be respectively disposed in the first region R1 and the second region R2 of the sub-pixels PX1 and PX2, such as at least two The three branches COM3 are disposed in the first region R1 and the second region R2 of the sub-pixel PX1 and the first region R1 and the second region R2 of the sub-pixel PX2. The third branch COM3 may be electrically connected to the first branch COM1 located in the first region R1 and the second region R2, respectively. In some embodiments, the third branch COM3 may be located on the opposite side or the same side of the corresponding scan line SL, but is not limited thereto. In some embodiments, the third branch COM3 may extend substantially along the extension direction of the corresponding scan line SL (eg, the second direction X) and is disposed between the corresponding scan line SL and the pixel electrode PE1 and / or PE2. However, the present invention is not limited to this. In this embodiment, the third branch COM3 may be located on opposite sides of the corresponding scan line SL and extend along the extending direction of the corresponding scan line SL, and the opposite ends of the first branch COM1 may be respectively connected to the third The branch COM3 and the second branch COM2. In this way, the common electrode COM can take the shape of, for example, "work or similar work", but the invention is not limited thereto. Furthermore, in addition to connecting the second branch COM2 at one end of the first branch COM1, the first branch COM1 may also extend substantially along the first main pattern MB1 and exceed the second branch COM2 to form, for example, a special shape as shown in FIG. 2, but is not limited thereto.

Based on the above, since the first branch COM1 respectively located in the first region R1 and the second region R2 extends substantially along the first main pattern MB1, and the second branch COM2 respectively located in the first region R1 and the second region R2 is substantially Extending along the second main pattern MB2, when the adjacent scan lines SL and the common electrode COM are connected in a line (for example: after the electronic device 10 is resized, the packaging process is performed on the cut surface, as shown in FIG. 3 As shown in FIG. 4), the position where the side electrode SE is connected to the common electrode COM may extend to the second branch COM2. For example, the position connected to the pad of the circuit board may extend from the third branch COM3 to the second branch COM2. In this way, a sufficient distance S between the side electrodes SE used to connect adjacent scan lines SL and the common electrode COM can be avoided, so as to avoid short circuits caused by the same side electrode SE being electrically connected to the scan lines SL and the common electrode COM at the same time. Problems, so that the electronic device has good stability.

The adhesive 110 is disposed between the first substrate 100 and the second substrate 102. In this embodiment, the first substrate 100 (eg, an active array substrate) having a plurality of sub-pixels PX1 and PX2 can be attached to each other by an adhesive 110 disposed between the first substrate 100 and the second substrate 102. And the second substrate 102 (for example, a color conversion substrate). Furthermore, the adhesive 110 can define an area where the dielectric layer 104 (for example, a liquid crystal layer) is located between the first substrate 100 and the second substrate 102, and can also prevent the dielectric layer from flowing out of the electronic device 10.

In this embodiment, a cutting tool (for example, a cutter (not shown), a laser (not shown), or another suitable tool) may be used to cut along a predetermined cutting line (for example, AA 'line). The electronic device 10 performs a resizing process, so that users can freely select the size of the substrate to be cut according to the design, and reduce the unnecessary area caused by the traditional cutting technology. The waste substrate can be recycled and reused to reduce the glass substrate. waste.

For example, please refer to both FIG. 1 and FIG. 3. Before the resizing process is performed, the dielectric layer 104 is located between the first substrate 100 and the second substrate 102. Next, the resizing process will first re-cut the electronic device 10 along a predetermined cutting line (for example, AA 'line), and then fill a side frame 201 (for example, the cutting surface) of the electronic device 20 with a frame adhesive. (Eg, adhesive 210a) to avoid the loss of the dielectric layer 104 (eg, liquid crystal), and the dielectric layer 104 (eg, the liquid crystal layer) in the electronic device 20 after the resizing process can be maintained as it was before being cut. The adhesive 110 is on an area defined between the first substrate 100 and the second substrate 102 (or referred to as a display area having a plurality of sub-pixels PX1 and PX2). Then, the side surface 201 (for example, the cutting surface) cut out by the electronic device 20 is ground to expose a conductive layer or at least one signal line (for example, the second branch COM2 of the common electrode COM) on the side surface 201 (for example, the cutting surface). And the third branch COM3 and at least one of the scan lines SL). On the other hand, when resizing, the frame adhesive (such as adhesive 110) at the predetermined cutting line (such as A-A 'line) will be removed to form a frame adhesive with a gap after removal. (Eg, adhesive 210) and the sub-pixel related lines near the gap (eg, the related lines of the predetermined cutting line AA '). Then, fill in another frame adhesive (for example: adhesive 210a) in the gap (for example, the area where the adhesive 210a is located) to avoid the loss of the dielectric layer 104 (for example: liquid crystal) and the frame adhesive (for example: adhesive 210a) It can cover part of the scanning lines SL located in one of the sub-pixels PX1 and PX2, part of the pixel electrodes PE1, PE2, and part of the common electrode COM in the first region R1 and the second region R2. Based on the above, the edges of the electronic device 10 can be cut and removed, so that the size of the frame area can be reduced. In some embodiments, the material of the frame adhesive (for example, the adhesive 210 a) may be substantially the same as or different from the material of the adhesive 110 described above, but the present invention is not limited thereto.

Hereinafter, the electronic device 20 formed after the resizing process (for example, the electronic device 10 is cut along line A-A 'shown in FIG. 1) will be described with reference to FIGS. 3 and 4. In addition, the electronic device 20 is substantially the same as the electronic device 10. The difference is that the electronic device 20 is subjected to a side packaging process on its cutting surface. Therefore, the same or similar components use the same or similar reference numerals, and the connection relationships, materials and The process has been described in detail in the previous article, so it will not be repeated hereafter. Wherein, the frame adhesive (for example, the adhesive 210a) is also omitted in FIG. 4, and the related description of the frame adhesive and the sub-pixels can refer to the foregoing embodiment.

Please refer to FIG. 3 and FIG. 4. In this embodiment, a common electrode COM is exposed on a side surface of the electronic device 20 (for example, a cutting surface cut along the line AA ′ in FIG. 1, which will be hereinafter referred to as a “cutting surface”). The second branch COM2 and the third branch COM3 and the scan line SL. In this embodiment, the electronic device 20 further includes at least three side electrodes SE.

The side electrodes SE are disposed on the at least one side surface 201 (eg, a cutting surface) of the first substrate 200 separately from each other, and the side electrodes SE may be respectively separated from the second branch COM2 of the first region R1 and the second branch of the second region R2 COM2 and the scan line SL are electrically connected (for example, the second branch COM2 and the scan line SL exposed by the cutting surface). The side electrode SE may be a mixture of a conductive material and a glue material having a conductive function (for example, silver glue, gold glue, copper glue, or other suitable materials), a conductive material, or other suitable materials.

In some embodiments, the electronic device 20 may further include a plurality of connection pads 116 and a plurality of connection wires 118. The connection pad 116 and the connection line 118 may be disposed on a side surface 201 (for example, a cutting surface) of the first substrate 200. Similarly, the second substrate 202 may also have a side surface 203 (for example, a cutting surface). The connection pad 116 is located below the side electrode SE, and the connection line 118 is disposed between the side electrode SE and the connection pad 116, and the side electrode SE can be electrically connected to the connection pad 116 through the connection line 118. In some embodiments, the connecting line 118 may be fabricated on the side surface 201 (eg, the cutting surface) of the first substrate 200 by using transfer printing, pad printing, screen printing, coating yellow etching, or other suitable methods.

In addition, in order to transmit signals, the electronic device 20 may optionally further include at least one circuit board 114 (for example, a flexible circuit board). The circuit board 114 may be disposed on at least one side surface 201 (eg, a cutting surface) of the first substrate 200, and the circuit board 114 is electrically connected to the side electrode SE. In some embodiments, the pads (not shown) of the circuit board 114 can be connected to the corresponding connection pads 116 respectively, that is, the circuit board 114 can be electrically connected to the side electrode SE through the connection wire 118, so that Improve the stability of the packaging process. In other embodiments, the circuit board 114 may also be directly connected to the side electrode SE, and the connection line 118 and the connection pad 116 are omitted.

In some embodiments, the distance S between the connection pads 116 may be selectively smaller than the distance S between the side electrodes SE, so that the first substrate 200 presents a fan-in on a side surface 201 (for example, a cutting surface). Structure, so that when the side packaging process is performed, it can have a good process tolerance space (when there are multiple circuit boards 114, it can prevent two adjacent circuit boards 114 from easily colliding or pressing each other) The problem of interfering mechanisms) to improve the accuracy of the circuit board adjoining the display panel, thereby improving the problem of discontinuous display. In addition, the width of each connection line 118 can be designed to be different, so as to compensate for the resistance difference between the wires (for example, the resistance difference caused by the different length of each connection line 118). In some embodiments, the length of each connection line 118 can also be designed to be different, so as to compensate for the difference in resistance between the wires.

FIG. 5 is a schematic top view of a sub-pixel according to another embodiment of the present invention. The common electrode COM ′ of FIG. 5 is similar to the common electrode COM, except that the second branch COM ′ 2 of the common electrode COM ′ is disposed at two adjacent first sub-pixels 106 and second sub-pixels. Between 108. Viewed from another aspect, the second branch COM'2 is located at the boundary between two adjacent first group sub-pixels 106 and the second group sub-pixels 108, and the second branch COM'2 will be at least partially from the aforementioned boundary. Copies overlap. In addition, the same or similar components use the same or similar reference numerals, and the connection relationships, materials and processes of the remaining components have been described in detail in the foregoing, so they will not be repeated hereafter.

Referring to FIG. 5, at least two common electrodes COM ′ may be respectively disposed on the first substrate 100. Each common electrode COM 'may include a first branch COM'1 and a second branch COM'2 interlaced with the first branch COM'1, and the first branch COM'1 may at least partially overlap the first main pattern MB1 and Substantially extends along the first main pattern MB1 (for example, extending along the first direction Y), and the second branch COM'2 is located adjacent to the first sub-pixel 106 and the second sub-pixel 108 respectively Between the sub-pixel PX1 and the sub-pixel PX2. Viewed from another aspect, the second branch COM'2 is located at the boundary between the sub-pixel PX1 and the sub-pixel PX2 adjacent to the first sub-pixel 106 and the second sub-pixel 108 108, then the second branch COM'2 will at least partially overlap the aforementioned boundary. In some embodiments, the second branch COM'2 may extend along a predetermined direction (for example, the second direction X). In this way, since the distance S between the second branch COM'2 and the scan line SL is greater than the distance S between the second branch COM2 and the scan line SL as shown in FIG. 3, a cutting tool (for example: a cutter ( (Not shown), laser (not shown), or other suitable tools) to cut the electronic device 30 along a predetermined cutting line (eg, BB 'line) for resizing, respectively, for connection Adequate spacing is provided between adjacent scan lines SL and the side electrodes SE of the common electrode COM ′ to avoid a short circuit caused by the same side electrode SE being electrically connected to the scan lines SL and the common electrode COM ′ at the same time.

In this embodiment, two adjacent sub-pixels PX1 and PX2 of the first group of sub-pixels 106 and the second group of sub-pixels 108 are located on opposite sides of the corresponding second branch COM'2, respectively. That is, the first branch COM'1 provided in the second region R2 of the sub-pixel PX1 and the first branch COM'1 provided in the first region R1 of the sub-pixel PX2 can be connected to the same second branch COM '2, for example: the common electrode COM' presents the shape of a "cross or cross-like" in the second region R2 of the sub-pixel PX1 and the first region R1 of the sub-pixel PX2. In this way, if two adjacent common electrodes COM 'provide substantially the same constant voltage or substantially the same signal, the voltage or signal can be input to the adjacent through the same second branch COM'2. In order to save the number of side electrodes PE connected to the second branch COM'2, the two common electrodes COM 'can simplify the packaging process and have good stability.

In this embodiment, after the resizing process, the adhesive 110 will cover a part of the corresponding scanning line SL of the sub-pixel PX1 and the sub-pixel PX adjacent to the first group of sub-pixels 106 bis, A part of the corresponding pixel electrode PE and a part of the common electrode COM '. For a more detailed description, refer to the foregoing embodiment.

FIG. 6 is a schematic top view of a sub-pixel according to another embodiment of the present invention. The sub-pixels PX11 and PX22 are similar to the sub-pixels PX1 and PX2. The difference is that the pixel electrodes in the sub-pixels PX11 and PX22 have a missing angle 204. Therefore, the same or similar components use the same or similar reference numerals. The connection relationship, materials and processes have been described in detail in the foregoing, so they will not be repeated hereafter. Wherein, the frame adhesive (for example, the adhesive 210a) is also omitted in FIG. 6, and the related description of the frame adhesive and the sub-pixels can refer to the foregoing embodiment.

Please refer to FIG. 6, the pixel electrodes PE11 and PE22 in the sub-pixel PX11 and the sub-pixel PX22 have at least one notch 204, wherein the notch 204 exposes one end of the second branch COM2 of the common electrode COM (for example, FIG. 6 ) Or one end of the second branch COM ′ 2 of the common electrode COM ′ (for example, FIG. 5). As such, when using a cutting tool (such as a cutter (not shown), laser (not shown), or other suitable cutting tool) to cut the electronic device along a predetermined cutting line (such as a C-C 'line) 40. In the resizing process, in addition to the second branch COM2 of the common electrode COM can be exposed to the cutting surface, one end of the second branch COM2 can also be exposed by the notch 204 of the pixel electrodes PE11 and PE22. In this embodiment, during the side-packaging process of the resized electronic device 40, the side electrode PE can be prevented from being electrically connected to the pixel electrodes PE11 and PE22 disposed on the second branch COM2, thereby improving The stability of the electronic device 40.

FIG. 7 is a schematic top view of a sub-pixel according to another embodiment of the present invention. The electronic device 10 is substantially the same as the electronic device 50. The difference is that the electronic device 50 further includes a common electrode layer CL, and the common electrode layer CL has an opening 206. Therefore, other identical or similar components use the same or similar reference numerals, and the connection of the remaining components The relationship, materials, and processes have been described in detail in the previous article, so they will not be repeated here. Among them, the frame glue (for example, adhesive 210a) is also omitted in FIG. 7, and the related description of the frame glue and the sub-pixels can refer to the foregoing embodiment.

Referring to FIG. 7, the electronic device 50 may further include a common electrode layer CL disposed on an inner surface of the second substrate 102. The common electrode layer CL has an opening 206, and the opening 206 exposes one end of a part of the scan line SL. For example, the opening 206 exposes one end of the scan line SL between the pixel electrodes PE1 and PE2 of the sub-pixel PX1 and the sub-pixel PX2 (eg, FIG. 5 or 7) or the sub-pixel PX11 and the sub-pixel. One end of the scanning line SL between the pixel electrodes PE11 and PE22 in the pixel PX22 (for example, FIG. 6). As such, when using a cutting tool (eg, a cutter (not shown), laser (not shown), or other suitable cutting tool) to cut the electronic device 50 along a predetermined cutting line (eg, D-D 'line) In order to perform the resizing process, in addition to the scan line SL being exposed to the cutting surface, one end of the scan line SL is also exposed by the opening 206 of the common electrode layer CL. On the other hand, when the electronic device 50 undergoing the resizing process is subjected to the side packaging process, the side electrode PE can be prevented from being connected to the common electrode layer CL provided on the scan line SL, so that the side electrode PE can be accurately The ground is connected to the scan line SL, thereby improving the stability of the electronic device 50. The common electrode layer CL may be a single-layer or multi-layer transparent conductive layer, and the material thereof includes indium tin oxide (ITO), indium zinc oxide (IZO), nano carbon tube, or nano Carbon rods, indium gallium zinc oxide, or other suitable conductive materials.

In summary, in the electronic device of the above embodiment, the first branches located in the first region and the second region, respectively, extend substantially along the first main pattern, and are located in the second region of the first region and the second region, respectively. The branches extend substantially along the second main pattern. In this way, when the adjacent scan lines and the common electrode are connected to each other, the position where the side electrode is connected to the common electrode can be extended to the second branch, so that the sides of the adjacent scan line and the common electrode can be connected respectively. There is sufficient space between the electrodes to avoid the short circuit caused by the electrodes on the same side being electrically connected to the scan line and the common electrode at the same time, so that the electronic device has good stability.

Although the present invention has been disclosed as above with the examples, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some modifications and retouching without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be determined by the scope of the attached patent application.

10, 20, 30, 40, 50‧‧‧ electronic devices

100, 200‧‧‧ first substrate

102‧‧‧second substrate

104‧‧‧ dielectric layer

106‧‧‧ The first group of pixels

108‧‧‧ second group of pixels

110, 210, 210a‧‧‧ Adhesive

114‧‧‧Circuit Board

116‧‧‧Connecting pad

118‧‧‧ connecting line

201, 203‧‧‧ side

204‧‧‧ missing angle

206‧‧‧ opening

PX1, PX2, PX11, PX22 ‧‧‧ sub pixels

R1‧‧‧ District 1

R2‧‧‧Second District

PE1, PE2, PE11, PE22 ‧‧‧ pixel electrodes

MB1‧‧‧The first main pattern

MB2‧‧‧Second main pattern

S‧‧‧Pitch

SL‧‧‧scan line

DL‧‧‧Data Line

CML‧‧‧Common electrode wire

COM, COM’‧‧‧ common electrode

COM1, COM’1‧‧‧ first branch

COM2, COM’2‧‧‧ second branch

COM3‧‧‧third branch

TFT1, TFT2, ST‧‧‧ switching elements

G1, G2, SG‧‧‧Gate

S1, S2, SS‧‧‧Source

CH1, CH2, SCH‧‧‧ semiconductor layer

D1, D2, SD‧‧‧ Drain

C1, C2‧‧‧ contact window

Y‧‧‧ first direction

X‧‧‧ second direction

SE‧‧‧Side electrode

Sli‧‧‧Main Slit

CL‧‧‧Common electrode layer

FIG. 1 is a schematic exploded perspective view of an electronic device according to an embodiment of the present invention. FIG. 2 is a schematic top view of a sub-pixel according to an embodiment of the present invention. FIG. 3 is a schematic exploded perspective view of FIG. 1 after cutting along line A-A '. Fig. 4 is a schematic plan view after cutting along Fig. 2 along line A-A '. FIG. 5 is a schematic top view of a sub-pixel according to another embodiment of the present invention. FIG. 6 is a schematic top view of a sub-pixel according to another embodiment of the present invention. FIG. 7 is a schematic top view of a sub-pixel according to another embodiment of the present invention.

Claims (14)

An electronic device includes: a first substrate, a second substrate, and a dielectric layer sandwiched between the first substrate and the second substrate; at least two sub-pixels disposed on an inner surface of the first substrate, Each sub-pixel has a first region and a second region; at least two pixel electrodes are respectively disposed in the first region and the second region of each of the sub-pixels, wherein each of the pixel electrodes has A first main pattern and a second main pattern; at least one scan line, a first switching element, and a second switching element are disposed on the first substrate, and among the pixel electrodes of each of the sub-pixels The first switch and the second switch are respectively electrically connected to the scanning line. At least two common electrodes are respectively disposed in the first region and the second region of each sub-pixel, wherein each of the common electrodes includes A first branch and a second branch connected to the first branch, and the first branch and the first main pattern at least in the first region and the second region respectively overlap at least partially and substantially along the The first main pattern extends and is respectively located in the first area and the first area The second branch of the area at least partially overlaps with the second main pattern and extends substantially along the second main pattern; an adhesive is disposed between the first substrate and the second substrate, wherein the adhesive Covering part of the scanning line located in one of the at least two sub-pixels, part of the pixel electrodes and part of the common electrodes in the first and second regions; and at least three side electrodes, arranged at On at least one side of the first substrate, the side electrodes are separated from each other, and the side electrodes are respectively separated from the second branch of the first region, the second branch of the second region, and the scan. Electrical connection. The electronic device according to item 1 of the patent application scope further includes: a third switching element disposed on the first substrate, wherein the third switching element located in each of the sub-pixels is electrically connected to the second Switching element. The electronic device according to item 1 of the scope of the patent application, wherein the first region and the second region of each sub-pixel are respectively located on two opposite sides of the scanning line. The electronic device according to item 1 of the patent application scope further includes: a circuit flexible board disposed on the at least one side of the first substrate, and the circuit flexible board is electrically connected to the side electrodes. The electronic device according to item 1 or 3 of the scope of patent application, further comprising: at least two third branches, which are respectively disposed in the first region and the second region of each sub-pixel, and the third branches are respectively Electrically connected to the first branch located in the first region and the second region. The electronic device according to item 5 of the scope of patent application, wherein the third branches are located on opposite sides of the scan line, respectively. An electronic device includes: a first substrate, a second substrate, and a dielectric layer sandwiched between the first substrate and the second substrate; a first group of sub-pixels and a second group of sub-pixels, And arranged on the first substrate, and the first group of sub-pixels and the second group of sub-pixels have two adjacent first and second sub-pixels, respectively; a plurality of pixel electrodes are provided respectively Among the first sub-pixels and the second sub-pixels, each of the pixel electrodes has a first main pattern and a second main pattern; a plurality of scanning lines and a plurality of switching elements are disposed in the On the first substrate, the pixel electrodes are respectively electrically connected to the corresponding scanning lines via the corresponding switching elements; at least two common electrodes are respectively disposed on the first substrate, and each of the common electrodes includes A first branch and a second branch interlaced with the first branch, and the first branches at least partially overlap the first main patterns and extend substantially along the first main patterns, the first branches Two branches are respectively located in the first group of sub pixels and the second group of sub pixels Between adjacent first sub-pixels and second sub-pixels; an adhesive is disposed between the first substrate and the second substrate, wherein the adhesive covers two phases of the first group of sub-pixels A portion corresponding to the scan line, a portion corresponding to the pixel electrodes, and a portion corresponding to the common electrode adjacent to the first sub-pixel and the second sub-pixel; and at least three sides of the electrode, disposed on On at least one side of the first substrate, the side electrodes are separated from each other, and the side electrodes are adjacent to two of the first group of sub pixels, the first sub pixel and the second sub pixel, respectively. The corresponding scanning line is electrically connected to the corresponding second branch. The electronic device according to item 7 of the scope of patent application, further comprising: a circuit flexible board disposed on the at least one side surface of the first substrate and electrically connected to the side electrodes. The electronic device according to item 7 of the scope of patent application, wherein the first group of sub-pixels and the second group of sub-pixels are adjacent to each other, and the first and second sub-pixels are respectively located in the corresponding first and second sub-pixels. Opposite two sides of two branches. The electronic device described in item 7 or 9 of the scope of patent application, further includes: at least two third branches, and the third branches are respectively electrically connected to the corresponding first branches. The electronic device according to item 10 of the scope of patent application, wherein the third branches are located on opposite sides of the scan line, respectively. The electronic device according to item 1 or 7 of the scope of patent application, wherein at least one of the first main pattern and the second main pattern includes a trunk or a main slit. The electronic device according to item 1 or 7 of the scope of patent application, wherein each of the pixel electrodes has at least one notch, and the notches expose one end of the second branches. The electronic device according to item 1 or 7 of the scope of patent application, further comprising: a common electrode layer disposed on the inner surface of the second substrate, wherein the common electrode layer has an opening that exposes a part of the scanning line One end.