TWI582506B - Pixel array and pixel structure - Google Patents

Pixel array and pixel structure Download PDF

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TWI582506B
TWI582506B TW105117957A TW105117957A TWI582506B TW I582506 B TWI582506 B TW I582506B TW 105117957 A TW105117957 A TW 105117957A TW 105117957 A TW105117957 A TW 105117957A TW I582506 B TWI582506 B TW I582506B
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electrode
pixel
sub
data line
strip
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TW105117957A
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TW201743122A (en
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劉維勲
李珉澤
陳奎百
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友達光電股份有限公司
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    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333Constructional arrangements; Manufacturing methods
    • G02F1/1343Electrodes
    • G02F1/134309Electrodes characterised by their geometrical arrangement

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Geometry (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Liquid Crystal (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Description

畫素陣列以及畫素結構Pixel array and pixel structure

本發明係關於一種畫素陣列以及畫素結構,尤指一種具有高對比之液晶顯示面板之畫素陣列以及畫素結構。The present invention relates to a pixel array and a pixel structure, and more particularly to a pixel array and a pixel structure of a liquid crystal display panel having high contrast.

液晶顯示面板由於具有輕薄短小與節能等優點,已被廣泛地應用在各式電子產品,如智慧型手機(smart phone)、筆記型電腦(notebook computer)、平板電腦(tablet PC)。為了提供廣視角顯示效果,一種聚合物穩定配向型(Polymer-Stabilized Alignment, PSA)液晶顯示面板已普遍地被用來製作高對比及廣視角的顯示器,如電視(TV)、監視器(Monitor)、筆記型電腦(notebook computer)與公共訊息傳遞用之看板(Public Information Display)。聚合物穩定配向型液晶顯示面板的製作的方式在於液晶材料中加入少許的光固化配向單體,並對液晶材料施加電壓使得液晶分子產生預傾角,再適當地照射紫外光使液晶分子的預傾角固定並完成聚合物的穩定。然而,於傳統液晶顯示面板中,為了避免畫素電極與資料線之間的耦合電容過大,畫素電極與資料線之間會有一間隙,因此在暗態時,畫素電極並無法控制對應間隙的液晶分子,光線容易從間隙洩漏出,造成暗態漏光。儘管間隙可透過黑色矩陣遮蔽,但如此設計則會限縮畫素的開口率。Due to its advantages of lightness, thinness, and energy saving, liquid crystal display panels have been widely used in various electronic products, such as smart phones, notebook computers, and tablet PCs. In order to provide a wide viewing angle display, a Polymer-Stabilized Alignment (PSA) liquid crystal display panel has been commonly used to produce high contrast and wide viewing angle displays such as televisions (TVs) and monitors (Monitor). , notebook computer (notebook computer) and public information transmission (Public Information Display). The polymer stabilized alignment type liquid crystal display panel is formed by adding a small amount of photocurable alignment monomer to the liquid crystal material, applying a voltage to the liquid crystal material to cause a pretilt angle of the liquid crystal molecules, and appropriately irradiating the ultraviolet light to make the liquid crystal molecules pretilt angle. Fix and complete the stabilization of the polymer. However, in the conventional liquid crystal display panel, in order to avoid excessive coupling capacitance between the pixel electrode and the data line, there is a gap between the pixel electrode and the data line, so in the dark state, the pixel electrode cannot control the corresponding gap. The liquid crystal molecules, the light easily leaks out of the gap, causing dark state light leakage. Although the gap can be shielded by the black matrix, this design will limit the aperture ratio of the pixels.

在此先前技術部份中公開的上述內容僅是為了加強對本發明背景的理解。因此,其可能包括不構成現有技術的任何部分且不構成現有技術可能對本領域具有通常知識者給出啟示的內容。The above disclosure in this prior art section is only for enhancement of understanding of the background of the invention. Accordingly, it may be included that does not constitute any part of the prior art and does not constitute an admission that the prior art may have the benefit of those of ordinary skill in the art.

本發明之目的之一在於提供一種畫素陣列以及畫素結構,其透過錯位設置畫素電極的第一部分與第二部分並搭配彎折結構之遮蔽電極與共通電極以提升畫素的開口率,並避免資料線與畫素電極之間產生暗態漏光。One of the objects of the present invention is to provide a pixel array and a pixel structure, which are configured by disposing a first portion and a second portion of a pixel electrode and matching a shielding electrode and a common electrode of the bent structure to increase the aperture ratio of the pixel. And to avoid dark light leakage between the data line and the pixel electrode.

本發明之一實施例提供一種畫素陣列,包括基板、第一子畫素、第二子畫素、第一資料線以及共通電極。第一子畫素設置於基板上,其中第一子畫素包含一第一畫素電極以及一第一遮蔽電極。第二子畫素設置於基板上,並與第一子畫素彼此相鄰,其中第二子畫素包含一第二畫素電極以及一第二遮蔽電極。第一資料線位於第一子畫素與第二子畫素之間,其中第一畫素電極與第一資料線之間具有一第一狹縫,且第二畫素電極與第一資料線之間具有一第二狹縫。共通電極沿著第一資料線設置,共通電極包含彼此電性連接的一第一子共通電極以及一第二子共通電極,其中第一子共通電極和第一遮蔽電極係與第一狹縫遮蔽重疊設置,以及第二子共通電極和第二遮蔽電極係與第二狹縫重疊設置。An embodiment of the present invention provides a pixel array including a substrate, a first sub-pixel, a second sub-pixel, a first data line, and a common electrode. The first sub-pixel is disposed on the substrate, wherein the first sub-pixel comprises a first pixel electrode and a first shielding electrode. The second sub-pixel is disposed on the substrate and adjacent to the first sub-pixels, wherein the second sub-pixel comprises a second pixel electrode and a second shielding electrode. The first data line is located between the first sub-pixel and the second sub-pixel, wherein the first pixel electrode and the first data line have a first slit, and the second pixel electrode and the first data line There is a second slit between them. The common electrode is disposed along the first data line, and the common electrode includes a first sub-common electrode and a second sub-common electrode electrically connected to each other, wherein the first sub-common electrode and the first shielding electrode are shielded from the first slit The overlapping arrangement, and the second sub-common electrode and the second shielding electrode are overlapped with the second slit.

本發明之另一實施例提供一種畫素結構,包括第一基板、掃描線、資料線、主動元件、第一遮蔽電極、畫素電極以及共通電極。掃描線設置於第一基板上。資料線與掃描線交錯設置,其中資料線沿一方向延伸,且資料線沿其延伸方向上具有彼此相對的一第一側與一第二側。主動元件與掃描線和資料線電性連接。第一遮蔽電極設置於第一基板上,第一遮蔽電極包括一第一條狀部、一第二條狀部以及一第一連接部,其中第一連接部的兩端分別與第一條狀部和第二條狀部連接,藉此第一連接部與第一條狀部和第二條狀部分別形成一彎折結構。畫素電極與主動元件電性連接,畫素電極包括一第一部分與一第二部分,分別設置於第一連接部的兩側,第一部分具有彼此相對的一第一邊與一第二邊,第二部分具有彼此相對的一第三邊與一第四邊,第一邊連接第三邊,第二邊連接第四邊,其中第一條狀部與畫素電極的第一邊重疊設置,第二條狀部與畫素電極的第四邊重疊設置,並且資料線與畫素電極的第三邊之間無狹縫。共通電極沿著資料線設置,其中共通電極包含彼此電性連接的一第一子共通電極以及一第二子共通電極,第一子共通電極與資料線的第一側重疊設置,以及第二子共通電極與資料線的第二側重疊設置。Another embodiment of the present invention provides a pixel structure including a first substrate, a scan line, a data line, an active device, a first shielding electrode, a pixel electrode, and a common electrode. The scan line is disposed on the first substrate. The data lines are alternately arranged with the scan lines, wherein the data lines extend in a direction, and the data lines have a first side and a second side opposite to each other along the extending direction thereof. The active component is electrically connected to the scan line and the data line. The first shielding electrode is disposed on the first substrate, the first shielding electrode includes a first strip portion, a second strip portion and a first connecting portion, wherein the two ends of the first connecting portion are respectively associated with the first strip The portion is coupled to the second strip, whereby the first connecting portion and the first strip portion and the second strip portion respectively form a bent structure. The pixel electrode is electrically connected to the active component, and the pixel electrode includes a first portion and a second portion respectively disposed on two sides of the first connecting portion, the first portion having a first side and a second side opposite to each other, The second portion has a third side and a fourth side opposite to each other, the first side is connected to the third side, and the second side is connected to the fourth side, wherein the first strip is overlapped with the first side of the pixel electrode, The second strip is overlapped with the fourth side of the pixel electrode, and there is no slit between the data line and the third side of the pixel electrode. The common electrode is disposed along the data line, wherein the common electrode includes a first sub-common electrode and a second sub-common electrode electrically connected to each other, the first sub-common electrode is overlapped with the first side of the data line, and the second sub-sub The common electrode is disposed to overlap the second side of the data line.

為使熟悉本發明所屬技術領域之一般技藝者能更進一步了解本發明,下文特列舉本發明之較佳實施例,並配合所附圖式,詳細說明本發明的構成內容及所欲達成之功效。The present invention will be further understood by the following detailed description of the preferred embodiments of the invention, .

請參考第1圖至第3圖,第1圖繪示了本發明第一實施例之畫素陣列的俯視示意圖,第2圖繪示了沿著第1圖剖線A-A’之剖面示意圖,第3圖繪示了沿著第1圖剖線B-B’之剖面示意圖。如第1圖至第3圖所示,本實施例所提供之畫素陣列PA可包括複數個畫素結構PS,呈陣列方式排列。為清楚顯示畫素陣列PA,第1圖僅以三個排列於同一列之畫素結構PS示意,但本發明不以此為限。畫素結構PS可包括第一基板Sub1、資料線DL、掃描線SL、子畫素SP與共通電極CE。資料線DL大體上沿第一方向D1設置,掃描線SL大體上沿第二方向D2設置,且資料線DL與掃描線SL彼此交錯設置,並定義出子畫素SP。資料線DL與掃描線SL可透過一絕緣層IN1彼此電性絕緣。舉例而言,第一方向D1可與第二方向D2垂直,但不限於此。於本發明中,與第一方向的D1銳角夾角在10度以內的延伸方向均可視為大體上沿第一方向D1設置。於本實施例中,畫素結構PS可另包括第二基板Sub2與顯示介質DM。第一基板Sub1與第二基板Sub2彼此相對設置,且顯示介質DM設置於第一基板Sub1與第二基板Sub2之間。第一基板Sub1與第二基板Sub2可分別包括透明基板例如玻璃基板、塑膠基板、石英基板、藍寶石基板或其他適合的硬質基板或可撓式基板。本實施例之資料線DL、掃描線SL與子畫素SP設置於第一基板Sub1與顯示介質DM之間的第一基板Sub1上,但不限於此。另外,第二基板Sub2可例如為一彩色濾光片基板,包含對向電極CTE、彩色濾光層CF以及黑色矩陣BM,且顯示介質DM包括一聚合物穩定配向液晶層,使畫素陣列PA可應用於液晶顯示面板中,但本發明不限於此。Please refer to FIG. 1 to FIG. 3 . FIG. 1 is a schematic top view of a pixel array according to a first embodiment of the present invention, and FIG. 2 is a cross-sectional view along line A-A′ of FIG. 1 . Figure 3 is a cross-sectional view taken along line BB' of Figure 1. As shown in FIG. 1 to FIG. 3, the pixel array PA provided in this embodiment may include a plurality of pixel structures PS arranged in an array manner. In order to clearly show the pixel array PA, the first figure is illustrated by only three pixel structures PS arranged in the same column, but the invention is not limited thereto. The pixel structure PS may include a first substrate Sub1, a data line DL, a scan line SL, a sub-pixel SP, and a common electrode CE. The data line DL is disposed substantially along the first direction D1, the scan line SL is disposed substantially along the second direction D2, and the data line DL and the scan line SL are alternately arranged with each other, and the sub-pixel SP is defined. The data line DL and the scan line SL are electrically insulated from each other through an insulating layer IN1. For example, the first direction D1 may be perpendicular to the second direction D2, but is not limited thereto. In the present invention, the extending direction of the acute angle of D1 in the first direction within 10 degrees can be regarded as being substantially along the first direction D1. In this embodiment, the pixel structure PS may further include a second substrate Sub2 and a display medium DM. The first substrate Sub1 and the second substrate Sub2 are disposed opposite to each other, and the display medium DM is disposed between the first substrate Sub1 and the second substrate Sub2. The first substrate Sub1 and the second substrate Sub2 may respectively include a transparent substrate such as a glass substrate, a plastic substrate, a quartz substrate, a sapphire substrate, or other suitable rigid substrate or flexible substrate. The data line DL, the scanning line SL, and the sub-pixel SP of the present embodiment are disposed on the first substrate Sub1 between the first substrate Sub1 and the display medium DM, but are not limited thereto. In addition, the second substrate Sub2 may be, for example, a color filter substrate including a counter electrode CTE, a color filter layer CF, and a black matrix BM, and the display medium DM includes a polymer stable alignment liquid crystal layer to make the pixel array PA It can be applied to a liquid crystal display panel, but the invention is not limited thereto.

子畫素SP可包括主動元件AD、遮蔽電極SE及畫素電極PE。主動元件AD可例如為薄膜電晶體元件,其閘極G、源極S與汲極D分別與對應之掃描線SL、對應之資料線DL以及畫素電極PE電性連接。遮蔽電極SE可用以遮蔽(shielding)畫素電極PE與資料線DL之間的暗態漏光並降低畫素電極PE與資料線DL之間的電容耦合程度。畫素電極PE可透過另一絕緣層IN2與資料線DL電性絕緣。The sub-pixel SP may include an active element AD, a shadow electrode SE, and a pixel electrode PE. The active device AD can be, for example, a thin film transistor device, and the gate G, the source S and the drain D are electrically connected to the corresponding scan line SL, the corresponding data line DL and the pixel electrode PE, respectively. The shielding electrode SE can be used to shield the dark state light leakage between the pixel electrode PE and the data line DL and reduce the degree of capacitive coupling between the pixel electrode PE and the data line DL. The pixel electrode PE can be electrically insulated from the data line DL through another insulating layer IN2.

為清楚說明各畫素結構PS以及相鄰之畫素結構PS之間的配置關係,下文以排列於同一列且彼此相鄰之第一畫素結構PS1與第二畫素結構PS2為例,但不限於此。請進一步參考第4圖,且一併參考第1圖至第3圖。第4圖繪示了本發明第一實施例之畫素結構之資料線、掃描線與子畫素之俯視示意圖。如第4圖所示,第一畫素結構PS1與第二畫素結構PS2之子畫素SP分別為第一子畫素SP1與第二子畫素SP2。第一子畫素SP1與第二子畫素SP2之遮蔽電極SE分別為第一遮蔽電極SE1與第二遮蔽電極SE2,第一子畫素SP1與第二子畫素SP2之畫素電極PE分別為第一畫素電極PE1以及第二畫素電極PE2。第一畫素結構PS1與第二畫素結構PS2之資料線DL分別為第一資料線DL1與第二資料線DL2,第一資料線DL1位於第一子畫素SP1與第二子畫素SP2之間,且第二子畫素SP2之第二遮蔽電極SE2與第二畫素電極PE2位於第一資料線DL1與第二資料線DL2之間。In order to clearly explain the arrangement relationship between each pixel structure PS and the adjacent pixel structure PS, the following is an example of the first pixel structure PS1 and the second pixel structure PS2 which are arranged in the same column and adjacent to each other, but Not limited to this. Please refer to Figure 4 for further reference and refer to Figures 1 to 3 together. FIG. 4 is a top plan view showing a data line, a scan line and a sub-pixel of the pixel structure of the first embodiment of the present invention. As shown in FIG. 4, the sub-pixels SP1 of the first pixel structure PS1 and the second pixel structure PS2 are the first sub-pixel SP1 and the second sub-pixel SP2, respectively. The shielding electrodes SE of the first sub-pixel SP1 and the second sub-pixel SP2 are the first shielding electrode SE1 and the second shielding electrode SE2, respectively, and the pixel electrodes PE of the first sub-pixel SP1 and the second sub-pixel SP2 are respectively It is a first pixel electrode PE1 and a second pixel electrode PE2. The data lines DL of the first pixel structure PS1 and the second pixel structure PS2 are the first data line DL1 and the second data line DL2, respectively, and the first data line DL1 is located at the first sub-pixel SP1 and the second sub-pixel SP2 The second shielding electrode SE2 and the second pixel electrode PE2 of the second sub-pixel SP2 are located between the first data line DL1 and the second data line DL2.

具體而言,第一遮蔽電極SE1可包括第一條狀部SEP1、第二條狀部SEP2以及第一連接部SEC1,其中第一連接部SEC1的兩端分別與第一條狀部SEP1和第二條狀部SEP2連接,藉此第一連接部SEC1與第一條狀部SEP1和第二條狀部SEP2形成一彎折結構。精確地說,第一條狀部SEP1與第二條狀部SEP2分別從第一連接部SEC1的兩端點朝相反方向延伸,第一條狀部SEP1與第二條狀部SEP2可大體上沿第二方向D2設置,以形成類似閃電的形狀圖案,也可以說是階梯狀。舉例而言,第一條狀部SEP1與第一連接部SEC1的夾角以及第二條狀部SEP2與第一連接部SEC1的夾角可介於75度至105度之間。同樣地,第二遮蔽電極SE2可與第一遮蔽電極SE1具有相同的彎折結構,亦即第二遮蔽電極SE2可包括第三條狀部SEP3、第四條狀部SEP4以及第二連接部SEC2,第二連接部SEC2的兩端分別與第三條狀部SEP3和第四條狀部SEP4連接,藉此第二連接部SEC2與第三條狀部SEP3和第四條狀部SEP4亦形成與第一遮蔽電極SE1具有相同形狀圖案之彎折結構。精確地說,第三條狀部SEP3與第四條狀部SEP4分別從第二連接部SEC2的兩端點朝相反方向延伸,且第三條狀部SEP3與第四條狀部SEP3可大體上沿第二方向D2設置。舉例而言,第三條狀部SEP3與第二連接部SEC2的夾角以及第四條狀部SEP4與第二連接部SEC2的夾角可介於75度至105度之間。於本實施例中,第一遮蔽電極SE1、第二遮蔽電極SE2與掃描線SL係由同一圖案化金屬層所構成,且第一遮蔽電極SE1和第二遮蔽電極SE2與掃描線SL結構上彼此分離。並且,第一遮蔽電極SE1與第二遮蔽電極SE2可分別包括第三連接部SEC3,且第三連接部SEC3以串聯方式彼此相連接而形成一共通線。於本實施例中,第一遮蔽電極SE1與第二遮蔽電極SE2之第三連接部SEC3係分別與第一條狀部SEP1以及第三條狀部SEP3連接,而未與第二條狀部SEP2以及第四條狀部SEP4連接。於另一變化實施例中,遮蔽電極SE亦可與掃描線SL由不同的金屬層所構成。Specifically, the first shielding electrode SE1 may include a first strip portion SEP1, a second strip portion SEP2, and a first connecting portion SEC1, wherein both ends of the first connecting portion SEC1 are respectively associated with the first strip portion SEP1 and The two strips SEP2 are connected, whereby the first connecting portion SEC1 forms a bent structure with the first strip portion SEP1 and the second strip portion SEP2. Precisely, the first strip SEP1 and the second strip SEP2 respectively extend from opposite ends of the first connecting portion SEC1 in opposite directions, and the first strip portion SEP1 and the second strip portion SEP2 may substantially follow The second direction D2 is set to form a shape pattern similar to lightning, which can also be said to be stepped. For example, the angle between the first strip SEP1 and the first connecting portion SEC1 and the angle between the second strip portion SEP2 and the first connecting portion SEC1 may be between 75 degrees and 105 degrees. Similarly, the second shielding electrode SE2 can have the same bending structure as the first shielding electrode SE1, that is, the second shielding electrode SE2 can include the third strip portion SEP3, the fourth strip portion SEP4, and the second connecting portion SEC2. The two ends of the second connecting portion SEC2 are respectively connected to the third strip portion SEP3 and the fourth strip portion SEP4, whereby the second connecting portion SEC2 and the third strip portion SEP3 and the fourth strip portion SEP4 are also formed. The first shielding electrode SE1 has a bent structure of the same shape pattern. Precisely, the third strip SEP3 and the fourth strip SEP4 respectively extend from opposite ends of the second connecting portion SEC2 in opposite directions, and the third strip portion SEP3 and the fourth strip portion SEP3 may substantially Set in the second direction D2. For example, the angle between the third strip SEP3 and the second connecting portion SEC2 and the angle between the fourth strip portion SEP4 and the second connecting portion SEC2 may be between 75 degrees and 105 degrees. In this embodiment, the first shielding electrode SE1, the second shielding electrode SE2 and the scanning line SL are formed by the same patterned metal layer, and the first shielding electrode SE1 and the second shielding electrode SE2 and the scanning line SL are structurally connected to each other. Separation. Moreover, the first shielding electrode SE1 and the second shielding electrode SE2 may respectively include a third connecting portion SEC3, and the third connecting portions SEC3 are connected to each other in series to form a common line. In this embodiment, the third connection portion SEC3 of the first shielding electrode SE1 and the second shielding electrode SE2 are respectively connected to the first strip portion SEP1 and the third strip portion SEP3, and not to the second strip portion SEP2. And the fourth strip SEP4 is connected. In another variant embodiment, the shielding electrode SE can also be formed from a different metal layer than the scanning line SL.

第一畫素電極PE1與第二畫素電極PE2可分別包括第一部分P1與第二部分P2。第一畫素電極PE1之第一部分P1與第二部分P2分別設置於第一連接部SEC1的兩側,同樣地第二畫素電極PE2之第一部分P1與第二部分P2分別設置於第二連接部SEC2的兩側。第一部分P1具有彼此相對的一第一邊S1與一第二邊S2,且第二部分P2具有彼此相對的一第三邊S3與一第四邊S4,其中第一畫素電極PE1之第一邊S1與第三邊S3面對第一資料線DL1,第二邊S2與第四邊S4面對第三資料線DL3,而第二畫素電極PE2之第一邊S1與第三邊S3面對第二資料線DL2,第二邊S2與第四邊S4面對第一資料線DL1。第一邊S1可連接第三邊S3,且第二邊S2可連接第四邊S4。換句話說,第一資料線DL沿其延伸方向(即第一方向D1)具有彼此相對的一第一側DLS1與一第二側DLS2,而第一畫素電極PE1鄰近第一資料線DL1的第一側DLS1可包括第一邊S1與第三邊S3,且第二畫素電極PE2鄰近第一資料線DL1的第二側DLS2可包括第二邊S2與第四邊S4。The first pixel electrode PE1 and the second pixel electrode PE2 may include a first portion P1 and a second portion P2, respectively. The first portion P1 and the second portion P2 of the first pixel electrode PE1 are respectively disposed on two sides of the first connecting portion SEC1, and the first portion P1 and the second portion P2 of the second pixel electrode PE2 are respectively disposed on the second connection. Both sides of the SEC2. The first portion P1 has a first side S1 and a second side S2 opposite to each other, and the second portion P2 has a third side S3 and a fourth side S4 opposite to each other, wherein the first pixel electrode PE1 is first The side S1 and the third side S3 face the first data line DL1, the second side S2 and the fourth side S4 face the third data line DL3, and the first side S1 and the third side S3 of the second pixel electrode PE2 face For the second data line DL2, the second side S2 and the fourth side S4 face the first data line DL1. The first side S1 can be connected to the third side S3, and the second side S2 can be connected to the fourth side S4. In other words, the first data line DL has a first side DLS1 and a second side DLS2 opposite to each other along the extending direction thereof (ie, the first direction D1), and the first pixel electrode PE1 is adjacent to the first data line DL1. The first side DLS1 may include a first side S1 and a third side S3, and the second pixel electrode PE2 adjacent to the second side DLS2 of the first data line DL1 may include a second side S2 and a fourth side S4.

具體而言,畫素電極PE並非為矩形,而是矩形之第一部分P1與矩形之第二部分P2可於第一方向D1上錯位設置,使得第一邊S1與第三邊S3並非位於同一直線上,且第二邊S2與第四邊S4並非位於同一直線上。並且,第一邊S1係透過一轉折邊與第三邊S3連接,同理第二邊S2係透過另一轉折邊與第四邊S4連接。於本實施例中,第一部分P1設置於第二部分P2與掃描線SL之間。第一畫素電極PE1之第一部分P1的第一邊S1較第二部分P2的第三邊S3遠離第一資料線DL1,且第一部分P1的第一邊S1與第一資料線DL1於第一基板Sub1的垂直投影方向Z上不重疊,因此第一資料線DL1與第一畫素電極PE1之第一邊S1之間具有一第一狹縫ST1。也就是,第一邊S1與第一資料線DL1之間的間距大於第三邊S3與第一資料線DL1之間的間距。第二畫素電極PE2之第二部分P2的第四邊S4較第一部分P1的第二邊S2遠離所面對之第一資料線DL1,且第二部分P2的第四邊S4與第一資料線DL1於垂直投影方向Z上不重疊,因此第一資料線DL1與第二畫素電極PE2之第四邊S4之間具有一第二狹縫ST2。也就是,第四邊S4與第一資料線DL1之間的間距大於第二邊S2與第一資料線DL1之間的間距。於本實施例中,第一畫素電極PE1之第二部分P2的第三邊S3與第一資料線DL1的第一側DLS1於垂直投影方向Z上可無間隙,且第一畫素電極PE1之第三邊S3與第一遮蔽電極SE1於垂直投影方向Z上不重疊。較佳地,第一畫素電極PE1之第三邊S3與第一資料線DL1面對第三邊S3之側邊可在垂直投影方向Z上實質上對齊,意即彼此重疊,以提升畫素的開口率,並避免第一資料線DL1與第一畫素電極PE1之第二部分P2之間產生漏光。第二畫素電極PE2之第一部分P1的第二邊S2係與第一資料線DL1的第二側DLS2於垂直投影方向Z上可無間隙,且第二畫素電極PE2之第二邊S2與第二遮蔽電極SE2於垂直投影方向Z上不重疊。較佳地,第二畫素電極PE2之第二邊S2與第一資料線DL1面對第二邊S2之側邊可在垂直投影方向Z上實質上對齊,意即兩者可彼此重疊,以提升畫素的開口率,並避免第一資料線與第二畫素電極PE2之第一部分P1之間產生漏光。於變化實施例中,第一資料線DL1亦可與第二畫素電極PE2之第一部分P1部分重疊,及/或第一資料線DL1亦可與第一畫素電極PE1之第二部分P2部分重疊。Specifically, the pixel electrode PE is not rectangular, but the first portion P1 of the rectangle and the second portion P2 of the rectangle may be dislocated in the first direction D1 such that the first side S1 and the third side S3 are not in the same straight line. On the line, the second side S2 and the fourth side S4 are not on the same straight line. Moreover, the first side S1 is connected to the third side S3 through a turning edge, and the second side S2 is connected to the fourth side S4 through another turning edge. In the embodiment, the first portion P1 is disposed between the second portion P2 and the scan line SL. The first side S1 of the first portion P1 of the first pixel electrode PE1 is away from the first data line DL1 than the third side S3 of the second portion P2, and the first side S1 of the first portion P1 and the first data line DL1 are first. The vertical projection direction Z of the substrate Sub1 does not overlap, so that the first data line DL1 and the first side S1 of the first pixel electrode PE1 have a first slit ST1. That is, the spacing between the first side S1 and the first data line DL1 is greater than the spacing between the third side S3 and the first data line DL1. The fourth side S4 of the second portion P2 of the second pixel electrode PE2 is away from the first side line S2 of the first portion P1 away from the first data line DL1 facing the first side, and the fourth side S4 of the second portion P2 and the first data The line DL1 does not overlap in the vertical projection direction Z, so that there is a second slit ST2 between the first data line DL1 and the fourth side S4 of the second pixel electrode PE2. That is, the spacing between the fourth side S4 and the first data line DL1 is greater than the spacing between the second side S2 and the first data line DL1. In this embodiment, the third side S3 of the second portion P2 of the first pixel electrode PE1 and the first side DLS1 of the first data line DL1 may have no gap in the vertical projection direction Z, and the first pixel electrode PE1 The third side S3 and the first shielding electrode SE1 do not overlap in the vertical projection direction Z. Preferably, the third side S3 of the first pixel electrode PE1 and the side of the first data line DL1 facing the third side S3 are substantially aligned in the vertical projection direction Z, that is, overlap each other to enhance the pixel. The aperture ratio is such that light leakage between the first data line DL1 and the second portion P2 of the first pixel electrode PE1 is avoided. The second side S2 of the first portion P1 of the second pixel electrode PE2 and the second side DLS2 of the first data line DL1 may have no gap in the vertical projection direction Z, and the second side S2 of the second pixel electrode PE2 The second shielding electrodes SE2 do not overlap in the vertical projection direction Z. Preferably, the second side S2 of the second pixel electrode PE2 and the side of the first data line DL1 facing the second side S2 are substantially aligned in the vertical projection direction Z, that is, the two can overlap each other to The aperture ratio of the pixel is increased, and light leakage between the first data line and the first portion P1 of the second pixel electrode PE2 is avoided. In a variant embodiment, the first data line DL1 may also partially overlap the first portion P1 of the second pixel electrode PE2, and/or the first data line DL1 may also overlap with the second portion P2 of the first pixel electrode PE1. overlapping.

請參考第5圖,且一併參考第1圖至第3圖。第5圖繪示了本發明第一實施例之畫素陣列之共通電極與資料線之俯視示意圖。如第1圖至第3圖與第5圖所示,第一畫素結構PS1與第二畫素結構PS2之共通電極CE分別為第一共通電極CE1與第二共通電極CE2,第一共通電極CE1沿著第一資料線DL1設置,且第二共通電極CE2沿著第二資料線DL2設置。第一共通電極CE1與第二共通電極CE2具有相同結構,下文將以第一共通電極CE1與其對應之第一資料線DL1為例來做說明。第一共通電極CE1可包括彼此電性連接之第一子共通電極SCE1以及第二子共通電極SCE2。第一子共通電極SCE1與對應之第一資料線DL1的第一側DLS1於垂直投影方向Z上重疊設置,且第二子共通電極SCE2與對應之第一資料線DL1的第二側DLS2重疊設置。Please refer to Figure 5 and refer to Figures 1 to 3 together. FIG. 5 is a top plan view showing a common electrode and a data line of the pixel array of the first embodiment of the present invention. As shown in FIGS. 1 to 3 and 5, the common electrode CE of the first pixel structure PS1 and the second pixel structure PS2 are the first common electrode CE1 and the second common electrode CE2, respectively, and the first common electrode The CE1 is disposed along the first data line DL1, and the second common electrode CE2 is disposed along the second data line DL2. The first common electrode CE1 and the second common electrode CE2 have the same structure. Hereinafter, the first common electrode CE1 and its corresponding first data line DL1 will be described as an example. The first common electrode CE1 may include a first sub-common electrode SCE1 and a second sub-common electrode SCE2 electrically connected to each other. The first sub-common electrode SCE1 is overlapped with the first side DLS1 of the corresponding first data line DL1 in the vertical projection direction Z, and the second sub-common electrode SCE2 is overlapped with the second side DLS2 of the corresponding first data line DL1. .

值得說明的是,第一遮蔽電極SE1的第一條狀部SEP1與第一畫素電極PE1的第一邊S1於垂直投影方向Z上彼此重疊設置,且第一遮蔽電極SE1的第一條狀部SEP1與對應之第一資料線DL1的第一側DLS1之間具有一第三狹縫ST3。並且,第一子共通電極SCE1與第一資料線DL1的第一側DLS1以及第三狹縫ST3於垂直投影方向Z上重疊。藉此,第一條狀部SEP1與第一子共通電極SCE1不僅可用以遮蔽第一畫素電極PE1之第一部分P1與對應之第一資料線DL1之間的電容耦合效應,還可避免第一資料線DL1與第一畫素電極PE1的第一邊S1之間的第一狹縫ST1產生漏光,進而提高對比。精確地說,當液晶顯示面板在運作時,第一遮蔽電極SE1與第一共通電極CE1會施加共通電壓,因此第一資料線DL1傳遞訊號所產生的電場可受到第一遮蔽電極SE1與第一共通電極CE1的吸引而降低對第一畫素電極PE1的第一部分P1干擾,進而有效地遮蔽第一畫素電極PE1的第一部分P1與對應之第一資料線DL1之間的電容耦合效應。除此之外,由於第一遮蔽電極SE1、第一共通電極CE1與對向電極CTE係施加共通電壓,因此位於第一條狀部SEP1與第一子共通電極SCE1正上方以及第一條狀部SEP1與第一子共通電極SCE1之間之顯示介質DM中的液晶分子可受到共通電壓所產生的電場的控制而避免光線穿透,如此可避免第一資料線DL1與第一邊S1之間的第一狹縫ST1產生漏光,特別是在畫素呈現暗態時可有效地避免光線洩漏,以提升畫面的對比度。較佳地,第一子共通電極SCE1與第一遮蔽電極SE1之第一條狀部SEP1可共同將第一狹縫ST1遮蔽,也就是第一共通電極CE1之第一子共通電極SCE1於垂直投影方向Z上與第一遮蔽電極SE1之第一條狀部SEP1彼此重疊,以提升遮蔽漏光的效果,並降低第一畫素電極PE1與第一資料線DL1之間的電容耦合。同理,與第一畫素電極PE1具有相同結構之第二畫素電極PE2與第二資料線DL2之間的電容耦合亦可被降低。It should be noted that the first strip SEP1 of the first shielding electrode SE1 and the first side S1 of the first pixel electrode PE1 overlap each other in the vertical projection direction Z, and the first strip of the first shielding electrode SE1 The portion SEP1 has a third slit ST3 between the first side DLS1 of the corresponding first data line DL1. Further, the first sub-common electrode SCE1 overlaps with the first side DLS1 and the third slit ST3 of the first data line DL1 in the vertical projection direction Z. Thereby, the first strip portion SEP1 and the first sub-common electrode SCE1 can be used not only to shield the capacitive coupling effect between the first portion P1 of the first pixel electrode PE1 and the corresponding first data line DL1, but also avoid the first The first slit ST1 between the data line DL1 and the first side S1 of the first pixel electrode PE1 generates light leakage, thereby improving contrast. Precisely, when the liquid crystal display panel is in operation, the first shielding electrode SE1 and the first common electrode CE1 apply a common voltage, so the electric field generated by the first data line DL1 transmitting the signal can be received by the first shielding electrode SE1 and the first The attraction of the common electrode CE1 reduces interference with the first portion P1 of the first pixel electrode PE1, thereby effectively shielding the capacitive coupling effect between the first portion P1 of the first pixel electrode PE1 and the corresponding first data line DL1. In addition, since the first shielding electrode SE1, the first common electrode CE1 and the opposite electrode CTE are applied with a common voltage, they are located directly above the first strip portion SEP1 and the first sub-common electrode SCE1 and the first strip portion. The liquid crystal molecules in the display medium DM between the SEP1 and the first sub-common electrode SCE1 can be controlled by the electric field generated by the common voltage to avoid light penetration, so that the first data line DL1 and the first side S1 can be avoided. The first slit ST1 generates light leakage, and particularly prevents light leakage when the pixel is in a dark state, thereby improving the contrast of the picture. Preferably, the first sub-common electrode SCE1 and the first strip SEP1 of the first shielding electrode SE1 together shield the first slit ST1, that is, the first sub-common electrode SCE1 of the first common electrode CE1 is vertically projected. The first strips SEP1 of the first shielding electrode SE1 overlap each other in the direction Z to enhance the effect of shielding light leakage and reduce the capacitive coupling between the first pixel electrode PE1 and the first data line DL1. Similarly, the capacitive coupling between the second pixel electrode PE2 and the second data line DL2 having the same structure as the first pixel electrode PE1 can also be reduced.

同樣地,第二遮蔽電極SE2的第四條狀部SEP4與第二畫素電極PE2的第四邊S4於垂直投影方向Z上重疊設置,且第二遮蔽電極SE2的第四條狀部SEP4與對應之第一資料線DL1的第二側DLS2之間具有一第四狹縫ST4。並且,第二子共通電極SCE2與第一資料線DL1的第二側DLS2以及第四狹縫ST4於垂直投影方向Z上重疊。因此,第四條狀部SEP4與第二子共通電極SCE2不僅可用以遮蔽第二畫素電極PE2之第二部分P2與對應之第一資料線DL1之間的電容耦合效應,還可避免第一資料線DL1與第二畫素電極PE2之第四邊S4之間的第二狹縫ST2產生漏光,特別是在畫素呈現暗態時可有效地避免光線洩漏,進而提高畫面的對比。較佳地,第二子共通電極SCE2與第二遮蔽電極SE2之第四條狀部SEP4可共同將第二狹縫ST2遮蔽,也就是第一共通電極CE1之第二子共通電極SCE2於垂直投影方向Z上與第二遮蔽電極SE2之第四條狀部SEP4彼此重疊,以提升遮蔽漏光的效果,並降低第二畫素電極PE2與第一資料線DL1之間的電容耦合。同理,與第二畫素電極PE2具有相同結構之第一畫素電極PE1與第三資料線DL3之間的電容耦合亦可被降低。Similarly, the fourth strip portion SEP4 of the second mask electrode SE2 and the fourth side S4 of the second pixel electrode PE2 are overlapped in the vertical projection direction Z, and the fourth strip portion SEP4 of the second mask electrode SE2 is There is a fourth slit ST4 between the second side DLS2 of the corresponding first data line DL1. Further, the second sub-common electrode SCE2 overlaps with the second side DLS2 and the fourth slit ST4 of the first data line DL1 in the vertical projection direction Z. Therefore, the fourth strip portion SEP4 and the second sub-common electrode SCE2 can be used not only to shield the capacitive coupling effect between the second portion P2 of the second pixel electrode PE2 and the corresponding first data line DL1, but also avoid the first The second slit ST2 between the data line DL1 and the fourth side S4 of the second pixel electrode PE2 generates light leakage, which can effectively avoid light leakage especially when the pixel is in a dark state, thereby improving the contrast of the picture. Preferably, the second sub-common electrode SCE2 and the fourth strip SEP4 of the second shielding electrode SE2 can collectively shield the second slit ST2, that is, the second sub-common electrode SCE2 of the first common electrode CE1 is vertically projected. The fourth strips SEP4 of the second shielding electrode SE2 in the direction Z overlap each other to enhance the effect of shielding light leakage and reduce the capacitive coupling between the second pixel electrode PE2 and the first data line DL1. Similarly, the capacitive coupling between the first pixel electrode PE1 and the third data line DL3 having the same structure as the second pixel electrode PE2 can also be reduced.

另外,由於第一畫素電極PE1之第三邊S3與第一資料線DL1的第一側DLS1之間在垂直投影方向Z上可無間隙,以避免其間產生漏光,因此第二子共通電極SCE2與對應之第一資料線DL1的第一側DLS1於垂直投影方向Z上可不重疊設置。並且,由於第二畫素電極PE2之第二邊S2與第一資料線DL1的第二側DLS2之間在垂直投影方向Z上可無間隙,以避免其間產生漏光,因此第一子共通電極SCE1與對應之第一資料線DL1的第二側DLS2於垂直投影方向Z上可不重疊設置。In addition, since there is no gap between the third side S3 of the first pixel electrode PE1 and the first side DLS1 of the first data line DL1 in the vertical projection direction Z to avoid light leakage therebetween, the second sub-common electrode SCE2 The first side DLS1 of the corresponding first data line DL1 may not be overlapped in the vertical projection direction Z. Moreover, since there is no gap between the second side S2 of the second pixel electrode PE2 and the second side DLS2 of the first data line DL1 in the vertical projection direction Z to avoid light leakage therebetween, the first sub-common electrode SCE1 The second side DLS2 of the corresponding first data line DL1 may not be overlapped in the vertical projection direction Z.

於本實施例中,第一共通電極CE1可分別另包括一橋接部CEB,橫跨對應之第一資料線DL1,並連接於第一子共通電極SCE1與第二子共通電極SCE2之間,使第一子共通電極SCE1、第二子共通電極SCE2以及橋接部CEB構成另一彎折結構。更具體而言,第一子共通電極SCE1的一端除了可透過橋接部CEB與同一第一共通電極CE1之第二子共通電極SCE2連接之外,另一端還可與排列於同一第二方向D2上並相鄰之另一共通電極CE之第二子共通電極SCE2連接。並且,第一共通電極CE1與第二共通電極CE2可分別包括共通連接部CEC,使得第一共通電極CE1之第一子共通電極SCE1可透過共通連接部CEC與第二共通電極CE2之第一子共通電極SCE1電性連接,且第一共通電極CE1之第二子共通電極SCE2可透過另一共通連接部CEC與第二共通電極CE2之第二子共通電極SCE2電性連接。藉此,畫素陣列PA之共通電極CE可形成一網狀結構,且網狀結構具有複數個開口O,分別對應一個畫素結構PS。每個畫素電極PE設置於對應之開口O內。值得說明的是,本實施例之第一共通電極CE1係與第一畫素電極PE1以及第二畫素電極PE2可由同一圖案化透明導電層所構成,透過錯位設置之第一畫素電極PE1與第二畫素電極PE2,第一共通電極CE1可設置於第一畫素電極PE1與第二畫素電極PE2之間,並與第一畫素電極PE1與第二畫素電極PE2分隔開。也就是第一共通電極CE1之第一子共通電極SCE1與第二子共通電極SCE2不僅可在製程可容忍範圍內分別以一定間距與兩相鄰之第一畫素電極PE1與第二畫素電極PE2分隔開,還可透過橋接部CEB連接,使共通電極CE構成網狀結構,進而降低畫素陣列PA中共通電極CE的連接電阻。於另一變化實施例中,共通電極CE與畫素電極PE亦可由不同的透明導電層所構成。In this embodiment, the first common electrode CE1 may further include a bridge portion CEB spanning the corresponding first data line DL1 and connected between the first sub-common electrode SCE1 and the second sub-common electrode SCE2, so that The first sub-common electrode SCE1, the second sub-common electrode SCE2, and the bridge portion CEB constitute another bent structure. More specifically, one end of the first sub-common electrode SCE1 is connected to the second sub-common electrode SCE2 of the same first common electrode CE1 through the bridge portion CEB, and the other end may be arranged in the same second direction D2. And connected to the second sub-common electrode SCE2 of another common electrode CE adjacent thereto. The first common electrode CE1 and the second common electrode CE2 may respectively include a common connection portion CEC such that the first sub-common electrode SCE1 of the first common electrode CE1 can pass through the first connection of the common connection portion CEC and the second common electrode CE2. The common electrode SCE1 is electrically connected, and the second sub-common electrode SCE2 of the first common electrode CE1 is electrically connected to the second sub-common electrode SCE2 of the second common electrode CE2 through another common connection portion CEC. Thereby, the common electrode CE of the pixel array PA can form a mesh structure, and the mesh structure has a plurality of openings O corresponding to one pixel structure PS. Each of the pixel electrodes PE is disposed in the corresponding opening O. It should be noted that the first common electrode CE1 of the embodiment and the first pixel electrode PE1 and the second pixel electrode PE2 may be formed by the same patterned transparent conductive layer, and the first pixel electrode PE1 disposed through the misalignment is The second pixel electrode PE2, the first common electrode CE1 may be disposed between the first pixel electrode PE1 and the second pixel electrode PE2, and is spaced apart from the first pixel electrode PE1 and the second pixel electrode PE2. That is, the first sub-common electrode SCE1 and the second sub-common electrode SCE2 of the first common electrode CE1 can be separated from the two adjacent first pixel electrodes PE1 and the second pixel electrode at a certain interval within the tolerance range of the process. The PE2 is separated and can also be connected through the bridging portion CEB, so that the common electrode CE constitutes a mesh structure, thereby reducing the connection resistance of the common electrode CE in the pixel array PA. In another variant embodiment, the common electrode CE and the pixel electrode PE may also be composed of different transparent conductive layers.

於本實施例中,畫素電極PE可包括四配向區,且第一部分P1對應兩配向區,第二部分P2對應另兩配向區。下文以第一畫素結構PS1為例,但不限於此。具體請參考第6圖,第6圖繪示了本發明第一實施例之第一畫素結構之俯視示意圖。如第6圖所示,本實施例之第一畫素電極PE1之第一部分P1對應至少一第一配向區AR1,第二部分P2對應至少一第二配向區AR2。第一畫素電極PE1可包括一第一主幹電極ME1、複數條第一分支電極BE1以及複數條第二分支電極BE2,第一主幹電極ME1與第一連接部SEC1於垂直投影方向Z上重疊,且第一分支電極BE1與第二分支電極BE2分別設置於第一主幹電極ME1的兩側,以形成至少一第一配向區AR1與至少一第二配向區AR2。具體而言,第一主幹電極ME1沿著第一方向D1設置,且第一畫素電極PE1可另包括一第二主幹電極ME2,沿著第二方向D2設置,並與第一主幹電極ME1交錯。並且,第一分支電極BE1可區分為第一子分支電極SBE1以及第二子分支電極SBE2,第一子分支電極SBE1與第二子分支電極SBE2分別設置於第二主幹電極ME2的兩側,以形成兩個第一配向區AR1,且第一配向區AR1具有不同的配向方向。第二分支電極BE2可區分為第三子分支電極SBE3以及第四子分支電極SBE4,第三子分支電極SBE3與第四子分支電極SBE4分別設置於第二主幹電極ME2的兩側,以形成兩個第二配向區AR2,且第二配向區AR2具有不同的配向方向。第一子分支電極SBE1、第二子分支電極SBE2、第三子分支電極SBE3以及第四子分支電極SBE4可分別不平行於第一主幹電極ME1與第二主幹電極ME2。第一子分支電極SBE1、第二子分支電極SBE2、第三子分支電極SBE3以及第四子分支電極SBE4可與第一主幹電極ME1和第二主幹電極ME2形成米字形結構。舉例而言,第一子分支電極SBE1、第二子分支電極SBE2、第三子分支電極SBE3以及第四子分支電極SBE4的延伸方向可分別與第一主幹電極ME1的延伸方向具有夾角例如45度,但不限於此。於另一變化實施例中,第一畫素電極PE1可不包括第二主幹電極,而第一分支電極BE1彼此平行,第二分支電極BE2彼此平行,且第一分支電極BE1的延伸方向與第二分支電極BE2的延伸方向對稱於第一主幹電極ME1,使第一分支電極BE1與第二分支電極BE2分別形成單一第一配向區AR1與單一第二配向區AR2。值得一提的是,由於第一主幹電極ME1位於第一配向區AR1與第二配向區AR2之間,因此第一主幹電極ME1係對應畫素之暗區。本實施例之第一連接部SEC1係沿著第一主幹電極ME1設置,較佳與第一主幹電極ME1完全重疊,使得第一連接部SEC1可對應畫素之暗區設置,而不會影響畫素的顯示。In this embodiment, the pixel electrode PE may include four alignment regions, and the first portion P1 corresponds to the two alignment regions, and the second portion P2 corresponds to the other two alignment regions. The first pixel structure PS1 is exemplified below, but is not limited thereto. For details, please refer to FIG. 6. FIG. 6 is a schematic top view of the first pixel structure of the first embodiment of the present invention. As shown in FIG. 6, the first portion P1 of the first pixel electrode PE1 of the embodiment corresponds to at least one first alignment area AR1, and the second portion P2 corresponds to at least one second alignment area AR2. The first pixel electrode PE1 may include a first main electrode ME1, a plurality of first branch electrodes BE1, and a plurality of second branch electrodes BE2. The first main electrode ME1 overlaps with the first connecting portion SEC1 in the vertical projection direction Z. The first branch electrode BE1 and the second branch electrode BE2 are respectively disposed on two sides of the first trunk electrode ME1 to form at least one first alignment area AR1 and at least one second alignment area AR2. Specifically, the first main electrode ME1 is disposed along the first direction D1, and the first pixel electrode PE1 may further include a second main electrode ME2 disposed along the second direction D2 and interlaced with the first main electrode ME1. . In addition, the first branch electrode BE1 can be divided into a first sub-branch electrode SBE1 and a second sub-branch electrode SBE2, and the first sub-branch electrode SBE1 and the second sub-branch electrode SBE2 are respectively disposed on two sides of the second trunk electrode ME2, Two first alignment regions AR1 are formed, and the first alignment regions AR1 have different alignment directions. The second branch electrode BE2 can be divided into a third sub-branch electrode SBE3 and a fourth sub-branch electrode SBE4, and the third sub-branch electrode SBE3 and the fourth sub-branch electrode SBE4 are respectively disposed on two sides of the second main electrode ME2 to form two Two second alignment areas AR2, and the second alignment area AR2 have different alignment directions. The first sub-branch electrode SBE1, the second sub-branch electrode SBE2, the third sub-branch electrode SBE3, and the fourth sub-branch electrode SBE4 may not be parallel to the first main electrode ME1 and the second main electrode ME2, respectively. The first sub-branch electrode SBE1, the second sub-branch electrode SBE2, the third sub-branch electrode SBE3, and the fourth sub-branch electrode SBE4 may form a m-shaped structure with the first main electrode ME1 and the second main electrode ME2. For example, the extending directions of the first sub-branch electrode SBE1, the second sub-branch electrode SBE2, the third sub-branch electrode SBE3, and the fourth sub-branch electrode SBE4 may respectively be at an angle of, for example, 45 degrees with the extending direction of the first trunk electrode ME1. , but not limited to this. In another variant embodiment, the first pixel electrode PE1 may not include the second trunk electrode, and the first branch electrodes BE1 are parallel to each other, the second branch electrodes BE2 are parallel to each other, and the extending direction of the first branch electrode BE1 is the second The extending direction of the branch electrode BE2 is symmetric with respect to the first main electrode ME1, so that the first branch electrode BE1 and the second branch electrode BE2 form a single first alignment area AR1 and a single second alignment area AR2, respectively. It is worth mentioning that since the first main electrode ME1 is located between the first alignment area AR1 and the second alignment area AR2, the first main electrode ME1 corresponds to the dark area of the pixel. The first connecting portion SEC1 of the embodiment is disposed along the first main electrode ME1, preferably completely overlaps with the first main electrode ME1, so that the first connecting portion SEC1 can be set corresponding to the dark area of the pixel without affecting the drawing. The display of prime.

值得說明的是,於本實施例之畫素陣列PA的設計中,位於第一資料線DL1之第一側DLS1與第二側DLS2之第一畫素電極PE1與第二畫素電極PE2分別以第二部分P2以及第一部分P1與第一資料線DL1重疊設置,而第一畫素電極PE1之第一部分P1以及第二畫素電極PE2之第二部分P2則與第一資料線DL1之間具有狹縫,如此可在第一資料線DL1與第一畫素電極PE1或第二畫素電極PE2之間的耦合電容在容許的範圍下,提升畫素陣列PA的畫素開口率。並且,透過具有彎折結構之第一遮蔽電極SE1與第二遮蔽電極SE2以及第一子共通電極SCE1與第二子共通電極SCE2不僅可遮蔽位於第一資料線DL1之第一側DLS1之第一狹縫ST1與第二側DLS2之第二狹縫ST2,還可降低第一資料線DL1與第一畫素電極PE1之第一部分P1以及第二畫素電極PE2之第二部分P2之間的耦合電容。It should be noted that, in the design of the pixel array PA of the embodiment, the first pixel electrode PE1 and the second pixel electrode PE2 of the first side DLS1 and the second side DLS2 of the first data line DL1 are respectively The second portion P2 and the first portion P1 are disposed to overlap with the first data line DL1, and the first portion P1 of the first pixel electrode PE1 and the second portion P2 of the second pixel electrode PE2 are disposed between the first data line DL1 and the first data line DL1. The slit is such that the coupling capacitance between the first data line DL1 and the first pixel electrode PE1 or the second pixel electrode PE2 increases the pixel aperture ratio of the pixel array PA within an allowable range. Moreover, the first shielding electrode SE1 and the second shielding electrode SE2 having the bent structure and the first sub-common electrode SCE1 and the second sub-common electrode SCE2 can shield not only the first side of the first side DLS1 of the first data line DL1. The slit ST1 and the second slit ST2 of the second side DLS2 can also reduce the coupling between the first data line DL1 and the first portion P1 of the first pixel electrode PE1 and the second portion P2 of the second pixel electrode PE2. capacitance.

本發明之畫素結構與畫素陣列並不以上述實施例為限。下文將繼續揭示本發明之其它實施例或變化實施例,然為了簡化說明並突顯各實施例或變化實施例之間的差異,下文中使用相同標號標注相同元件,並不再對重覆部分作贅述。The pixel structure and pixel array of the present invention are not limited to the above embodiments. In the following, other embodiments or variations of the present invention will be disclosed. However, in order to simplify the description and highlight the differences between the various embodiments or the modified embodiments, the same reference numerals are used to denote the same elements, and no more Narration.

請參考第7圖與第8圖,第7圖與第8圖分別繪示了本發明第一實施例之另一變化實施例之畫素結構對應第1圖之剖線A-A’與B-B’的剖面示意圖。如第7圖與第8圖所示,本實施例所提供之畫素結構PS’之第一共通電極CE1於垂直投影方向Z上可不與第一遮蔽電極SE1重疊設置。具體而言,第一共通電極CE1之第一子共通電極SCE1可不與第一遮蔽電極SE1之第一條狀部SEP1重疊設置,且兩者之間於垂直投影方向Z上可具有一第五狹縫ST5。第一共通電極CE1之第二子共通電極SCE2可不與第二遮蔽電極SE2之第四條狀部SEP4重疊設置,且兩者之間於垂直投影方向Z上可具有一第六狹縫ST6。值得說明的是,由於第一遮蔽電極SE1、第一共通電極CE1與對向電極CTE係施加共通電壓,因此不僅第一遮蔽電極SE1之第一條狀部SEP1、第二遮蔽電極SE2之第四條狀部SEP4、第一子共通電極SCE1與第二子共通電極SCE2之正上方的液晶分子可受到共通電壓所產生的電場的控制而避免光線穿透,並且位於第一遮蔽電極SE1之第一條狀部SEP1與第一子共通電極SCE1之間以及位於第二遮蔽電極SE2之第四條狀部SEP4與第二子共通電極SCE2之間的液晶分子亦可受到此電場的控制而避免光線穿透,進而避免第一狹縫ST1與第二狹縫ST2產生漏光。Please refer to FIG. 7 and FIG. 8 . FIG. 7 and FIG. 8 respectively illustrate the pixel structure of the other embodiment of the first embodiment of the present invention corresponding to the line A-A′ and B of FIG. 1 . Schematic diagram of the profile of -B'. As shown in Fig. 7 and Fig. 8, the first common electrode CE1 of the pixel structure PS' provided in this embodiment may not overlap with the first shield electrode SE1 in the vertical projection direction Z. Specifically, the first sub-common electrode SCE1 of the first common electrode CE1 may not overlap with the first strip portion SEP1 of the first shielding electrode SE1, and may have a fifth narrowness between the two in the vertical projection direction Z. Sew ST5. The second sub-common electrode SCE2 of the first common electrode CE1 may not overlap with the fourth strip portion SEP4 of the second shielding electrode SE2, and may have a sixth slit ST6 in the vertical projection direction Z therebetween. It is to be noted that since the first shielding electrode SE1, the first common electrode CE1 and the opposite electrode CTE are applied with a common voltage, not only the first strip portion SEP1 of the first mask electrode SE1 but also the fourth mask electrode SE2 is fourth. The liquid crystal molecules directly above the strip portion SEP4, the first sub-common electrode SCE1 and the second sub-common electrode SCE2 can be controlled by the electric field generated by the common voltage to avoid light penetration, and are located at the first of the first shielding electrode SE1. The liquid crystal molecules between the strip portion SEP1 and the first sub-common electrode SCE1 and between the fourth strip portion SEP4 and the second sub-common electrode SCE2 of the second mask electrode SE2 can also be controlled by the electric field to prevent light from being worn. Through, the first slit ST1 and the second slit ST2 are prevented from leaking light.

請參考第9圖,第9圖繪示了本發明第二實施例之畫素陣列對應第1圖之剖線A-A’的剖面示意圖。如第9圖所示,相較於第一實施例,本實施例所提供的畫素結構PS”的彩色濾光片CF’係設置於畫素電極PE與第一基板Sub1之間,即所謂彩色濾光片於陣列上(color filter on array, COA)類型之畫素結構。舉例而言,彩色濾光片CF’可設置於畫素電極PE與絕緣層IN2之間。Please refer to FIG. 9. FIG. 9 is a cross-sectional view showing the pixel array of the second embodiment of the present invention corresponding to the line A-A' of FIG. 1. As shown in FIG. 9, the color filter CF' of the pixel structure PS" provided in this embodiment is disposed between the pixel electrode PE and the first substrate Sub1 as compared with the first embodiment. The color filter is a pixel structure of a color filter on array (COA) type. For example, the color filter CF' may be disposed between the pixel electrode PE and the insulating layer IN2.

請參考第10圖,第10圖繪示了本發明第三實施例之畫素陣列的俯視示意圖。如第10圖所示,本實施例所提供的畫素陣列PA’更包括一第三畫素結構PS3,其包括第三子畫素SP3,設置於第一基板(圖未示)上。第三畫素結構PS3與第一畫素結構PS1排列於同一行(即排列於第二方向D2上)且彼此相鄰。因此,第三子畫素SP3與第一子畫素SP1分別設置於掃描線SL的兩側。於本實施例中,第三子畫素SP3包括一第三畫素電極PE3以及一第三遮蔽電極SE3,並且第一遮蔽電極SE1與第三遮蔽電極SE3具有相同的形狀圖案。也就是說,位於兩相鄰列之畫素結構PS之遮蔽電極SE可具有相同的形狀圖案。本實施例之第一畫素結構PS1與第三畫素結構PS3可與上述第一實施例之第一畫素結構相同,因此不多贅述。Please refer to FIG. 10, which illustrates a top view of a pixel array according to a third embodiment of the present invention. As shown in FIG. 10, the pixel array PA' provided in this embodiment further includes a third pixel structure PS3, which includes a third sub-pixel SP3 disposed on a first substrate (not shown). The third pixel structure PS3 is arranged in the same row as the first pixel structure PS1 (ie, arranged in the second direction D2) and adjacent to each other. Therefore, the third sub-pixel SP3 and the first sub-pixel SP1 are respectively disposed on both sides of the scanning line SL. In the embodiment, the third sub-pixel SP3 includes a third pixel electrode PE3 and a third shielding electrode SE3, and the first shielding electrode SE1 and the third shielding electrode SE3 have the same shape pattern. That is to say, the mask electrodes SE of the pixel structures PS located in two adjacent columns may have the same shape pattern. The first pixel structure PS1 and the third pixel structure PS3 of the present embodiment may be the same as the first pixel structure of the first embodiment described above, and therefore will not be described again.

請參考第11圖,第11圖繪示了本發明第四實施例之畫素陣列的俯視示意圖。如第11圖所示,相較於第三實施例,本實施例所提供的畫素陣列PA”之第一遮蔽電極SE1與第三遮蔽電極SE3’的形狀圖案對稱於掃描線SL。具體而言,本實施例之第三畫素結構PS3’的第三遮蔽電極SE3’可包括一第五條狀部SEP1’、一第六條狀部SEP2’、一第一連接部SEC1以及一第三連接部SEC3。第三遮蔽電極SE3’之第五條狀部SEP1’與第六條狀部SEP2’係分別沿著第二方向D2與朝相反方向延伸。第三遮蔽電極SE3’的形狀圖案與第一遮蔽電極SE1的形狀圖案對稱於掃描線SL。於本實施例中,第五條狀部SEP1’係連接於第一連接部SEC1與第三連接部SEC3之間。並且,第三畫素電極PE3’之第一部分P1’的第一邊S1’較第二部分P2’的第三邊S3’鄰近第一資料線DL1,且第二部分P2’的第四邊S4’較第一部分P1’的第二邊S2’鄰近第三資料線DL3。因此,第三遮蔽電極SE3’的第五條狀部SEP1’與第三畫素電極PE3’的第二邊S2’於垂直投影方向上彼此重疊設置,且第三遮蔽電極SE3’的第六條狀部SEP2’與第三畫素電極PE3’的第三邊S3’於垂直投影方向上彼此重疊設置。另外,第三畫素結構PS3’之第一子共通電極SCE1’係與第一資料線DL1的第二側DLS2於垂直投影方向上重疊設置,且第二子共通電極SCE2’與第一資料線DL1的第一側DLS1重疊設置。Please refer to FIG. 11. FIG. 11 is a schematic top view of a pixel array according to a fourth embodiment of the present invention. As shown in FIG. 11, the shape pattern of the first shielding electrode SE1 and the third shielding electrode SE3' of the pixel array PA" provided in this embodiment is symmetric with respect to the scanning line SL, as compared with the third embodiment. The third shielding electrode SE3' of the third pixel structure PS3' of the embodiment may include a fifth strip portion SEP1', a sixth strip portion SEP2', a first connecting portion SEC1, and a third portion. The connecting portion SEC3. The fifth strip portion SEP1' and the sixth strip portion SEP2' of the third shielding electrode SE3' extend in opposite directions along the second direction D2, respectively. The shape pattern of the third shielding electrode SE3' is The shape pattern of the first shielding electrode SE1 is symmetric with respect to the scanning line SL. In the present embodiment, the fifth strip portion SEP1' is connected between the first connecting portion SEC1 and the third connecting portion SEC3. The first side S1' of the first portion P1' of the electrode PE3' is closer to the first data line DL1 than the third side S3' of the second portion P2', and the fourth side S4' of the second portion P2' is closer to the first portion P1' than The second side S2' is adjacent to the third data line DL3. Therefore, the fifth strip portion SE of the third shielding electrode SE3' P1' and the second side S2' of the third pixel electrode PE3' are disposed to overlap each other in the vertical projection direction, and the sixth strip portion SEP2' of the third mask electrode SE3' and the third pixel electrode PE3' The three sides S3' are disposed to overlap each other in the vertical projection direction. In addition, the first sub-common electrode SCE1' of the third pixel structure PS3' is overlapped with the second side DLS2 of the first data line DL1 in the vertical projection direction. The second sub-common electrode SCE2' is disposed to overlap with the first side DLS1 of the first data line DL1.

綜上所述,於本發明之畫素陣列中,位於第一資料線之第一側與第二側之第一畫素電極與第二畫素電極分別以第一畫素電極的第二部分以及第二畫素電極的第一部分與第一資料線重疊設置,而第一畫素電極的第一部分以及第二畫素電極的第二部分則與第一資料線之間具有狹縫,如此可在第一資料線與第一畫素電極或第二畫素電極之間的耦合電容在容許的範圍下,提升畫素陣列的畫素開口率。並且,透過具有彎折結構之第一遮蔽電極與第二遮蔽電極以及第一子共通電極與第二子共通電極不僅可遮蔽位於第一資料線之第一側之第一狹縫與第二側之第二狹縫,還可降低第一資料線與第一畫素電極之第一部分以及第二畫素電極之第二部分之間的耦合電容。   以上所述僅為本發明之較佳實施例,凡依本發明申請專利範圍所做之均等變化與修飾,皆應屬本發明之涵蓋範圍。In summary, in the pixel array of the present invention, the first pixel electrode and the second pixel electrode on the first side and the second side of the first data line are respectively the second portion of the first pixel electrode. And the first portion of the second pixel electrode is disposed to overlap with the first data line, and the first portion of the first pixel electrode and the second portion of the second pixel electrode have a slit between the first data line and the first data line. The coupling capacitance between the first data line and the first pixel electrode or the second pixel electrode increases the pixel aperture ratio of the pixel array within an allowable range. Moreover, the first shielding electrode and the second shielding electrode having the bent structure and the first sub-common electrode and the second sub-common electrode can shield not only the first slit and the second side of the first side of the first data line The second slit can also reduce the coupling capacitance between the first data line and the first portion of the first pixel electrode and the second portion of the second pixel electrode. The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

AD‧‧‧主動元件 AD‧‧‧ active components

AR1‧‧‧第一配向區 AR1‧‧‧ first alignment area

AR2‧‧‧第二配向區 AR2‧‧‧Second Alignment Area

BE1‧‧‧第一分支電極 BE1‧‧‧ first branch electrode

BE2‧‧‧第二分支電極 BE2‧‧‧Second branch electrode

BM‧‧‧黑色矩陣 BM‧‧‧ Black Matrix

CE、CE’‧‧‧彩色濾光片 CE, CE’‧‧‧ color filters

CE‧‧‧共通電極 CE‧‧‧Common electrode

CE1‧‧‧第一共通電極 CE1‧‧‧first common electrode

CE2‧‧‧第二共通電極 CE2‧‧‧Second common electrode

CTE‧‧‧對向電極 CTE‧‧‧ opposite electrode

CEB‧‧‧橋接部 CEB‧‧‧Bridge

CEC‧‧‧共通連接部 CEC‧‧‧Common Connection

D1‧‧‧第一方向 D1‧‧‧ first direction

D2‧‧‧第二方向 D2‧‧‧ second direction

DL‧‧‧資料線 DL‧‧‧ data line

DL1‧‧‧第一資料線 DL1‧‧‧ first data line

DL2‧‧‧第二資料線 DL2‧‧‧ second data line

DL3‧‧‧第三資料線 DL3‧‧‧ third data line

DLS1‧‧‧第一側 DLS1‧‧‧ first side

DLS2‧‧‧第二側 DLS2‧‧‧ second side

DM‧‧‧顯示介質 DM‧‧‧ display media

IN1、IN2‧‧‧絕緣層 IN1, IN2‧‧‧ insulation

ME1‧‧‧第一主幹電極 ME1‧‧‧first main electrode

ME2‧‧‧第二主幹電極 ME2‧‧‧Second main electrode

P1、P1’‧‧‧第一部分 P1, P1’‧‧‧ Part 1

P2、P2’‧‧‧第二部分 P2, P2’‧‧‧ Part II

PA、PA’、PA”‧‧‧畫素陣列 PA, PA', PA" ‧ ‧ pixel array

PS、PS’、PS”‧‧‧畫素結構 PS, PS', PS" ‧ ‧ pixel structure

PS1‧‧‧第一畫素結構 PS1‧‧‧ first pixel structure

PS2‧‧‧第二畫素結構 PS2‧‧‧second pixel structure

PS3、PS3’‧‧‧第三畫素結構 PS3, PS3'‧‧‧ third pixel structure

PE‧‧‧畫素電極 PE‧‧‧ pixel electrode

PE1‧‧‧第一畫素電極 PE1‧‧‧ first pixel electrode

PE2‧‧‧第二畫素電極 PE2‧‧‧second pixel electrode

PE3、PE3’‧‧‧第三畫素電極 PE3, PE3'‧‧‧ third pixel electrode

Sub1‧‧‧第一基板 Sub1‧‧‧ first substrate

Sub2‧‧‧第二基板 Sub2‧‧‧second substrate

SP‧‧‧子畫素 SP‧‧‧Subpixel

SP1‧‧‧第一子畫素 SP1‧‧‧ first sub-pixel

SP2‧‧‧第二子畫素 SP2‧‧‧Second sub-pixel

SP3、SP3’‧‧‧第三子畫素 SP3, SP3’‧‧‧ third sub-pixel

SL‧‧‧掃描線 SL‧‧‧ scan line

S1、S1’‧‧‧第一邊 S1, S1’‧‧‧ first side

S2、S2’‧‧‧第二邊 S2, S2’‧‧‧ second side

S3、S3’‧‧‧第三邊 S3, S3’‧‧‧ third side

S4、S4’‧‧‧第四邊 S4, S4’‧‧‧ fourth side

SE‧‧‧遮蔽電極 SE‧‧‧shading electrode

SE1‧‧‧第一遮蔽電極 SE1‧‧‧first shielding electrode

SE2‧‧‧第二遮蔽電極 SE2‧‧‧second shielding electrode

SE3、SE3’‧‧‧第三遮蔽電極 SE3, SE3'‧‧‧ third shielding electrode

SEP1‧‧‧第一條狀部 SEP1‧‧‧ first article

SEP2‧‧‧第二條狀部 SEP2‧‧‧Second Section

SEP3‧‧‧第三條狀部 SEP3‧‧‧ third section

SEP4‧‧‧第四條狀部 SEP4‧‧‧Article 4

SEP1’‧‧‧第五條狀部 SEP1’‧‧‧Article 5

SEP2’‧‧‧第六條狀部 SEP2’‧‧‧Article 6

SEC1‧‧‧第一連接部 SEC1‧‧‧First Connection

SEC2‧‧‧第二連接部 SEC2‧‧‧Second connection

SEC3‧‧‧第三連接部 SEC3‧‧‧ Third Connection

ST1‧‧‧第一狹縫 ST1‧‧‧first slit

ST2‧‧‧第二狹縫 ST2‧‧‧Second slit

ST3‧‧‧第三狹縫 ST3‧‧‧ third slit

ST4‧‧‧第四狹縫 ST4‧‧‧ fourth slit

ST5‧‧‧第五狹縫 ST5‧‧‧ fifth slit

ST6‧‧‧第六狹縫 ST6‧‧‧ sixth slit

SBE1‧‧‧第一子分支電極 SBE1‧‧‧ first sub-branch electrode

SBE2‧‧‧第二子分支電極 SBE2‧‧‧Second sub-branch electrode

SBE3‧‧‧第三子分支電極 SBE3‧‧‧ third sub-branch electrode

SBE4‧‧‧第四子分支電極 SBE4‧‧‧ fourth sub-branch electrode

SCE1、SCE1’‧‧‧第一子共通電極 SCE1, SCE1'‧‧‧ first sub-common electrode

SCE2、SCE2’‧‧‧第二子共通電極 SCE2, SCE2'‧‧‧ second sub-common electrode

O‧‧‧開口 O‧‧‧ openings

Z‧‧‧垂直投影方向 Z‧‧‧Vertical projection direction

D‧‧‧汲極 D‧‧‧汲

G‧‧‧閘極 G‧‧‧ gate

S‧‧‧源極 S‧‧‧ source

第1圖繪示了本發明第一實施例之畫素陣列的俯視示意圖。 第2圖繪示了沿著第1圖剖線A-A’之剖面示意圖。 第3圖繪示了沿著第1圖剖線B-B’之剖面示意圖。 第4圖繪示了本發明第一實施例之畫素陣列之資料線、掃描線與子畫素之俯視示意圖。 第5圖繪示了本發明第一實施例之畫素陣列之共通電極與資料線之俯視示意圖。 第6圖繪示了本發明第一實施例之畫素結構之俯視示意圖。 第7圖與第8圖繪示了本發明第一實施例之另一變化實施例之畫素陣列分別對應剖線A-A’與B-B’的剖面示意圖。 第9圖繪示了本發明第二實施例之畫素陣列對應剖線A-A’的剖面示意圖。 第10圖繪示了本發明第三實施例之畫素陣列的俯視示意圖。 第11圖繪示了本發明第四實施例之畫素陣列的俯視示意圖。FIG. 1 is a schematic top plan view of a pixel array according to a first embodiment of the present invention. Fig. 2 is a schematic cross-sectional view taken along line A-A' of Fig. 1. Fig. 3 is a schematic cross-sectional view taken along line B-B' of Fig. 1. 4 is a top plan view showing a data line, a scan line, and a sub-pixel of the pixel array of the first embodiment of the present invention. FIG. 5 is a top plan view showing a common electrode and a data line of the pixel array of the first embodiment of the present invention. Fig. 6 is a top plan view showing the pixel structure of the first embodiment of the present invention. Fig. 7 and Fig. 8 are schematic cross-sectional views showing the pixel arrays according to another variation of the first embodiment of the present invention corresponding to the cross-sectional lines A-A' and B-B', respectively. Fig. 9 is a cross-sectional view showing the pixel array corresponding to the line A-A' of the second embodiment of the present invention. Figure 10 is a top plan view showing a pixel array of a third embodiment of the present invention. 11 is a top plan view showing a pixel array of a fourth embodiment of the present invention.

AD‧‧‧主動元件 AD‧‧‧ active components

CE‧‧‧共通電極 CE‧‧‧Common electrode

CE1‧‧‧第一共通電極 CE1‧‧‧first common electrode

CE2‧‧‧第二共通電極 CE2‧‧‧Second common electrode

D1‧‧‧第一方向 D1‧‧‧ first direction

D2‧‧‧第二方向 D2‧‧‧ second direction

DL‧‧‧資料線 DL‧‧‧ data line

DL1‧‧‧第一資料線 DL1‧‧‧ first data line

DL2‧‧‧第二資料線 DL2‧‧‧ second data line

DL3‧‧‧第三資料線 DL3‧‧‧ third data line

PA‧‧‧畫素陣列 PA‧‧‧ pixel array

PS‧‧‧畫素結構 PS‧‧‧ pixel structure

PS1‧‧‧第一畫素結構 PS1‧‧‧ first pixel structure

PS2‧‧‧第二畫素結構 PS2‧‧‧second pixel structure

PE‧‧‧畫素電極 PE‧‧‧ pixel electrode

PE1‧‧‧第一畫素電極 PE1‧‧‧ first pixel electrode

PE2‧‧‧第二畫素電極 PE2‧‧‧second pixel electrode

SP‧‧‧子畫素 SP‧‧‧Subpixel

SP1‧‧‧第一子畫素 SP1‧‧‧ first sub-pixel

SP2‧‧‧第二子畫素 SP2‧‧‧Second sub-pixel

SL‧‧‧掃描線 SL‧‧‧ scan line

S1‧‧‧第一邊 S1‧‧‧ first side

S2‧‧‧第二邊 S2‧‧‧ second side

S3‧‧‧第三邊 S3‧‧‧ third side

S4‧‧‧第四邊 S4‧‧‧ fourth side

SE‧‧‧遮蔽電極 SE‧‧‧shading electrode

SE1‧‧‧第一遮蔽電極 SE1‧‧‧first shielding electrode

SE2‧‧‧第二遮蔽電極 SE2‧‧‧second shielding electrode

D‧‧‧汲極 D‧‧‧汲

G‧‧‧閘極 G‧‧‧ gate

S‧‧‧源極 S‧‧‧ source

Claims (21)

一種畫素陣列,包括:一基板;一第一子畫素,設置於該基板上,其中該第一子畫素包含一第一畫素電極以及一第一遮蔽電極;一第二子畫素,設置於該基板上,並與該第一子畫素彼此相鄰,其中該第二子畫素包含一第二畫素電極以及一第二遮蔽電極;一第一資料線,位於該第一子畫素與該第二子畫素之間,其中該第一資料線沿其延伸方向上具有彼此相對的一第一側與一第二側,該第一畫素電極鄰近該第一資料線的該第一側包括一第一邊與連接該第一邊的一第三邊,該第二畫素電極鄰近該第一資料線的該第二側包括一第二邊與連接該第二邊的一第四邊,該第一畫素電極的該第一邊與該第一資料線之間具有一第一狹縫,該第二畫素電極的該第四邊與該第一資料線之間具有一第二狹縫,該第一畫素電極的該第三邊與該第一資料線彼此重疊,且該第二畫素電極的該第二邊與該第一資料線彼此重疊;以及一共通電極,沿著該第一資料線設置,該共通電極包含彼此電性連接的一第一子共通電極以及一第二子共通電極,其中該第一子共通電極和該第一遮蔽電極係與該第一狹縫重疊設置,以及該第二子共通電極和該第二遮蔽電極係與該第二狹縫遮蔽重疊設置。 A pixel array includes: a substrate; a first sub-pixel disposed on the substrate, wherein the first sub-pixel comprises a first pixel electrode and a first shielding electrode; and a second sub-pixel And disposed on the substrate and adjacent to the first sub-pixels, wherein the second sub-pixel comprises a second pixel electrode and a second shielding electrode; a first data line is located at the first Between the sub-pixel and the second sub-pixel, wherein the first data line has a first side and a second side opposite to each other along the extending direction thereof, the first pixel electrode is adjacent to the first data line The first side includes a first side and a third side connected to the first side, and the second side of the second pixel electrode adjacent to the first data line includes a second side and connects the second side a fourth side, the first side of the first pixel electrode and the first data line have a first slit, the fourth side of the second pixel electrode and the first data line Having a second slit therebetween, the third side of the first pixel electrode and the first data line overlap each other, and the second drawing The second side of the electrode and the first data line overlap each other; and a common electrode is disposed along the first data line, the common electrode includes a first sub-common electrode electrically connected to each other and a second sub-common The electrode, wherein the first sub-common electrode and the first shielding electrode are overlapped with the first slit, and the second sub-common electrode and the second shielding electrode are overlapped with the second slit mask. 如請求項1所述的畫素陣列,其中該第一子共通電極與該第一資料線的第一側重疊設置,以及該第二子共通電極與該第一資料線的第二側重疊設置。 The pixel array of claim 1, wherein the first sub-common electrode is disposed to overlap with a first side of the first data line, and the second sub-common electrode is overlapped with a second side of the first data line . 如請求項1所述的畫素陣列,其中:該第一遮蔽電極包括一第一條狀部、一第二條狀部以及一第一連接部,該第一連接部的兩端分別與該第一條狀部和該第二條狀部連接,藉此該第一連接部與該第一條狀部和該第二條狀部分別形成一彎折結構;以及該第二遮蔽電極包括一第三條狀部、一第四條狀部以及一第二連接部,該第二連接部的兩端分別與該第三條狀部和該第四條狀部連接,藉此該第二連接部與該第三條狀部和該第四條狀部分別形成一彎折結構。 The pixel array of claim 1, wherein the first shielding electrode comprises a first strip portion, a second strip portion and a first connecting portion, and the two ends of the first connecting portion respectively The first strip portion and the second strip portion are connected, wherein the first connecting portion and the first strip portion and the second strip portion respectively form a bent structure; and the second shielding electrode comprises a a third strip portion, a fourth strip portion and a second connecting portion, wherein the two ends of the second connecting portion are respectively connected to the third strip portion and the fourth strip portion, whereby the second connection The portion and the third strip portion and the fourth strip portion respectively form a bent structure. 如請求項3所述的畫素陣列,其中於該基板的垂直投影方向上,該第一邊與該第一條狀部彼此重疊,且該第四邊與該第四條狀部彼此重疊。 The pixel array of claim 3, wherein the first side and the first strip overlap each other in a vertical projection direction of the substrate, and the fourth side and the fourth strip overlap each other. 如請求項3所述的畫素陣列,其中:該第一子共通電極於該基板的垂直投影方向上與該第一資料線的第一側以及該第一條狀部彼此重疊;以及該第二子共通電極於該基板的垂直投影方向上與該第一資料線的第二側以及該第四條狀部彼此重疊。 The pixel array of claim 3, wherein: the first sub-common electrode overlaps with the first side of the first data line and the first strip in a vertical projection direction of the substrate; and the first The two sub-common electrodes overlap the second side of the first data line and the fourth strip in a vertical projection direction of the substrate. 如請求項1所述的畫素陣列,其中該共通電極另包括一橋接部,橫跨該第一資料線以連接該第一子共通電極與該第二子共通電極,並且於該基板的垂直投影方向上,該第一子共通電極不與該第一資料線的第二側重疊以及該第二子共通電極不與該第一資料線的第一側重疊。 The pixel array of claim 1, wherein the common electrode further comprises a bridge portion spanning the first data line to connect the first sub-common electrode and the second sub-common electrode, and perpendicular to the substrate In the projection direction, the first sub-common electrode does not overlap with the second side of the first data line and the second sub-common electrode does not overlap with the first side of the first data line. 如請求項1所述的畫素陣列,更包括:一第二資料線,其中該第二畫素電極設置於該第一資料線與該第二資料線之 間;一掃描線,與該第一資料線和該第二資料線交錯設置;以及一主動元件,與該掃描線、該第一資料線以及該第一畫素電極電性連接。 The pixel array of claim 1, further comprising: a second data line, wherein the second pixel electrode is disposed on the first data line and the second data line a scan line interleaved with the first data line and the second data line; and an active component electrically connected to the scan line, the first data line, and the first pixel electrode. 如請求項7所述的畫素陣列,更包含一第三子畫素,設置於該基板上,其中該第三子畫素與該第一子畫素分別設置於該掃描線的兩側,該第三子畫素包含一第三畫素電極與一第三遮蔽電極,並且該第一遮蔽電極與該第三遮蔽電極具有相同的形狀圖案。 The pixel array of claim 7, further comprising a third sub-pixel disposed on the substrate, wherein the third sub-pixel and the first sub-pixel are respectively disposed on two sides of the scan line, The third sub-pixel includes a third pixel electrode and a third shielding electrode, and the first shielding electrode and the third shielding electrode have the same shape pattern. 如請求項7所述的畫素陣列,更包含一第三子畫素,設置於該基板上,其中該第三子畫素與該第一子畫素分別設置於該掃描線的兩側,該第三子畫素包含一第三畫素電極與一第三遮蔽電極,並且該第一遮蔽電極的形狀圖案與該第二遮蔽電極的形狀圖案對稱於該掃描線。 The pixel array of claim 7, further comprising a third sub-pixel disposed on the substrate, wherein the third sub-pixel and the first sub-pixel are respectively disposed on two sides of the scan line, The third sub-pixel includes a third pixel electrode and a third shielding electrode, and the shape pattern of the first shielding electrode and the shape pattern of the second shielding electrode are symmetric to the scanning line. 一種畫素結構,包括:一第一基板;一掃描線,設置於該第一基板上;一資料線,與該掃描線交錯設置,其中該資料線沿其延伸方向上具有彼此相對的一第一側與一第二側;一主動元件,與該掃描線和該資料線電性連接;一遮蔽電極,設置於該第一基板上,該遮蔽電極包括一第一條狀部、一第二條狀部以及一第一連接部,其中該第一連接部的兩端分別與該第一條狀部和該第二條狀部連接,藉此該第一連接部與該第一條狀部和該第二條狀部分別形成一彎折結構; 一畫素電極,與該主動元件電性連接,該畫素電極包括一第一部分與一第二部分,分別設置於該第一連接部的兩側,該第一部分具有彼此相對的一第一邊與一第二邊,該第二部分具有彼此相對的一第三邊與一第四邊,該第一邊連接該第三邊,該第二邊連接該第四邊,其中該第一條狀部與該畫素電極的第一邊重疊設置,該第二條狀部與該畫素電極的第四邊重疊設置,並且該資料線與該畫素電極的第三邊之間無狹縫;以及一共通電極,沿著該資料線設置,其中該共通電極包含彼此電性連接的一第一子共通電極以及一第二子共通電極,該第一子共通電極與該資料線的第一側重疊設置,以及該第二子共通電極與該資料線的第二側重疊設置。 A pixel structure includes: a first substrate; a scan line disposed on the first substrate; a data line interlaced with the scan line, wherein the data line has a first side opposite to each other along a direction in which the data line extends a first component and a second side; an active component electrically connected to the scan line and the data line; a shielding electrode disposed on the first substrate, the shielding electrode comprising a first strip, a second a strip portion and a first connecting portion, wherein two ends of the first connecting portion are respectively connected to the first strip portion and the second strip portion, whereby the first connecting portion and the first strip portion Forming a bent structure with the second strip; a pixel electrode electrically connected to the active component, the pixel electrode includes a first portion and a second portion respectively disposed on two sides of the first connecting portion, the first portion having a first side opposite to each other And a second side having a third side and a fourth side opposite to each other, the first side connecting the third side, the second side connecting the fourth side, wherein the first strip is The portion is overlapped with the first side of the pixel electrode, the second strip portion is disposed to overlap with the fourth side of the pixel electrode, and there is no slit between the data line and the third side of the pixel electrode; And a common electrode disposed along the data line, wherein the common electrode includes a first sub-common electrode electrically connected to each other and a second sub-common electrode, the first sub-common electrode and the first side of the data line An overlapping arrangement, and the second sub-common electrode is disposed to overlap the second side of the data line. 如請求項10所述的畫素結構,其中該遮蔽電極的第一條狀部與該資料線之間具有一狹縫。 The pixel structure of claim 10, wherein the first strip of the shielding electrode has a slit between the data line and the data line. 如請求項11所述的畫素結構,其中該第一子共通電極與該資料線的第一側以及該狄縫於該第一基板的垂直投影方向上重疊。 The pixel structure of claim 11, wherein the first sub-common electrode overlaps with a first side of the data line and a vertical projection direction of the first substrate. 如請求項10所述的畫素結構,其中該畫素電極的第三邊與該資料線於該第一基板的垂直投影方向上重疊。 The pixel structure of claim 10, wherein the third side of the pixel electrode overlaps the data line in a vertical projection direction of the first substrate. 如請求項10所述的畫素結構,其中該共通電極另包括一橋接部,橫跨該資料線,並連接於該第一子共通電極與該第二子共通電極。 The pixel structure of claim 10, wherein the common electrode further comprises a bridge portion spanning the data line and connected to the first sub-common electrode and the second sub-common electrode. 如請求項10所述的畫素結構,其中於該第一基板的垂直投影方向上,該遮蔽電極與該畫素電極的第二邊和第三邊不重疊。 The pixel structure of claim 10, wherein the shielding electrode does not overlap the second side and the third side of the pixel electrode in a vertical projection direction of the first substrate. 如請求項10所述的畫素結構,其中該畫素電極包括一主幹電極、複數條第一分支電極以及複數條第二分支電極,該主幹電極與該第一連接部於該第一基板的垂直投影方向上重疊,且該些第一分支電極與該些第二分支電極分別設置於該主幹電極的兩側,以形成至少一第一配向區與至少一第二配向區。 The pixel structure of claim 10, wherein the pixel electrode comprises a trunk electrode, a plurality of first branch electrodes, and a plurality of second branch electrodes, the main electrode and the first connecting portion on the first substrate The first branch electrodes and the second branch electrodes are respectively disposed on opposite sides of the trunk electrode to form at least one first alignment region and at least one second alignment region. 如請求項10所述的畫素結構,更包括一第二基板以及一顯示介質,該顯示介質設置於該第一基板與該第二基板之間。 The pixel structure of claim 10, further comprising a second substrate and a display medium disposed between the first substrate and the second substrate. 一種畫素陣列,包括:一基板;一第一子畫素,設置於該基板上,其中該第一子畫素包含一第一畫素電極以及一第一遮蔽電極,該第一遮蔽電極包括一第一條狀部、一第二條狀部以及一第一連接部,該第一連接部的兩端分別與該第一條狀部和該第二條狀部連接,藉此該第一連接部與該第一條狀部和該第二條狀部分別形成一彎折結構;一第二子畫素,設置於該基板上,並與該第一子畫素彼此相鄰,其中該第二子畫素包含一第二畫素電極以及一第二遮蔽電極,該第二遮蔽電極包括一第三條狀部、一第四條狀部以及一第二連接部,該第二連接部的兩端分別與該第三條狀部和該第四條狀部連接,藉此該第二連接部與該第三條狀部和該第四條狀部分別形成一彎折結構;一第一資料線,位於該第一子畫素與該第二子畫素之間,其中該第一畫素電極與該第一資料線之間具有一第一狹縫,且該第二畫素電極與該第一資 料線之間具有一第二狹縫;以及一共通電極,沿著該第一資料線設置,該共通電極包含彼此電性連接的一第一子共通電極以及一第二子共通電極,其中該第一子共通電極和該第一遮蔽電極係與該第一狹縫重疊設置,以及該第二子共通電極和該第二遮蔽電極係與該第二狹縫遮蔽重疊設置。 A pixel array includes: a substrate; a first sub-pixel disposed on the substrate, wherein the first sub-pixel comprises a first pixel electrode and a first shielding electrode, and the first shielding electrode comprises a first strip, a second strip, and a first connecting portion, wherein the two ends of the first connecting portion are respectively connected to the first strip and the second strip, whereby the first The connecting portion and the first strip portion and the second strip portion respectively form a bent structure; a second sub-pixel is disposed on the substrate and adjacent to the first sub-pixels, wherein the The second sub-pixel includes a second pixel electrode and a second shielding electrode, the second shielding electrode includes a third strip portion, a fourth strip portion and a second connecting portion, the second connecting portion The two ends are respectively connected to the third strip portion and the fourth strip portion, whereby the second connecting portion and the third strip portion and the fourth strip portion respectively form a bent structure; a data line between the first sub-pixel and the second sub-pixel, wherein the first pixel electrode and the first data Having between a first slit and the second pixel electrode and the first resource a second slit is disposed between the feed lines; and a common electrode is disposed along the first data line, the common electrode includes a first sub-common electrode electrically connected to each other and a second sub-common electrode, wherein the common sub-electrode The first sub-common electrode and the first shielding electrode are disposed to overlap the first slit, and the second sub-common electrode and the second shielding electrode are overlapped with the second slit. 如請求項18所述的畫素陣列,其中該第一資料線沿其延伸方向上具有彼此相對的一第一側與一第二側,該第一子共通電極與該第一資料線的該第一側重疊設置,以及該第二子共通電極與該第一資料線的該第二側重疊設置。 The pixel array of claim 18, wherein the first data line has a first side and a second side opposite to each other along the extending direction thereof, the first sub-common electrode and the first data line The first side overlaps the setting, and the second sub-common electrode is disposed to overlap the second side of the first data line. 如請求項18所述的畫素陣列,其中:該第一資料線沿其延伸方向上具有彼此相對的一第一側與一第二側;該第一畫素電極鄰近該第一資料線的第一側包括一第一邊與一第三邊,該第一邊連接該第三邊,其中於該基板的垂直投影方向上,該第一邊與該第一條狀部彼此重疊,且該第三邊與該第一資料線彼此重疊;以及該第二畫素電極鄰近該第一資料線的第二側包括一第二邊與一第四邊,該第二邊連接該第四邊,其中於該基板的垂直投影方向上,該第二邊與該第一資料線彼此重疊,且該第四邊與該第四條狀部彼此重疊。 The pixel array of claim 18, wherein: the first data line has a first side and a second side opposite to each other along an extending direction thereof; the first pixel electrode is adjacent to the first data line The first side includes a first side and a third side, the first side is connected to the third side, wherein the first side and the first strip overlap each other in a vertical projection direction of the substrate, and the The third side and the first data line overlap each other; and the second side of the second pixel electrode adjacent to the first data line includes a second side and a fourth side, the second side is connected to the fourth side, The second side and the first data line overlap each other in a vertical projection direction of the substrate, and the fourth side and the fourth strip overlap each other. 如請求項20所述的畫素陣列,其中:該第一子共通電極於該基板的垂直投影方向上與該第一資料線的第一側以及該第一條狀部彼此重疊;以及該第二子共通電極於該基板的垂直投影方向上與該第一資料線的第二側以 及該第四條狀部彼此重疊。The pixel array of claim 20, wherein: the first sub-common electrode overlaps with the first side of the first data line and the first strip in a vertical projection direction of the substrate; and the first a two-substance common electrode in a vertical projection direction of the substrate and a second side of the first data line And the fourth strip overlaps each other.
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