TW201934792A - Layer forming method - Google Patents

Layer forming method Download PDF

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TW201934792A
TW201934792A TW107128027A TW107128027A TW201934792A TW 201934792 A TW201934792 A TW 201934792A TW 107128027 A TW107128027 A TW 107128027A TW 107128027 A TW107128027 A TW 107128027A TW 201934792 A TW201934792 A TW 201934792A
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precursor
substrate
layer
reactant
depositing
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TW107128027A
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TWI784036B (en
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朱馳宇
基蘭 什雷斯塔
琦 謝
巴山 羅普
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荷蘭商Asm智慧財產控股公司
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Priority claimed from US15/691,241 external-priority patent/US11056344B2/en
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    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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    • C23C16/45523Pulsed gas flow or change of composition over time
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Abstract

There is provided a method of forming a layer, comprising depositing a seed layer on the substrate; and depositing a bulk layer on the seed layer. Depositing the seed layer comprises supplying a first precursor comprising metal and halogen atoms to the substrate; and supplying a first reactant to the substrate. Depositing the bulk layer comprises supplying a second precursor comprising metal and halogen atoms to the seed layer; and, supplying a second reactant to the seed layer.

Description

層形成方法 Layer formation method 〔相關專利申請案之交叉參考〕 [Cross-reference to related patent applications]

本申請案係2017年8月30日申請的名稱為「層形成方法(LAYER FORMING METHOD)」之美國非臨時申請案第15/691,241號的部分接續申請案,且主張2017年12月18日申請的名稱為「層形成方法」之美國臨時專利申請案第62/607,070號的權益,兩案皆以引用之方式併入本文中。 This application is a partial continuation of US Non-Provisional Application No. 15 / 691,241 entitled “LAYER FORMING METHOD” filed on August 30, 2017, and claims to be filed on December 18, 2017 The benefit of US Provisional Patent Application No. 62 / 607,070, entitled "Layer Formation Method", both cases are incorporated herein by reference.

本發明大體上係關於一種在一基板上形成一層之方法。更具體地說,本發明係關於依序重複原子層沈積(ALD)循環或化學氣相沈積(CVD)程序以在具有間隙之基板上形成層之至少一部分,該等間隙係在特徵之製造過程中產生。在基板上之層可用於製造半導體裝置。 The present invention relates generally to a method for forming a layer on a substrate. More specifically, the present invention relates to sequentially repeating an atomic layer deposition (ALD) cycle or a chemical vapor deposition (CVD) procedure to form at least a portion of a layer on a substrate having gaps, the gaps being in the manufacturing process of features Generated. The layer on the substrate can be used for manufacturing semiconductor devices.

在原子層沈積(ALD)及化學氣相沈積(CVD)中,對基板施加適於在基板上反應形成所需層的第一前驅體及第一反應物。該層可沈積於基板上在製造特徵過程中所產生之間隙中以填充間隙。 In atomic layer deposition (ALD) and chemical vapor deposition (CVD), a substrate is applied with a first precursor and a first reactant suitable for reacting to form a desired layer on the substrate. This layer can be deposited on the substrate to fill the gaps created during the manufacturing process.

在ALD中,使基板暴露於第一前驅體之脈衝且第一前驅體單層可以化學吸附於該基板之表面上。表面位置可由第一前驅體之全部或由第一前驅體之片段佔據。該反應可以為化學自限式反應,因為第一前驅體不會吸附於基板表面上或不與已經吸附於基板表面上之第一前驅體之部分反應。接著,過量 的第一前驅體藉由例如提供惰性氣體及/或自反應室移除第一前驅體進行淨化。隨後,使基板暴露於第一反應物之脈衝,該第一反應物與所吸附的第一前驅體之全部或片段發生化學反應,直至該反應完成且表面經反應產物單層覆蓋。 In ALD, a substrate is exposed to a pulse of a first precursor and a single layer of the first precursor can be chemically adsorbed on the surface of the substrate. The surface position may be occupied by the entirety of the first precursor or by a fragment of the first precursor. This reaction can be a chemical self-limiting reaction because the first precursor does not adsorb on the substrate surface or does not react with a portion of the first precursor that has already adsorbed on the substrate surface. Then, excess The first precursor is purified by, for example, supplying an inert gas and / or removing the first precursor from the reaction chamber. Subsequently, the substrate is exposed to a pulse of a first reactant that chemically reacts with all or a portion of the adsorbed first precursor until the reaction is complete and the surface is covered with a single layer of reaction product.

已發現可能需要改善沈積層之品質。 It has been found that it may be necessary to improve the quality of the deposited layer.

可能需要一種在基板上形成沈積層之改良方法。因此,可提供一種形成層之方法,該方法包括:提供具有在特徵製造過程中產生之間隙的基板並將種子層沈積於該基板上;以及在該種子層上沈積主體層。沈積該種子層可包括:將包含金屬及鹵素原子之第一前驅體供應至該基板;並將第一反應物供應至該基板,其中該第一前驅體與該第一反應物之一部分反應以形成該種子層之至少一部分。沈積該主體層可包括:將包含金屬及鹵素原子之第二前驅體供應至該種子層;並將第二反應物供應至該種子層,其中該第二前驅體及該第二反應物之一部分反應以在該種子層上形成該主體層之至少一部分。第一及第二前驅體可為不同。 An improved method for forming a deposited layer on a substrate may be needed. Therefore, a method of forming a layer may be provided, the method including: providing a substrate having a gap generated during a feature manufacturing process and depositing a seed layer on the substrate; and depositing a main body layer on the seed layer. Depositing the seed layer may include: supplying a first precursor including a metal and a halogen atom to the substrate; and supplying a first reactant to the substrate, wherein the first precursor reacts with a portion of the first reactant to Forming at least a portion of the seed layer. Depositing the host layer may include: supplying a second precursor including a metal and a halogen atom to the seed layer; and supplying a second reactant to the seed layer, wherein the second precursor and a portion of the second reactant Reacting to form at least a portion of the host layer on the seed layer. The first and second precursors may be different.

藉由具有不同的第一及第二前驅體用於種子層及主體層,種子層及主體層之特性可得到優化,由此使總體層之品質可得到改善。第一及第二反應物可為相同且包含氫原子。 By having different first and second precursors for the seed layer and the host layer, the characteristics of the seed layer and the host layer can be optimized, thereby improving the quality of the overall layer. The first and second reactants may be the same and include a hydrogen atom.

在一些其他具體例中,提供一種用於半導體處理之方法。該方法包括將金屬層沈積於基板中之間隙中,由此填充該間隙。 In some other specific examples, a method for semiconductor processing is provided. The method includes depositing a metal layer in a gap in a substrate, thereby filling the gap.

本文所揭示的本發明之此等及其他特徵、態樣及優點在下文參考某些具體例之圖式來描述,該等具體例意欲說明且不限制本發明。 These and other features, aspects, and advantages of the invention disclosed herein are described below with reference to the drawings of certain specific examples, which are intended to illustrate and not limit the invention.

圖1a及1b顯示一流程圖,說明根據一個具體例沈積一層之方法。 1a and 1b show a flowchart illustrating a method for depositing a layer according to a specific example.

圖2顯示根據一個具體例在基板上填充一層的間隙結構之截面。 FIG. 2 shows a cross-section of a gap structure filled with a layer on a substrate according to a specific example.

金屬層可在半導體裝置中被需要作為導電層。在積體電路裝置之特徵的製造過程中產生的間隙可用金屬層來填充。該等間隙可具有高縱橫比,因其深度為遠大於其寬度。 A metal layer may be required as a conductive layer in a semiconductor device. The gap generated during the manufacturing process of the features of the integrated circuit device may be filled with a metal layer. These gaps can have a high aspect ratio because their depth is much larger than their width.

該等間隙可在所製造的具有實質上水平之頂表面的層中豎直地延伸。沿豎直方向且填充有金屬之間隙可例如用於動態隨機存取記憶體(DRAM)型記憶體積體電路之字線中。沿豎直方向且填充有金屬之間隙亦可例如用於邏輯積體電路中。舉例而言,金屬填充間隙可以用作P型金屬氧化物半導體(PMOS)或互補金屬氧化物半導體(CMOS)積體電路中或源極/汲極溝槽型接觸中之閘極填充。 The gaps may extend vertically in a layer that is manufactured with a substantially horizontal top surface. The vertical and metal-filled gap can be used, for example, in a word line of a dynamic random access memory (DRAM) type memory volume circuit. The gaps that are vertical and filled with metal can also be used, for example, in logic integrated circuits. For example, metal-filled gaps can be used as gate fills in P-type metal-oxide-semiconductor (PMOS) or complementary metal-oxide-semiconductor (CMOS) integrated circuits or in source / drain trench contacts.

該等間隙亦可沿水平方向配置於所製造之層中。此外,該等間隙可具有高縱橫比,因其深度,現於水平方向上,為遠大於其寬度。沿水平方向且填充有金屬之間隙可例如用於3D NAND型記憶體積體電路之字線中。該等間隙亦可沿豎直方向與水平方向之組合配置。 These gaps can also be arranged in the manufactured layers in the horizontal direction. In addition, these gaps can have a high aspect ratio, because of their depth, now in the horizontal direction, much larger than their width. The gap filled with metal in the horizontal direction can be used, for example, in a word line of a 3D NAND type memory volume circuit. These gaps can also be arranged in a combination of vertical and horizontal directions.

間隙之表面可包含一個種類之沈積材料。或者,間隙之表面可包含不同種類之沈積材料。間隙之表面可例如包含氧化鋁及/或氮化鈦。當例如鉬導電層可能為間隙中所需時,可能很難將鉬沈積於間隙中之不同材料上。可能需要的是,鉬層可以覆蓋間隙之全部表面且填充整個間隙。另外,亦可能需要鉬層可以覆蓋包括不同種類材料之間隙的全部表面。 The surface of the gap may contain one type of deposition material. Alternatively, the surface of the gap may contain different kinds of deposition materials. The surface of the gap may, for example, comprise alumina and / or titanium nitride. When, for example, a molybdenum conductive layer may be required in the gap, it may be difficult to deposit molybdenum on a different material in the gap. It may be required that the molybdenum layer can cover the entire surface of the gap and fill the entire gap. In addition, it may be required that the molybdenum layer can cover all surfaces including gaps of different kinds of materials.

為了填充整個間隙,種子層可沈積於間隙中且主體層可沈積於該種子層上。種子層可藉由依序重複預處理原子層沈積(ALD)循環來形成。或者, 種子層可藉由化學氣相沈積(CVD)程序來形成。CVD程序可為脈衝式的,其中第一前驅體以脈衝供應至基板上,同時將第一反應物持續地供應至基板上,或反之亦然。主體層可藉由依序重複主體ALD循環來沈積於種子層上。或者,該主體層可藉由CVD程序來沈積於種子層上。CVD程序可為脈衝式的,其中第二前驅體以脈衝供應至基板上,同時將第二反應物持續地供應至基板上,或反之亦然。 To fill the entire gap, a seed layer may be deposited in the gap and a body layer may be deposited on the seed layer. The seed layer may be formed by sequentially repeating a pretreatment atomic layer deposition (ALD) cycle. or, The seed layer may be formed by a chemical vapor deposition (CVD) process. The CVD process may be pulsed, where the first precursor is supplied to the substrate in pulses while the first reactant is continuously supplied to the substrate, or vice versa. The host layer can be deposited on the seed layer by sequentially repeating the host ALD cycle. Alternatively, the host layer may be deposited on the seed layer by a CVD process. The CVD procedure may be pulsed, where the second precursor is supplied to the substrate in a pulse while the second reactant is continuously supplied to the substrate, or vice versa.

圖1a及1b顯示一流程圖,說明根據一個具體例沈積一層之方法,其中種子層可沈積於間隙中且主體層可沈積於種子層上。關於種子層之預處理ALD循環1可如圖1a中所示且關於主體層之主體ALD循環2可如圖1b中所示。 1a and 1b show a flowchart illustrating a method of depositing a layer according to a specific example, in which a seed layer can be deposited in a gap and a main layer can be deposited on the seed layer. The pre-processing ALD cycle 1 regarding the seed layer may be as shown in FIG. 1 a and the main ALD cycle 2 regarding the body layer may be as shown in FIG. 1 b.

在步驟3中將具有間隙之基板提供於反應室中之後,包含金屬及鹵素原子之第一前驅體可以在步驟5中供應至基板,持續第一供應時段T1(參看圖1a)。隨後,藉由例如在步驟7中自反應室移除,例如淨化掉,第一前驅體之一部分,持續第一移除時段R1,可停止第一前驅體向基板之另外供應。另外,該循環可包括將第一反應物供應9至基板,持續第二供應時段T2。第一前驅體及第一反應物的一部分可反應以在基板上形成種子層之至少一部分。通常,在種子層沈積開始之前,其可花費數個(約50個)循環。可例如藉由在步驟11中自反應室移除,例如淨化掉第一反應物之一部分,持續第二移除時段R1,而停止第一反應物向基板之另外供應。 After the substrate with the gap is provided in the reaction chamber in step 3, the first precursor containing metal and halogen atoms may be supplied to the substrate in step 5 for the first supply period T1 (see FIG. 1a). Subsequently, by removing, for example, purifying, a part of the first precursor from the reaction chamber in step 7, for a first removal period R1, the additional supply of the first precursor to the substrate can be stopped. In addition, the cycle may include supplying the first reactant 9 to the substrate for a second supply period T2. The first precursor and a portion of the first reactant may react to form at least a portion of a seed layer on the substrate. Generally, it can take several (about 50) cycles before the seed layer deposition begins. For example, by removing from the reaction chamber in step 11, for example, purifying a part of the first reactant, the second removal period R1 is continued, and the other supply of the first reactant to the substrate is stopped.

第一前驅體及第一反應物可經選擇以在間隙之表面上具有適當成核作用。預處理ALD循環1可重複N次以沈積種子層,其中N係選擇在100與1000之間,較佳在200與800之間,且更佳在300與600之間。種子層可具有的厚度係在1與20nm之間,較佳在2與10nm之間,更佳在3與7nm之間。 The first precursor and the first reactant can be selected to have proper nucleation on the surface of the gap. The pretreatment ALD cycle 1 can be repeated N times to deposit the seed layer, where N is selected between 100 and 1000, preferably between 200 and 800, and more preferably between 300 and 600. The seed layer may have a thickness between 1 and 20 nm, preferably between 2 and 10 nm, and more preferably between 3 and 7 nm.

在預處理之後,將ALD循環1重複N次。包含金屬及鹵素原子之第二前驅體可以在步驟11中,藉由主體ALD循環2供應至基板,持續第三供應時 段T3(參看圖1b)。這可以在與圖1a之預處理ALD循環1相同之反應室中或在不同反應室中進行。當有關預處理循環之溫度要求可能不同時,在與預處理ALD循環不同的反應室中進行主體ALD循環可能係有利的。因此,基板轉移可能為必要的。隨後,例如藉由在步驟13中自反應室移除,例如淨化掉第二前驅體之一部分,持續第三移除時段R3,可停止第二前驅體向基板之另外供應。 After pretreatment, the ALD cycle 1 was repeated N times. The second precursor containing metal and halogen atoms can be supplied to the substrate by the main body ALD cycle 2 in step 11, while the third supply is continued Segment T3 (see Figure 1b). This can be done in the same reaction chamber as the pre-treatment ALD cycle 1 of FIG. 1a or in a different reaction chamber. When the temperature requirements regarding the pretreatment cycle may be different, it may be advantageous to perform a bulk ALD cycle in a reaction chamber different from the pretreatment ALD cycle. Therefore, substrate transfer may be necessary. Subsequently, for example, by removing from the reaction chamber in step 13, for example, purifying a part of the second precursor, and continuing the third removal period R3, the additional supply of the second precursor to the substrate can be stopped.

另外,該循環可包括將第二反應物供應15至基板,持續第四供應時段T4。第二前驅體及第二反應物的一部分可反應以在基板上形成主體層之至少一部分。可例如藉由在步驟17中自反應室移除,例如淨化掉第二反應物之一部分,持續第四移除時段R4,而停止第二反應物向基板之另外供應。第二前驅體及第二反應物可經選擇以具有適當電子特性。舉例而言,以具有低電阻率。鉬膜可具有的電阻率係低於3000μΩ-cm,或低於1000μΩ-cm,或低於500μΩ-cm,或低於200μΩ-cm,或低於100μΩ-cm,或低於50μΩ-cm,或低於25μΩ-cm,或低於15μΩ-cm或甚至低於10μΩ-cm。 In addition, the cycle may include supplying the second reactant 15 to the substrate for a fourth supply period T4. The second precursor and a part of the second reactant may react to form at least a part of the host layer on the substrate. For example, by removing from the reaction chamber in step 17, for example, purifying a part of the second reactant for a fourth removal period R4, the additional supply of the second reactant to the substrate is stopped. The second precursor and the second reactant may be selected to have appropriate electronic characteristics. For example, to have a low resistivity. Molybdenum films can have resistivities below 3000 μΩ-cm, or below 1000 μΩ-cm, or below 500 μΩ-cm, or below 200 μΩ-cm, or below 100 μΩ-cm, or below 50 μΩ-cm, or Below 25 μΩ-cm, or below 15 μΩ-cm or even below 10 μΩ-cm.

關於主體層之主體ALD循環2可以重複M次,其中M選擇係在200與2000之間,較佳在400與1200之間,且更佳在600與1000之間。主體層可具有的厚度係在1與100nm之間,較佳在5與50nm之間,更佳在10與30nm之間。 The main body ALD cycle 2 of the main body layer can be repeated M times, where M selection is between 200 and 2000, preferably between 400 and 1200, and more preferably between 600 and 1000. The host layer may have a thickness between 1 and 100 nm, preferably between 5 and 50 nm, and more preferably between 10 and 30 nm.

第一及第二前驅體可包含相同金屬原子。金屬可為過渡金屬原子。該過渡金屬原子可為鉬。 The first and second precursors may include the same metal atom. The metal may be a transition metal atom. The transition metal atom may be molybdenum.

第一及第二前驅體可包含相同鹵素原子。該鹵素原子可為氯。藉由具有相同鹵素,fab中工具及程序之檢核可以簡化,因為只有一種鹵素需要評估。第一前驅體可包含五氯化鉬(MoCl5)。 The first and second precursors may include the same halogen atom. The halogen atom may be chlorine. By having the same halogen, the inspection of tools and procedures in the fab can be simplified because only one halogen needs to be evaluated. The first precursor may include molybdenum pentachloride (MoCl 5 ).

在預處理ALD循環期間,反應室中之處理溫度可選擇在300與800℃之間,較佳在400與700℃之間且更佳在450與550℃之間。使第一前驅體汽化之容器可以維持在40與100℃之間,較佳在60與80℃之間且更佳維持在約70℃。 During the pretreatment ALD cycle, the processing temperature in the reaction chamber can be selected between 300 and 800 ° C, preferably between 400 and 700 ° C and more preferably between 450 and 550 ° C. The container that vaporizes the first precursor can be maintained between 40 and 100 ° C, preferably between 60 and 80 ° C and more preferably at about 70 ° C.

第二前驅體可包含不為金屬或鹵素原子之另外的原子。該另外的原子可為硫屬元素。硫屬元素可為氧、硫、硒或碲。第二前驅體可包含二氯二氧化鉬(VI)(MoO2Cl2)。 The second precursor may include another atom that is not a metal or halogen atom. The additional atom may be a chalcogen. The chalcogen can be oxygen, sulfur, selenium or tellurium. The second precursor may include molybdenum (VI) dichloride (MoO 2 Cl 2 ).

在主體ALD循環期間,處理溫度可在300與800℃之間,較佳在400與700℃之間且更佳在500與650℃之間。使第二前驅體汽化之容器可維持在20與150℃之間,較佳在30與120℃之間且更佳在40與110℃之間。 During the bulk ALD cycle, the processing temperature may be between 300 and 800 ° C, preferably between 400 and 700 ° C and more preferably between 500 and 650 ° C. The container for vaporizing the second precursor can be maintained between 20 and 150 ° C, preferably between 30 and 120 ° C and more preferably between 40 and 110 ° C.

將第一及/或第二前驅體供應至反應室中可花費在0.1與10秒之間,較佳在0.5與5秒之間且更佳在0.8與2秒之間選擇的持續時間T1、T3。舉例而言,T1可為1秒且T3可為1.3秒。反應室中第一或第二前驅體之流量可選擇在50與1000sccm之間,較佳在100與500sccm之間,且更佳在200與400sccm之間。反應室中的壓力可選擇在0.1與100托(Torr)之間,較佳在1與50托之間,且更佳在4與20托之間。 Supplying the first and / or second precursor into the reaction chamber may take a duration T1, selected between 0.1 and 10 seconds, preferably between 0.5 and 5 seconds, and more preferably between 0.8 and 2 seconds T3. For example, T1 may be 1 second and T3 may be 1.3 seconds. The flow rate of the first or second precursor in the reaction chamber can be selected between 50 and 1000 sccm, preferably between 100 and 500 sccm, and more preferably between 200 and 400 sccm. The pressure in the reaction chamber can be selected between 0.1 and 100 Torr, preferably between 1 and 50 Torr, and more preferably between 4 and 20 Torr.

第一及第二反應物中之一種或兩種可具有氫原子。第一及第二反應物中之至少一種可包含氫氣(H2)。第一及第二反應物可為相同。將第一及/或第二反應物供應至反應室中的持續時間T2、T4可花費在0.5與50秒之間,較佳在1與10秒之間,且更佳在2與8秒之間。反應室中第一或第二反應物之流量可在50與50000sccm之間,較佳在100與20000sccm之間,且更佳在500與10000sccm之間。 One or both of the first and second reactants may have a hydrogen atom. At least one of the first and second reactants may include hydrogen (H 2 ). The first and second reactants can be the same. The duration T2, T4 of supplying the first and / or second reactant to the reaction chamber may take between 0.5 and 50 seconds, preferably between 1 and 10 seconds, and more preferably between 2 and 8 seconds between. The flow rate of the first or second reactants in the reaction chamber may be between 50 and 50,000 sccm, preferably between 100 and 20,000 sccm, and more preferably between 500 and 10,000 sccm.

矽烷可視為第一及/或第二反應物。矽烷之通式係SixH2(x+2),其中x係整數1、2、3、4...矽烷(SiH4)、二矽烷(Si2H6)或三矽烷(Si3H8)可為具有氫原子之第一及或第二反應物之適合例子。 Silane can be considered as the first and / or second reactant. The general formula of silane is Si x H2 (x + 2) , where x is an integer of 1, 2, 3, 4, ... silane (SiH 4 ), disilane (Si 2 H 6 ), or trisilane (Si 3 H 8 ) May be a suitable example of the first and or second reactant having a hydrogen atom.

自反應室移除,例如淨化掉第一前驅體、第一反應物、第二前驅體及第二反應物中至少一種之一部分,持續時間R1、R2、R3或R4可在0.5與50秒之間、較佳在1與10之間,且更佳在2與8秒之間進行。淨化可使用在將第一前 驅體供應至基板之後;在將第一反應物供應至基板之後;在將第二前驅體供應至種子層之後;以及在將第二反應物供應至種子層之後,以自反應室移除第一前驅體、第一反應物、第二前驅體及第二反應物中至少一種之一部分,持續時間R1、R2、R3或R4。移除可藉由泵送及/或藉由提供淨化氣體來實現。淨化氣體可為惰性氣體,諸如氮氣。 Remove from the reaction chamber, for example, purify at least one of the first precursor, the first reactant, the second precursor, and the second reactant. The duration R1, R2, R3, or R4 can be between 0.5 and 50 seconds. Time, preferably between 1 and 10, and more preferably between 2 and 8 seconds. Purification can be used before the first After the precursor is supplied to the substrate; after the first reactant is supplied to the substrate; after the second precursor is supplied to the seed layer; and after the second reactant is supplied to the seed layer, the first reactant is removed from the reaction chamber A precursor, a first reactant, a second precursor, and at least one of the second reactants have a duration of R1, R2, R3, or R4. Removal can be achieved by pumping and / or by providing purge gas. The purge gas may be an inert gas, such as nitrogen.

該方法可用於單個或分批式晶圓ALD設備中。該方法包括將基板提供於反應室中且在反應室中之預處理ALD循環可包括:將第一前驅體供應至反應室中之基板上;自反應室淨化掉第一前驅體之一部分;將第一反應物供應反應室中之基板上;且自反應室淨化掉第一反應物之一部分。另外,該方法包括將基板提供於反應室中且在反應室中之主體ALD循環包括:將第二前驅體供應至反應室中之基板上;自反應室淨化掉第二前驅體之一部分;將第二反應物供應至反應室中之基板上;且自反應室淨化掉第二反應物之一部分。 This method can be used in single or batch wafer ALD equipment. The method includes providing a substrate in a reaction chamber and a pre-treatment ALD cycle in the reaction chamber may include: supplying a first precursor to the substrate in the reaction chamber; purifying a portion of the first precursor from the reaction chamber; and The first reactant is supplied on a substrate in the reaction chamber; and a part of the first reactant is purified from the reaction chamber. In addition, the method includes providing a substrate in the reaction chamber and subjecting the body to ALD in the reaction chamber including: supplying a second precursor to the substrate in the reaction chamber; purifying a portion of the second precursor from the reaction chamber; and The second reactant is supplied to the substrate in the reaction chamber; and a part of the second reactant is purified from the reaction chamber.

專門設計用於執行ALD程序的示例性單晶圓反應器為商品名Pulsar®、Emerald®、Dragon®及Eagle®購自ASM International NV(荷蘭阿爾梅勒(Almere,The Netherlands))。該方法亦可在分批式晶圓反應器,例如立式熔爐中執行。舉例而言,沈積程序可在亦購自ASM International N.V.之A412TM立式熔爐中執行。熔爐可具有能容納150個直徑為300mm之半導體基板或晶圓負荷的處理腔室。 Exemplary single-wafer reactors specifically designed for performing ALD procedures are available under the trade names Pulsar®, Emerald®, Dragon®, and Eagle® from ASM International NV (Almere, The Netherlands). This method can also be performed in a batch wafer reactor, such as a vertical furnace. For example, the deposition process can be performed in an A412 vertical furnace, also purchased from ASM International NV. The furnace may have a processing chamber capable of holding 150 semiconductor substrate or wafer loads with a diameter of 300 mm.

晶圓反應器可設置有可以控制反應器之控制器及記憶體。記憶體可用程式編程以在控制器上執行時,根據本發明之具體例將前驅體及反應物供應於反應室中。 The wafer reactor can be provided with a controller and a memory that can control the reactor. When the memory can be programmed to execute on the controller, the precursor and the reactant are supplied into the reaction chamber according to a specific example of the present invention.

圖2顯示根據本發明之一具體例在基板上填充一層的間隙結構之截面。如所示,該間隙可在所製造的具有實質上水平之頂表面的層中豎直地及水平地延伸。 FIG. 2 shows a cross-section of a gap structure filled with a layer on a substrate according to a specific example of the present invention. As shown, the gap may extend vertically and horizontally in a layer that is manufactured with a substantially horizontal top surface.

該等間隙可具有高縱橫比,因在豎直方向及或水平方向上之深度為遠大於寬度。舉例而言,在豎直方向上,該間隙具有的寬度在頂部為207nm、在中間為169nm且在底部為149nm,而該間隙之深度要大得多,為432nm。舉例而言,在水平方向上,第一間隙自頂部具有34nm之寬度,而該間隙之深度要大得多,為163nm(四捨五入)。該間隙之縱橫比(間隙深度/間隙寬度)可為大於約2、大於約5、大於約10、大於約20、大於約50、大於約75,或在一些情況下甚至大於約100或大於約150或大於約200。 These gaps may have a high aspect ratio because the depth in the vertical and / or horizontal direction is much greater than the width. For example, in the vertical direction, the gap has a width of 207 nm at the top, 169 nm in the middle, and 149 nm at the bottom, and the gap has a much larger depth of 432 nm. For example, in the horizontal direction, the first gap has a width of 34 nm from the top, and the depth of the gap is much larger, which is 163 nm (rounded). The aspect ratio (gap depth / gap width) of the gap may be greater than about 2, greater than about 5, greater than about 10, greater than about 20, greater than about 50, greater than about 75, or in some cases even greater than about 100 or greater than about 150 or greater.

可以注意到,間隙之縱橫比可能很難測定,但在本文中,縱橫比可用表面增強比率(surface enhancement ratio)替代,該表面增強比率可為晶圓或晶圓之部分中間隙之總表面積相對於晶圓或晶圓之部分之平坦表面面積的比率。間隙之表面增強比率(表面間隙/表面晶圓)可為大於約2、大於約5、大於約10、大於約20、大於約50、大於約75,或在一些情況下甚至大於約100或大於約150或大於約200。 It can be noted that the aspect ratio of the gap may be difficult to measure, but in this article, the aspect ratio may be replaced by a surface enhancement ratio, which may be the relative surface area of the gap in the wafer or part of the wafer. The ratio of the flat surface area on a wafer or a portion of a wafer. The surface enhancement ratio (surface gap / surface wafer) of the gap can be greater than about 2, greater than about 5, greater than about 10, greater than about 20, greater than about 50, greater than about 75, or in some cases even greater than about 100 or greater About 150 or more.

間隙之表面可包含不同種類之沈積材料19、21。該表面可例如包含Al2O3或TiN。 The surface of the gap may contain different kinds of deposition materials 19,21. The surface may, for example, contain Al 2 O 3 or TiN.

共形金屬層23藉由用第一前驅體依序重複預處理ALD循環沈積種子層且藉由用第二前驅體依序重複主體ALD循環沈積主體層來沈積於間隙之表面上。所用方法之詳細為顯示於圖1a及1b和相關說明中。在一些具體例中,所沈積的含Mo膜可具有階梯覆蓋率為大於約50%、大於約80%、大於約90%、大於約95%、大於約98%、大於約99%。 The conformal metal layer 23 is deposited on the surface of the gap by sequentially repeating the pre-treatment ALD cycle with the first precursor to deposit the seed layer and sequentially repeating the main ALD cycle with the second precursor. The details of the method used are shown in Figures 1a and 1b and the related description. In some specific examples, the deposited Mo-containing film may have a step coverage of greater than about 50%, greater than about 80%, greater than about 90%, greater than about 95%, greater than about 98%, greater than about 99%.

第一及第二前驅體可包含相同金屬原子,例如過渡金屬原子,諸如鉬。第一及第二前驅體可包含相同鹵素原子,例如氯。第一前驅體可包含MoCl5。第二前驅體可包含不為金屬或鹵素原子的另外的原子,例如硫屬原子,諸如氧。第二前驅體可包含二氯二氧化鉬(VI)(MoO2Cl2)。該方法可在原子層沈 積設備中執行。舉例而言,該等沈積程序可在EMERALD® XPALD設備中執行。 The first and second precursors may include the same metal atom, such as a transition metal atom, such as molybdenum. The first and second precursors may contain the same halogen atom, such as chlorine. The first precursor may include MoCl5. The second precursor may include another atom that is not a metal or halogen atom, such as a chalcogen atom, such as oxygen. The second precursor may include molybdenum (VI) dichloride (MoO 2 Cl 2 ). This method can be performed in an atomic layer deposition apparatus. For example, these deposition procedures can be performed in an EMERALD® XPALD equipment.

第一及第二反應物係氫氣(H2),其係以495sccm流量供應於反應室中,持續5秒時間T2、T4。沖洗氣體氮氣係被用在供應第一前驅體之後;供應第一反應物之後;供應第二前驅體之後;以及供應第二反應物之後,持續5秒時間R1、R2、R3或R4。 The first and second reactants are hydrogen (H 2 ), which are supplied into the reaction chamber at a flow rate of 495 sccm for a period of 5 seconds T2 and T4. The purge gas nitrogen is used after supplying the first precursor; after supplying the first reactant; after supplying the second precursor; and after supplying the second reactant, for a duration of 5 seconds R1, R2, R3 or R4.

在預處理及主體ALD循環期間,處理溫度係約550℃且壓力係約10托。使第一前驅體汽化之容器係約70℃。使第二前驅體汽化之容器係約35℃。 During the pretreatment and bulk ALD cycles, the processing temperature was about 550 ° C and the pressure was about 10 Torr. The container for vaporizing the first precursor was about 70 ° C. The container for vaporizing the second precursor was about 35 ° C.

約4.6nm之種子層係使用預處理ALD循環沈積,持續500個循環,且約21.4nm之主體層係使用主體ALD循環沈積,持續800個循環。如所示,鉬層23係極均勻地沈積於間隙之表面上且具有約26nm總厚度。 A seed layer of about 4.6 nm was deposited using a pretreatment ALD cycle for 500 cycles, and a main layer of about 21.4 nm was deposited using a main ALD cycle for 800 cycles. As shown, the molybdenum layer 23 is deposited very uniformly on the surface of the gap and has a total thickness of about 26 nm.

間隙之取向,無論其係水平的抑或豎直的,以及間隙之寬度看來不會實質上影響層23之厚度。此外,該表面之材料,無論其係Al2O3 19抑或TiN 21看來也不會影響層23之厚度。以此方式,有可能以良好均勻性產生金屬填充之間隙。 The orientation of the gap, whether it is horizontal or vertical, and the width of the gap does not appear to substantially affect the thickness of the layer 23. In addition, the surface material, whether it is Al 2 O 3 19 or TiN 21 does not appear to affect the thickness of the layer 23. In this way, it is possible to produce metal-filled gaps with good uniformity.

該方法亦可用於空間原子層沈積設備中。在空間ALD中,將前驅體及反應物持續地供應於不同物理區段中且基板在該等區段之間移動。可提供至少兩個區段,在此情況下,於基板存在下,可以進行半反應。若基板存在於此類半反應區段中,則單層可由第一或第二前驅體形成。接著,該基板移動至另一個半反應區,在其中ALD循環利用第一或第二反應物完成以形成一個ALD單層。或者,基板位置可以為固定的且氣體供應可以移動,或該兩者之某一組合。為了獲得較厚的膜,此工序可以重複。 This method can also be used in space atomic layer deposition equipment. In spatial ALD, precursors and reactants are continuously supplied in different physical sections and the substrate moves between these sections. At least two sections can be provided, in which case a semi-reaction can be performed in the presence of the substrate. If the substrate is present in such a semi-reactive section, a single layer may be formed from the first or second precursor. The substrate is then moved to another half-reaction zone where the ALD cycle is completed using the first or second reactants to form an ALD monolayer. Alternatively, the substrate position may be fixed and the gas supply may be moved, or some combination of the two. In order to obtain a thicker film, this process can be repeated.

根據空間ALD設備中之一個具體例,該方法包括:將基板放入包含複數個區段之反應室中,每一區段藉由氣幕與相鄰區段分開; 將第一前驅體供應至反應室之第一區段中的基板上;將基板表面對於反應室側向地移動穿過氣幕進入反應室之第二區段;將第一反應物供應至反應室之第二區段中的基板上以形成種子層;將基板表面對於反應室側向地移動穿過氣幕;且重複供應第一前驅體及反應物,包括將基板表面對於反應室側向地移動,以形成種子層。 According to a specific example of the spatial ALD equipment, the method includes: placing a substrate in a reaction chamber including a plurality of sections, each section being separated from an adjacent section by an air curtain; The first precursor is supplied to the substrate in the first section of the reaction chamber; the substrate surface is moved laterally through the air curtain into the second section of the reaction chamber with respect to the reaction chamber; the first reactant is supplied to the reaction The substrate in the second section of the chamber to form a seed layer; move the substrate surface laterally through the air curtain with respect to the reaction chamber; and repeatedly supply the first precursor and reactants, including the substrate surface with the reaction chamber laterally Ground to form a seed layer.

為了形成主體層,該方法進一步包括:將基板放入包含複數個區段之反應室中,每一區段藉由氣幕與相鄰區段分開;將第二前驅體供應至反應室之第一區段中的基板上;將基板表面對於反應室側向地移動穿過氣幕進入反應室之第二區段;將第二反應物供應至反應室之第二區段中的基板上以形成主體層;將基板表面對於反應室側向地移動穿過氣幕;且重複供應第二前驅體及反應物,包括將基板表面對於反應室側向地移動,以形成主體層。 In order to form the main body layer, the method further includes: placing the substrate in a reaction chamber including a plurality of sections, each section being separated from an adjacent section by an air curtain; and supplying a second precursor to the first section of the reaction chamber. The substrate in one section; the substrate surface is moved laterally through the air curtain into the second section of the reaction chamber with respect to the reaction chamber; the second reactant is supplied to the substrate in the second section of the reaction chamber to Forming the body layer; moving the substrate surface laterally through the air curtain with respect to the reaction chamber; and repeatedly supplying the second precursor and the reactant, including moving the substrate surface laterally with respect to the reaction chamber to form the body layer.

第一及第二前驅體可為不同。第一及第二反應物可為相同且包含氫原子。 The first and second precursors may be different. The first and second reactants may be the same and include a hydrogen atom.

根據一個具體例,種子層可用化學氣相沈積(CVD)程序沈積,其中第一前驅體及第一反應物係同時供應至基板。主體層可用CVD程序沈積,其中第二前驅體及第二反應物亦可同時供應至基板。 According to a specific example, the seed layer may be deposited by a chemical vapor deposition (CVD) process, wherein the first precursor and the first reactant system are simultaneously supplied to the substrate. The host layer can be deposited by a CVD process, wherein the second precursor and the second reactant can also be supplied to the substrate at the same time.

CVD程序可為脈衝式CVD程序,其中前驅體係以脈衝供應至基板,同時將反應物持續地供應至基板。其優勢可在於,較高濃度之反應物可降低鹵素之濃度。高濃度鹵素可能損害在基板上之半導體裝置。 The CVD process may be a pulsed CVD process in which the precursor system is supplied to the substrate in pulses while the reactants are continuously supplied to the substrate. The advantage can be that higher concentrations of reactants can reduce the concentration of halogens. High concentrations of halogen may damage semiconductor devices on the substrate.

舉例而言,在對於種子層之脈衝式CVD程序中,第一前驅體五 氯化鉬(MoCl5)可以1秒之脈衝與5秒沖洗氣體流量交替地提供。第一反應物氫氣可在500sccm流動速率下持續地供應且基板可保持在550℃。 For example, in a pulsed CVD process for a seed layer, the first precursor Molybdenum chloride (MoCl5) can be alternately provided with a pulse of 1 second and a flow rate of flushing gas of 5 seconds. The first reactant hydrogen can be continuously supplied at a flow rate of 500 sccm and the substrate can be maintained at 550 ° C.

專門設計用於執行CVD程序的示例性單晶圓反應器可用商品名Dragon®購自ASM International NV(荷蘭阿爾梅勒)。該方法亦可在分批式晶圓反應器,例如立式熔爐中執行。舉例而言,沈積程序可在亦購自ASM International N.V.之A400TM或A412TM立式熔爐中執行。熔爐可具有能容納150個半導體基板或晶圓負荷之處理腔室。 An exemplary single-wafer reactor specifically designed to perform CVD procedures is available under the trade name Dragon® from ASM International NV (Almere, The Netherlands). This method can also be performed in a batch wafer reactor, such as a vertical furnace. For example, the deposition process can be performed in an A400 TM or A412 TM vertical furnace, also purchased from ASM International NV. The furnace may have a processing chamber capable of holding 150 semiconductor substrate or wafer loads.

對於製造3D NAND記憶體,字線可具有需要低電阻率金屬填充之間隙。現有解決方案可利用TiN作為種子層用於CVD鎢間隙填充。對於當前基於氟之鎢沈積程序,來自WF6前驅體之氟可以擴散。較厚(=3nm)的TiN阻擋層可能係防止氟擴散及擴散之氟攻擊高k Al2O3膜所必需的。然而,錫膜之高電阻率(在3nm下,800μΩ-cm)導致TiN/W疊層電阻率增加,該電阻率增加可能為不合需要的。 For manufacturing 3D NAND memory, the word lines may have gaps that require low resistivity metal fill. Existing solutions can utilize TiN as a seed layer for CVD tungsten gap filling. For current fluorine-based tungsten deposition procedures, fluorine from the WF6 precursor can diffuse. A thicker (= 3nm) TiN barrier layer may be necessary to prevent fluorine diffusion and diffusing fluorine from attacking high-k Al2O3 films. However, the high resistivity of the tin film (800 μΩ-cm at 3 nm) leads to an increase in the resistivity of the TiN / W stack, which may be undesirable.

可能需要一種在基板上形成具有低電阻率同時不含氟之沈積層的改良方法。因此,可提供一種形成層之方法,該方法包括:提供具有間隙之基板,該等間隙係在特徵製造過程中產生;將種子層沈積於該基板上;並將主體層沈積於該種子層上。沈積主體層可包括:供應包含過渡金屬諸如鎢之第二前驅體以在種子層之頂部上沈積主體層。 There may be a need for an improved method of forming a deposited layer on a substrate having a low resistivity while not containing fluorine. Therefore, a method of forming a layer can be provided, the method comprising: providing a substrate having gaps which are generated during a feature manufacturing process; depositing a seed layer on the substrate; and depositing a body layer on the seed layer . Depositing the host layer may include supplying a second precursor including a transition metal such as tungsten to deposit the host layer on top of the seed layer.

第二前驅體可包含鹵素,諸如氯,以沈積主體層。第二前驅體可為五氯化鎢(V)(WCl5)或六氯化鎢(VI)(WCl6)。主體層可藉由五氯化鎢(V)(WCl5)或六氯化鎢(VI)(WCl6)與氫氣H2以ALD或CVD操作模式反應來沈積。例如,WCl5之反應可在450℃溫度及40托壓力下實現。該等前驅體可以ALD或CVD操作模式提供。 The second precursor may contain a halogen, such as chlorine, to deposit a host layer. The second precursor may be tungsten (V) (WCl 5 ) or tungsten (VI) hexachloride (WCl 6 ). The host layer may be deposited by reacting tungsten (V) (WCl 5 ) or tungsten (VI) hexachloride (WCl 6 ) with hydrogen H 2 in an ALD or CVD operation mode. For example, the reaction of WCl 5 can be achieved at a temperature of 450 ° C and a pressure of 40 Torr. Such precursors can be provided in ALD or CVD modes of operation.

種子層可藉由包含鉬之第一前驅體與氫氣反應來沈積。使用鉬之 種子層的電阻率可為107μΩ-cm(3nm),小於TiN層。特別是對於15nm疊層厚度(相當於30nm CD結構中之間隙填充),使用此方法實現良好間隙填充。藉由使用五氯化鎢(V)(WCl5)或六氯化鎢(VI)(WCl6)在種子層之頂部上沈積主體層,有可能在不使用氟情況下沈積鎢層且仍具有低電阻率。種子層之前驅體可包含過渡金屬(例如鉬(Mo))、鹵素(例如氯(Cl))及可選硫屬原子(例如氧(O))。種子層之前驅體可例如為五氯化物(MoCl5)或二氯二氧化鉬(VI)(MoO2Cl2),兩種皆與氫氣反應。若五氯化鉬(MoCl5)與二氯二氧化鉬(MoO2Cl2)一起使用時,則氫氣之分壓可降低100倍。 The seed layer may be deposited by reacting a first precursor including molybdenum with hydrogen. The resistivity of the seed layer using molybdenum can be 107 μΩ-cm (3 nm), which is smaller than that of the TiN layer. Especially for 15nm stack thickness (equivalent to gap filling in a 30nm CD structure), use this method to achieve good gap filling. By using tungsten (V) (WCl 5 ) or tungsten (VI) hexachloride (VI) (WCl 6 ) to deposit a bulk layer on top of the seed layer, it is possible to deposit a tungsten layer without using fluorine and still have Low resistivity. The seed layer precursor may include a transition metal (such as molybdenum (Mo)), a halogen (such as chlorine (Cl)), and optionally a chalcogen atom (such as oxygen (O)). The seed layer precursor may be, for example, pentachloride (MoCl 5 ) or molybdenum (VI) dichloride (MoO 2 Cl 2 ), both of which react with hydrogen. If molybdenum pentachloride (MoCl 5 ) is used together with molybdenum dichloride (MoO 2 Cl 2 ), the partial pressure of hydrogen can be reduced by 100 times.

鉬種子層之沈積速度可為每個循環1.2埃。為進行比較,TiN種子層之沈積速度在相同情況下可為每個循環0.6埃。鉬種子層之沈積速度因而可為足夠的。 The deposition rate of the molybdenum seed layer can be 1.2 Angstroms per cycle. For comparison, the deposition rate of the TiN seed layer can be 0.6 Angstroms per cycle under the same conditions. The deposition rate of the molybdenum seed layer may thus be sufficient.

沈積於種子層上之金屬可為銅。第二前驅體可包含銅。第二前驅體可包含鹵素,諸如氯,以沈積主體層。第二前驅體可包含二氯化銅(II)(CuCl2)或氯化亞銅(CuCl)。該等前驅體可用與氫氣反應之ALD或CVD操作模式提供。 The metal deposited on the seed layer may be copper. The second precursor may include copper. The second precursor may contain a halogen, such as chlorine, to deposit a host layer. The second precursor may include copper (II) dichloride (CuCl 2 ) or cuprous chloride (CuCl). The precursors can be provided in an ALD or CVD mode of operation that reacts with hydrogen.

沈積於種子層上之金屬可為來自以下之群之過渡金屬或貴金屬:Ti、V、Cr、Mn、Nb、Mo、Ru、Rh、Pd、Ag、Hf、Ta、W、Re、Os、Ir及Pt。在一些具體例中,該層可包含Co或Ni。 The metals deposited on the seed layer can be transition metals or precious metals from the following groups: Ti, V, Cr, Mn, Nb, Mo, Ru, Rh, Pd, Ag, Hf, Ta, W, Re, Os, Ir And Pt. In some specific examples, the layer may include Co or Ni.

在其他具體例中,種子或主體層可包含小於約40原子%、小於約30原子%、小於約20原子%、小於約10原子%、小於約5原子%或甚至小於約2原子%氧。在其他具體例中,種子或主體層可包含小於約30原子%、小於約20原子%、小於約10原子%或小於約5原子%,或小於約2原子%,或甚至小於約1原子%氫。在一些具體例中,種子或主體層可包含小於約10原子%,或小於約5原子%、小於約1原子%,或甚至小於約0.5原子%鹵素原子或氯。在又其他具體例中,種子或主體層可包含小於約10原子%,或小於約5原子%,或小於約2原子%,或小 於約1原子%,或甚至小於約0.5原子%碳。在本文所概述之具體例中,元素之原子百分比(原子%)濃度可利用拉塞福後向散射(Rutherford backscattering,RBS)測定。 In other specific examples, the seed or host layer may contain less than about 40 atomic%, less than about 30 atomic%, less than about 20 atomic%, less than about 10 atomic%, less than about 5 atomic%, or even less than about 2 atomic% oxygen. In other specific examples, the seed or host layer may contain less than about 30 atomic%, less than about 20 atomic%, less than about 10 atomic% or less than about 5 atomic%, or less than about 2 atomic%, or even less than about 1 atomic% hydrogen. In some specific examples, the seed or host layer may contain less than about 10 atomic%, or less than about 5 atomic%, less than about 1 atomic%, or even less than about 0.5 atomic% of a halogen atom or chlorine. In yet other specific examples, the seed or host layer may contain less than about 10 atomic%, or less than about 5 atomic%, or less than about 2 atomic%, or less At about 1 atomic%, or even less than about 0.5 atomic% carbon. In the specific examples outlined herein, the atomic percentage (atomic%) concentration of an element can be measured using Rutherford backscattering (RBS).

在本發明之一些具體例中,形成一半導體裝置結構,諸如半導體裝置結構可包括形成包含鉬膜之閘電極結構,該閘電極結構具有之有效功函數為大於約4.9eV,或大於約5.0eV,或大於約5.1eV,或大於約5.2eV,或大於約5.3eV,或甚至大於約5.4eV。在一些具體例中,以上提供之有效功函數值可由包含厚度小於約100埃,或小於約50埃,或小於約40埃,或甚至小於約30埃之鉬膜的電極結構展示。 In some specific examples of the present invention, forming a semiconductor device structure, such as a semiconductor device structure, may include forming a gate electrode structure including a molybdenum film, the gate electrode structure having an effective work function greater than about 4.9 eV, or greater than about 5.0 eV , Or greater than about 5.1 eV, or greater than about 5.2 eV, or greater than about 5.3 eV, or even greater than about 5.4 eV. In some specific examples, the effective work function value provided above may be demonstrated by an electrode structure including a molybdenum film having a thickness of less than about 100 Angstroms, or less than about 50 Angstroms, or less than about 40 Angstroms, or even less than about 30 Angstroms.

熟習此項技術者將理解,在不偏離本發明之範疇情況下,可對上述程序以及結構進行各種省略、添加以及修改。預期可進行具體例之特定特徵及態樣的各種組合或子組合且仍在說明內容之範疇內。所揭示具體例之各種特徵及態樣可依序相互組合或經取代。所有該等修改及變化意欲歸屬於如由隨附申請專利範圍所界定之發明範疇內。 Those skilled in the art will understand that various omissions, additions, and modifications to the above procedures and structures can be made without departing from the scope of the present invention. Various combinations or sub-combinations of the specific features and aspects of the specific examples are contemplated and are still within the scope of the description. Various features and aspects of the specific examples disclosed may be sequentially combined with each other or replaced. All such modifications and variations are intended to fall within the scope of the invention as defined by the scope of the accompanying patent application.

Claims (28)

一種形成一層之方法,其包括:提供一具有間隙之基板,該等間隙係在一特徵之製造過程中產生;將一種子層沈積於該基板上;且將一主體層沈積於該種子層上,其中,沈積該種子層包括:將包含金屬及鹵素原子之第一前驅體供應至該基板;且將第一反應物供應至該基板,其中,該第一前驅體及該第一反應物之一部分反應形成該種子層之至少一部分;其中,沈積該主體層包括:將包含金屬及鹵素原子之第二前驅體供應至該種子層;且將第二反應物供應至該種子層,其中該第二前驅體及該第二反應物之一部分反應以在該種子層上形成該主體層之至少一部分,且其中,該第一及第二前驅體係不同的。 A method of forming a layer, comprising: providing a substrate having gaps, the gaps being generated during a feature manufacturing process; depositing a sub-layer on the substrate; and depositing a main layer on the seed layer Wherein, depositing the seed layer includes: supplying a first precursor including a metal and a halogen atom to the substrate; and supplying a first reactant to the substrate, wherein the first precursor and the first reactant A portion of the reaction forms at least a portion of the seed layer; wherein depositing the host layer includes: supplying a second precursor including a metal and a halogen atom to the seed layer; and supplying a second reactant to the seed layer, wherein the first Two precursors and one of the second reactants partially react to form at least a portion of the host layer on the seed layer, and wherein the first and second precursor systems are different. 如請求項1之方法,其中,該第一及第二反應物中之至少一種包含氫原子。 The method of claim 1, wherein at least one of the first and second reactants comprises a hydrogen atom. 如請求項2之方法,其中,該第一及第二反應物中之至少一種包含氫氣(H2)。 The method of claim 2, wherein at least one of the first and second reactants comprises hydrogen (H 2 ). 如請求項1之方法,其中,該第一及第二前驅體包含相同金屬原子。 The method of claim 1, wherein the first and second precursors include the same metal atom. 如請求項1之方法,其中,該第一及第二前驅體中之至少一種包含過渡金屬原子。 The method of claim 1, wherein at least one of the first and second precursors includes a transition metal atom. 如請求項5之方法,其中,該過渡金屬原子係鉬。 The method of claim 5, wherein the transition metal atom is molybdenum. 如請求項1之方法,其中,該第一及第二前驅體包含相同鹵素原 子。 The method of claim 1, wherein the first and second precursors contain the same halogenogen child. 如請求項1之方法,其中,該鹵素原子係氯。 The method of claim 1, wherein the halogen atom is chlorine. 如請求項1之方法,其中,該第一前驅體包含五氯化鉬(MoCl5)。 The method of claim 1, wherein the first precursor comprises molybdenum pentachloride (MoCl 5 ). 如請求項1之方法,其中,該第二前驅體包含不為金屬或鹵素原子之另外的原子。 The method of claim 1, wherein the second precursor includes another atom that is not a metal or halogen atom. 如請求項10之方法,其中,該另外的原子係硫屬原子。 The method of claim 10, wherein the additional atom is a chalcogen atom. 如請求項11之方法,其中,該硫屬原子係氧。 The method according to claim 11, wherein the chalcogen atom is oxygen. 如請求項12之方法,其中,該第二前驅體包含二氯二氧化鉬(VI)(MoO2Cl2)。 The method of claim 12, wherein the second precursor comprises molybdenum (VI) dichloride (MoO 2 Cl 2 ). 如請求項1之方法,其中,該第一及第二前驅體中之至少一種係以脈衝供應至反應室中且該等脈衝係在0.1與10秒之間。 The method of claim 1, wherein at least one of the first and second precursors is supplied to the reaction chamber in pulses and the pulses are between 0.1 and 10 seconds. 如請求項1之方法,其中,該第一或第二前驅體至該反應室中之流量係在50與1000sccm之間。 The method of claim 1, wherein the flow rate of the first or second precursor into the reaction chamber is between 50 and 1000 sccm. 如請求項1之方法,其中,該第一或第二反應物至該反應室中之流量係在50與50000sccm之間。 The method of claim 1, wherein the flow rate of the first or second reactant into the reaction chamber is between 50 and 50,000 sccm. 如請求項1之方法,其中,該反應室中之壓力係在0.1與100托之間。 The method of claim 1, wherein the pressure in the reaction chamber is between 0.1 and 100 Torr. 如請求項1之方法,其中,該處理溫度係在300與800℃之間。 The method of claim 1, wherein the processing temperature is between 300 and 800 ° C. 如請求項1之方法,其中沈積該種子及主體層中之至少一種包括重複包含將該第一或第二前驅體依序供應至該基板之原子層沈積(ALD)循環;以及將該第一或第二反應物供應至該基板。 The method of claim 1, wherein depositing at least one of the seed and the host layer includes repeating an atomic layer deposition (ALD) cycle including sequentially supplying the first or second precursor to the substrate; and the first Or a second reactant is supplied to the substrate. 如請求項19之方法,其中,在將該第一前驅體、該第一反應物、該第二前驅體或該第二反應物供應至該基板之間,將該基板淨化在0.5與50秒之間的時間。 The method of claim 19, wherein the substrate is purified between 0.5 and 50 seconds before the first precursor, the first reactant, the second precursor, or the second reactant is supplied to the substrate. Time between. 如請求項19之方法,其中,將該第一及/或第二反應物供應至該反應室中花費在0.5與50秒之間的時間。 The method of claim 19, wherein supplying the first and / or second reactant to the reaction chamber takes a time between 0.5 and 50 seconds. 如請求項19之方法,其中,對於沈積該種子層,將預處理ALD循環重複在100與1000次之間的次數,且對於沈積該主體層,將主體ALD循環重複在200與2000次之間的次數。 The method of claim 19, wherein for depositing the seed layer, the pretreatment ALD cycle is repeated a number of times between 100 and 1000 times, and for depositing the main layer, the main ALD cycle is repeated between 200 and 2000 times Times. 如請求項1之方法,其中,沈積該種子及主體層中之至少一種包括化學氣相沈積(CVD)程序,其中該前驅體係與該反應物同時供應至該基板。 The method of claim 1, wherein depositing at least one of the seed and the host layer includes a chemical vapor deposition (CVD) process, wherein the precursor system and the reactant are simultaneously supplied to the substrate. 如請求項5之方法,其中,該過渡金屬原子係鎢(W)。 The method according to claim 5, wherein the transition metal atom is tungsten (W). 如請求項1之方法,其中,該第二前驅體包含鎢(W)。 The method of claim 1, wherein the second precursor includes tungsten (W). 如請求項25之方法,其中,該第二前驅體包含五氯化鎢(V)(WCl5)或六氯化鎢(VI)(WCl6)。 The method of claim 25, wherein the second precursor comprises tungsten (V) (WCl 5 ) or tungsten (VI) hexachloride (WCl 6 ). 如請求項1之方法,其中,該第二前驅體包含銅。 The method of claim 1, wherein the second precursor comprises copper. 如請求項24之方法,其中,該第二前驅體包含二氯化銅(II)(CuCl2)或氯化亞銅(CuCl)。 The method of claim 24, wherein the second precursor comprises copper (II) chloride (CuCl 2 ) or cuprous chloride (CuCl).
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12119228B2 (en) 2018-01-19 2024-10-15 Asm Ip Holding B.V. Deposition method

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20200131628A1 (en) * 2018-10-24 2020-04-30 Entegris, Inc. Method for forming molybdenum films on a substrate
WO2020106649A1 (en) 2018-11-19 2020-05-28 Lam Research Corporation Molybdenum templates for tungsten
WO2020159882A1 (en) 2019-01-28 2020-08-06 Lam Research Corporation Deposition of metal films
JP7117336B2 (en) * 2020-01-30 2022-08-12 株式会社Kokusai Electric Semiconductor device manufacturing method, program and substrate processing apparatus
TW202218133A (en) * 2020-06-24 2022-05-01 荷蘭商Asm Ip私人控股有限公司 Method for forming a layer provided with silicon
TW202204662A (en) * 2020-07-20 2022-02-01 荷蘭商Asm Ip私人控股有限公司 Method and system for depositing molybdenum layers
JP7539481B2 (en) 2020-09-23 2024-08-23 株式会社Kokusai Electric SUBSTRATE PROCESSING METHOD, PROGRAM, AND SUBSTRATE PROCESSING APPARATUS
CN115943487A (en) * 2020-11-19 2023-04-07 朗姆研究公司 Low Resistivity Contacts and Interconnects
WO2024201647A1 (en) * 2023-03-27 2024-10-03 株式会社Kokusai Electric Substrate processing method, method for producing semiconductor device, program, and substrate processing apparatus

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1386043A (en) * 2001-05-14 2002-12-18 长春石油化学股份有限公司 Deposition method for IC copper inner conductive wire inculating crystal layer
US6869876B2 (en) * 2002-11-05 2005-03-22 Air Products And Chemicals, Inc. Process for atomic layer deposition of metal films
KR100487639B1 (en) * 2002-12-11 2005-05-03 주식회사 하이닉스반도체 Method for forming metal line of semiconductor device
US20040168627A1 (en) * 2003-02-27 2004-09-02 Sharp Laboratories Of America, Inc. Atomic layer deposition of oxide film
JP2006228923A (en) 2005-02-17 2006-08-31 Kyushu Univ Method for manufacturing thin film
KR100719803B1 (en) * 2005-09-08 2007-05-18 주식회사 아이피에스 Method of manufacturing TiAlN thin film using atomic layer deposition
US7432200B2 (en) * 2005-12-15 2008-10-07 Intel Corporation Filling narrow and high aspect ratio openings using electroless deposition
US7354849B2 (en) * 2006-02-28 2008-04-08 Intel Corporation Catalytically enhanced atomic layer deposition process
US20080242097A1 (en) * 2007-03-28 2008-10-02 Tim Boescke Selective deposition method
CN101308794B (en) * 2007-05-15 2010-09-15 应用材料股份有限公司 Atomic layer deposition of tungsten material
JP5582727B2 (en) * 2009-01-19 2014-09-03 株式会社東芝 Semiconductor device manufacturing method and semiconductor device
US8945305B2 (en) * 2010-08-31 2015-02-03 Micron Technology, Inc. Methods of selectively forming a material using parylene coating
WO2014140672A1 (en) * 2013-03-15 2014-09-18 L'air Liquide, Societe Anonyme Pour I'etude Et I'exploitation Des Procedes Georges Claude Bis(alkylimido)-bis(alkylamido)molybdenum molecules for deposition of molybdenum-containing films
US20150001720A1 (en) * 2013-06-27 2015-01-01 Taiwan Semiconductor Manufacturing Co., Ltd. Interconnect Structure and Method for Forming Interconnect Structure
US9556516B2 (en) 2013-10-09 2017-01-31 ASM IP Holding B.V Method for forming Ti-containing film by PEALD using TDMAT or TDEAT
US10109534B2 (en) * 2014-03-14 2018-10-23 Applied Materials, Inc. Multi-threshold voltage (Vt) workfunction metal by selective atomic layer deposition (ALD)
JP2016098406A (en) 2014-11-21 2016-05-30 東京エレクトロン株式会社 Film deposition method of molybdenum film
US10121671B2 (en) * 2015-08-28 2018-11-06 Applied Materials, Inc. Methods of depositing metal films using metal oxyhalide precursors
JP6417051B2 (en) 2015-09-29 2018-10-31 株式会社Kokusai Electric Semiconductor device manufacturing method, substrate processing apparatus, and program

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12119228B2 (en) 2018-01-19 2024-10-15 Asm Ip Holding B.V. Deposition method

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