TW201933584A - Split-gate flash memory cell and method for forming the same - Google Patents

Abstract

Embodiments of the disclosure relate to a split-gate flash memory cell. The split-gate flash memory cell includes a semiconductor substrate, a floating gate dielectric on the semiconductor substrate, and a floating gate. The floating gate includes a conductive layer on the floating gate dielectric, and a pair of conductive spacers on a top surface of the conductive layer. The split-gate flash memory cell also includes an inter-gate dielectric covering the floating gate, including sidewalls of the conductive layer and the conductive spacers. The split-gate flash memory cell also includes a control gate on the inter-gate dielectric.

Description

Split gate flash memory component and method of forming same

The present disclosure relates to a flash memory component, and more particularly to a split-gate flash memory cell.

Non-volatile memory devices are widely used in the electronics industry. Even if the power of the system disappears, the data stored in the non-volatile memory can be retained. The non-volatile memory device can be a one-time programmable device (for example, an electrically programmable read-only memory (EPROM)) or a re-programmable device (re-programmable devices). For example, an electrically-erasable programmable read-only memory (EEPROM).

An example of a non-volatile memory is a flash memory. Flash memory is becoming more and more popular because of its advantages such as small size and low power consumption.

However, existing flash memory is not satisfactory in all respects.

Embodiments of the present invention provide a split gate flash memory component. The split gate flash memory device includes a semiconductor substrate, a floating gate dielectric layer on the semiconductor substrate, and a floating gate. The floating gate includes a conductive layer on the floating gate dielectric layer and a pair of conductive spacers on a top surface of the conductive layer. The split gate flash memory device also includes an inter-gate dielectric layer covering the floating gate. The inter-gate dielectric layer covers the conductive layer and sidewalls of the conductive spacers. The split gate flash memory device also includes a control gate on the dielectric layer between the gates.

Embodiments of the present invention also provide a method of forming a split gate flash memory device. The method includes providing a semiconductor substrate, forming a first dielectric layer on the semiconductor substrate, forming a first conductive layer on the first dielectric layer, and forming a mask layer on the first conductive layer. The mask layer has an opening exposing the first portion of the first conductive layer. The method also includes forming a pair of conductive spacers on opposite sidewalls of the opening and on a top surface of the first portion of the first conductive layer, forming a dielectric material to fill the opening, removing the mask layer, and the above Portion of the first conductive layer under the mask layer but retaining the pair of conductive spacers and the first portion of the first conductive layer to form a floating gate on the first dielectric layer to form a second dielectric And a layer on the sidewalls of the pair of conductive spacers and the first portion of the first conductive layer. The method also includes forming a control gate on the first dielectric layer, the second dielectric layer, and the dielectric material.

10‧‧‧Separate gate flash memory components

100‧‧‧Semiconductor substrate

100a‧‧‧Channel area

102‧‧‧Source/Bungee Zone

202‧‧‧First dielectric layer

202a‧‧‧Floating gate dielectric layer

302‧‧‧First conductive layer

304‧‧‧ Conductive layer

304’‧‧‧ Sidewall

302t‧‧‧ top surface

402‧‧‧ Cover layer

404‧‧‧ openings

404a, 404b‧‧‧ open side wall

502‧‧‧Second conductive layer

602a, 602b‧‧‧ conductive spacers

602a", 602b"‧‧‧ side wall

602a’‧‧‧First sloping side wall

602b’‧‧‧Second inclined side wall

702‧‧‧ dielectric materials

702a‧‧‧Parts of dielectric materials

702b‧‧‧ dielectric material bottom surface

702t‧‧‧ dielectric material top surface

802‧‧‧Floating gate

902‧‧‧Second dielectric layer

902t‧‧‧ top surface of the dielectric layer

1002‧‧‧Control gate

1102‧‧‧Inter-gate dielectric layer

T1, T2, T3, T4, T5‧‧‧ thickness

H‧‧‧height

W1, W2‧‧‧ width

The embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Should pay attention The various features are not drawn to scale and are merely illustrative. In fact, the dimensions of the elements may be enlarged or reduced to clearly show the technical features of the embodiments of the present invention.

1 through 11 are a series of cross-sectional views illustrating a method of forming a split gate flash memory device in accordance with an embodiment of the present disclosure.

The following disclosure provides many different embodiments or examples to implement various features of the present invention. The following disclosure sets forth specific examples of various components and their arrangement to simplify the description. Of course, these specific examples are not intended to be limiting. For example, if an embodiment of the present invention describes that a first feature is formed on or above a second feature, that is, it may include an embodiment in which the first feature is in direct contact with the second feature, and may also include Additional features are formed between the first feature and the second feature described above, such that the first feature and the second feature may not be in direct contact with each other. In addition, the different examples disclosed below may reuse the same reference symbols and/or labels. These repetitions are not intended to limit the specific relationship between the various embodiments and/or structures discussed.

Various embodiments of the present disclosure will be described hereinafter. Like numbers may be used to indicate like elements. It will be appreciated that additional operational steps may be performed before, during or after the method, and that in other embodiments of the method, portions of the operational steps may be substituted or omitted.

The split gate flash memory device of the embodiment of the invention comprises a floating gate comprising a pair of conductive spacers disposed on a top surface of the conductive layer. The above pair of conductive spacers can enhance the hair The performance of the split gate flash memory component of the embodiment (e.g., shortening the erasing time). A method of forming a split gate flash memory device in accordance with an embodiment of the present invention will be described hereinafter.

Figure 1 illustrates the initial steps of a method of forming a split gate flash memory device in accordance with an embodiment of the present disclosure. As shown in FIG. 1, a semiconductor substrate 100 is provided. For example, the semiconductor substrate 100 may include germanium. In some embodiments, the semiconductor substrate 100 may include other elemental semiconductors (eg, germanium), compound semiconductors (eg, tantalum carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP). )) and alloy semiconductors (for example: SiGe, SiGeC, GaAsP or GaInP). In other embodiments, the semiconductor substrate 100 may include a semiconductor-on-insulator (SOI) substrate. The semiconductor substrate on the insulating layer may include a bottom plate, a buried oxide layer provided on the bottom plate, and a semiconductor layer provided on the buried oxide layer.

In some embodiments, the semiconductor substrate 100 is a p-type germanium substrate. For example, the dopant of the p-type germanium substrate 100 may include boron, aluminum, gallium, indium, other suitable dopants, or a combination thereof, and the dopant concentration of the p-type germanium substrate 100 may be 5× ^{10 14} to 5× ^{10 16} cm. ^-3 . In other embodiments, the semiconductor substrate 100 can be an n-type germanium substrate. For example, the dopant of the n-type germanium substrate 100 may include arsenic, phosphorus, antimony, other suitable dopants or a combination thereof, and the n-type germanium substrate 100 may have a dopant concentration of 5× ^{10 14} to 5× ^{10 16} cm ^{−3 .} . For the sake of brevity, the following embodiments will be described using the p-type germanium substrate 100 as an example, but the disclosure is not limited thereto.

As shown in FIG. 2, a first dielectric layer 202 is formed over the semiconductor substrate 100. A portion of the first dielectric layer 202 can serve as a floating gate dielectric layer for a separate gate flash memory component, as will be described in more detail below. In the present embodiment, the first dielectric layer 202 includes hafnium oxide. Cerium oxide can be formed via an oxidation process, a chemical vapor deposition process, other suitable processes, or a combination thereof. For example, the above oxidation process may include a dry oxidation process (eg, Si+O ₂ →SiO ₂ ), a wet oxidation process (eg, Si+2H ₂ O→SiO ₂ +2H ₂ ), or a combination thereof.

In some other embodiments, the first dielectric layer 202 comprises a high-k dielectric material (eg, a material having a dielectric constant greater than 3.9). For example, the above high-k dielectric material may include HfO ₂ , LaO, AlO, ZrO, TiO, Ta ₂ O ₅ , Y ₂ O ₃ , SrTiO ₃ , BaTiO ₃ , BaZrO, HfZrO, HfLaO, HfTaO, HfSiO. HfSiON, HfTiO, LaSiO, AlSiO, (Ba, Sr)TiO ₃ , Al ₂ O ₃ , other suitable high dielectric constant dielectric materials or combinations thereof. For example, the high dielectric can be formed by a chemical vapor deposition process, an atomic layer deposition (ALD) process, a physical vapor deposition (PVD) process, other suitable processes, or a combination thereof. Constant dielectric layer. For example, the chemical vapor deposition process may be a plasma enhanced chemical vapor deposition (PECVD) process or a metalorganic chemical vapor deposition (MOCVD) process. For example, the above atomic layer deposition process may be a plasma enhanced atomic layer deposition (PEALD) process. For example, the physical vapor deposition process described above may be a vacuum evaporation process or a sputtering process.

In some embodiments, the thickness T1 of the first dielectric layer 202 can be 50Å to 300Å, but this disclosure is not limited to this.

Next, as shown in FIG. 3, a first conductive layer 302 is formed over the first dielectric layer 202. In the present embodiment, the first conductive layer 302 includes polysilicon. In other embodiments, the first conductive layer 302 may comprise a metal (eg, tungsten, titanium, aluminum, copper, molybdenum, nickel, platinum, a similar material, or a combination thereof), a metal alloy, a metal nitride (eg, Tungsten nitride, molybdenum nitride, titanium nitride, tantalum nitride, similar materials or combinations thereof, metal telluride (for example: tungsten telluride, titanium telluride, cobalt telluride, nickel telluride, platinum telluride, antimony telluride, similar A material or a combination thereof, a metal oxide (e.g., yttria, indium oxide, a similar material, or a combination thereof), other suitable materials, or a combination thereof.

For example, a chemical vapor deposition process (eg, a low pressure chemical vapor deposition process (LPCVD) or a plasma assisted chemical vapor deposition process), a physical vapor deposition process (eg, a vacuum evaporation process or a sputtering process) The first conductive layer 302 is formed by other suitable processes or a combination thereof.

In some embodiments, the thickness T2 of the first conductive layer 302 may be 0.05 to 0.5 μm, but the disclosure is not limited thereto.

Next, as shown in FIG. 4, a mask layer 402 is formed over the first conductive layer 302, and an opening 404 is formed in the mask layer 402. The opening 402 can have opposing side walls 404a and 404b. As shown in FIG. 4, the opening 404 exposes a portion of the conductive layer 302. In some embodiments, a portion of the conductive layer 302 exposed by the opening 404 will be the floating gate of the split gate flash memory device, as will be described in more detail below.

In some embodiments, the mask layer 402 can comprise tantalum nitride, silicon oxynitride, other suitable materials, or a combination thereof. For example, the mask layer 402 can be formed by a low pressure chemical vapor deposition process, a plasma assisted chemical vapor deposition process, other suitable processes, or a combination thereof. For example, the thickness T3 of the mask layer 402 may be 0.1 to 0.5 μm , but the disclosure is not limited thereto.

In some embodiments, the opening 404 can be formed in the mask layer 402 by a patterning process. For example, the above patterning process may include a lithography process (eg, photoresist coating, soft baking, mask aligning, exposure, post-exposure bake) Post-exposure baking, developing photoresist, other suitable processes, or combinations thereof, etching processes (eg, wet etching processes, dry etching processes, other suitable processes, or combinations thereof), Other suitable processes or combinations of the above. In some embodiments, a patterned photoresist layer (not shown) having an opening corresponding to the opening 404 may be formed on the mask layer 402 by a lithography process, followed by an etching process to remove the patterned photoresist layer. A portion of the mask layer 402 exposed by the opening forms an opening 404 in the mask layer 402.

Next, as shown in FIG. 5, a second conductive layer 502 is formed on the mask layer 402 and a portion of the first conductive layer 302 exposed by the opening 404. The second conductive layer 502 in the opening 404 will be anisotropically etched back to form conductive spacers on the opposing sidewalls 404a and 404b of the opening 404. In the present embodiment, the second conductive layer 502 includes polysilicon. In other embodiments, the second conductive layer 502 may comprise a metal (eg, tungsten, titanium, aluminum, copper, molybdenum, nickel, platinum, a similar material, or a combination thereof), a metal alloy, a metal nitride (eg, Tungsten nitride, molybdenum nitride, titanium nitride, tantalum nitride, similar materials or combinations thereof, metal telluride (for example: tungsten telluride, titanium telluride, cobalt telluride, nickel telluride, platinum telluride, antimony telluride, similar Material or combination of the above), metal oxygen A compound (e.g., yttria, indium oxide, a similar material, or a combination thereof), other suitable materials, or a combination thereof.

For example, a chemical vapor deposition process (eg, a low pressure chemical vapor deposition process or a plasma assisted chemical vapor deposition process), a physical vapor deposition process (eg, a vacuum evaporation process or a sputtering process), other appropriate The process or combination of the above forms a second conductive layer 502.

In some embodiments, the first conductive layer 302 and the second conductive layer 502 may include the same material (for example, in the embodiment, the first conductive layer 302 and the second conductive layer 502 both include polysilicon). However, in other embodiments, the first conductive layer 302 and the second conductive layer 502 may comprise different materials.

For example, the thickness T4 of the second conductive layer 502 may be 0.1 to 0.4 μm , but the disclosure is not limited thereto.

Next, as shown in FIG. 6, the second conductive layer 502 is anisotropically etched back to form the conductive spacers 602a and 602b of the floating gate of the split gate flash memory device at opposite sidewalls 404a of the opening 404. And 404b and a portion of the top surface 302t of the portion of the first conductive layer 302 exposed by the opening 404. The conductive spacers 602a and 602b and portions of the conductive layer 302 under the opening 404 will collectively function as a floating gate of the split gate flash memory device.

In some embodiments, the second conductive layer 502 can be anisotropically etched back by a dry etch process (eg, a plasma etch process or a reactive ion etch process).

In some embodiments, after the etch back process described above, the conductive spacer 602a can have a first sloped sidewall 602a', and the conductive spacer 602b can have a second sloped sidewall 602b' that faces the first sloped sidewall 602a' (eg, Figure 6 Show).

In some embodiments, after the etch back process, the pair of conductive spacers 602a and 602b are lower than the top surface of the mask layer 402, which may facilitate subsequent formation of the floating of the split gate flash memory device. The process of the gate will be described in detail later. For example, the height h of any of the conductive spacers 602a and 602b may be 0.08 to 0.33 μm , and the ratio of the height h to the thickness T3 of the mask layer 402 may be 0.6 to 0.95.

Next, as shown in FIG. 7, a dielectric material 702 is formed to fill the opening 404. The dielectric material 702 is different from the material of the mask layer 402 and the first conductive layer 302 and will be used as an etch mask in the subsequent process of forming the floating gate of the split gate flash memory device.

In the present embodiment, the dielectric material 702 includes yttrium oxide. In other embodiments, the dielectric material 702 may include HfO ₂ , LaO, AlO, ZrO, TiO, Ta ₂ O ₅ , Y ₂ O ₃ , SrTiO ₃ , BaTiO ₃ , BaZrO, HfZrO, HfLaO, HfTaO, HfSiO, HfSiON, HfTiO, LaSiO, AlSiO, (Ba, Sr)TiO ₃ , Al ₂ O ₃ , other suitable high dielectric constant dielectric materials or combinations thereof.

In some embodiments, the opening 404 can be overfilled and then planarized to form a dielectric material 702. For example, a chemical vapor deposition process (eg, a plasma-assisted chemical vapor deposition process or an organometallic chemical vapor deposition process), a spin-on coating process, an atomic layer deposition process (eg, : a plasma-assisted atomic layer deposition process, a physical vapor deposition process (eg, a vacuum evaporation process or a sputtering process), other suitable processes, or a combination thereof to form a dielectric layer on the mask layer 402 (not Illustrated in the figure) to overfill the opening 404, followed by an etch back process or a chemical mechanical polishing process A chemical-mechanical-polishing (CMP) process is performed to remove portions of the dielectric layer outside the opening 404, and a residual portion of the dielectric layer in the opening 404 is used as the dielectric material 702.

In some embodiments, as shown in FIG. 7, the dielectric material 702 may have a substantially flat top surface 702t that may be adjacent to the top surface of the mask layer 402 after performing the above-described CMP process or etchback process. Qi Ping.

In some embodiments, as shown in FIG. 7, dielectric material 702 has a substantially flat bottom surface 702b that can directly contact top surface 302t of a portion of first conductive layer 302 below opening 404.

Next, as shown in FIG. 8, an etching process (eg, a wet etching process or a dry etching process) or other suitable process removal mask layer 402 and portions of the first conductive layer 302 under the mask layer 402 may be performed, However, the pair of conductive spacers 602a and 602b and portions of the first conductive layer 302 under the opening 404 remain on the first dielectric layer 202 as the floating gate 802 (i.e., the floating gate 802 includes an opening). Portions of the first conductive layer 302 below 404 and pairs of conductive spacers 602a and 602b). It should be noted that in the subsequent paragraphs of the present disclosure, the portion of the first conductive layer 302 remaining on the first dielectric layer 202 may also be referred to as the conductive layer 304 of the floating gate 802.

Referring back to FIG. 7, dielectric material 702 can be used to serve as an etch mask in an etch process that forms floating gate 802. In some embodiments, the conductive spacers 602a and 602b are lower than the top surface of the mask layer 402, such that the dielectric material 702 can have portions 702a substantially on top of the conductive spacers 602a and 602b to protect the conductive spacers. 602a and 602b are protected from etching damage.

In some embodiments, as shown in Figure 8, the paired conductive spacing Objects 602a and 602b are located on opposite ends of conductive layer 304 of floating gate 802.

As shown in FIG. 8, any of the conductive spacers 602a and 602b may have a bottom width W1, and the conductive layer 304 of the floating gate 802 may have a top width W2. The ratio of W1 to W2 (i.e., W1/W2) may depend on the ratio of h to T3 (i.e., h/T3). In some embodiments where the ratio of h to T3 is close to one (e.g., 0.8 to 1), the ratio of W1 to W2 may be small (e.g., 0.3 to 0.425), but its production cost is high. In some embodiments where the ratio of h to T3 is small (eg, 0.3 to 0.7), the ratio of W1 to W2 may be large (eg, greater than 0.485), but the tip of the spacer may be less sharp and less erased. effectiveness. Therefore, in the present embodiment, the ratio of the bottom width W1 of the conductive spacers 602a and 602b to the top width W2 of the conductive layer 304 of the floating gate 802 is 0.425 to 0.485, which avoids the above disadvantages.

Next, as shown in FIG. 9, the second dielectric layer 902 is formed on the first dielectric layer 202, the sidewall 304' of the conductive layer 304 of the floating gate 802, and the sidewall 602a of the conductive spacers 602a and 602b. 602b" and dielectric material 702. The second dielectric layer 902 and a portion of the dielectric material 702 can serve as an inter-gate dielectric layer of a separate gate flash memory component, as will be described in more detail below. In some embodiments, since the second dielectric layer 902 is conformally formed on the substantially flat top surface 702t of the dielectric material 702, the top surface 902t of the second dielectric layer 902 can be substantially flat.

In the present embodiment, the second dielectric layer 902 includes hafnium oxide. The above-described cerium oxide may be formed by an oxidation process (for example, a dry oxidation process or a wet oxidation process), a chemical vapor deposition process, other suitable processes, or a combination thereof.

In other embodiments, the second dielectric layer 902 comprises a high-k dielectric material (eg, a material having a dielectric constant greater than 3.9). For example, the above high-k dielectric material may include HfO ₂ , LaO, AlO, ZrO, TiO, Ta ₂ O ₅ , Y ₂ O ₃ , SrTiO ₃ , BaTiO ₃ , BaZrO, HfZrO, HfLaO, HfTaO, HfSiO. HfSiON, HfTiO, LaSiO, AlSiO, (Ba, Sr)TiO ₃ , Al ₂ O ₃ , other suitable high dielectric constant dielectric materials or combinations thereof. For example, the high-k dielectric layer described above may be formed via a chemical vapor deposition process, an atomic layer deposition process, a physical vapor deposition process, other suitable processes, or a combination thereof. For example, the above chemical vapor deposition process may be a plasma assisted chemical vapor deposition process or an organometallic chemical vapor deposition process. For example, the above atomic layer deposition process may be a plasma assisted atomic layer deposition process. For example, the physical vapor deposition process described above may be a vacuum evaporation process or a sputtering process.

For example, the thickness T5 of the second dielectric layer 902 may be 50 Å to 250 Å, but the disclosure is not limited thereto.

Next, as shown in FIG. 10, a control gate 1002 is formed on the first dielectric layer 202, the second dielectric layer 902, and the dielectric material 702. In the present embodiment, the control gate 1002 includes a polysilicon. In other embodiments, the control gate 1002 can comprise a metal (eg, tungsten, titanium, aluminum, copper, molybdenum, nickel, platinum, a similar material, or a combination thereof), a metal alloy, a metal nitride (eg, nitrogen) Tungsten, molybdenum nitride, titanium nitride, tantalum nitride, similar materials or combinations thereof, metal telluride (for example: tungsten telluride, titanium telluride, cobalt telluride, nickel telluride, platinum telluride, antimony telluride, similar A material or a combination thereof, a metal oxide (e.g., yttria, indium oxide, a similar material, or a combination thereof), other suitable materials, or a combination thereof.

For example, via a deposition process and subsequent patterning The process forms a control gate 1002. The deposition process may include a chemical vapor deposition process (eg, a low pressure chemical vapor deposition process or a plasma assisted chemical vapor deposition process), a physical vapor deposition process (eg, a vacuum evaporation process or a sputtering process), other suitable Process or a combination of the above. The patterning process can include an etch process.

Next, as shown in FIG. 11, the source/drain regions 102 may be formed in the semiconductor substrate 100. The channel region 100a in the semiconductor substrate 100 under the control gate 1002 can separate the source/drain regions 102. In this embodiment, the source/drain regions 102 are doped with an n-type dopant. For example, the control gate 1002 can be used as a mask in the implantation process to implant phosphorous or arsenic ions into the semiconductor substrate 100 on opposite sides of the control gate 1002 to form a dopant concentration of 5×10. Source/drain region 102 of ¹⁷ cm ^-3 to 5x10 ²⁰ cm ^-3 . In other embodiments, the semiconductor substrate 100 is an n-type germanium substrate, and thus the source/drain regions 102 are doped with a p-type dopant (eg, boron, aluminum, gallium, indium, other suitable dopants, or the like) The combination of the source/drain regions 102 may have a dopant concentration of 5 x ^{10 17} cm ^-3 to 5 x ^{10 20} cm ^-3 .

As shown in Fig. 11, a split gate flash memory device 10 is formed. The split gate flash memory device 10 includes a floating gate 802 that includes a conductive layer 304 and pairs of conductive spacers 602a and 602b. A portion 202a of the first dielectric layer 202 under the floating gate 802 may be referred to as a floating gate dielectric layer, and a portion of the second dielectric layer 902 covering the floating gate 802 and the dielectric material 702 may be referred to as It is an inter-gate dielectric layer 1102. In some embodiments, as shown in FIG. 11, the floating gate 802 can be completely covered by the floating gate dielectric layer 202a and the inter-gate dielectric layer 1102. As shown in FIG. 11, the inter-gate dielectric layer 1102 can cover the sidewalls 304' of the conductive layer 304 and the sidewalls 602a" and 602b" of the conductive spacers 602a and 602b.

In summary, the split gate flash memory device of the embodiment of the present invention includes a floating gate. The floating gate includes a pair of conductive spacers disposed on a top surface of the conductive layer. The pair of conductive spacers can increase the current between the floating gate and the control gate, thereby improving the performance of the split gate flash memory device (eg, shortening the erase time).

The foregoing summary of the various embodiments of the invention may be Those skilled in the art will understand that other processes and structures can be readily designed or modified based on the embodiments of the present invention to achieve the same objectives and/or to achieve the embodiments described herein. The same advantages. Those of ordinary skill in the art should also understand that such equivalent structures are not departing from the spirit and scope of the invention. Various changes, permutations, or modifications may be made to the embodiments of the invention without departing from the spirit and scope of the invention.

In addition, each of the claims of the present disclosure may be an individual embodiment, and the scope of the disclosure includes each of the claims and each embodiment of the disclosure.

In addition, although the embodiments of the present disclosure are disclosed herein, the embodiments are not intended to limit the scope of the disclosure. In addition, not all advantages of the disclosed embodiments are described. Furthermore, various changes, permutations, or alterations may be made in the embodiments of the present disclosure without departing from the spirit and scope of the invention. Therefore, the scope of the claimed invention should depend on the scope of the patent application.

Claims (20)

A split gate flash memory device comprising: a semiconductor substrate; a floating gate dielectric layer on the semiconductor substrate; and a floating gate comprising: a conductive layer on the floating gate a pair of conductive spacers on a top surface of the conductive layer; an inter-gate dielectric layer covering the floating gate, wherein the inter-gate dielectric layer covers the conductive layer and the Side walls of the conductive spacers; and a control gate on the inter-gate dielectric layer. The split gate flash memory device of claim 1, wherein the inter-gate dielectric layer has a flat top surface. The split gate flash memory device of claim 1, wherein the inter-gate dielectric layer and the floating gate dielectric layer completely cover the floating gate. The split gate flash memory device of claim 1, wherein the inter-gate dielectric layer comprises a portion having a flat bottom surface contacting the top of the conductive layer of the floating gate surface. The split gate flash memory device of claim 1, wherein the pair of conductive spacers are disposed on opposite top ends of the conductive layer. The split gate flash memory device of claim 1, wherein one of the conductive spacers has a first inclined sidewall, and the other of the conductive spacers has a second The side wall is inclined, and the first inclined side wall and the second inclined side wall are opposed to each other. The split gate flash memory device of claim 1, wherein one of the conductive spacers has a height of 0.08 to 0.33 micrometers. The split gate flash memory device of claim 1, wherein a ratio of a bottom width of one of the conductive spacers to a top width of the conductive layer is 0.425 to 0.485. A method for forming a split gate flash memory device, comprising: providing a semiconductor substrate; forming a first dielectric layer on the semiconductor substrate; forming a first conductive layer on the first dielectric layer; forming a mask layer on the first conductive layer, wherein the mask layer has an opening to expose a first portion of the first conductive layer; forming a pair of conductive spacers on the opposite sidewalls of the opening and located at the first conductive layer a top surface of the first portion of the layer; forming a dielectric material to fill the opening; removing the mask layer and portions of the first conductive layer below the mask layer, but retaining the pair of conductive spacers a first portion of the first conductive layer to form a floating gate on the first dielectric layer; a second dielectric layer on the sidewalls of the pair of conductive spacers and the first portion of the first conductive layer; Forming a control gate on the first dielectric layer, the second dielectric layer and the dielectric material. The method for forming a split gate flash memory device according to claim 9, wherein the step of forming the pair of conductive spacers on opposite sidewalls of the opening comprises: Forming a second conductive layer on the mask layer and the first portion of the first conductive layer; and anisotropically etching back the second conductive layer to form the pair of conductive spacers on opposite sidewalls of the opening. The method of forming a split gate flash memory device according to claim 9, wherein the dielectric material has a flat bottom surface contacting a top surface of the first portion of the first conductive layer. The method of forming a split gate flash memory device according to claim 9, wherein the dielectric material has a flat top surface. The method of forming a split gate flash memory device according to claim 9, wherein the pair of conductive spacers is lower than a top surface of the mask layer. The method of forming a split gate flash memory device according to claim 9, wherein the step of removing the mask layer and a portion of the first conductive layer under the mask layer comprises: using the The dielectric material acts as a mask to perform an etch process to remove the mask layer and portions of the first conductive layer below the mask layer. The method of forming a split gate flash memory device according to claim 9, wherein the first conductive layer comprises polysilicon. The method for forming a split gate flash memory device according to claim 9, wherein the step of forming the dielectric material comprises: performing an etching process, a chemical mechanical polishing process, or a combination thereof. The method for forming a split gate flash memory device according to claim 9, wherein the pair of conductive spacers are formed on the first conductive layer The opposite part of the first part. The method of forming a split gate flash memory device according to claim 9, wherein one of the conductive spacers has a first inclined sidewall, and the other of the conductive spacers has a second inclined side wall, and the first inclined side wall and the second inclined side wall are opposite to each other. The method of forming a split gate flash memory device according to claim 9, wherein one of the conductive spacers has a height of 0.08 to 0.33 micrometers. The method for forming a split gate flash memory device according to claim 9, wherein a bottom width of one of the conductive spacers and a top width of the first portion of the first conductive layer The ratio is 0.425 to 0.485.