TW201931576A - Three-dimensional non-volatile memory and manufacturing method thereof - Google Patents

Abstract

A three-dimensional non-volatile memory and a method manufacturing the same are provided. The three-dimensional non-volatile memory includes a substrate, a charge storage structure, a stacked structure and a channel layer. The charge storage structure is disposed on the substrate. The stacked structure is disposed at one side of the charge storage structure and includes insulating layers, gates, a buffer layer and a barrier layer. The insulating layers and the gates are alternately stacked. The buffer layer is disposed between each of the gates and the charge storage structure and on the surfaces of the insulating layers. The barrier layer is disposed between each of the gates and the buffer layer. An end of the gate is convex with respect to an end of the barrier layer in the direction away from the channel layer.

Description

Three-dimensional non-volatile memory and manufacturing method thereof

The present invention relates to a memory and a method of fabricating the same, and more particularly to a three-dimensional non-volatile memory and a method of fabricating the same.

Non-volatile memory components (eg, flash memory) are a memory component widely used in personal computers and other electronic devices because they have the advantage that the stored data does not disappear after power is turned off.

Flash memory arrays currently used in the industry include reverse OR gate (NOR) flash memory and NAND flash memory. Since the structure of the NAND flash memory is such that the memory cells are connected in series, the degree of integration and area utilization is more efficient than that of the NOR flash memory, so the memory density of the NAND flash memory is higher than that of the NOR flash memory. The memory density is much higher. Therefore, NAND flash memory has been widely used in a variety of electronic products, especially in the field of large data storage.

In addition, in order to further increase the storage density and the degree of integration of the memory elements, a three-dimensional NAND flash memory has been developed. However, in the current operation of three-dimensional NAND flash memory, the interference of memory cells is one of the main challenges in three-dimensional NAND flash memory, especially the presence of trace residues.

The present invention provides a three-dimensional non-volatile memory and a method of fabricating the same that eliminates interference phenomena between gates, such as electrical connections/bridges, during operation.

The present invention provides a three-dimensional non-volatile memory comprising a substrate, a charge storage structure, a stacked structure, and a channel layer. The charge storage structure is disposed on the substrate. The stacked structure is disposed on one side of the charge storage structure and includes a plurality of insulating layers, a plurality of gates, a buffer layer, and a barrier layer. The insulating layer and the gate are alternately stacked. The buffer layer is disposed between each gate and the charge storage structure and disposed on a surface of the insulating layer. The barrier layer is disposed between each of the gates and the buffer layer. The channel layer is disposed on the other side of the charge storage structure. The end of the gate is convex relative to the end of the barrier layer in a direction away from the channel layer.

In some embodiments of the present invention, the end E1 of the insulating layer 102a is at a distance L1 from the end portion E2 of the gate 124a in a direction perpendicular to the channel layer, and the end E1 of the insulating layer 102a is perpendicular to the channel layer. The distance in the direction from the end E3 of the barrier layer 122a is L2, and 1 < L2 / L1 < 2.

In some embodiments of the present invention, the thickness of the first portion of the buffer layer in contact with the barrier layer is T1, and the thickness of the second portion of the buffer layer not in contact with the barrier layer is T2, and 0<T1− T2 ≦ 30 angstroms (Å).

In some embodiments of the invention, the second portion of the buffer layer described above is discontinuous.

In some embodiments of the present invention, the atomic concentration of the atoms containing the barrier layer in the second portion may be less than 1 atom%.

In some embodiments of the invention, the material of the barrier layer is, for example, titanium, titanium nitride, tantalum, tantalum nitride or a combination thereof.

In some embodiments of the invention, the material of the buffer layer described above is, for example, a material having a high dielectric constant.

The invention provides a method for manufacturing a three-dimensional non-volatile memory, comprising the following steps. A charge storage structure and a stacked structure are formed on the substrate. The charge storage structure is disposed on the sidewall of the stacked structure. The stacked structure includes a plurality of insulating layers, a plurality of gates, a buffer layer, and a barrier layer. The insulating layer and the gate are alternately stacked. The buffer layer is disposed between each gate and the charge storage structure and disposed on a surface of the insulating layer. The barrier layer is disposed between each of the gates and the buffer layer. A channel layer is formed on the charge storage structure. The end of the gate is convex relative to the end of the barrier layer in a direction away from the channel layer.

In some embodiments of the present invention, the end E1 of the insulating layer 102a is at a distance L1 from the end portion E2 of the gate 124a in a direction perpendicular to the channel layer, and the end E1 of the insulating layer 102a is perpendicular to the channel layer. The distance in the direction from the end E3 of the barrier layer 122a is L2, and 1 < L2 / L1 < 2.

In some embodiments of the present invention, the thickness of the first portion of the buffer layer in contact with the barrier layer is T1, and the thickness of the second portion of the buffer layer not in contact with the barrier layer is T2, and 0<T1− T2 ≦ 30 angstroms.

In some embodiments of the invention, the second portion of the buffer layer described above is discontinuous.

In some embodiments of the present invention, the atomic concentration of the atoms containing the barrier layer in the second portion may be less than 1 atom%.

In some embodiments of the invention, the method of forming the stacked structure described above includes the following steps. A plurality of layers of insulating material and a plurality of sacrificial layers alternately stacked are formed on the substrate. A patterning process is performed on the insulating material layer and the sacrificial layer to form a first opening. The sacrificial layer exposed by the first opening is removed to form a second opening exposing a portion of the charge storage structure. A gate layer is formed on the surface of the first opening and a gate layer is filled in the second opening. The gate layer includes a buffer material layer, a barrier material layer and a gate material layer which are sequentially formed. A portion of the gate material layer, a portion of the buffer material layer, and a portion of the barrier material layer are removed to form a gate, a buffer layer, and a barrier layer.

In some embodiments of the invention, the method of removing a portion of the gate material layer, a portion of the barrier material layer, and a portion of the buffer material layer includes the following steps. A first etching process is performed to remove a portion of the gate material layer to expose the barrier material layer. A second etching process is performed to remove a portion of the barrier material layer to expose the buffer material layer. A third etching process is performed to remove a portion of the buffer material layer to form a buffer layer.

In some embodiments of the invention, the first etching process described above is, for example, an etch back process.

In some embodiments of the present invention, the second etching process is, for example, a dry etching process or a wet etching process.

In some embodiments of the invention, the third etching process described above is, for example, alternately performing dry processing and wet processing.

In some embodiments of the invention, the dry process described above is, for example, a plasma process.

In some embodiments of the invention, the wet treatment described above is, for example, a wet treatment using a fluorine-containing solvent as an etchant.

Based on the above, in the three-dimensional non-volatile memory and the method of fabricating the same according to the present invention, the step residue in the insulating layer is simultaneously removed by removing the insulating layer between the portions of the gates, thereby greatly reducing Interference between gates (eg metal residues) and short circuit problems during operation.

The above described features and advantages of the invention will be apparent from the following description.

1A through 1I are cross-sectional views showing a manufacturing process of a three-dimensional non-volatile memory according to some embodiments of the present invention. Figure 2 is a top view of Figure 1B.

Referring to FIG. 1A, a stacked structure 101 is formed on the substrate 100. The substrate 100 is, for example, a crucible substrate. In some embodiments, a doped region (eg, an N+ doped region) (not shown) may be formed in the substrate 100 depending on design requirements. The stacked structure 101 includes a plurality of insulating material layers 102 and a plurality of sacrificial layers 104 that are alternately stacked. The material of the layer of insulating material 102 comprises a dielectric material such as yttrium oxide. The material of the sacrificial layer 104 is different from the insulating material layer 102 and has a sufficient etching selectivity ratio with the insulating material layer 102, and is not particularly limited. In some embodiments, the material of the sacrificial layer 104 is, for example, tantalum nitride. The insulating material layer 102 and the sacrificial layer 104 are formed, for example, by performing a plurality of chemical vapor deposition processes. The number of layers of the insulating material layer 102 and the sacrificial layer 104 in the stacked structure 101 may be greater than 16. However, the invention is not limited thereto, and the number of layers of the insulating material layer 102 and the sacrificial layer 104 in the stacked structure 101 may depend on the design and density of the memory device.

Next, the stacked structure 101 is etched to form an opening 106 through the stacked structure 101. In some embodiments, a portion of the substrate 100 can be selectively removed during the etching process described above such that the opening 106 extends into the substrate 100. The opening 106 is, for example, a hole as shown in FIG.

Referring to FIG. 1B and FIG. 2 simultaneously, a charge storage structure 112 is formed on the sidewall of the opening 106. The charge storage structure 112 covers the insulating material layer 102 and the sacrificial layer 104. The charge storage structure 112 can be an oxide, a nitride, or a combination thereof. In some embodiments, charge storage structure 112 includes an oxide-nitride-oxide (ONO) composite layer. In an exemplary embodiment, charge storage structure 112 includes a hafnium oxide layer 109, a tantalum nitride layer 110, and a hafnium oxide layer 111. In some embodiments, charge storage structure 112 includes an oxide-nitride-oxide-nitride-oxide (ONONO) composite layer. In an exemplary embodiment, the charge storage structure 112 includes a hafnium oxide layer 135, a tantalum nitride layer 136, a hafnium oxide layer 137, a tantalum nitride layer 138, and a hafnium oxide layer 139, as shown in FIG. 1B-1. More specifically, the charge storage structure 112 is formed in the form of a spacer on the sidewall of the opening 106 to expose the substrate 100 of the bottom surface of the opening 106.

In the present embodiment, the openings 106 in FIG. 2 are arranged in an array, but the invention is not limited thereto. In some embodiments, the openings 106 are randomly arranged as long as the distance between the openings 106 is greater than 100 angstroms.

Next, a channel layer 114 is formed over the charge storage structure 112. Specifically, the channel layer 114 covers the charge storage structure 112 on the side of the opening 106 and is in contact with the substrate 100 exposed by the bottom surface of the opening 106. In some embodiments, the channel layer 114 can be implemented as a bit line. The material of the channel layer 114 is, for example, a semiconductor material such as polysilicon or doped polysilicon or the like. Doping may be performed by in-situ doping or by ion implantation.

Referring to FIG. 1C, a dielectric layer 115 is formed in the opening 106. The method for forming the dielectric layer 115 is, for example, forming a dielectric material layer (not shown) filling the opening 106 by chemical vapor deposition or spin coating, and then performing an etch back process on the dielectric material layer to form the dielectric layer 115. The upper surface of the dielectric layer 115 is lower than the top surface of the stacked structure 101.

Next, a conductor plug 116 is formed on the dielectric layer 115. The conductor plug 116 is in contact with the channel layer 114. In some embodiments, the material of the conductor plug 116 is, for example, polysilicon or doped polysilicon. The conductor plug 116 is formed by, for example, forming a conductive material layer (not shown) filling the opening 106, and then performing a chemical mechanical polishing process and/or an etch back process on the conductive material layer to remove the conductor outside the opening 106. Material layer.

Then, an insulating layer 117 is formed on the stacked structure 101. The insulating layer 117 covers the charge storage structure 112, the channel layer 114, the conductor plugs 116, and the stacked structure 101. In some embodiments, the material of the insulating layer 117 is, for example, yttria or other insulating material.

Referring to FIG. 1D, the insulating layer 117, the insulating material layer 102, and the sacrificial layer 104 are patterned to form openings (also referred to as trenches) 118 through the insulating layer 117, the insulating material layer 102, and the sacrificial layer 104. In some embodiments, during the patterning process, portions of the substrate 100 are also removed simultaneously such that the openings 118 extend to the substrate 100. Further, after the patterning process of the insulating material layer 102, the remaining portion of the insulating material layer 102 forms the insulating layer 102a.

Next, the sacrificial layer 104 exposed by the opening 118 is removed to form a lateral opening 120 that exposes a portion of the charge storage structure 112. The method of removing the sacrificial layer 104 exposed by the opening 118 is, for example, a dry etching method or a wet etching method. The etchant used in the dry etching method is, for example, NF ₃ , H ₂ , HBr, O ₂ , N ₂ or He. The etching liquid used in the above wet etching method is, for example, a phosphoric acid (H ₃ PO ₄ ) solution.

Referring to FIG. 1E, a gate layer 126 is formed on the surface of the opening 118 and a gate layer 126 is filled in the lateral opening 120. The gate layer 126 includes a buffer material layer 121, a barrier material layer 122, and a gate conductor material layer 124 that are sequentially formed. In some embodiments, a buffer material layer 121 is formed between the barrier material layer 122 and the charge storage structure 112 and on the surface of the insulating layer 102a. The material of the buffer material layer 121 is, for example, a material having a high dielectric constant having a dielectric constant of more than 7, such as alumina (Al ₂ O ₃ ), HfO ₂ , La ₂ O ₅ , a transition metal oxide, a lanthanide oxide or Its combination and so on. In some embodiments, the method of forming the buffer material layer 121 requires good step coverage to achieve good film thickness uniformity throughout the structure. The method is, for example, chemical vapor deposition or atomic layer deposition (ALD). The buffer material layer 121 can be used to enhance erase and programming characteristics. The material of the barrier material layer 122 is, for example, titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or a combination thereof. The method of forming the barrier material layer 122 is, for example, a chemical vapor deposition method. The material of the gate conductor material layer 124 is, for example, polycrystalline germanium, amorphous germanium, tungsten (W), cobalt (Co) aluminum (Al), tungsten germanium (WSix) or cobalt telluride (CoSix). The method of forming the gate conductor material layer 124 is, for example, a chemical vapor deposition method.

Referring to FIGS. 1F through 1H, a portion of the gate conductor material layer 124, a portion of the barrier material layer 122, and a portion of the buffer material layer 121 are removed to form the gate 124a, the buffer layer 121a, and the barrier layer 122a.

In some embodiments, as shown in FIG. 1F, a first etch process is performed to remove a portion of the gate conductor material layer 124 to expose the barrier material layer 122. The first etch process can be an etch back process, such as a wet etch process or a dry etch process. Dry etching processes or wet etching processes are possible. In some embodiments, the dry etching can be performed under a plasma system including inductively coupled plasma (ICP), remote plasma, capacitive coupled plasma (CCP), or electrons. An electron cyclotron resonance (ECR) system. And a fluorine compound such as NF ₃ , SF ₆ or CF ₄ can be applied. In some embodiments, in the case of wet etching, NH ₄ OH, H ₂ O ₂ , H ₂ SO ₄ , HNO ₃ or acetic acid may be applied. In some embodiments, a portion of the gate conductor material layer 124 in the lateral opening 120 is removed in addition to removing the gate conductor material layer 124 in the opening 118 during the first etching process. Moreover, after the first etch process of the gate conductor material layer 124, the remaining portion of the gate conductor material layer 124 forms the gate 124a. In some embodiments, gate 124a can be used as a word line. In some embodiments, the end E1 of the insulating layer 102a is convex relative to the end E2 of the gate 124a exposed in the lateral opening 120. Specifically, the end portion E1 of the insulating layer 102a is convex with respect to the end portion E2 of the gate 124a in a direction away from the channel layer 114. In the present embodiment, the adjacent two gates 124a are isolated by the insulating layer 102a located therebetween, and since the insulating layer 102a protrudes from the two adjacent gates 124a of the adjacent lateral openings 120 (upper and lower) Therefore, adjacent gates 124a can be prevented from contacting each other. In the present embodiment, the end portion E2 of the gate 124a has a substantially flat surface, but the present invention is not limited thereto. In other embodiments, the end E2 of the gate 124a has an arcuate surface. In some embodiments, the end E2 of the gate 124a protrudes from the surface near the center of the opening 120 than the end E2 of the gate 124a near the edge of the opening 120 (ie, near the barrier material layer 122) (eg, a dashed line) Shown).

Next, referring to FIG. 1G, a second etching process is performed to remove a portion of the barrier material layer 122 to expose the buffer material layer 121. The second etching process is, for example, a dry etching process or a wet etching process. In some embodiments, during the second etching process, in addition to removing the barrier material layer 122 on the opening 118, the barrier material layer 122 and the gate 124a exposed in the lateral opening 120 are also removed. A portion of the barrier material layer 122 between the buffer material layers 121. After the second etching process is performed on the barrier material layer 122, the remaining portion of the barrier material layer 122 forms the barrier layer 122a. In some embodiments, the end E2 of the gate 124a exposed in the lateral opening 120 is convex relative to the end E3 of the barrier layer 122a exposed in the lateral opening 120. Specifically, the end portion E2 of the gate 124a is convex with respect to the end portion E3 of the barrier layer 122a in a direction away from the channel layer 114. In this embodiment, by removing the barrier material layer 122 on the opening 118 and even removing the barrier material layer 122 in the lateral opening 120 to the end E2 below the gate 124a, the phase can be facilitated. The isolation between the gates 124a in the lateral openings 120 is adjacent and the stringer between adjacent lateral openings 120 (i.e., the residue of the barrier material layer) is reduced. In the present embodiment, the end portion E3 of the barrier layer 122a has a substantially flat surface, but the present invention is not limited thereto. In other embodiments, the end E3 of the barrier layer 122a has an inclined surface. Specifically, the end portion E3 of the barrier layer 122a has an inclined surface from the point of contact with the buffer material layer 121 toward the channel layer 114.

In some embodiments, a portion of the gate conductor material layer 124 and a portion of the barrier material layer 122 can be simultaneously removed by a single etch process.

Referring to FIG. 1H, a third etching process is performed to remove a portion of the exposed buffer material layer 121 to form a buffer layer 121a. In some embodiments, the third etch process can be alternately dry and wet. The dry treatment is, for example, a plasma treatment. In some embodiments, the dry processing can be performed under a plasma system including inductively coupled plasma (ICP), remote plasma, capacitive coupled plasma (CCP), or electrons. An electron cyclotron resonance (ECR) system. In some embodiments, the plasma treatment can be performed using an oxidizing gas, an inert gas, or a combination thereof. The oxidizing gas hardly reacts with the semiconductor material and the gate material. The oxidizing gas is, for example, oxygen or an inert gas. The inert gas is, for example, nitrogen, helium or argon. In some embodiments, the wet treatment is, for example, a wet treatment using a fluorine-containing solvent as an etchant, such as diluted hydrofluoric acid (DHF) or buffered oxide etch (BOE). However, the present invention is not limited thereto, and other etching liquids may be used for the wet processing. In some embodiments, during the third etch process, in addition to removing portions of the buffer material layer 121 on the opening 118, the portion of the buffer material 121 exposed in the portion of the lateral opening 120 is also removed. Specifically, after the exposed buffer material layer 121 is dry-treated, the surface of the dry-processed buffer material layer 121 becomes looser or amorphous than the plasma-free buffer material layer 121. Next, the dry-processed buffer material layer 121 is subjected to a wet treatment to remove a portion of the buffer material layer 121.

In particular, in the conventional process of avoiding interference between gates, the barrier material layer between the gates is removed to reduce the step residue between adjacent gates (ie, the barrier material layer) Residue), but there is still a small amount of step residue buried in the surface of the buffer material layer that is in contact with the barrier material layer. The above-mentioned step residue easily forms a leak path and a gate bridge, which causes interference between the gates and a short circuit. However, in the present invention, a third etching process is performed on the exposed buffer material layer to remove a portion of the buffer material layer while removing the step residue in the buffer material layer.

In some embodiments, the dry processing and the wet processing may be alternately repeated until the step string in the exposed buffer material layer 121 is completely removed. Further, after performing the third etching process on the exposed buffer material layer 121, the remaining portion of the buffer material layer 121 forms the buffer layer 121a. In some embodiments, alternating dry processing and wet processing may remove gate 124a, barrier layer 122a, buffer layer 121a by an amount greater than 1 angstrom.

In some embodiments, as shown in FIG. 1H, after the third etching process is performed on the exposed buffer material layer 121, the formed buffer layer 121a is continuously overlaid on the surface of the insulating layer 102a. In some embodiments, after the third etching process is performed on the exposed buffer material layer 121, the formed buffer layer 121a is discontinuously overlaid on the surface of the insulating layer 102a. In other embodiments, after the third etching process is performed on the exposed buffer material layer 121, the formed buffer layer 121a exposes a corner (not shown) of the insulating layer 102a, thereby blocking metal/metal oxidation. Physical connection between objects.

Referring to FIG. 1I, an insulating layer 128 is formed that covers the sidewalls of the opening 118 and fills the lateral opening 120. In some embodiments, the material of the insulating layer 128 is, for example, yttrium oxide. The method of forming the insulating layer 128 is, for example, a chemical vapor deposition method or an atomic layer deposition method (ALD). Next, an etching process is performed to remove the insulating layer 128 at the bottom of the opening 118. In some embodiments, a portion of the substrate 100 can be selectively removed after the insulating process is performed on the insulating layer 128. The barrier layer 130 and the metal layer 132 are sequentially filled in the opening 118. The material of the barrier layer 130 is, for example, titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or a combination thereof. A method of forming the barrier layer 130 is, for example, a chemical vapor deposition method. The material of the metal layer 132 is, for example, tungsten (W), polycrystalline germanium, cobalt, tungsten germanium (WSix) or cobalt telluride (CoSix). A method of forming the metal layer 132 is, for example, a chemical vapor deposition method. In some embodiments, metal layer 132 can serve as a common source line. So far, the fabrication of the three-dimensional non-volatile memory of the present invention has been completed.

Hereinafter, the structure of the three-dimensional non-volatile memory of the present invention will be described with reference to FIG. 1I. Further, although the method for manufacturing a three-dimensional non-volatile memory of the present embodiment has been described by taking the above method as an example, the method of forming the three-dimensional non-volatile memory of the present invention is not limited thereto. Fig. 3 is a partial enlarged view of a region A of Fig. 1I. Fig. 4 is a partial enlarged view of a region A of another embodiment.

1I, 3, and 4, the three-dimensional non-volatile memory includes a substrate 100, a charge storage structure 112, a stacked structure 127, and a channel layer 114. The stacked structure 127 and the charge storage structure 112 are disposed on the substrate 100, and the stacked structure 127 is disposed on one side of the charge storage structure 112. The stacked structure 127 includes a plurality of insulating layers 102a, a plurality of gates 124a, a buffer layer 121a, and a barrier layer 122a. The insulating layer 102a and the gate 124a are alternately stacked. The buffer layer 121a is disposed between each of the gates 124a and the charge storage structure 112 and disposed on the surface of the insulating layer 102a. The barrier layer 122a is disposed between each of the gates 124a and the buffer layer 121a. The channel layer 114 is disposed on the charge storage structure 112.

In some embodiments, the end E2 of the gate 124a is convex relative to the end E3 of the barrier layer 122a in a direction away from the channel layer 114. In some embodiments, the end E1 of the insulating layer 102a is at a distance L1 from the end portion E2 of the gate 124a in a direction perpendicular to the channel layer, and the end E1 of the insulating layer 102a is in a direction perpendicular to the channel layer. The distance of the end portion E3 of the barrier layer 122a is L2, and 1 < L2 / L1 < 2. In some embodiments, 50 Angstroms < L2−L1 < 400 Angstroms. In some embodiments, L1 is generally greater than 50 angstroms. In other embodiments, the end E3 of the barrier layer 122a has an inclined surface. Specifically, the end portion E3 of the barrier layer 122a has an inclined surface from the point of contact with the buffer material layer 121 toward the channel layer 114, as shown in FIG. In this case, the distance E1 of the end portion E1 of the insulating layer 102a in the direction perpendicular to the channel layer to the point where the end portion E3 is in contact with the buffer material layer 121 is L2.

In some embodiments, the buffer layer 121a includes a first portion 123 that is in contact with the barrier layer 122a and a second portion 125 that is not in contact with the barrier layer 122a, wherein the first portion 123 of the buffer layer 121a has a thickness T1, and the buffer layer 121a The second portion 125 has a thickness T2 and 0 < T1 − T2 ≦ 30 angstroms. In some embodiments, the second portion 125 of the buffer layer 121a is discontinuous. Specifically, the second portion 125 of the buffer layer 121a exposes a corner (not shown) of the insulating layer 102a, thereby blocking the physical connection between the metal/metal oxide.

In some embodiments, the atomic concentration of atoms in the second portion 125 of the buffer layer 121a containing the buffer layer 121a is less than 1 atomic percent.

In some embodiments, the three-dimensional non-volatile memory can further include a dielectric layer 115 and a conductor plug 116. The dielectric layer 115 is located at a lower portion of the opening 106, and the channel layer 114 surrounds the dielectric layer 115. The conductor plug 116 is located at an upper portion of the opening 106 and is in contact with the channel layer 114.

In summary, in the three-dimensional non-volatile memory of the above embodiment and the method of fabricating the same, the step residue remaining in the insulating layer is simultaneously removed by removing the insulating layer between the gates, thereby improving Interference between the gates and short-circuit problems during operation.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

100‧‧‧Base

101, 127‧‧‧ stacked structure

102, 121‧‧‧Insulation material layer

102a, 117‧‧‧ insulation

104‧‧‧ Sacrifice layer

106, 118‧‧‧ openings

109, 111, 135, 137, 139‧‧ ‧ yttrium oxide layer

110, 136, 138‧‧‧ tantalum nitride layer

112‧‧‧ Charge storage structure

114‧‧‧Channel layer

115‧‧‧ dielectric layer

116‧‧‧ Conductor plug

120‧‧‧ lateral opening

121‧‧‧buffer material layer

121a‧‧‧buffer layer

122‧‧‧Disability material layer

122a‧‧‧Barrier layer

123‧‧‧Part 1

124‧‧‧ gate material layer

124a‧‧‧ gate

125‧‧‧Part II

126‧‧ ‧ gate layer

128‧‧‧Insulation

130‧‧‧Barrier layer

132‧‧‧metal layer

A‧‧‧ area

E1, E2, E3‧‧‧ end

L1, L2‧‧‧ length

T1, T2‧‧‧ thickness

1A, 1B, 1B-1, and 1C-1I are cross-sectional views showing a manufacturing process of a three-dimensional non-volatile memory according to some embodiments of the present invention. Figure 2 is a top view of Figure 1B. Fig. 3 is a partial enlarged view of a region A of Fig. 1I. Fig. 4 is a partial enlarged view of a region A of another embodiment.

Claims (10)

A three-dimensional non-volatile memory, comprising: a substrate; a charge storage structure disposed on the substrate; a stacked structure disposed on one side of the charge storage structure, and comprising: a plurality of insulating layers and a plurality of gates, Wherein the insulating layer and the gate are alternately stacked; a buffer layer disposed between each gate and the charge storage structure and disposed on a surface of the insulating layer; and a barrier layer disposed in the Between each of the gates and the buffer layer; and a channel layer disposed on the other side of the charge storage structure, wherein an end of the gate is away from the channel layer with respect to an end of the barrier layer The direction is convex. The three-dimensional non-volatile memory according to claim 1, wherein an end of the insulating layer has a distance L1 from a direction perpendicular to the channel layer to an end of the gate, the insulating layer The distance of the end portion in the direction perpendicular to the channel layer to the end of the barrier layer is L2, and 1 < L2 / L1 < 2. The three-dimensional non-volatile memory according to claim 1, wherein a thickness of the first portion of the buffer layer in contact with the barrier layer is T1, and the buffer layer is not opposite to the barrier layer. The second portion of the contact has a thickness T2 and 0 < T1 − T2 ≦ 30 angstroms. The three-dimensional non-volatile memory of claim 3, wherein the second portion of the buffer layer is discontinuous. The three-dimensional non-volatile memory of claim 1, wherein the material of the barrier layer comprises titanium, titanium nitride, tantalum, tantalum nitride or a combination thereof. The three-dimensional non-volatile memory of claim 1, wherein the material of the buffer layer comprises a material having a high dielectric constant. A method of fabricating a three-dimensional non-volatile memory, comprising: forming a charge storage structure on a substrate and a stacked structure, the charge storage structure being disposed on a sidewall of the stacked structure, wherein the stacked structure comprises: a plurality of insulating layers And a plurality of gates, wherein the insulating layer and the gate are alternately stacked; a buffer layer disposed between each gate and the charge storage structure and disposed on a surface of the insulating layer; and a barrier a layer, configured between the gates and the buffer layer; and a channel layer formed on the charge storage structure, wherein an end of the gate is away from the end of the barrier layer The channel layer is convex in the direction. The method of manufacturing a three-dimensional non-volatile memory according to claim 8, wherein an end of the insulating layer has a distance L1 from a direction perpendicular to the channel layer to an end of the gate. The distance of the end portion of the insulating layer in the direction perpendicular to the channel layer to the end of the barrier layer is L2, and 1 < L2 / L1 < 2. The method of manufacturing a three-dimensional non-volatile memory according to claim 8, wherein a thickness of the first portion of the buffer layer in contact with the barrier layer is T1, and the buffer layer is not The thickness of the second portion of the barrier layer contact is T2, and 0 angstroms <T1−T2≦30 angstroms. The method of manufacturing a three-dimensional non-volatile memory according to claim 9, wherein the second portion of the buffer layer is discontinuous.