TW201929171A - Bond pad structure and manufacturing method thereof - Google Patents

Bond pad structure and manufacturing method thereof Download PDF

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Publication number
TW201929171A
TW201929171A TW107107509A TW107107509A TW201929171A TW 201929171 A TW201929171 A TW 201929171A TW 107107509 A TW107107509 A TW 107107509A TW 107107509 A TW107107509 A TW 107107509A TW 201929171 A TW201929171 A TW 201929171A
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metal layer
metal
pad structure
layer
layers
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TW107107509A
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TWI762597B (en
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熊險峰
宋征華
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大陸商合肥杰發科技有限公司
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165Reinforcing structures
    • H01L2224/02166Collar structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)

Abstract

A bond pad structure and a manufacturing method thereof are disclosed. The bond pad structure includes a first metal layer, and at least two second metal layers laminated successively on the first metal layer. Dielectric layers are provided between the first metal layer and the second metal layers, and between every two adjacent second metal layers. The first metal layer and the the second metal layer adjacent to the first metal layer are electrically connected to each other in a region outside the bonding pad structure. Every two adjacent second metal layers are electrically connected to each other. A manufacturing method of the bond pad structure is further disclosed. In this way, it may avoid pits generated by the bonding of copper wires having large sizes.

Description

接合墊結構及接合墊結構的製作方法 Bonding pad structure and manufacturing method of bonding pad structure

本發明涉及積體電路技術領域,特別是涉及一種接合墊結構及接合墊結構的製作方法。 The invention relates to the technical field of integrated circuits, in particular to a bonding pad structure and a manufacturing method of the bonding pad structure.

接合墊(Bond Pad)是介於容納在半導體晶片內的積體電路(Integrated Circuit,IC)及晶片封裝體之間的介面,用於傳送電力、接地及輸入/輸出訊號至晶片元件。引線鍵合(Wire Bonding,WB)是一種使用細金屬線,藉由熱、壓力、超聲波等能量使金屬引線與接合墊緊密焊合,實現晶片與外部的電氣互連和晶片間的資訊互通。 Bond pad is an interface between an integrated circuit (IC) contained in a semiconductor chip and a chip package, and is used to transmit power, ground, and input/output signals to chip components. Wire bonding (Wire Bonding, WB) is a kind of use of thin metal wires, through heat, pressure, ultrasound and other energy to make the metal leads and bonding pads tightly welded, to achieve electrical interconnection between the chip and the outside and information exchange between the chip.

結合第1圖所示,習知接合墊結構包括第一金屬層10,複數第二金屬層21-23,由金屬層間介電層(inter-metal dielectric layer,IMD)所隔離,各金屬層透過貫穿介電層的通孔(Via)40實現電性連接,目前銅線以其價格低廉、高可靠度及良好電導率和熱導率,相比其他材質使用同樣線徑可承受更大電流的優勢成為愈來愈多大功率器件的選擇,而當大尺寸銅線在接合墊上進行鍵合,所需鍵合力較大,該力度直接作用在接合墊的第一金屬層10時,容易在第一金屬層10與第二金 屬層21的通孔40之間形成凹坑,當凹坑嚴重時所有的通孔40和金屬層皆出現裂痕,對晶片的可靠度造成重大威脅,甚至導致晶片功能失效。 With reference to FIG. 1, the conventional bonding pad structure includes a first metal layer 10 and a plurality of second metal layers 21-23, separated by an inter-metal dielectric layer (IMD), each metal layer penetrates Via 40 penetrates through the dielectric layer to achieve electrical connection. At present, copper wires are inexpensive, highly reliable, and have good electrical and thermal conductivity. Compared with other materials, the same wire diameter can withstand larger currents. The advantage becomes the choice of more and more high-power devices, and when large-size copper wires are bonded on the bonding pads, the required bonding force is large. When the force directly acts on the first metal layer 10 of the bonding pad, it is easy to Metal layer 10 and second gold There are pits formed between the through holes 40 of the metal layer 21. When the pits are severe, all the through holes 40 and the metal layer are cracked, which poses a significant threat to the reliability of the chip and even causes the chip to fail.

本發明主要解決的技術問題是提供一種接合墊結構及接合墊結構的製作方法,在兼顧成本與性能的同時避免大尺寸銅鍵合線產生的凹坑問題。 The technical problem mainly solved by the present invention is to provide a bonding pad structure and a manufacturing method of the bonding pad structure, which can take into account both cost and performance while avoiding the pit problem caused by large-sized copper bonding wires.

為解決上述技術問題,本發明採用的一個技術方案是:提供一種接合墊結構,包括:第一金屬層;相對該第一金屬層依次層疊設置的至少兩第二金屬層;該第一金屬層與該第二金屬層之間及該第二金屬層之間設置有介電層;該第一金屬層及與該第一金屬層相鄰的第二金屬層在該接合墊結構區域外電性連接;該第二金屬層的相鄰兩層之間電性連接。 In order to solve the above technical problems, a technical solution adopted by the present invention is to provide a bonding pad structure including: a first metal layer; at least two second metal layers stacked in sequence with respect to the first metal layer; the first metal layer A dielectric layer is provided between the second metal layer and the second metal layer; the first metal layer and the second metal layer adjacent to the first metal layer are electrically connected outside the bonding pad structure area ; The second metal layer is electrically connected between two adjacent layers.

為解決上述技術問題,本發明採用的另一個技術方案是:提供一種接合墊結構的製作方法,包括:提供半導體晶片;相對該半導體晶片形成第一介電層;相對該第一介電層依次層疊形成至少兩第二金屬層,在該第二金屬層之間設置第二介電層;將該第二金屬層的相鄰兩層之間電性連接; 相對該第二金屬層形成第一金屬層,且在該第一金屬層與該第二金屬層之間設置第三介電層;在該接合墊結構區域外將該第一金屬層及與該第一金屬層相鄰的第二金屬層之間電性連接。 To solve the above technical problems, another technical solution adopted by the present invention is to provide a method for manufacturing a bonding pad structure, including: providing a semiconductor wafer; forming a first dielectric layer relative to the semiconductor wafer; and sequentially opposing the first dielectric layer Stacking to form at least two second metal layers, providing a second dielectric layer between the second metal layers; electrically connecting adjacent two layers of the second metal layer; A first metal layer is formed opposite to the second metal layer, and a third dielectric layer is provided between the first metal layer and the second metal layer; the first metal layer and the The second metal layer adjacent to the first metal layer is electrically connected.

本發明的有益效果是:區別于習知技術的情況,本發明透過在該接合墊結構區域外將該第一金屬層及與該第一金屬層相鄰的第二金屬層之間電性連接,從而避免大尺寸銅鍵合線產生的凹坑問題。 The beneficial effects of the present invention are: different from the case of the conventional technology, the present invention electrically connects the first metal layer and the second metal layer adjacent to the first metal layer outside the bonding pad structure area In order to avoid the pit problem caused by large-size copper bonding wires.

10‧‧‧第一金屬層 10‧‧‧First metal layer

21、22、23‧‧‧第二金屬層 21, 22, 23‧‧‧Second metal layer

31‧‧‧第一介電層 31‧‧‧First dielectric layer

32‧‧‧第二介電層 32‧‧‧Second dielectric layer

33‧‧‧第三介電層 33‧‧‧third dielectric layer

40‧‧‧第二通孔 40‧‧‧Second through hole

50‧‧‧鈍化層 50‧‧‧passivation layer

60‧‧‧半導體晶片 60‧‧‧Semiconductor chip

S1至S6‧‧‧步驟 S1 to S6‧‧‧ steps

第1圖是習知的設置於半導體晶片上接合墊結構的截面示意圖;第2圖是本發明第一實施例接合墊結構的金屬層立體結構示意圖;第3圖是本發明第二實施例接合墊結構的金屬層立體結構示意圖;第4圖是本發明第三實施例接合墊結構的金屬層立體結構示意圖;第5圖是本發明第三實施例接合墊結構的金屬層設置於半導體晶片上的截面結構示意圖;第6圖是本發明第四實施例接合墊結構的金屬層立體結構示意圖;第7圖是本發明第五實施例接合墊結構的金屬層設置於半導體晶片上的截面結構示意圖; 第8圖是本發明接合墊結構的製作方法流程示意圖。 FIG. 1 is a schematic cross-sectional view of a conventional bonding pad structure provided on a semiconductor wafer; FIG. 2 is a schematic view of a three-dimensional structure of a metal layer of a bonding pad structure according to a first embodiment of the invention; FIG. 3 is a bonding according to a second embodiment of the invention 3D schematic diagram of the metal layer of the pad structure; FIG. 4 is a schematic diagram of the metal layer of the bonding pad structure of the third embodiment of the present invention; FIG. 5 is a metal layer of the bonding pad structure of the third embodiment of the present invention provided on a semiconductor wafer 6 is a schematic diagram of a three-dimensional structure of a metal layer of a bonding pad structure according to a fourth embodiment of the invention; FIG. 7 is a schematic diagram of a sectional structure of a metal layer of a bonding pad structure according to a fifth embodiment of the invention provided on a semiconductor wafer ; FIG. 8 is a schematic flow chart of the manufacturing method of the bonding pad structure of the present invention.

下面結合附圖和實施例對本發明進行詳細的說明。 The present invention will be described in detail below with reference to the drawings and embodiments.

請參閱第2圖,是本發明第一實施例接合墊結構的金屬層立體結構示意圖(沿第2圖中虛線a縱截),該接合墊結構位於半導體晶片60上,包括:第一金屬層10;相對該第一金屬層10依次層疊設置的至少兩個第二金屬層(在本實施例中,包括三個第二金屬層,分別為第二金屬層21,第二金屬層22,第二金屬層23,在其他實施例中,該第二金屬層的數量可以根據需要進行設置);該第一金屬層10與該第二金屬層21之間及該第二金屬層21-23之間均設置有介電層;該接合墊結構區域外設置第一通孔(圖中未標出),該第一通孔透過導線將該第一金屬層10及與該第一金屬層相鄰的第二金屬層21連接,實現該第一金屬層10與該第一金屬層相鄰的第二金屬層21的電性連接。 Please refer to FIG. 2, which is a schematic view of a three-dimensional structure of a metal layer of a bonding pad structure according to a first embodiment of the present invention (a longitudinal section along dotted line a in FIG. 2 ). The bonding pad structure is located on a semiconductor wafer 60 and includes: a first metal layer 10; at least two second metal layers stacked in sequence with respect to the first metal layer 10 (in this embodiment, including three second metal layers, respectively a second metal layer 21, a second metal layer 22, the first Two metal layers 23, in other embodiments, the number of the second metal layer can be set as needed); between the first metal layer 10 and the second metal layer 21 and between the second metal layers 21-23 A dielectric layer is provided between the two; a first through hole (not shown in the figure) is provided outside the bonding pad structure area, and the first through hole connects the first metal layer 10 and the first metal layer through the wire The second metal layer 21 is connected to achieve electrical connection between the first metal layer 10 and the second metal layer 21 adjacent to the first metal layer.

該第二金屬層21-23的相鄰兩層之間透過第二通孔40電性連接。 The adjacent two layers of the second metal layers 21-23 are electrically connected through the second through holes 40.

在該接合墊結構的第一金屬層10上設置鈍化層50,且該鈍化層50覆蓋該第一金屬層10的邊緣而將第一金屬層10的中間位置暴露,以對接合墊結構進行保護。 A passivation layer 50 is provided on the first metal layer 10 of the bonding pad structure, and the passivation layer 50 covers the edge of the first metal layer 10 to expose the middle position of the first metal layer 10 to protect the bonding pad structure .

本實施例中,該第一金屬層10及該第二金屬層21-23的材質為鋁(Al);該介電層31-33為氮化矽(SiNx);該第二通孔40內的導電材料為鎢(W)。 In this embodiment, the materials of the first metal layer 10 and the second metal layers 21-23 are aluminum (Al); the dielectric layers 31-33 are silicon nitride (SiNx); and the second through holes 40 The conductive material is tungsten (W).

當大尺寸(如1.8mil)銅線(在其他實施例中並不限定為銅線)在該接合墊結構上進行鍵合時,該第一金屬層10和該第二金屬層21之間的第一介電層可以大面積承受鍵合帶來的應力,讓銅鍵合線鍵合時產生的衝擊力均勻分散到每一第二金屬層21-23上。 When a large-size (such as 1.8 mil) copper wire (not limited to copper wire in other embodiments) is bonded on the bonding pad structure, between the first metal layer 10 and the second metal layer 21 The first dielectric layer can withstand the stress caused by the bonding in a large area, so that the impact force generated when the copper bonding wire is bonded is evenly distributed to each second metal layer 21-23.

請參閱第3圖,是本發明第二實施例接合墊結構的金屬層立體結構示意圖(沿第3圖中虛線a縱截),該接合墊結構位於半導體晶片60上,與第2圖的區別在於:本實施例中,該第二金屬層21分割為複數條狀金屬(在其他實施例中可為其他某一第二金屬層分割為條狀金屬),該每一第二金屬層21上的金屬條的總面積小於對應該第二金屬層總面積,具體的,該每一第二金屬層21上的金屬條的總面積小於對應該第二金屬層總面積的60%。 Please refer to FIG. 3, which is a schematic diagram of a three-dimensional structure of a metal layer of a bonding pad structure according to a second embodiment of the present invention (a longitudinal section along dotted line a in FIG. 3). The bonding pad structure is located on a semiconductor wafer 60, which is different from FIG. 2 In this embodiment, the second metal layer 21 is divided into a plurality of strip-shaped metals (in other embodiments, it can be divided into strip-shaped metals by some other second metal layer), and on each second metal layer 21 The total area of the metal strips is less than the total area corresponding to the second metal layer. Specifically, the total area of the metal strips on each second metal layer 21 is less than 60% of the total area corresponding to the second metal layer.

當大尺寸(如1.8mil)銅線(在其他實施例中並不限定為銅線)在該接合墊結構上進行鍵合時,該第一金屬層10和該第二金屬層21之間的第一介電層可以大面積承受鍵合帶來的應力,讓銅鍵合線鍵合時產生的衝擊力均勻分散到第二金屬層21上,沿第二金屬層21上的金屬條分散,由於該每一第二金屬層21上的金屬條的總面積占對應該第二金屬層總面積小於60%,使得衝擊力分散到相鄰兩層之間的介電層上。 When a large-size (such as 1.8 mil) copper wire (not limited to copper wire in other embodiments) is bonded on the bonding pad structure, between the first metal layer 10 and the second metal layer 21 The first dielectric layer can withstand the stress caused by bonding in a large area, so that the impact force generated when the copper bonding wire is bonded is evenly distributed to the second metal layer 21 and along the metal strips on the second metal layer 21, Since the total area of the metal strips on each second metal layer 21 accounts for less than 60% of the total area of the corresponding second metal layer, the impact force is dispersed on the dielectric layer between two adjacent layers.

請參閱第4圖及第5圖,第4圖是本發明第三實施例接合墊結構的金屬層立體結構示意圖,結合第5圖,第5圖是本發明第三實施例接合墊結構的金屬層設置於半導體晶片上的截面結構示意圖(沿第4圖中虛線a縱截),該接合墊結構位於半導體晶片60上,與第3圖的區別在於:本實施例中,該第二金屬層21-23均分割為複數條狀金屬。 Please refer to FIG. 4 and FIG. 5, FIG. 4 is a three-dimensional schematic diagram of the metal layer of the bonding pad structure of the third embodiment of the present invention. Combined with FIG. 5, FIG. 5 is a metal of the bonding pad structure of the third embodiment of the present invention Schematic diagram of the cross-sectional structure of the layer disposed on the semiconductor wafer (longitudinal line along the dotted line a in FIG. 4), the bonding pad structure is located on the semiconductor wafer 60, and the difference from FIG. 3 is that in this embodiment, the second metal layer 21-23 are divided into multiple strips of metal.

該第二金屬層21及22上的金屬條在同一平面內的投影相交,且相交處透過第二通孔40將該第二金屬層21與22電性連接,同時該第二金屬層22及23上的金屬條在同一平面內的投影相交,且相交處透過第二通孔40將該第二金屬層22與23電性連接。 The projections of the metal strips on the second metal layers 21 and 22 in the same plane intersect, and the second metal layers 21 and 22 are electrically connected through the second through hole 40 at the intersection, and the second metal layer 22 and 22 The projections of the metal strips on 23 in the same plane intersect, and the second metal layer 22 and 23 are electrically connected through the second through hole 40 at the intersection.

具體地,該第二金屬層21-23中的相鄰兩個上的金屬條在同一平面內的投影垂直相交,即在同一平面內的投影,第二金屬層21上的金屬條垂直第二金屬層22上的金屬條,第二金屬層22上的金屬條垂直第二金屬層23上的金屬條,且每相鄰兩第二金屬層21-23上金屬條投影相交處透過第二通孔40將第二金屬層21-23中的相鄰兩個金屬層電性連接(在本實施例中每相鄰兩第二金屬層上金屬條所有投影相交處均設置第二通孔,在其他實施例中可在每相鄰兩第二金屬層上金屬條部分投影相交處設置第二通孔,亦可在每相鄰兩第二金屬層其他位置設置第二通孔,將相鄰兩第二金屬層電性連接)。 Specifically, the projections of the metal strips on adjacent two of the second metal layers 21-23 in the same plane intersect vertically, that is, the projections in the same plane, the metal strips on the second metal layer 21 are perpendicular to the second The metal strips on the metal layer 22, the metal strips on the second metal layer 22 are perpendicular to the metal strips on the second metal layer 23, and the projected intersections of the metal strips on every two adjacent second metal layers 21-23 pass through the second pass The hole 40 electrically connects two adjacent metal layers in the second metal layers 21-23 (in this embodiment, a second through hole is provided at all the intersections of the metal strips on each adjacent two second metal layers. In other embodiments, a second through hole may be provided at the projected intersection of the metal strips on each adjacent two second metal layers, or a second through hole may be provided at other positions of each adjacent two second metal layers to connect the adjacent two The second metal layer is electrically connected).

具體的,兩間隔設置的第二金屬層如該第二金屬層21和23上的金屬條在同一平面的投影重合(在其他實施例 中兩間隔設置的第二金屬層上的金屬條在同一平面的投影可不重合)。 Specifically, the projections of the second metal layers disposed at two intervals, such as the metal strips on the second metal layers 21 and 23, coincide on the same plane (in other embodiments (The projections of the metal strips on the second metal layer spaced apart in the middle on the same plane may not overlap).

本實施例中,該每一第二金屬層21-23上的金屬條的總面積小於對應該第二金屬層總面積,具體的,該每一第二金屬層21-23上的金屬條的總面積小於對應該第二金屬層總面積的60%。 In this embodiment, the total area of the metal strips on each second metal layer 21-23 is smaller than the total area of the corresponding second metal layer. Specifically, the metal strips on each second metal layer 21-23 The total area is less than 60% of the total area corresponding to the second metal layer.

當大尺寸(如1.8mil)銅線(在其他實施例中並不限定為銅線)在該接合墊結構上進行鍵合時,該第一金屬層10和該第二金屬層21之間的第一介電層31可以大面積承受鍵合帶來的應力,讓銅鍵合線鍵合時產生的衝擊力均勻分散到每一第二金屬層21-23上,之後再沿第二金屬層21-23上的金屬條垂直相交的X,Y軸分散,由於該每一第二金屬層21-23上的金屬條的總面積占對應該第二金屬層總面積小於60%,使得衝擊力分散到相鄰兩層之間的介電層31-33上。 When a large-size (such as 1.8 mil) copper wire (not limited to copper wire in other embodiments) is bonded on the bonding pad structure, between the first metal layer 10 and the second metal layer 21 The first dielectric layer 31 can withstand the stress caused by bonding in a large area, so that the impact force generated when the copper bonding wire is bonded is evenly distributed on each second metal layer 21-23, and then along the second metal layer The vertical intersecting X, Y axis of the metal strips on 21-23 is dispersed. Since the total area of the metal strips on each second metal layer 21-23 accounts for less than 60% of the total area of the corresponding second metal layer, the impact force Dispersed on the dielectric layers 31-33 between two adjacent layers.

請參閱第6圖,是本發明第四實施例接合墊結構的金屬層立體結構示意圖,與第5圖的區別在於:在該相鄰兩第二金屬層間設置第二通孔40電性連接,層與層間的第二通孔40對應間隔排布,如第二金屬層21和22之間設置的兩相鄰第二通孔41和42,第二金屬層22和23之間設置的第二通孔43與該第二通孔41和42在同一平面內的投影位於該第二通孔41和42之間。 Please refer to FIG. 6, which is a schematic view of a three-dimensional structure of a metal layer of a bonding pad structure according to a fourth embodiment of the present invention. The difference from FIG. 5 is that a second through hole 40 is electrically connected between two adjacent second metal layers. The second through holes 40 between the layers are arranged correspondingly at intervals, such as two adjacent second through holes 41 and 42 provided between the second metal layers 21 and 22, and the second between the second metal layers 22 and 23 The projection of the through hole 43 and the second through holes 41 and 42 in the same plane is between the second through holes 41 and 42.

請參閱第7圖,是本發明第五實施例接合墊結構的金屬層設置於半導體晶片上的截面結構示意圖(沿垂直於虛 線a方向縱截),該接合墊結構位於半導體晶片60上,與第5圖的區別在於:兩間隔設置的第二金屬層如該第二金屬層21和23上的金屬條在同一平面的投影不重合,如該第二金屬層21上的兩個金屬條211與212平行,在同一投影平面上,第二金屬層23上的金屬條231在金屬條211與金屬條212之間。 Please refer to FIG. 7, which is a schematic view of the cross-sectional structure of the metal layer of the bonding pad structure provided on the semiconductor wafer according to the fifth embodiment of the present invention Vertical line a), the bonding pad structure is located on the semiconductor wafer 60, the difference from FIG. 5 is that two spaced apart second metal layers such as the metal strips on the second metal layers 21 and 23 are on the same plane The projections do not coincide. For example, the two metal strips 211 and 212 on the second metal layer 21 are parallel. On the same projection plane, the metal strip 231 on the second metal layer 23 is between the metal strip 211 and the metal strip 212.

請參閱第8圖,是本發明接合墊結構的製作方法流程示意圖,包括: Please refer to FIG. 8, which is a schematic flowchart of the method for manufacturing the bonding pad structure of the present invention, including:

步驟S1:提供半導體晶片60。 Step S1: A semiconductor wafer 60 is provided.

該半導體晶片為矽(Si)。 The semiconductor wafer is silicon (Si).

步驟S2:相對該半導體晶片60形成第一介電層31。 Step S2: Form a first dielectric layer 31 relative to the semiconductor wafer 60.

透過旋轉塗布的方式沉積介電材料於該半導體晶片60上,形成第一介電層31,本實施例中,該介電材料為氮化矽(SiNx)。 A dielectric material is deposited on the semiconductor wafer 60 by spin coating to form a first dielectric layer 31. In this embodiment, the dielectric material is silicon nitride (SiNx).

步驟S3:相對該第一介電層31依次層疊形成至少兩第二金屬層(在本實施例中,包括三個第二金屬層,分別為第二金屬層21,第二金屬層22,第二金屬層23,在其他實施例中,該第二金屬層的數量可以根據需要進行設置),在該第二金屬層21-23之間設置第二介電層32。 Step S3: Relative to the first dielectric layer 31 is sequentially stacked to form at least two second metal layers (in this embodiment, it includes three second metal layers, namely a second metal layer 21, a second metal layer 22, a second The second metal layer 23, in other embodiments, the number of the second metal layer can be set as needed), and a second dielectric layer 32 is provided between the second metal layers 21-23.

具體的,該第二金屬層21-23均分割為複數條狀金屬。該第二金屬層21及22上的金屬條在同一平面內的投影相交,同時該第二金屬層22及23上的金屬條在同一平面內的投影相交。 Specifically, the second metal layers 21-23 are all divided into a plurality of strip-shaped metals. The projections of the metal strips on the second metal layers 21 and 22 in the same plane intersect, and the projections of the metal strips on the second metal layers 22 and 23 in the same plane intersect.

具體地,該第二金屬層21-23中的相鄰兩個上的金屬條在同一平面內的投影垂直相交,即在同一平面內的投影,第二金屬層21上的金屬條垂直第二金屬層22上的金屬條,第二金屬層22上的金屬條垂直第二金屬層23上的金屬條。 Specifically, the projections of the metal strips on adjacent two of the second metal layers 21-23 in the same plane intersect vertically, that is, the projections in the same plane, the metal strips on the second metal layer 21 are perpendicular to the second The metal strip on the metal layer 22 and the metal strip on the second metal layer 22 are perpendicular to the metal strip on the second metal layer 23.

具體的,兩間隔設置的第二金屬層如該第二金屬層21和23上的金屬條在同一平面的投影重合(在其他實施例中兩間隔設置的第二金屬層上的金屬條在同一平面的投影可不重合)。 Specifically, the second metal layers disposed at two intervals, such as the projections of the metal strips on the second metal layers 21 and 23 on the same plane, overlap (in other embodiments, the metal strips on the second metal layers disposed at the two intervals are the same (The plane projections may not coincide.)

透過旋轉塗布的方式沉積該第二金屬層23於該第一介電層31上,透過蝕刻的方法使第二金屬層23為平行條狀分佈,之後沉積介電材料於該第二金屬層23上,形成第二介電層32,之後再沉積該第二金屬層22於該第二介電層32上,蝕刻第二金屬層22呈平行條狀分佈,之後再沉積介電材料於該第二金屬層22上,形成第二介電層32,之後再沉積該第二金屬層21於該第二介電層32上,蝕刻第二金屬層21呈平行條狀分佈,其中,第二金屬層21-23上的金屬條在同一平面內的投影垂直相交,即在同一平面內的投影,第二金屬層21上的金屬條垂直第二金屬層22上的金屬條,第二金屬層22上的金屬條垂直第二金屬層23上的金屬條。當大尺寸銅線在該接合墊結構的第一金屬層10上進行鍵合時,每一第二金屬層21-23所受衝擊力可沿第二金屬層21-23中的相鄰兩個金屬層上的金屬條垂直相交的X,Y軸分散。 The second metal layer 23 is deposited on the first dielectric layer 31 by spin coating, the second metal layer 23 is distributed in parallel strips by etching, and then the dielectric material is deposited on the second metal layer 23 The second dielectric layer 32 is formed, and then the second metal layer 22 is deposited on the second dielectric layer 32, the second metal layer 22 is etched to be distributed in parallel stripes, and then the dielectric material is deposited on the first A second dielectric layer 32 is formed on the two metal layers 22, and then the second metal layer 21 is deposited on the second dielectric layer 32, and the second metal layer 21 is etched to be distributed in parallel stripes, wherein the second metal The projections of the metal strips on the layers 21-23 in the same plane intersect vertically, that is, the projections in the same plane, the metal strips on the second metal layer 21 are perpendicular to the metal strips on the second metal layer 22, the second metal layer 22 The upper metal strip is perpendicular to the metal strip on the second metal layer 23. When a large-sized copper wire is bonded on the first metal layer 10 of the bonding pad structure, the impact force of each second metal layer 21-23 can be along the adjacent two of the second metal layers 21-23 The metal strips on the metal layer intersect the X and Y axes that intersect vertically.

本實施例中,該第一金屬層10及該第二金屬層21-23的材質為鋁(Al)。 In this embodiment, the materials of the first metal layer 10 and the second metal layers 21-23 are aluminum (Al).

步驟S4:將該第二金屬層21-23的相鄰兩層之間電性連接。 Step S4: electrically connect two adjacent layers of the second metal layer 21-23.

具體的,在該第二金屬層21-23的每相鄰兩層上的金屬條在同一平面內的投影相交處設置第二通孔40將該相鄰兩第二金屬層21-23電性連接(在本實施例中每相鄰兩第二金屬層上金屬條所有投影相交處均設置第二通孔,在其他實施例中可在每相鄰兩第二金屬層上金屬條部分投影相交處設置通孔,亦可在每相鄰兩第二金屬層其他位置設置第二通孔,將相鄰兩第二金屬層電性連接)。 Specifically, a second through hole 40 is provided at the intersection of the projections of the metal strips on each adjacent two layers of the second metal layer 21-23 in the same plane to electrically connect the two adjacent second metal layers 21-23 Connection (in this embodiment, a second through hole is provided at all projected intersections of the metal strips on every two adjacent second metal layers, in other embodiments, the metal strips on each adjacent two second metal layers can be projected to intersect Through holes are provided at each location, and second through holes can also be provided at other positions of each adjacent two second metal layers to electrically connect the two adjacent second metal layers).

具體的,該第二通孔40可以透過鎢插塞工藝形成。 Specifically, the second through hole 40 may be formed through a tungsten plug process.

在其他實施例中,該第二金屬層間的電性連接可以透過在同一連接點處,設置複數個導線連接,將相鄰兩金屬層電性連接,該等導線除具有導電性能外,還可以實現相鄰兩金屬層之間的支撐作用。 In other embodiments, the electrical connection between the second metal layers can be established by connecting a plurality of wires at the same connection point to electrically connect two adjacent metal layers. In addition to the conductive properties, the wires can also To achieve the support between two adjacent metal layers.

步驟S5:相對該第二金屬層21-23形成第一金屬層10,且在該第一金屬層10與該第二金屬層21-23之間設置第三介電層33。 Step S5: A first metal layer 10 is formed relative to the second metal layers 21-23, and a third dielectric layer 33 is provided between the first metal layer 10 and the second metal layers 21-23.

透過旋轉塗布的方式沉積介電材料於該第二金屬層21上,形成第三介電層33,再沉積該第一金屬層10於該第三介電層33上,該第一金屬層10和該第二金屬層21之間的第三介電層33可以大面積承受鍵合帶來的衝擊力。 A dielectric material is deposited on the second metal layer 21 by spin coating to form a third dielectric layer 33, and then the first metal layer 10 is deposited on the third dielectric layer 33, the first metal layer 10 The third dielectric layer 33 between the second metal layer 21 and the second metal layer 21 can withstand the impact force caused by the bonding in a large area.

步驟S6:在該接合墊結構區域外將該第一金屬層10及與該第一金屬層相鄰的第二金屬層21之間電性連接。 Step S6: electrically connecting the first metal layer 10 and the second metal layer 21 adjacent to the first metal layer outside the bonding pad structure area.

具體的,在該接合墊結構區域外設置第一通孔(圖中未標出),該第一通孔透過導線將該第一金屬層10及與該第一金屬層相鄰的第二金屬層21連接,實現該第一金屬層10與該第一金屬層相鄰的第二金屬層21的電性連接。 Specifically, a first through hole (not shown in the figure) is provided outside the bonding pad structure area, the first through hole connects the first metal layer 10 and the second metal adjacent to the first metal layer through a wire The layer 21 is connected to achieve electrical connection between the first metal layer 10 and the second metal layer 21 adjacent to the first metal layer.

在該接合墊結構的第一金屬層10上設置鈍化層50,且該鈍化層50覆蓋該第一金屬層10的邊緣而將該第一金屬層的中間位置暴露,以對接合墊結構進行保護。 A passivation layer 50 is provided on the first metal layer 10 of the bonding pad structure, and the passivation layer 50 covers the edge of the first metal layer 10 and exposes the middle position of the first metal layer to protect the bonding pad structure .

本實施例中,該每一第二金屬層21-23上的金屬條的總面積占對應該第二金屬層總面積的比例小於60%(如第二金屬層21上的金屬條的總面積占該第二金屬層21總面積的比例小於60%),使得衝擊力分散到相鄰兩第二金屬層的介電層31-33上。 In this embodiment, the ratio of the total area of the metal strips on each second metal layer 21-23 to the total area of the corresponding second metal layer is less than 60% (such as the total area of the metal strips on the second metal layer 21 The proportion of the total area of the second metal layer 21 is less than 60%), so that the impact force is dispersed on the dielectric layers 31-33 of the two adjacent second metal layers.

本發明透過層疊設置至少兩第二金屬層且將每一第二金屬層分割為複數平行的金屬條,並且相鄰兩第二金屬層上的金屬條在同一平面內的投影垂直相交,垂直相交處將該相鄰兩第二金屬層電性連接,且該第二金屬層上的金屬條的總面積占對應該第二金屬層總面積比例小於60%,在該第一金屬層與該第二金屬層之間的結合墊結構區域外電性連接,從而使得大尺寸銅線鍵合至該第一金屬層上時作用于接合墊結構上的衝擊力得以分散,實現在兼顧成本與性能的同時避免大尺寸銅鍵合線產生的凹坑問題。 According to the present invention, at least two second metal layers are stacked and each second metal layer is divided into a plurality of parallel metal strips, and the projections of the metal strips on the adjacent two second metal layers in the same plane intersect vertically and intersect vertically The two adjacent second metal layers are electrically connected, and the total area of the metal strips on the second metal layer accounts for less than 60% of the total area of the corresponding second metal layer. In the first metal layer and the first metal layer Electrical connection outside the bonding pad structure area between the two metal layers, so that the impact force on the bonding pad structure when the large-size copper wire is bonded to the first metal layer is dispersed, achieving both cost and performance Avoid the pit problem caused by large-size copper bonding wires.

以上該僅為本發明的實施方式,並非因此限制本發明的專利範圍,凡是藉由本發明說明書及附圖內容所作的等 效結構或等效流程變換,或直接或間接運用在其他相關的技術領域,均同理包括在本發明的專利保護範圍內。 The above are only the embodiments of the present invention, and therefore do not limit the patent scope of the present invention. Anything made by the description and drawings of the present invention Effective structure or equivalent process transformation, or direct or indirect application in other related technical fields, are also included in the patent protection scope of the present invention.

Claims (10)

一種接合墊結構,包括:第一金屬層;相對該第一金屬層依次層疊設置的至少兩第二金屬層;該第一金屬層與該第二金屬層之間及該第二金屬層之間設置有介電層;該第一金屬層及與該第一金屬層相鄰的第二金屬層在該接合墊結構區域外電性連接;該第二金屬層的相鄰兩層之間電性連接。 A bonding pad structure includes: a first metal layer; at least two second metal layers stacked in sequence with respect to the first metal layer; between the first metal layer and the second metal layer and between the second metal layer A dielectric layer is provided; the first metal layer and the second metal layer adjacent to the first metal layer are electrically connected outside the bonding pad structure area; the two adjacent metal layers are electrically connected between two adjacent layers . 根據申請專利範圍第1項所述之接合墊結構,其中,該第二金屬層中至少一層分割為複數條狀金屬。 The bonding pad structure according to item 1 of the patent application scope, wherein at least one layer of the second metal layer is divided into a plurality of strip-shaped metals. 根據申請專利範圍第2項所述之接合墊結構,其中,與該第一金屬層相鄰的第二金屬層分割為複數條狀金屬。 The bonding pad structure according to item 2 of the patent application scope, wherein the second metal layer adjacent to the first metal layer is divided into a plurality of strip-shaped metals. 根據申請專利範圍第2項所述之接合墊結構,其中,所有該第二金屬層分割為複數條狀金屬。 The bonding pad structure according to item 2 of the patent application scope, wherein all the second metal layers are divided into a plurality of strip-shaped metals. 根據申請專利範圍第4項所述之接合墊結構,其中,該第二金屬層的相鄰兩層上的金屬條在同一平面內的投影相交。 The bonding pad structure according to item 4 of the patent application scope, wherein the projections of the metal strips on adjacent two layers of the second metal layer in the same plane intersect. 根據申請專利範圍第5項所述之接合墊結構,其中,該第二金屬層的相鄰兩層上的金屬條在同一平面內的投影垂直相交。 The bonding pad structure according to item 5 of the patent application scope, wherein the projections of the metal strips on adjacent two layers of the second metal layer in the same plane intersect perpendicularly. 根據申請專利範圍第6項所述之接合墊結構,其中,該第二金屬層的相鄰兩層上的金屬條在同一平面內的投影相交處將該相鄰兩第二金屬層電性連接。 The bonding pad structure according to item 6 of the patent application scope, wherein the metal strips on adjacent two layers of the second metal layer electrically connect the adjacent two second metal layers at the intersection of projections in the same plane . 根據申請專利範圍第2項所述之接合墊結構,其中,該每一第二金屬層上的金屬條的總面積占對應該第二金屬層總面積一定比例。 The bonding pad structure according to item 2 of the patent application scope, wherein the total area of the metal strips on each second metal layer accounts for a certain proportion of the total area of the corresponding second metal layer. 根據申請專利範圍第1項所述之接合墊結構,其中,在該接合墊結構的第一金屬層上設置鈍化層,且該鈍化層覆蓋該第一金屬層的邊緣而將該第一金屬 層的中間位置暴露,以對接合墊結構進行保護。 The bonding pad structure according to item 1 of the patent application scope, wherein a passivation layer is provided on the first metal layer of the bonding pad structure, and the passivation layer covers the edge of the first metal layer to connect the first metal The middle of the layer is exposed to protect the bond pad structure. 一種接合墊結構的製作方法,包括:提供半導體晶片;相對該半導體晶片形成第一介電層;相對該第一介電層依次層疊形成至少兩第二金屬層,在該第二金屬層之間設置第二介電層;將該第二金屬層的相鄰兩層之間電性連接;相對該第二金屬層形成第一金屬層,且在該第一金屬層與該第二金屬層之間設置第三介電層;在該接合墊結構區域外將該第一金屬層及與該第一金屬層相鄰的第二金屬層之間電性連接。 A method for manufacturing a bonding pad structure includes: providing a semiconductor wafer; forming a first dielectric layer relative to the semiconductor wafer; sequentially stacking at least two second metal layers relative to the first dielectric layer, between the second metal layers Providing a second dielectric layer; electrically connecting two adjacent layers of the second metal layer; forming a first metal layer opposite to the second metal layer, and between the first metal layer and the second metal layer A third dielectric layer is provided between them; the first metal layer and the second metal layer adjacent to the first metal layer are electrically connected outside the bonding pad structure area.
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