TW201929098A - Fabrication method of circuit components for matrix-batch die package for fabricating circuit components in matrix batches with high efficiency and at low cost - Google Patents

Fabrication method of circuit components for matrix-batch die package for fabricating circuit components in matrix batches with high efficiency and at low cost Download PDF

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TW201929098A
TW201929098A TW106144126A TW106144126A TW201929098A TW 201929098 A TW201929098 A TW 201929098A TW 106144126 A TW106144126 A TW 106144126A TW 106144126 A TW106144126 A TW 106144126A TW 201929098 A TW201929098 A TW 201929098A
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electrode
circuit component
die
component
vertical
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TW106144126A
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Chinese (zh)
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胡志良
胡哲愷
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胡志良
胡哲愷
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Priority to TW106144126A priority Critical patent/TW201929098A/en
Priority to CN201811532954.1A priority patent/CN109979825A/en
Priority to US16/220,868 priority patent/US11521862B2/en
Publication of TW201929098A publication Critical patent/TW201929098A/en

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Abstract

Provided is method for batch fabrication of circuit component through simultaneously packaging multiple units of component die in a matrix form of multiple-unit. The component die includes at least two electrodes, wherein at least one electrode is disposed on the top surface of the component die, and the remaining electrode or electrodes are disposed on the bottom surface of opposite component die correspondingly. In the method, each electrode of the component die packaged and protected in each circuit component is electrically connected to a corresponding terminal electrode of the circuit component package. The method comprises the steps of: forming a preparative structure of at least two terminal electrodes for each circuit component in the matrix on a copper matrix substrate; then, for each circuit component, picking and placing a component die, so that the electrode on the bottom surface of the die faces the surface of a preparative structure of a corresponding terminal electrode in the preparative structure of at least two terminal electrodes of the copper matrix substrate; then, for each circuit component, picking and placing a horizontal conductor plate having a bottom connection surface on the horizontal side oppositely disposed to the electrode on the top surface of the component die; then, for each circuit component, picking and placing a vertical conductor block including an upper end placed into a vertical connection hole at the other horizontal side of the horizontal conductor plate, and a vertical connection surface oppositely connected with the upper end of the vertical conductor block, wherein a bottom connection surface of a lower end of the vertical conductor block is oppositely placed on the surface of the preparative structure of the corresponding terminal electrode in the preparative structure of at least two terminal electrodes of the copper matrix substrate; and finally, performing a thermal reflow to simultaneously melt: the soldering material pre-applied between the electrode on the bottom surface of the die and the surface of the preparative structure of the terminal electrode of the corresponding copper matrix substrate; the soldering material pre-applied between the bottom connection surface of the horizontal conductor plate and the electrode on the top surface of the corresponding die; the soldering material pre-applied between the top end of the vertical conductor block and the vertical connection surface in the vertical connection hole of the corresponding horizontal conductor plate; and the soldering material pre-applied between the bottom connection surface of the lower end of the vertical conductor block and the surface of the preparative structure of the corresponding terminal electrode of the copper matrix substrate. Then solder the same.

Description

陣列批次式封裝元件晶粒之電路元件製作方法 Circuit component manufacturing method for array batch package component die

本發明係有關於半導體電路元件之封裝體及封裝方法,特別是有關於需求較大功率,良好熱散的表面黏著電路元件之封裝體及封裝方法。本發明更係有關於以多單位之陣列形態,同時封裝多個單位之電路元件晶粒以批次方式,有效率且高良率地製作電路元件之方法。 The present invention relates to a package and a package method for a semiconductor circuit component, and more particularly to a package and a package method for a surface mount circuit component requiring high power and good heat dissipation. More particularly, the present invention relates to a method of fabricating circuit elements in a multi-unit array form while packaging a plurality of units of circuit element dies in a batch manner, efficiently and with high yield.

目前諸如二極體、發光二極體、電晶體及閘流體等離散式電路元件(Discrete Circuit Component)的表面黏著型(Surface Mount)構裝,一般常見者大致有圓柱型玻璃/塑膠封裝,導線架(Lead-frame)有引腳封裝(Leaded package),方形無引腳的平板式封裝(Flat-pack leadless),以及覆晶(Flit-chip)封裝等。其中,覆晶封裝雖有輕薄短小優點,但因製程昂貴,應用不便,及零件相對易於老化諸多缺點,故少使用在訴求大功率及耐久等應用上。相較之下,前述除覆晶封裝以外是為目前功率型封裝體之市場主流。不過,隨著電性要求越高,功率增大,熱傳及高溫等因素所引致問題,上述常見封裝製程技術亦已趨近技術瓶頸。 At present, the surface mount structure of Discrete Circuit Component such as diode, light-emitting diode, transistor and thyristor is generally common in cylindrical glass/plastic package, wire Lead-frames are available in leaded packages, square-lead-free lead-packages, and flip-chip packages. Among them, the flip chip package has the advantages of lightness, thinness and shortness, but it is inconvenient to use, and the parts are relatively easy to aging, so it is rarely used in applications such as high power and durability. In contrast, the foregoing except the flip chip package is the mainstream of the current power type package. However, with the higher electrical requirements, increased power, heat transfer and high temperature, the above-mentioned common packaging process technology has also approached the technical bottleneck.

高功率電路元件,特別是諸如功率二極體,電晶體及閘流體等是為功率電子(Power Electronics)應用領域不可或缺之離散式元件。其性能,可靠度,使用壽命等對於諸如再生能源,電動車等重要用途之推廣有關鍵 性的影響。但性能壽命以外,其製造成本亦為其廣泛應用之同等重要因素。 High-power circuit components, particularly power diodes, transistors, and thyristors, are discrete components that are indispensable for power electronics applications. Its performance, reliability, and service life are key to the promotion of important uses such as renewable energy and electric vehicles. Sexual influence. However, in addition to the performance life, its manufacturing cost is also an equally important factor for its widespread application.

習知技術製作具良好散熱性及高電功率之電路元件封裝體之封裝方法,例如中華民國專利I583282號,以及發明申請105110137號,係以兩大片導電銅板為基礎,以多單位之陣列形態,同時封裝多個單位之電路元件晶粒,以便利用批次方式,尋求有效率地大量製作電路元件,以降低單位成本。然而,該二習知技術利用兩大整片銅板之方法需要將其基底陣列銅板、電路元件晶粒體、平行陣列排列的平行導電片,以及焊錫料的厚度公差控制在一定程度之內。一旦其此些製程參數之實質差異控制不佳,其整批產品之中即會發生焊接品質、對位精準不佳的嚴重後果。換言之,生產良率降低,直接結果即是合格產品的單位成本升高。 A conventional method for packaging a circuit component package having good heat dissipation and high electric power, for example, the Republic of China Patent No. I583282, and the invention application No. 105110137, based on two large conductive copper plates, in the form of an array of multiple units, A plurality of units of circuit component dies are packaged in order to utilize batch mode to seek efficient mass production of circuit components to reduce unit cost. However, the two conventional techniques utilize two large copper sheets to control the thickness tolerance of the substrate array copper plate, the circuit element grain body, the parallel array of parallel conductive sheets, and the solder material to a certain extent. Once the actual difference of these process parameters is not well controlled, the serious consequences of welding quality and poor alignment accuracy will occur in the whole batch of products. In other words, the production yield is reduced, and the direct result is the increase in the unit cost of the qualified product.

為克服習知技術前述問題,本發明提供一種以多單位之陣列形態同時封裝多個單位之元件晶粒以批次製作電路元件之方法,其元件晶粒體上包含有至少二電極,其中至少一電極位於元件晶粒體頂面,而其餘電極則位於相反對應之晶粒體底面。該方法係將每一電路元件其所封裝保護之元件晶粒之每一電極電性連接至電路元件構體之一對應端電極。此方法之步驟包含先於一基底陣列銅板上形成陣列中每一電路元件之至少二端電極初步構造。其後為每一電路元件取置元件晶粒,使晶粒體底面電極面對基底陣列銅板之至少二端電極初步構造中之一對應端電極初步構造之表面。再為每一電路元件取置一水平導電片,其水平一側之一底接面對置於元件晶粒體頂面之電極。然後為每一電路元件取置一垂直導電塊,其上端置入水平導電片其水平另一側之一垂直接孔內,其具有一垂直接面以與垂 直導電塊上端對接,垂直導電塊下端之一底接面則對置於基底陣列銅板之至少二端電極初步構造中之一對應端電極初步構造之表面。之後則進行迴焊,將晶粒體底面電極與其所對應之基底陣列銅板之端電極初步構造表面間之預施焊錫料,水平導電片其底接面與其所對應之晶粒體頂面電極間之預施焊錫料,垂直導電塊上端與其所對應之水平導電片垂直接孔內垂直接面間之預施焊錫料,與垂直導電塊下端底接面與其所對應之端電極初步構造表面間之預施焊錫料,全皆同時融熔後固焊。 In order to overcome the foregoing problems of the prior art, the present invention provides a method for simultaneously packaging a plurality of units of element dies in an array form of a plurality of units to batch-produce circuit elements, wherein the element die includes at least two electrodes, at least One electrode is located on the top surface of the element die, and the remaining electrodes are located on the bottom surface of the opposite corresponding grain body. In the method, each of the circuit elements of each of the circuit elements protected by the package is electrically connected to one of the corresponding terminal electrodes of the circuit element body. The method of the method includes preliminarily constructing at least two terminal electrodes of each circuit component in the array prior to forming on a substrate array copper plate. Thereafter, the component die is taken for each circuit component such that one of the preliminary structures of the at least two terminal electrodes of the bottom surface of the die body facing the base array copper plate corresponds to the surface of the preliminary configuration of the terminal electrode. Then, a horizontal conductive sheet is taken for each circuit component, and one of the horizontal sides thereof is bottomed to face the electrode placed on the top surface of the element die. Then, a vertical conductive block is disposed for each circuit component, and the upper end of the horizontal conductive sheet is placed in one of the horizontally opposite sides of the horizontal conductive strip, and has a vertical joint to hang The upper end of the straight conductive block is butted, and one of the bottom joints of the lower end of the vertical conductive block is opposite to the surface of the preliminary structure of the terminal electrode of one of the preliminary structures of the at least two electrodes of the base array copper plate. After that, reflow is performed to pre-apply the solder between the bottom surface electrode of the grain body and the terminal electrode of the base array copper plate corresponding thereto, and the bottom surface of the horizontal conductive sheet and the corresponding top surface electrode of the grain body The pre-applied solder material, the pre-applied solder between the upper end of the vertical conductive block and the vertical joint of the horizontal conductive sheet corresponding to the horizontal conductive strip, and the bottom surface of the vertical conductive block and the corresponding end surface of the terminal electrode Pre-applied solder materials, all of which are simultaneously melted and then fixed.

1000‧‧‧基底陣列銅板 1000‧‧‧Base array copper plate

1011、1012‧‧‧上表面端電極 1011, 1012‧‧‧ upper surface electrode

1020‧‧‧單位 1020‧‧ units

200‧‧‧電路元件晶粒體 200‧‧‧Circuit component grain

210‧‧‧電路元件晶粒體頂面電極 210‧‧‧ Circuit element top surface electrode

220‧‧‧電路元件晶粒體底面電極 220‧‧‧ Circuit element bottom surface electrode

3001、3001A‧‧‧水平導電片 3001, 3001A‧‧‧ horizontal conductive sheet

3002‧‧‧水平導電片垂直接面 3002‧‧‧Horizontal conductive sheet vertical joint

3003‧‧‧垂直接孔 3003‧‧‧Vertical hole

3005、3005A‧‧‧垂直導電塊 3005, 3005A‧‧‧ vertical conductive block

3100、3100A‧‧‧單位結構體 3100, 3100A‧‧‧ unit structure

5100‧‧‧水氣隔絕封裝材料 5100‧‧‧Water and gas barrier packaging materials

218、1028、3008、1018‧‧‧錫料 218, 1028, 3008, 1018‧‧‧ tin

6009‧‧‧下表面端電極 6009‧‧‧ lower surface electrode

2000‧‧‧電路元件結構體 2000‧‧‧Circuit component structure

圖1顯示應用於本發明一實施例製作具有三端電極一電路元件之基底陣列銅板之局部區域。 1 shows a partial region of a substrate array copper plate having a three-terminal electrode-circuit element fabricated in accordance with an embodiment of the present invention.

圖2之透視圖顯示可適用於圖1之基底陣列銅板之電路元件之元件晶粒體之基本構造。 2 is a perspective view showing the basic configuration of a component die of a circuit component applicable to the substrate array copper of FIG. 1.

圖3A之示意圖顯示本發明製作電路元件時於基底陣列銅板之上依序所進行之取置作業。 3A is a schematic view showing the mounting operation performed on the substrate array copper plate in sequence when the circuit component is fabricated in the present invention.

圖3B之透視圖顯示圖3A中取置程序完成且經迴焊處理後每一電路元件單位所完成之單位結構體。 3B is a perspective view showing the unit structure completed in each circuit component unit after the completion of the fetching process and the reflow process in FIG. 3A.

圖4之透視圖顯示依據本發明先取置垂直導電塊,其後再取置水平導電片之另種作法,其迴焊處理後每一電路元件單位所完成之單位結構體。 4 is a perspective view showing a unit structure in which a vertical conductive block is first taken in accordance with the present invention, and then a horizontal conductive sheet is taken, which is completed by each circuit component unit after the reflow process.

圖5A為圖3B之單位結構體進行水氣密封裝之後,沿aa’面切割之剖面圖。 Fig. 5A is a cross-sectional view of the unit structure of Fig. 3B cut along the aa' plane after being hermetically sealed.

圖5B為圖3B之單位結構體進行水氣密封裝之後,沿bb’面切割之 剖面圖。 FIG. 5B is a view showing the unit structure of FIG. 3B after being water-sealed and sealed along the bb' plane. Sectional view.

圖6之透視圖係為水氣密封裝後,個別電路元件單位被分別切割分離之前,整個陣列的背面構造。 Figure 6 is a perspective view of the back side of the entire array before the individual circuit component units are separately cut and separated after the moisture seal.

圖7顯示依據本發明方法所製作電路元件其結構體之外形構造。 Figure 7 shows the structural configuration of the circuit element fabricated in accordance with the method of the present invention.

圖1顯示應用於本發明一實施例製作具有三端電極的電路元件之基底陣列銅板1000,其局部區域,放大透視圖。依據本發明,典型的批次製作會使用數十乘數十之電路元件單位之矩陣。圖1中僅顯示其中之四個單位,如圖中以標號1020所標示之虛線框線所圍之範圍。此實例中,基底陣列銅板1000之上表面預先指定或初步形成上表面端電極1011,1012。 BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 shows a substrate array copper plate 1000 which is applied to a circuit element having a three-terminal electrode according to an embodiment of the present invention, a partial area thereof, an enlarged perspective view. In accordance with the present invention, a typical batch production would use a matrix of tens of times and tens of circuit component units. Only four of the units are shown in Figure 1, as indicated by the dashed line indicated by the numeral 1020 in the figure. In this example, the upper surface terminal electrodes 1011, 1012 are pre-designated or preliminarily formed on the upper surface of the base array copper plate 1000.

在圖1之例中,此些端電極初步構造可以突出於基底陣列銅板1000之上表面,其可利用諸如蝕刻之減法製程、電鍍/化學之加法製程或常用的機械加工,如車、銑、鑽、磨、鋸、沖壓等技術於一基礎銅板上形成,此可整批製作多個電路元件單位1020的端電極初步構造1011及1012。在另一實施例中,此些端電極初步構造1010亦可不須突出於基底陣列銅板1000之上表面。 In the example of FIG. 1, the preliminary configuration of the terminal electrodes may protrude from the upper surface of the substrate array copper plate 1000, and may be subjected to a subtractive process such as etching, an electroplating/chemical addition process, or a common mechanical process such as turning, milling, or the like. Drilling, grinding, sawing, stamping, etc. are formed on a base copper plate, which can be used to make a plurality of terminal electrode preliminary structures 1011 and 1012 of a plurality of circuit component units 1020. In another embodiment, the terminal electrode preliminary structures 1010 may not protrude from the upper surface of the substrate array copper plate 1000.

圖2之透視圖顯示可適用於圖1之基底陣列銅板之電路元件之元件晶粒體之基本構造。典型之功率二極體,電晶體或閘流體之元件晶粒,一般而言,係為矩型體之構造。依據本發明,一整批的此種元件晶粒200將分別被取置於圖1基底陣列銅板1000表面上的各自對應電路元件單位1020上。於此圖1及2之實例中,元件晶粒體200,當利用自動取置設備(automatic pick-and-place equipment)正確地置放於基底陣列銅板1000表面上的對應單 位1020上時,其二底面電極220將分別與基底陣列銅板1000表面上的端電極初步構造1011對正吻合。 2 is a perspective view showing the basic configuration of a component die of a circuit component applicable to the substrate array copper of FIG. 1. A typical power diode, a transistor or a thyristor element die, in general, is a rectangular body structure. In accordance with the present invention, a batch of such component die 200 will be placed on respective corresponding circuit component units 1020 on the surface of substrate array copper plate 1000 of FIG. In the examples of FIGS. 1 and 2, the element die 200 is properly placed on the surface of the base array copper plate 1000 when the automatic pick-and-place equipment is used. In position 1020, the two bottom electrode 220 will respectively align with the terminal electrode preliminary structure 1011 on the surface of the base array copper plate 1000.

圖3A之示意圖顯示本發明製作電路元件時於基底陣列銅板之上依序所進行之取置作業,其中包含首先取置元件晶粒體200,將此晶粒體定置於其指定元件單位1020之定位上。如同前述,晶粒體200之底面電極220分別與基底陣列銅板1000的端電極初步構造1011吻合。 3A is a schematic view showing the process of sequentially performing the circuit component on the substrate array copper plate, in which the component die 200 is first taken, and the die is placed in its designated component unit 1020. Positioning. As before, the bottom electrode 220 of the die 200 conforms to the terminal electrode preliminary configuration 1011 of the base array copper plate 1000, respectively.

接著取置一水平導電片3001,其水平一側,即圖3中之左側,其一底接面對置於元件晶粒體200頂面之電極210。 Then, a horizontal conductive sheet 3001 is disposed on the horizontal side, that is, the left side in FIG. 3, and a bottom surface thereof faces the electrode 210 placed on the top surface of the element die 200.

其後再取置一垂直導電塊3005,其上端置入水平導電片3001其水平另一側,即圖中右側之一垂直接孔3003內。此垂直接孔3003具有垂直接面3002以與垂直導電塊3005上端對接。垂直導電塊3005下端之一底接面則對置於基底陣列銅板1000上之對應端電極初步構造1012之表面。 Then, a vertical conductive block 3005 is disposed, and the upper end is placed on the horizontal other side of the horizontal conductive sheet 3001, that is, in one of the right vertical holes 3003 in the figure. The vertical via 3003 has a vertical junction 3002 to interface with the upper end of the vertical conductive block 3005. One of the bottom surfaces of the lower end of the vertical conductive block 3005 is opposite to the surface of the corresponding end electrode preliminary structure 1012 on the base array copper plate 1000.

注意到垂直接孔3003可為具有完整週緣之洞孔。其亦可為不具完整週緣之開放洞孔,如圖中所示。 It is noted that the vertical through hole 3003 can be a hole having a complete circumference. It can also be an open hole that does not have a complete circumference, as shown in the figure.

前述元件晶粒體200,水平導電片3001,與垂直導電塊3005先後取置動作完成之後,即可進行迴焊(thermal reflow)。此迴焊處理可將晶粒體200底面電極220與其所對應之基底陣列銅板1000之端電極初步構造1011表面間所預先施佈之焊錫料;水平導電片3001其底接面與其所對應之晶粒體200頂面電極210間所預先施佈之焊錫料;垂直導電塊3005上端與其所對應之水平導電片3001垂直接孔3003內垂直接面3002間所預先施佈之焊錫料;以及垂直導電塊3005下端底接面與其所對應之基底陣列銅板1000的端電極初步構造1012表面間所預先施佈之焊錫料,全皆同時融熔後固焊。 After the element die 200, the horizontal conductive sheet 3001, and the vertical conductive block 3005 are sequentially taken out, thermal reflow can be performed. The reflow process can pre-apply the solder material between the bottom electrode 220 of the die body 200 and the surface of the terminal electrode of the base array copper plate 1000 corresponding to the preliminary structure 1011; the bottom conductive surface of the horizontal conductive plate 3001 and the corresponding crystal a solder material pre-applied between the top electrodes 210 of the granules 200; a solder material pre-applied between the upper ends of the vertical conductive blocks 3005 and the vertical conductive pads 3001 of the corresponding horizontal conductive sheets 3001; and vertical conductive The solder material pre-applied between the bottom end of the block 3005 and the surface of the terminal electrode preliminary structure 1012 of the corresponding base array copper plate 1000 is all melted and then welded.

前述之預先施佈之施焊錫料可為一般常用含錫顆粒之錫膏,或含錫之焊片。此些焊料可在元件晶粒體200,水平導電片3001,與垂直導電塊3005之取置程序步驟之間適時施用。若用錫膏,可利用諸如自動點錫膏設備進行,若用焊片,則可利用元件晶粒之取置設備進行。 The foregoing pre-applied solder can be a solder paste containing tin particles in general, or a solder piece containing tin. Such solder may be applied between the element die 200, the horizontal conductive sheet 3001, and the vertical conductive block 3005. If a solder paste is used, it can be carried out using, for example, an automatic solder paste device. If a solder tab is used, it can be carried out using a device for removing the die.

圖3B之透視圖顯示圖3A中取置程序完成且經迴焊處理,所有焊料皆固焊而形成永久性電性導接之後,為每一電路元件單位所完成之單位結構體3100。 The perspective view of FIG. 3B shows the unit structure 3100 completed for each circuit component unit after the soldering process of FIG. 3A is completed and the solder reflow process is performed, after all solders are soldered to form a permanent electrical junction.

圖3B之中,前述晶粒體200底面電極220與其所對應之基底陣列銅板1000之端電極初步構造1011表面間所預先施佈之焊錫料,此時已焊固為焊接層1018;水平導電片3001其底接面與其所對應之晶粒體200頂面電極210間所預先施佈之焊錫料,此時已焊固為焊接層218;垂直導電塊3005上端與其所對應之水平導電片3001垂直接孔3003內垂直接面3002間所預先施佈之焊錫料,此時已焊固為焊接層3008;而垂直導電塊3005下端底接面與其所對應之基底陣列銅板1000的端電極初步構造1012表面間所預先施佈之焊錫料,此時則已焊固為焊接層1028。 In FIG. 3B, the solder material pre-applied between the bottom electrode 220 of the die body 200 and the surface of the terminal electrode preliminary structure 1011 of the corresponding base array copper plate 1000 is soldered to the solder layer 1018; the horizontal conductive sheet The solder material pre-applied between the bottom surface of the 3001 and the corresponding top surface electrode 210 of the grain body 200 is soldered to the solder layer 218; the upper end of the vertical conductive block 3005 is perpendicular to the corresponding horizontal conductive sheet 3001. The solder material pre-applied between the vertical joints 3002 in the direct hole 3003 is soldered to the solder layer 3008 at this time; and the bottom end of the vertical conductive block 3005 and the corresponding terminal electrode of the base array copper plate 1000 are initially constructed 1012. The solder material previously applied between the surfaces is then soldered to the solder layer 1028.

依據本發明,於另一實施例中,水平導電片及垂直導電塊之取置順序亦可對調。此時,水平導電片之一側即不需具備有垂直接孔(3003,圖3A)。換言之,圖3A及3B之實施例係先取置水平導電片3001,然後才取置垂直導電塊3005,而此另種作法則是先取置垂直導電塊,然後才取置水平導電片。 According to the present invention, in another embodiment, the order of the horizontal conductive sheets and the vertical conductive blocks can also be reversed. At this time, one side of the horizontal conductive sheet does not need to have a vertical connection hole (3003, FIG. 3A). In other words, in the embodiment of FIGS. 3A and 3B, the horizontal conductive sheet 3001 is first taken, and then the vertical conductive block 3005 is taken, and the other method is to first take the vertical conductive block and then take the horizontal conductive sheet.

圖4之透視圖顯示此先取置垂直導電塊3005A,其後再取置水平導電片3001A之作法,其取置程序完成且經迴焊處理後每一電路元件單位所完 成之單位結構體3100A。依據本發明,製作圖4單位結構體3100A之程序係如下述。 4 is a perspective view showing the method of first taking the vertical conductive block 3005A, and then taking the horizontal conductive sheet 3001A, and the taking process is completed and the circuit component unit is finished after the reflow process. The unit structure is 3100A. According to the present invention, the procedure for producing the unit structure 3100A of Fig. 4 is as follows.

首先取置元件晶粒體200,將此晶粒體定置於其指定元件單位之定位上。晶粒體200之底面電極220分別與基底陣列銅板1000的端電極初步構造1011吻合。 The component die 200 is first placed and positioned to position it in its designated component unit. The bottom electrode 220 of the die body 200 coincides with the terminal electrode preliminary structure 1011 of the base array copper plate 1000, respectively.

接著取置一垂直導電塊3005A,其下端之一底接面對置於基底陣列銅板1000之對應端電極初步構造1012之表面; 其後再取置一水平導電片3001A,其水平一側之一底接面對置於元件晶粒體200頂面之電極210,其水平另一側之另一底接面則對置於垂直導電塊3005A其上端之一頂接面。 Then, a vertical conductive block 3005A is disposed, and one of the lower ends thereof is bottomed to face the surface of the corresponding terminal electrode preliminary structure 1012 of the base array copper plate 1000; Thereafter, a horizontal conductive sheet 3001A is taken, one of the horizontal sides of which is connected to the electrode 210 placed on the top surface of the element die 200, and the other bottom of the horizontal side is placed vertically. The conductive block 3005A has a top surface of one of its upper ends.

前述元件晶粒體200,垂直導電塊3005A,與水平導電片3001A先後取置動作完成之後,即可進行迴焊(thermal reflow)。此迴焊處理可將晶粒體200底面電極220與其所對應之基底陣列銅板1000之端電極初步構造1011表面間所預先施佈之焊錫料;水平導電片3001A其底接面與其所對應之晶粒體200頂面電極210間所預先施佈之焊錫料;垂直導電塊3005A上端與其所對應之水平導電片3001A其底接面間所預先施佈之焊錫料;以及垂直導電塊3005A下端底接面與其所對應之基底陣列銅板1000的端電極初步構造1012表面間所預先施佈之焊錫料,全皆同時融熔後固焊。 After the element die 200, the vertical conductive block 3005A, and the horizontal conductive sheet 3001A are successively removed, thermal reflow can be performed. The reflow process can pre-apply the solder material between the bottom electrode 220 of the die body 200 and the surface of the terminal electrode of the base array copper plate 1000 corresponding to the preliminary structure 1011; the bottom conductive surface of the horizontal conductive plate 3001A and the corresponding crystal a solder material pre-applied between the top electrodes 210 of the granular body 200; a solder material pre-applied between the upper end of the vertical conductive block 3005A and the bottom conductive surface of the horizontal conductive sheet 3001A corresponding thereto; and a bottom end of the vertical conductive block 3005A The pre-applied solder material between the surface of the terminal electrode 1012 of the base array copper plate 1000 corresponding thereto is all melted and then welded.

圖4之中,前述晶粒體200底面電極220與其所對應之基底陣列銅板1000之端電極初步構造1011表面間所預先施佈之焊錫料,此時已焊固為焊接層1018;水平導電片3001A其底接面與其所對應之晶粒體200頂面電極210間所預先施佈之焊錫料,此時已焊固為焊接層218;垂直導電塊3005A上 端與其所對應之水平導電片3001A其底接面間所預先施佈之焊錫料,此時已焊固為焊接層3008;而垂直導電塊3005A下端底接面與其所對應之基底陣列銅板1000的端電極初步構造1012表面間所預先施佈之焊錫料,此時則已焊固為焊接層1028。 In FIG. 4, the solder material pre-applied between the bottom surface electrode 220 of the die body 200 and the surface of the terminal electrode preliminary structure 1011 of the corresponding base array copper plate 1000 is soldered to the solder layer 1018; the horizontal conductive sheet 3001A solder material pre-applied between the bottom joint surface and the corresponding top surface electrode 210 of the grain body 200, which has been welded to the solder layer 218 at this time; the vertical conductive block 3005A The solder material pre-applied between the end of the horizontal conductive sheet 3001A and the bottom surface thereof is soldered to the solder layer 3008; and the lower end of the vertical conductive block 3005A is connected to the corresponding base array copper plate 1000. The terminal electrode preliminarily constructs the solder material pre-applied between the surfaces of 1012, at which point it is soldered to the solder layer 1028.

依據本發明之陣列批次式封裝元件晶粒之電路元件製作方法,圖3B電路元件之單位結構體3100及其製作方法可適用於整批元件晶粒體的厚度公差變異較大的情況。相較之下,圖4電路元件之單位結構體3100A及其製作方法則可適用於整批元件晶粒體的厚度公差變異較小的情況。二者相比,雖然水平導電片與垂直導電快塊構造稍有不同,且取置次序前後相反,但基本上,本發明電路元件封裝體內之電路元件之單位結構體,皆是利用垂直導電塊上端與水平導電片一端的焊接而將元件晶粒體200的頂面電極210電性連結到基底陣列銅板1000上的對應端電極初步構造1012。兩者所具有的大面積焊接面是為本發明方法所製作電路元件具備高功率,良好散熱性之關鍵。 According to the method for fabricating the circuit component of the array batch package element die of the present invention, the unit structure 3100 of the circuit component of FIG. 3B and the manufacturing method thereof can be applied to the case where the thickness tolerance variation of the whole batch of the die body is large. In contrast, the unit structure 3100A of the circuit component of FIG. 4 and the method of fabricating the same can be applied to the case where the variation of the thickness tolerance of the whole batch of the element body is small. Compared with the two, although the horizontal conductive sheet and the vertical conductive fast block structure are slightly different, and the order of the arrangement is reversed, basically, the unit structure of the circuit component in the circuit component package of the present invention utilizes the vertical conductive block. The upper end is soldered to one end of the horizontal conductive sheet to electrically connect the top surface electrode 210 of the element die 200 to the corresponding end electrode preliminary structure 1012 on the base array copper plate 1000. The large-area soldering surface of the two is the key to the high power and good heat dissipation of the circuit components produced by the method of the present invention.

此外,本發明圖3A及4中所描述之電路元件之單位結構體中的四個焊接面,其容許加溫迴焊時融熔焊料的整體系統平衡特性,其結果為批次製程良率的極為顯著改善。此改善直接代表電路元件產品成本的降低。 In addition, the four soldering faces in the unit structure of the circuit component described in the present invention in FIGS. 3A and 4 allow the overall system balance characteristics of the molten solder during warm reflow, and the result is the batch process yield. Significantly improved. This improvement directly represents a reduction in the cost of the circuit component product.

依據本發明,再形成圖3B或4中之強固高性能單位結構體後,即可進行水氣密封裝保護。一般典型作法係利用模具以膠狀或膠餅樹酯進行灌注並冷卻固化。固化後之樹酯體5100即可保護整個單位結構體。圖5A為圖3B之單位結構體進行水氣密封裝之後,沿aa’面切割之剖面圖。圖5B則為圖3B之單位結構體進行水氣密封裝之後,沿bb’面切割之剖面圖。 According to the present invention, after the formation of the strong high-performance unit structure in Fig. 3B or 4, the water gas seal protection can be performed. In a typical practice, the mold is filled with a gel or gum resin and cooled and solidified. The cured resin body 5100 protects the entire unit structure. Fig. 5A is a cross-sectional view of the unit structure of Fig. 3B cut along the aa' plane after being hermetically sealed. Fig. 5B is a cross-sectional view of the unit structure of Fig. 3B cut along the bb' plane after moisture sealing.

其後,便可對基底陣列銅板1000之底面進行減法處理,以將整個陣列所有個別電路元件之所有端電極分離開來。一般典型之減法處理可以是,例如,化學蝕刻處理。圖6之透視圖即為水氣密封裝,並分離所有端電極之後,個別電路元件單位被分別切割分離之前,整個陣列的背面構造。注意到圖6中此例係為具二端電極6009之電路元件,例如功率二極體。 Thereafter, the bottom surface of the base array copper plate 1000 can be subtracted to separate all of the terminal electrodes of all the individual circuit elements of the entire array. A typical typical subtractive treatment can be, for example, a chemical etching process. The perspective view of Fig. 6 is a water-tight seal, and after separating all of the terminal electrodes, the individual circuit element units are separately cut and separated, and the back side of the entire array is constructed. Note that this example in Figure 6 is a circuit component having a two-terminal electrode 6009, such as a power diode.

接著,圖6之整體陣列便可以沿圖中之AA’與BB’切割面進行切割,以將陣列中所有個別電路元件實體分離開。圖7即顯示依據本發明方法所製作電路元件2000其結構體之外形構造。 Next, the overall array of Figure 6 can be cut along the AA' and BB' cut faces in the figure to physically separate all of the individual circuit components in the array. Figure 7 shows the structural configuration of the circuit component 2000 produced in accordance with the method of the present invention.

如同本技藝中所熟知,圖7中各別分離之後之電路元件單體,其所有端電極皆已電性分離,此時可對每一個別端電極進行鎳-金或鎳-錫鍍覆處理。 As is well known in the art, all of the terminal electrodes of the circuit component unit after separation in FIG. 7 are electrically separated, and each individual terminal electrode can be subjected to nickel-gold or nickel-tin plating treatment. .

如同本技藝中所熟知,本發明方法所製作之電路元件可為具有二、三或更多端電極之離散式電路元件。此電路元件可為二極體。其亦可為電晶體。其亦可為光耦合開關。其更可為具有至少四端電極之積體電路元件。 As is well known in the art, the circuit components fabricated by the method of the present invention can be discrete circuit components having two, three or more terminal electrodes. This circuit component can be a diode. It can also be a transistor. It can also be an optically coupled switch. It may even be an integrated circuit component having at least four terminal electrodes.

本發明已經由較佳實例揭示說明如上,然以上說明並非用以限定本發明。在不脫離於本發明精神之情況下,一般熟習於本技藝者當可作些許更動與變化。因此本發明之保護範圍當視後附之申請範圍所界定者為準。 The invention has been described above by way of a preferred example, and the above description is not intended to limit the invention. It will be appreciated that those skilled in the art will be able to make a few changes and changes without departing from the spirit of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

Claims (8)

以多單位之陣列形態同時封裝多個單位之元件晶粒以批次製作電路元件之方法,元件晶粒體上包含有至少二電極,其中至少一電極位於元件晶粒體頂面,其餘電極則位於相反對應之晶粒體底面,該方法將每一電路元件其所封裝保護之元件晶粒之每一電極電性連接至電路元件構體之一對應端電極,其包含有下列步驟:於一基底陣列銅板上形成陣列中每一電路元件之至少二端電極初步構造;為每一電路元件取置元件晶粒,使晶粒體底面電極面對基底陣列銅板之至少二端電極初步構造中之一對應端電極初步構造之表面;為每一電路元件取置一垂直導電塊,其下端之一底接面對置於基底陣列銅板之至少二端電極初步構造中之一對應端電極初步構造之表面;為每一電路元件取置一水平導電片,其水平一側之一底接面對置於元件晶粒體頂面之電極,其水平另一側之另一底接面則對置於垂直導電塊其上端之一頂接面;與進行迴焊(thermal reflow),將晶粒體底面電極與其所對應之基底陣列銅板之端電極初步構造表面間之預施焊錫料,水平導電片其底接面與其所對應之晶粒體頂面電極間之預施焊錫料,垂直導電塊上端頂接面與其所對應之水平導電片間之預施焊錫料,與垂直導電塊下端底接面與其所對應之端電極初步構造表面間之預施焊錫料,全皆同時融熔後固焊。 The method further comprises: encapsulating a plurality of unit element dies in an array form of a plurality of units to form a circuit component in batches, wherein the element die body comprises at least two electrodes, wherein at least one electrode is located on a top surface of the element die body, and the remaining electrodes are The method is located on the bottom surface of the opposite corresponding crystal body. The method electrically connects each electrode of the circuit element protected by each circuit component to one end electrode of the circuit component body, and comprises the following steps: Forming at least two terminal electrodes of each circuit component in the array on the base array copper plate; arranging the component die for each circuit component such that the bottom surface electrode of the die body faces at least two terminal electrodes of the base array copper plate a surface corresponding to the preliminary configuration of the terminal electrode; a vertical conductive block is disposed for each circuit component, and one of the lower ends of the bottom electrode is opposite to the one of the preliminary structures of the at least two terminal electrodes disposed on the substrate array copper plate. a surface; a horizontal conductive sheet is taken for each circuit component, and one of the horizontal sides thereof is bottomed to face the electrode placed on the top surface of the element die, and the level is another The other bottom junction is opposite to one of the upper ends of the vertical conductive block; and the thermal reflow is performed, and the bottom surface electrode of the grain body and the corresponding terminal electrode of the base array copper plate are between the preliminary structural surfaces. Pre-applied solder material, pre-applied solder between the bottom joint surface of the horizontal conductive sheet and the corresponding top surface electrode of the grain body, pre-applied solder between the upper end of the vertical conductive block and the horizontal conductive sheet corresponding thereto The pre-applied solder material between the bottom end of the vertical conductive block and the corresponding initial surface of the terminal electrode of the vertical conductive block is all melted and then fixed. 申請專利範圍項1之方法,其中迴焊處理之後更包含有:形成水氣密隔絕封裝結構,其包覆基底陣列銅板上所固焊之元件晶粒,水平導電片,及垂直導電塊; 對基底陣列銅板之底面進行減法處理,以分離該陣列中所有個別電路元件之所有端電極;與切割水氣密隔絕封裝結構以將陣列中所有個別電路元件實體分離開。 The method of claim 1 , wherein the reflow process further comprises: forming a water-tight insulating package structure, which covers the component die, the horizontal conductive sheet, and the vertical conductive block which are fixed on the substrate array copper plate; The bottom surface of the base array copper plate is subtracted to separate all of the end electrodes of all of the individual circuit components in the array; the package structure is hermetically sealed from the cut water to physically separate all of the individual circuit elements in the array. 申請專利範圍項2之方法,更包含有:於減法處理,陣列中所有個別電路元件之所有端電極皆分離之後,對每一個別端電極進行鎳-金或鎳-錫鍍覆處理。 The method of claim 2, further comprising: after the subtraction process, all the terminal electrodes of all the individual circuit components in the array are separated, and then each of the individual terminal electrodes is subjected to nickel-gold or nickel-tin plating treatment. 申請專利範圍項1之方法,其中該電路元件係為具有二、三或更多端電極之離散式電路元件。 The method of claim 1, wherein the circuit component is a discrete circuit component having two, three or more terminal electrodes. 申請專利範圍項4之方法,其中該電路元件係為二極體。 The method of claim 4, wherein the circuit component is a diode. 申請專利範圍項4之方法,其中該電路元件係為電晶體。 The method of claim 4, wherein the circuit component is a transistor. 申請專利範圍項4之方法,其中該電路元件係為光耦合開關。 The method of claim 4, wherein the circuit component is an optically coupled switch. 申請專利範圍項1之方法,其中該電路元件係為具有至少四端電極之積體電路元件。 The method of claim 1, wherein the circuit component is an integrated circuit component having at least four terminal electrodes.
TW106144126A 2017-12-15 2017-12-15 Fabrication method of circuit components for matrix-batch die package for fabricating circuit components in matrix batches with high efficiency and at low cost TW201929098A (en)

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TW106144126A TW201929098A (en) 2017-12-15 2017-12-15 Fabrication method of circuit components for matrix-batch die package for fabricating circuit components in matrix batches with high efficiency and at low cost
CN201811532954.1A CN109979825A (en) 2017-12-15 2018-12-14 The circuit element production method of array batch potted element crystal grain
US16/220,868 US11521862B2 (en) 2017-12-15 2018-12-14 Process for fabricating circuit components in matrix batches

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