TW201923887A - Systems and methods for patterning features in tantalum nitride (TaN) layer - Google Patents

Abstract

Embodiments of systems and methods for patterning features in tantalum nitride (TaN) are described. In an embodiment, a method may include receiving a substrate comprising a TaN layer. The method may also include etching the substrate to expose at least a portion of the TaN layer. Additionally, the method may include performing a passivation process to reduce lateral etching of the TaN layer. The method may further include etching the TaN layer to form a feature therein, wherein the passivation process is controlled to meet one or more target passivation objectives.

Description

System and method for patterning feature parts in tantalum nitride layer

The present invention relates to a system and method for substrate processing, and more particularly to a patterning system and method for a feature portion in tantalum nitride (TaN).

The described embodiment relates to the plasma processing of TaN used in industry. TaN is used as a hard mask for patterning the back-end process (BEOL) of semiconductor memory and logic devices. The plasma process includes etching a plurality of films. In some devices, the films may include silicon-containing anti-reflective coating (SiARC) films, carbon planarization (OPL) films, tetraethoxysilane (TEOS) films, and tantalum nitride (TaN) films. In some systems, the films are etched using a capacitively coupled plasma reactor. Although the operating parameters of the plasma reactor may vary depending on the application and the target processing results, such a system can operate at a high frequency of 60 MHz RF power at the first electrode and at a low frequency of 13.5 MHz RF power at the second electrode .

One problem with SF ₆ plasma etching of TaN is isotropic etching of the sidewall, which can degrade the critical dimension of the established feature. In some extreme cases, the established features may be destroyed by catastrophic undercuts, or degraded to the point where any final device does not work.

An embodiment of a patterning system and method for a feature portion in tantalum nitride (TaN) is described. In one embodiment, the method may include receiving a substrate including a TaN layer. The method may also include etching the substrate to expose at least a portion of the TaN layer. In addition, the method may include performing a passivation process to reduce lateral etching of the TaN layer. The method may further include etching the TaN layer to form features therein, wherein the passivation process is controlled to meet one or more target passivation results.

Methods and systems for patterning TaN are described. In one embodiment, these methods can be used to control the formation of features in a TaN layer of a multilayer stack that forms part of a memory device or a similar BEOL pattern. In various embodiments, an etching gas may be used to pattern the TaN layer in the plasma reactor chamber. The etching gas includes sulfur hexafluoride (SF ₆ ) gas, argon (Ar) gas, and boron trichloride (BCl ₃ ) Gas, and hydrogen bromide (HBr) gas and the like. In one embodiment, the plasma chamber may be a capacitively coupled plasma reactor. Additional processing parameters including temperature, pressure, and exposure time can be adjusted to control pattern formation in the TaN layer.

Those skilled in the relevant art will recognize that the various embodiments may be practiced without one or more of the specific details, or with other alternatives and / or additional methods, materials, or components. In other instances, well-known structures, materials, or operations have not been shown or described in detail to avoid obscuring aspects of various embodiments of the invention.

Similarly, for the purpose of explanation, specific numbers, materials, and configurations are proposed in order to provide a thorough understanding of the present invention. However, the invention may be practiced without specific details. Furthermore, it should be understood that the various embodiments shown in the drawings are illustrative and are not necessarily drawn to scale. In referring to the drawings, like numbers refer to similar parts throughout.

References throughout the specification to "one embodiment" or "an embodiment" or variations thereof mean that special features, structures, materials, or characteristics described in connection with the embodiment are included in at least one implementation of the invention Examples, but not indicative of their presence in every embodiment. As such, phrases such as "in one embodiment" or "in an embodiment" appearing throughout the specification are not necessarily intended to refer to the same embodiment of the invention. Furthermore, the particular features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments. Various other layers and / or structures may be included in other embodiments, and / or features described may be omitted.

In addition, it should be understood that "an (a)" or "an" may mean "one or more" unless explicitly stated otherwise.

Various operations will be described in sequence as a plurality of individual operations in a manner that is most helpful in understanding the present invention. However, the order of narratives should not be interpreted as implying that the operations must be in order. In particular, these operations need not be performed in the order presented. The described operations may be performed in a different order than the described embodiments. In additional embodiments, various additional operations may be performed and / or operations described may be omitted.

As used herein, the term "substrate" means and includes the base material or construction on which the material is formed. It should be understood that the substrate may include a single material, a plurality of layers of different materials, one or more layers of regions having different materials or different structures, and the like. These materials may include semiconductors, insulators, conductors, or a combination thereof. For example, the substrate may be a semiconductor substrate, a base semiconductor layer on a support structure, a metal electrode or a semiconductor substrate on which one or more layers, structures, or regions are formed. The substrate may be a conventional silicon substrate or other large substrates including a semiconductor material layer. As used herein, the term "bulk substrate" means not only and includes silicon wafers, but also silicon-on-insulator ("SOI") substrates, such as silicon-on-sapphire ("SOS") substrates and silicon-on-glass ("SOG") substrate, a silicon epitaxial layer on a base semiconductor substrate, and other semiconductor or optoelectronic materials such as silicon-germanium, germanium, gallium arsenide, gallium nitride, and indium phosphide. The substrate may be doped or undoped.

FIG. 1 is an embodiment of a system 100 for patterning TaN. In another embodiment, the system can be constructed to perform patterning of TaN materials, as described with reference to FIGS. 2A-8B. The etching and passivation processing system 100 configured to perform the above process conditions is described in FIG. 1 and includes a processing chamber 110, a substrate holder 120, a wafer 125 to be processed fixed on the substrate holder 120, and a vacuum pumping system 150. The wafer 125 may be a semiconductor substrate, a wafer, a flat panel display, or a liquid crystal display. The processing chamber 110 may be constructed to facilitate etching of the processing region 145 near the surface of the wafer 125. An ionizable gas or mixture of process gases is introduced via the gas distribution system 140. For a given process gas flow, the vacuum pumping system 150 is used to adjust the process pressure.

The wafer 125 can be fixed to the substrate holder 120 via a clamping system (not shown), such as a mechanical clamping system or an electrical clamping system (eg, an electrostatic clamping system). Furthermore, the substrate holder 120 can include a heating system (not shown) or a cooling system (not shown), which is configured to adjust and / or control the temperature of the substrate holder 120 and the wafer 125. The heating system or cooling system may include a recirculating flow of a heat transfer fluid that receives heat from the substrate holder 120 and transfers the heat to a heat exchanger system (not shown) when cooled, or transfers heat from the heat when heated The exchanger system is transferred to the substrate holder 120. In other embodiments, a heating / cooling element, such as a resistance heating element, or a thermoelectric heater / cooler may be included in the substrate holder 120, the wall of the processing chamber 110, and any other components in the processing system 100. in.

In addition, the heat transfer gas can be transferred to the back side of the wafer 125 through the back side gas supply system 126 to improve the air gap thermal conductivity between the wafer 125 and the substrate holder 120. This system can be utilized when temperature control of the wafer 125 is required at an increased or decreased temperature. For example, the backside gas supply system may include a dual-zone gas distribution system, wherein the helium gas gap pressure may vary independently between the center and edge of the wafer 125.

In the embodiment shown in FIG. 1, the substrate holder 120 may include an electrode 122 through which RF power is coupled to the processing region 145. For example, RF power may be transmitted from the RF generator 130 to the substrate holder 120 through the optional impedance matching network 132, and the substrate holder 120 may be electrically biased at the RF voltage. This RF electrical bias can be used to heat the electrons to form and maintain a plasma. In this configuration, the system 100 is operable as a RIE reactor in which the chamber and the upper gas injection electrode serve as a grounded surface.

Furthermore, the electrical bias of the electrode 122 to the RF voltage may be a pulsating type, and a pulsating type bias signal controller 131 is used. For example, the RF power output from the RF generator 130 may pulsate between an off state and an on state. Alternately, RF power is applied to the substrate holder electrode at a plurality of frequencies. Furthermore, the impedance matching network 132 can improve the transmission of RF power to the plasma in the plasma processing chamber 110 by reducing the reflected power. Matching network topologies (such as L-type, π-type, T-type, etc.) and automatic control methods are well known to those skilled in the art.

The gas distribution system 140 may include a shower head design for introducing a mixture of process gases. Alternatively, the gas distribution system 140 may include a multi-zone shower head design for introducing a mixture of process gases and adjusting the distribution of the mixture of process gases above the wafer 125. For example, the multi-zone sprinkler design can be constructed to adjust the amount of process gas flow or components relative to the process gas flow or composition to a generally central area above the wafer 125 to the generally peripheral area above the wafer 125. In this embodiment, the gas can be distributed in a suitable combination to form a highly uniform plasma in the chamber 110.

The vacuum pumping system 150 may include a turbo molecular vacuum pump (TMP) and a gate valve for throttling the pressure in the chamber. The turbo molecular vacuum pump is capable of a pumping rate of about 8000 liters (or higher) per second. In conventional plasma processing equipment for dry plasma etching, TMP of 800 to 3000 liters per second can be used. The TMP system can be used for low pressure processing, typically less than about 50 mTorr. For high pressure processing (ie, greater than about 80 mTorr), mechanical booster pumps and dry low vacuum pumps can be used. Furthermore, a device (not shown) for monitoring the chamber pressure may be coupled to the plasma processing chamber 110.

In one embodiment, the source controller 155 may include a microprocessor, a memory, and a digital input / output port to generate a control voltage, which is sufficient to transmit and activate the input to the processing system 100, and monitor the input from Output of the plasma processing system 100. Furthermore, the source controller 155 can be coupled to and can be connected to the RF generator 130, the pulsating bias signal controller 131, the impedance matching network 132, the gas distribution system 140, the power supply 190, the vacuum pumping system 150, and The substrate heating / cooling system (not shown), the backside gas supply system 126, and / or the electrostatic clamping system 128 exchange information. For example, the program stored in the memory can be used to input the aforementioned components to the processing system 100 according to the process recipe to perform a plasma assisted process, such as a plasma etching process or a post-heating process on the wafer 125. .

In addition, the processing system 100 may further include an upper electrode 170, and RF power may be coupled to the upper electrode 170 by the RF generator 172 via a selective impedance matching network 174. In one embodiment, the frequency range for applying RF power to the upper electrode may be from about 0.1 MHz to about 200 MHz. Alternatively, this embodiment may be combined with an inductively coupled plasma (ICP) source, a capacitively coupled plasma (CCP) source, and a radial line slot antenna (RLSA) source operating in the GHz frequency range. Electron cyclotron resonance (ECR) sources operating in the sub-GHz to GHz range, and others. In addition, the frequency of applying power to the lower electrode may range from about 0.1 MHz to about 80 MHz. Furthermore, the source controller 155 is coupled to the RF generator 172 and the impedance matching network 174 in order to control the application of RF power to the upper electrode 170. The design and implementation of the upper electrode are well known to those skilled in the art. As shown, the upper electrode 170 and the gas distribution system 140 may be designed within the same chamber assembly. Alternatively, the upper electrode 170 may include a multi-zone electrode design for adjusting the RF power distribution of the plasma coupled above the wafer 125. For example, the upper electrode 170 may be segmented into a center electrode and an edge electrode.

The processing system 100 may further include a direct current (DC) power source 190 coupled to an upper electrode 170 opposite to the substrate 125. The upper electrode 170 may include an electrode plate. The electrode plate may include a silicon-containing electrode plate. Furthermore, the electrode plate may include a doped silicon electrode plate. The DC power source 190 can include a variable DC power source. In addition, the DC power supply 190 may include a bipolar DC power supply. The DC power supply 190 may further include a system configured to monitor, adjust, or control at least one of the polarity, current, voltage, or on / off status of the DC power supply 190. Once the plasma is formed, the DC power source 190 helps to form a ballistic electron beam. An electric filter (not shown) may be used to decouple RF power from the DC power supply 190.

For example, the DC voltage range applied to the upper electrode 170 by the DC power source 190 may be from about -2000 volts (V) to about 1000V. Ideally, the absolute value of the DC voltage has a value equal to or greater than about 100V, and more desirably, the absolute value of the DC voltage has a value equal to or greater than about 1300V. In addition, it is desirable that the DC voltage has a negative polarity. Furthermore, what it wants is that the DC voltage is a negative voltage with an absolute value that is greater than the self-bias voltage generated on the surface of the upper electrode 170. The surface of the upper electrode 170 facing the substrate holder 120 may include a silicon-containing material.

The processing system 100 may further include a direct current (DC) power source 190 coupled to an upper electrode 170 opposite to the substrate 125. The upper electrode 170 may include an electrode plate. The electrode plate may include a silicon-containing electrode plate. Furthermore, the electrode plate may include an electrode plate doped with silicon. The DC power source 190 can include a variable DC power source. In addition, the DC power supply 190 may include a bipolar DC power supply. The DC power supply 190 may further include a system configured to monitor, adjust, or control at least one of the polarity, current, voltage, or on / off status of the DC power supply 190. Once the plasma is formed, the DC power source 190 helps to form a ballistic electron beam. An electric filter (not shown) may be used to decouple RF power from the DC power supply 190.

For example, the DC voltage range applied to the upper electrode 170 by the DC power source 190 may be from about -2000 volts (V) to about 1000V. Ideally, the absolute value of the DC voltage has a value equal to or greater than about 100V, and more desirably, the absolute value of the DC voltage has a value equal to or greater than about 1300V. In addition, it is desirable that the DC voltage has a negative polarity. Furthermore, what it wants is that the DC voltage is a negative voltage with an absolute value that is greater than the self-bias voltage generated on the surface of the upper electrode 170. The surface of the upper electrode 170 facing the substrate holder 120 may include a silicon-containing material.

Depending on the applications, additional devices such as sensors or metering devices can be coupled to the processing chamber 110 and to the source controller 155 to collect real-time data and use this real-time data to control simultaneously in two or more steps Two or more selected integration operation variables, such steps involving the etching process, passivation process, deposition process, RIE process, pulling process, contour reforming process, heat treatment process, nitride including tantalum nitride of the integration scheme Layer patterning and / or pattern transfer process. Furthermore, the same information can be used to ensure that the integration goals are achieved, including post-heat treatment, patterning uniformity (uniformity), structure removal (pulling out), structure narrowing (fine narrowing), structure Aspect ratio (aspect ratio), line width roughness, substrate production, cost of ownership and the like.

By adjusting the applied power, typically by varying the pulse frequency and load ratio, it is possible to obtain plasma properties that are significantly different from those produced in continuous wave (CW). Therefore, the RF power adjustment of these electrodes can provide control of time-averaged ion flux and ion energy.

FIG. 2A illustrates an embodiment of a patterning method 200 for a feature in a TaN layer. In one embodiment, the method 200 includes accepting a substrate including a TaN layer, as shown at block 202. In addition, the method 200 may include etching the substrate to expose at least a portion of the TaN layer, as shown at block 204. At block 206, the method 200 may include performing a passivation process to reduce lateral etching of the TaN layer. In addition, an embodiment of the method 200 may include etching the TaN layer to form features therein, where the passivation process is controlled to meet one or more target passivation results, as shown at block 208.

FIG. 2B illustrates another embodiment of a method 220 for patterning features in a TaN layer. In one embodiment, at block 222, the substrate in the process chamber is provided with an input patterning feature, which includes a photoresist structure, a patterning layer, a tantalum nitride-containing layer, and an underlying layer. A series of material opening processes are performed on the patterned layer using the mask, and the opening processes establish intermediate patterned features at block 224. A passivation process and an etching process are performed on the intermediate patterned features. The passivation process uses a boron-containing and / or hydrogen-containing gas mixture at block 226. The one or more operating variables are adjusted and the passivation and etching processes are repeatedly performed until one or more process goals are achieved in step 228. The patterned layer may include a silicon-containing anti-reflection coating, a carbon planarization film, and a tetraethoxysilane film. The one or more operational variables may include a flow rate of the boron-containing gas, a flow rate of the hydrogen-containing gas, a flow rate ratio of the boron-containing gas to the hydrogen-containing gas, and a flow rate of other gases including argon, SF ₆ , High-frequency power, low-frequency power, pressure in the process chamber, electrostatic chuck temperature, and other operational variables in the material opening process. The one or more process objectives may include a target etch rate for the TaN, a target contour including a target substrate width, a target hip width, a target cap width, a target height of the patterned feature, and / or the The total target height of the patterned features is output.

3A-3E are cross-sectional views illustrating a workpiece for forming a BEOL interconnect pattern for a memory device or a logic device on a substrate such as a wafer 125. In this embodiment, the workpiece may include multiple layers. The plurality of layers can form one layer on another layer in the form of a stacked structure. In one embodiment, the workpiece may include a first TaN layer 302, a copper (Cu) layer 304, a second TaN layer 306, and any other BEOL interconnect patterning device for a memory device or a logic device. Metal stack 308, third TaN layer 316, tetraethoxysilane (TEOS) layer 318, organic planarization (OPL) layer 320, anti-reflection layer such as silicon anti-reflection coating (SiARC) layer 322, and photoresist layer 324. The stack 308 may be a single-layer or multi-layer metal stack containing metals such as Cu, Co, Ge, Cr, Al, As, Ru, Ti, Te and the like. In one embodiment, the photoresist layer 324 can be patterned. In an embodiment, the plasma chamber 110 can accommodate a workpiece with a layered structure disposed thereon, as shown in FIG. 3A. Although the described embodiment includes three separate TaN layers, ordinary artisans will recognize that actual workpieces may include a greater or lesser number of TaN layers. Actually, the number of TaN layers has nothing to do with the operation of this embodiment. Those of ordinary skill will further recognize that the workpiece may include various layers, including a greater or lesser number of layers than the materials described herein. As long as there is at least one TaN layer, the embodiment can be utilized.

As in a series of etching processes described in FIGS. 3B-3D, several layers are opened to expose the third TaN layer 316 according to one or more conventional processes. In the process of FIG. 3B, the anti-reflection layer 322 can be etched in a pattern defined by the photoresist layer 324. The anti-reflection layer 322 may be removed using one of the appropriate processing parameters of the complex array. For example, in one embodiment, it can operate at a pressure in the range of 13mT to 17mT, high-frequency power in the range of 425W to 575W, low-frequency power in the range of 43W to 58W, and 30 ° C to 52 The etching process of the anti-reflection layer 322 is performed at a temperature in a range of ° C. In one embodiment, a combination of C ₄ F ₈ with a flow rate of 3 sccm to 5 sccm, CHF ₃ with a flow rate of 43 sccm to 58 sccm, and CF ₄ with a flow rate of 68 sccm to 92 sccm can be used as the etching gas chemistry. Those of ordinary skill will recognize alternative embodiments, including alternative gas combinations or processing parameter ranges that may depend on the materials used in the anti-reflective layer 322.

In the process of FIG. 3C, the OPL layer 320 may be opened in a pattern defined by the SiARC layer 322. In the process of FIG. 3C, the TEOS layer 318 may be opened in a pattern defined by the OPL layer 320. The OPL layer 320 may be removed using one of the appropriate processing parameters of a complex array. For example, in one embodiment, it can operate at a pressure in the range of 10mT to 15mT, high-frequency power in the range of 425W to 575W, low-frequency power in the range of 85W to 115W, and 30 ° C to 52 ° The OPL layer 320 etching process is performed at a temperature in a range of C. In one embodiment, HBr in a flow rate range of 77 sccm to 104 sccm, CO ₂ in a flow rate of 68 sccm to 92 sccm, O ₂ in a flow rate of ₂₆ sccm to 35 sccm, and flow rate in a range of 170 sccm to 230 sccm can be used. The combination of He as an etching gas chemical. One of ordinary skill will recognize additional embodiments, including alternative gas combinations or processing parameter ranges that may depend on the materials used in the OPL layer 320.

In the process of FIG. 3D, the TEOS layer 318 may be etched in a pattern defined by the OPL layer 320. The TEOS layer 318 may be removed using one of the appropriate processing parameters of the complex array. For example, in one embodiment, it can operate at a pressure in the range of 26mT to 35mT, high-frequency power in the range of 170W to 230W, low-frequency power in the range of 680W to 920W, and 43 ° C to 69 ° The TEOS layer 318 is etched at a temperature in the range of C. In one embodiment, Ar at a flow rate range of 765 sccm to 1035 sccm, C ₄ F ₈ at a flow rate of ₉ sccm to 19 sccm, O ₂ at a flow rate of 4 sccm to 6 sccm, and between 85 sccm to 115 sccm can be used. The combination of N ₂ at the flow rate serves as the etching gas chemistry. Those of ordinary skill will recognize additional embodiments, including alternative gas combinations or processing parameter ranges that may depend on the materials used in the TEOS layer 318.

In an embodiment, the third TaN layer 316 can be etched according to the process of FIG. 3E. In this embodiment, the TaN layer 316 can be opened in a pattern defined by the TEOS layer 318. In one embodiment, it can operate at a pressure in the range of 34mT to 46mT, high-frequency power in the range of 255W to 345W, low-frequency power in the range of 150W to 200W, and 38 ° C to 52 ° C. The temperature in the range is used to perform the third TaN layer 316 etching process. In this embodiment, a combination of Ar for a flow rate range of 170 sccm to 230 sccm, S ₄ F ₆ at a flow rate of 43 sccm to 58 sccm, and BCl ₃ at a flow rate of 10 sccm to 14 sccm can be used as the etching gas chemistry substance. One of ordinary skill will recognize additional embodiments, including alternative gas combinations or processing parameter ranges that may be used depending on the application or target processing results.

Although this embodiment is described with reference to the process performed on the third TaN layer 316, ordinary artisans will recognize that the process system is also applicable to other layers of TaN, including the first TaN layer 302 and the second TaN Layer 306. In fact, the embodiments may be useful in processing TaN in various structures or applications. Furthermore, equivalent processes can be used with substances other than TaN, where the materials exhibit similar etch profiles and respond similarly to additives in the etch gas.

FIG. 4A illustrates a baseline process for etching a TaN material such as the third TaN layer 316 for forming the patterned features 402. In an embodiment, the patterned feature portion 402 may include a patterned portion of the third TaN layer 316. In another embodiment, the patterned features 402 may include a portion of the TEOS layer 318. In the embodiment, a plasma etching gas system including SF ₆ is used to etch the third TaN layer 316. In this embodiment, the reaction of SF ₆ and TaN does not provide sufficient sidewall passivation to prevent the third TaN layer 316 from being etched relative to the bottom of the TEOS layer 318. In this embodiment, the TaN may be etched isotropically to pattern the underlying layers (eg, the metal-containing stack 308) to a point where they may be damaged or substantially degraded. Therefore, the process of FIG. 4A may not be sufficient for some applications or may reduce overall product throughput.

The embodiment of FIG. 4B includes the addition of BCl _{3 to} the etching gas chemistry. In this embodiment, the boron can react with nitrogen in TaN to generate a boron nitride (BN) passivation layer 404 on the sidewall of the TaN layer. The boron nitride (BN) can passivate the TaN layer, thereby reducing necking of the third TaN layer 316 by slowing the etching of the third TaN layer 316 along the sidewalls.

The embodiment of FIG. 4C illustrates an alternative embodiment where the HBr gas system is added to the plasma gas chemistry. In this embodiment, hydrogen (H) from the HBr can be combined with fluorine (F) from SF ₆ to reduce F radicals in the plasma. Reducing the F radicals can reduce the etching rate of the sidewalls of the third TaN layer 316. Furthermore, bromine (Br) from HBr may be combined with tantalum (Ta) from TaN to generate a tantalum bromide (TaBr) passivation layer 406 on the sidewall of the third TaN layer 316.

FIG. 5 is a dimensional drawing illustrating a cross-sectional dimension of an embodiment of the patterned feature portion 402 formed on the substrate 502 according to the baseline process described with reference to FIG. 4A. The substrate 502 is a metal-containing film similar to the stack 308 in FIG. 4A. In one embodiment, the obtained patterned features 402 have a base width of 45-65 nm, a neck width of 35-55 nm, and a cap width of 45-65 nm. The patterned feature 402 further includes a TaN layer having a height of 80-100 nm and a total height of 100-120 nm.

In the embodiment of FIG. 5, the etching process may be a pressure in a range of 34mT to 46mT, a high-frequency power in a range of 255W to 345W, a low-frequency power in a range of 150W to 230W, and 38 ° C to Performed at a temperature in the range of 52 ° C. In one such embodiment, a combination of Ar at a flow rate range of 170 sccm to 230 sccm, and sulfur hexafluoride (SF ₆ ) at a flow rate of 43 sccm to 58 sccm can be used as the etching gas chemistry.

For comparison, FIGS. 6A-6F illustrate a cross section of a patterned feature 402 formed on a substrate 502. In various embodiments, additional gas may be added to the etching chemistry at various flow rate ranges. For example, BCl ₃ , HBr, CH ₄ , CHF ₃ and the like can be added to the etching chemistry.

FIG. 6A illustrates the results of forming patterned features 402 using a process that includes adding BCl ₃ to the etching chemistry at a flow rate range of 10 sccm to 14 sccm for an 85% etching process. The remaining 15% is performed without the additional BCl ₃ to etch back the BN passivation layer 404. The results of FIG. 6B are produced using a process that includes adding BCl ₃ to the etching chemistry during the entire TaN etch. These two results show the accumulation of the BN passivation layer 404 on the TaN, and both results show an improved cross-sectional size of the third TaN layer 316 after patterning.

FIG. 6C shows the results of a process that includes adding HBr gas to the etching chemical at a flow rate range of 10 sccm to 14 sccm for an 85% etching process. The remaining 15% is performed without additional HBr to etch back the TaBr passivation layer 406. The obtained patterned features 402 have a base width of 45-65nm, a neck width of 35-55nm, and a cap width of 35-55nm, a height of the TaN layer of 80-100nm, and a total feature height of 100-120nm . This result shows an improvement in this baseline process without the accumulation of as much sidewall passivation material as in the BCl ₃ example. The embodiment using HBr has the additional benefit of not introducing additional chlorine (Cl) into the plasma chamber 110, as Cl-based etchant is known.

The results of additional embodiments are illustrated in Figures 6D-6F. FIG. 6D illustrates an embodiment where fluoroform (CHF ₃ ) at a flow rate of 10 sccm to 14 sccm is added to the etching gas chemistry for an etching period of 85%. FIG. 6E illustrates the results of an embodiment where methane (CH ₄ ) is added to the etching gas chemical for 85% of the etching period. Two examples show important control over the passivation of this TaN sidewall.

FIG. 6F shows the results of the embodiment of the baseline process, where the temperature of the substrate holder 120 is reduced from 40 ° C. to 20 ° C. during the etching process. The decrease in temperature indicates a further improvement in the selectivity of the TaN / TEOS, so control of additional processing parameters including temperature and pressure can be used for passivation of the TaN sidewalls.

7A-7C are cross-sectional views illustrating experimental results of a method for patterning TaN. FIG. 7A illustrates the results of a method performed by adding 12 sccm of BCl ₃ passivation gas to the plasma chemical at 30 ° C. FIG. FIG. 7B illustrates the results of a method performed by adding 12 sccm of BCl ₃ passivation gas to the plasma chemical at 45 ° C. FIG. FIG. 7C illustrates the results of a method performed by adding 12 sccm of BCl ₃ passivation gas to the plasma chemical at 45 ° C. and a pressure of 60 mT. Although each result is better than the baseline process, it is clear from these results that controlling the temperature and pressure in the processing chamber 110 can control the results so as to meet the target processing results. Examples of the target processing result may include a critical dimension of the patterned feature portion 402, a cumulative amount of a passivation layer on the upright wall surface of the third TaN layer 316, a size and shape of the TEOS cap, and the like.

8A-8B are sectional views illustrating experimental results of a method of adding HBr as a passivation gas to a patterned TaN performed by the etching chemical. FIG. 8A illustrates the result of combining 50 sccm of SF ₆ with 12 sccm of HBr at 45 ° C. and a pressure of 40 mT. Figure 8B illustrates the results of combining 50 sccm of SF ₆ with 24 sccm of HBr at 45 ° C and a pressure of 40 mT. As explained, varying the concentration of the passivation gas in the etching chemistry can also adjust the result. In this way, the concentration of the gas can also be controlled to meet one or more target processing results.

Although specific processing parameters have been described herein for embodiments that can be used to produce a formulation similar to the results shown in Figures 6A-8B, ordinary artisans will recognize that the described parameters can be controlled within a range to Achieve the goal to deal with the results. For example, the flow rate of the passivation gas may be in the range of 1-50 sccm or 12-24 sccm. In fact, depending on device and system requirements, greater flow rates may be used in some embodiments. In addition, the operating pressure may be in a range of 1-100 mT or 34 to 60 mT. Higher pressures may also be used in some embodiments, depending on the device and system requirements. Similarly, the temperature can be controlled in the range of 30-60 degrees Celsius. The average artist will recognize that higher or lower temperatures can be used, such as in the range of 1-100 degrees Celsius, depending on the device and system requirements. In fact, a variety of temperatures can be used depending on the device and system requirements.

Additional advantages and modifications will readily appear to those skilled in the art. Accordingly, the invention in its broader aspects is not limited to the specific details, representative apparatus and methods, and illustrative examples shown and described. Accordingly, departures from such details can be made without departing from the scope of the general inventive concept.

100‧‧‧ Etching and passivation system

110‧‧‧treatment room

120‧‧‧ substrate clamp

122‧‧‧electrode

125‧‧‧ wafer

126‧‧‧Back side gas supply system

128‧‧‧ Electrostatic clamping system

130‧‧‧RF generator

131‧‧‧ bias signal controller

132‧‧‧Impedance matching network

140‧‧‧Gas distribution system

145‧‧‧processing area

150‧‧‧Vacuum Pumping System

155‧‧‧Source Controller

170‧‧‧up electrode

172‧‧‧RF generator

174‧‧‧Impedance Matching Network

190‧‧‧Power

302‧‧‧First TaN layer

304‧‧‧copper (Cu) layer

306‧‧‧Second TaN layer

308‧‧‧ with metal stack

316‧‧‧Third TaN layer

318‧‧‧Tetraethoxysilane (TEOS) layer

320‧‧‧ organic planarization (OPL) layer

322‧‧‧SiARC layer

324‧‧‧Photoresistive layer

402‧‧‧Patterned Features

404‧‧‧BN passivation layer

406‧‧‧TaBr passivation layer

502‧‧‧ substrate

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and, together with the general description of the invention given above, and the detailed description given below, are used to describe the invention.

FIG. 1 illustrates one embodiment of a patterning system for feature portions in a TaN layer.

FIG. 2A illustrates an embodiment of a method for patterning features in a TaN layer.

FIG. 2B illustrates another embodiment of a patterning method for a feature portion in a TaN layer.

3A is a cross-sectional view illustrating one embodiment of a workflow for processing a patterned workpiece.

3B is a cross-sectional view illustrating one embodiment of a workflow for processing a patterned workpiece.

3C is a cross-sectional view illustrating one embodiment of a workflow for processing a patterned workpiece.

3D is a cross-sectional view illustrating one embodiment of a workflow for processing a patterned workpiece.

3E is a cross-sectional view illustrating one embodiment of a workflow for processing a patterned workpiece.

4A is a cross-sectional view illustrating an embodiment of a workpiece having a patterned TaN layer.

4B is a cross-sectional view illustrating an embodiment of a workpiece having a patterned TaN layer.

4C is a cross-sectional view illustrating an embodiment of a workpiece having a patterned TaN layer.

FIG. 5 is a dimensional drawing illustrating the dimensions of the feature portions patterned in the TaN layer.

6A is a cross-sectional view illustrating the outline of a feature portion patterned in a TaN layer according to an embodiment of a patterning method for a feature portion in a TaN layer.

6B is a cross-sectional view illustrating the outline of a feature portion patterned in a TaN layer according to an embodiment of a patterning method for a feature portion in a TaN layer.

6C is a cross-sectional view illustrating the outline of a feature portion patterned in a TaN layer according to an embodiment of a patterning method for a feature portion in a TaN layer.

6D is a cross-sectional view illustrating the outline of a feature portion patterned in a TaN layer according to an embodiment of a patterning method for a feature portion in a TaN layer.

6E is a cross-sectional view illustrating the outline of a feature portion patterned in a TaN layer according to an embodiment of a patterning method for a feature portion in a TaN layer.

6F is a cross-sectional view illustrating the outline of a feature portion patterned in a TaN layer according to an embodiment of a patterning method for a feature portion in a TaN layer.

7A is a cross-sectional view illustrating an outline of a feature portion patterned in a TaN layer according to an embodiment of a patterning method for a feature portion in a TaN layer.

7B is a cross-sectional view illustrating the outline of a feature portion patterned in a TaN layer according to an embodiment of a patterning method for a feature portion in a TaN layer.

7C is a cross-sectional view illustrating the outline of a feature portion patterned in a TaN layer according to an embodiment of a patterning method for a feature portion in a TaN layer.

8A is a cross-sectional view illustrating the outline of a feature portion patterned in a TaN layer according to an embodiment of a patterning method for a feature portion in a TaN layer.

8B is a cross-sectional view illustrating the outline of a feature portion patterned in a TaN layer according to an embodiment of a patterning method for a feature portion in a TaN layer.

Claims (21)

A method for processing a substrate includes: Accept substrates containing tantalum nitride (TaN) layers; Etching the substrate to expose at least a portion of the TaN layer; Performing a passivation process to reduce lateral etching of the TaN layer; and Etching the TaN layer to form a feature portion therein; The passivation process is controlled to meet one or more target passivation results. For example, the method for processing a substrate according to item 1 of the application, wherein the passivation process is performed at the same time as the TaN layer is etched. For example, the method for processing a substrate according to item 1 of the patent application, wherein performing the passivation process further includes reducing the number of free radicals in the plasma for etching the TaN layer. For example, the method for processing a substrate according to item 1 of the patent application, wherein the passivation process further includes reducing the fluorine in the plasma formed by the sulfur hexafluoride (SF ₆ ) gas used for etching the TaN layer. (F) Free radicals. For example, the method for processing a substrate according to item 4 of the application, further comprising adding hydrogen bromide (HBr) to the SF ₆ gas, and the hydrogen from the HBr reduces the number of F radicals in the SF ₆ plasma. For example, the method for processing a substrate according to item 1 of the patent application, wherein performing the passivation process further includes adding a passivation gas to the plasma gas mixture. For example, the method for processing a substrate according to item 6 of the application, wherein the passivation gas includes boron trichloride (BCl ₃ ) gas. The method for processing a substrate according to item 6 of the application, wherein the passivation gas comprises hydrogen bromide (HBr) gas. For example, the method for processing a substrate according to item 6 of the application, wherein the passivation gas includes trifluoromethane (CHF ₃ ) gas. The method for processing a substrate according to item 6 of the patent application, wherein the passivation gas comprises methane (CH ₄ ) gas. For example, the method for processing a substrate according to item 6 of the patent application, wherein controlling the passivation process further includes controlling the flow rate of the passivation gas. For example, the method for processing a substrate according to item 11 of the application, wherein the flow rate of the passivation gas is in the range of 1-50 sccm or in the range of 12-24 sccm. For example, the method for processing a substrate according to item 1 of the patent application, wherein controlling the passivation process further includes controlling the pressure in the processing chamber. For example, the method for processing a substrate according to item 13 of the patent application range, wherein the pressure is in the range of 1-100 mT or in the range of 34-60 mT. For example, the method for processing a substrate according to item 1 of the patent application, wherein controlling the passivation process further includes controlling the temperature in the processing chamber. For example, the method for processing a substrate according to item 15 of the patent application range, wherein the temperature is in the range of 30-60 degrees Celsius. For example, the method for processing a substrate according to item 1 of the application, wherein the passivation gas includes boron trichloride (BCl ₃ ) gas and hydrogen bromide (HBr) gas. For example, the method for processing a substrate according to item 1 of the application, wherein the passivation process and the etching process are repeatedly performed to meet the passivation target. A method for processing a substrate, the method includes: Providing an input patterning feature in the process chamber, which includes a patterning layer and a tantalum nitride (TaN) layer; Performing a series of material opening processes on the patterned layer using a mask, the opening process establishing an intermediate patterned feature; Performing a passivation process and an etching process on the intermediate feature, the passivation process using a boron-containing and / or hydrogen-containing gas mixture, the passivation process and the etching process generating an output patterned feature; One or more operating variables of the passivation process and the etching process are adjusted so as to achieve one or more process goals. For example, the method for processing a substrate according to claim 19, wherein the one or more operating variables include one or more of the following: the flow rate of the boron-containing gas, the flow rate of the hydrogen-containing gas, the boron-containing gas pair The flow rate ratio of the hydrogen-containing gas, the flow rates of other gases including argon, SF ₆ , high-frequency power, low-frequency power, pressure in the process chamber, and electrostatic chuck temperature. For example, the method for processing a substrate according to item 19 of the application, wherein the one or more process targets include one or more of the following: the target etch rate of the TaN layer, the target substrate width, the target neck width, and the target cap Width, target height of the target contour of the patterned feature, and / or total target height of the output patterned feature.